1 /*
2 * SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3 * SPDX-License-Identifier: MIT
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24
25
26 #include <nv_ref.h>
27 #include <nv.h>
28 #include <nv-priv.h>
29 #include <os/os.h>
30 #include <osapi.h>
31 #include <class/cl0000.h>
32 #include <rmosxfac.h> // Declares RmInitRm().
33 #include "gpu/gpu.h"
34 #include "gps.h"
35 #include <osfuncs.h>
36 #include <platform/chipset/chipset.h>
37
38 #include <objtmr.h>
39 #include <gpu/subdevice/subdevice.h>
40 #include <mem_mgr/mem.h>
41 #include "kernel/gpu/mem_mgr/mem_mgr.h"
42
43 #include <gpu/mem_sys/kern_mem_sys.h>
44
45 #include <diagnostics/journal.h>
46 #include <nvrm_registry.h>
47
48 #include <nvUnixVersion.h>
49 #include <gpu_mgr/gpu_mgr.h>
50 #include <core/thread_state.h>
51 #include <platform/acpi_common.h>
52 #include <core/locks.h>
53
54 #include <mem_mgr/p2p.h>
55
56 #include "rmapi/exports.h"
57 #include "rmapi/rmapi_utils.h"
58 #include "rmapi/rs_utils.h"
59 #include "rmapi/resource_fwd_decls.h"
60 #include <nv-kernel-rmapi-ops.h>
61 #include <rmobjexportimport.h>
62 #include "nv-reg.h"
63 #include "nv-firmware-registry.h"
64 #include "core/hal_mgr.h"
65 #include "gpu/device/device.h"
66
67 #include "resserv/rs_server.h"
68 #include "resserv/rs_client.h"
69 #include "resserv/rs_resource.h"
70 #include "gpu/gpu_uuid.h"
71
72 #include "platform/chipset/pci_pbi.h"
73
74 #include "ctrl/ctrl0000/ctrl0000system.h"
75 #include "ctrl/ctrl0073/ctrl0073dp.h"
76 #include "ctrl/ctrl0073/ctrl0073system.h"
77 #include "ctrl/ctrl0073/ctrl0073specific.h"
78 #include "ctrl/ctrl2080/ctrl2080bios.h"
79 #include "ctrl/ctrl2080/ctrl2080fb.h"
80 #include "ctrl/ctrl2080/ctrl2080perf.h"
81 #include "ctrl/ctrl2080/ctrl2080gpu.h"
82 #include "ctrl/ctrl402c.h"
83
84 #include "g_nv_name_released.h" // released chip entries from nvChipAutoFlags.h
85
86 #include <virtualization/hypervisor/hypervisor.h>
87
88 #include "gpu/bus/kern_bus.h"
89
90 //
91 // If timer callback comes when PM resume is in progress, then it can't be
92 // serviced. The timer needs to be rescheduled in this case. This time controls
93 // the duration of rescheduling.
94 //
95 #define TIMER_RESCHED_TIME_DURING_PM_RESUME_NS (100 * 1000 * 1000)
96
97 //
98 // Helper function which can be called before doing any RM control
99 // This function:
100 //
101 // a. Performs threadStateInit().
102 // b. Acquires API lock.
103 // c. Checks if RMAPI client handle is valid (i.e. RM is initialized) and
104 // returns early if RMAPI client handle is invalid.
105 // d. Increments the dynamic power refcount. If GPU is in RTD3 suspended
106 // state, then it will wake-up the GPU.
107 // e. Returns the RMAPI interface handle.
108 //
109 // This function should be called only when caller doesn't have acquired API
110 // lock. Caller needs to use RmUnixRmApiEpilogue() after RM control, if
111 // RmUnixRmApiPrologue() is successful.
112 //
RmUnixRmApiPrologue(nv_state_t * pNv,THREAD_STATE_NODE * pThreadNode,NvU32 module)113 RM_API *RmUnixRmApiPrologue(nv_state_t *pNv, THREAD_STATE_NODE *pThreadNode, NvU32 module)
114 {
115 threadStateInit(pThreadNode, THREAD_STATE_FLAGS_NONE);
116
117 if ((rmapiLockAcquire(API_LOCK_FLAGS_NONE, module)) == NV_OK)
118 {
119 if ((pNv->rmapi.hClient != 0) &&
120 (os_ref_dynamic_power(pNv, NV_DYNAMIC_PM_FINE) == NV_OK))
121 {
122 return rmapiGetInterface(RMAPI_API_LOCK_INTERNAL);
123 }
124
125 rmapiLockRelease();
126 }
127
128 threadStateFree(pThreadNode, THREAD_STATE_FLAGS_NONE);
129
130 return NULL;
131 }
132
133 //
134 // Helper function which can be called after doing RM control, if
135 // caller has used RmUnixRmApiPrologue() helper function. This function:
136 //
137 // a. Decrements the dynamic power refcount.
138 // b. Release API lock.
139 // c. Performs threadStateFree().
140 //
RmUnixRmApiEpilogue(nv_state_t * pNv,THREAD_STATE_NODE * pThreadNode)141 void RmUnixRmApiEpilogue(nv_state_t *pNv, THREAD_STATE_NODE *pThreadNode)
142 {
143 os_unref_dynamic_power(pNv, NV_DYNAMIC_PM_FINE);
144 rmapiLockRelease();
145 threadStateFree(pThreadNode, THREAD_STATE_FLAGS_NONE);
146 }
147
RmGpuHasIOSpaceEnabled(nv_state_t * nv)148 NvBool RmGpuHasIOSpaceEnabled(nv_state_t * nv)
149 {
150 NvU16 val;
151 NvBool has_io;
152 os_pci_read_word(nv->handle, NV_CONFIG_PCI_NV_1, &val);
153 has_io = FLD_TEST_DRF(_CONFIG, _PCI_NV_1, _IO_SPACE, _ENABLED, val);
154 return has_io;
155 }
156
157 // This is a stub function for unix
osHandleDeferredRecovery(OBJGPU * pGpu)158 void osHandleDeferredRecovery(
159 OBJGPU *pGpu
160 )
161 {
162
163 }
164
165 // This is a stub function for unix
osIsSwPreInitOnly(OS_GPU_INFO * pOsGpuInfo)166 NvBool osIsSwPreInitOnly
167 (
168 OS_GPU_INFO *pOsGpuInfo
169 )
170 {
171 return NV_FALSE;
172 }
173
RmGetGpuUuidRaw(nv_state_t * pNv)174 const NvU8 * RmGetGpuUuidRaw(
175 nv_state_t *pNv
176 )
177 {
178 NV_STATUS rmStatus;
179 OBJGPU *pGpu = NULL;
180 NvU32 gidFlags;
181 NvBool isApiLockTaken = NV_FALSE;
182
183 if (pNv->nv_uuid_cache.valid)
184 return pNv->nv_uuid_cache.uuid;
185
186 if (!rmapiLockIsOwner())
187 {
188 rmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU);
189 if (rmStatus != NV_OK)
190 {
191 return NULL;
192 }
193
194 isApiLockTaken = NV_TRUE;
195 }
196
197 pGpu = NV_GET_NV_PRIV_PGPU(pNv);
198
199 //
200 // PBI is not present in simulation and the loop inside
201 // pciPbiReadUuid takes up considerable amount of time in
202 // simulation environment during RM load.
203 //
204 if (pGpu && IS_SIMULATION(pGpu))
205 {
206 rmStatus = NV_ERR_NOT_SUPPORTED;
207 }
208 else
209 {
210 rmStatus = pciPbiReadUuid(pNv->handle, pNv->nv_uuid_cache.uuid);
211 }
212
213 if (rmStatus == NV_OK)
214 {
215 rmStatus = gpumgrSetUuid(pNv->gpu_id, pNv->nv_uuid_cache.uuid);
216 if (rmStatus != NV_OK)
217 {
218 goto err;
219 }
220
221 pNv->nv_uuid_cache.valid = NV_TRUE;
222 goto done;
223 }
224 else if (rmStatus == NV_ERR_NOT_SUPPORTED)
225 {
226 nv_printf(NV_DBG_INFO,
227 "NVRM: PBI is not supported for GPU " NV_PCI_DEV_FMT "\n",
228 NV_PCI_DEV_FMT_ARGS(pNv));
229 }
230
231 gidFlags = DRF_DEF(2080_GPU_CMD,_GPU_GET_GID_FLAGS,_TYPE,_SHA1)
232 | DRF_DEF(2080_GPU_CMD,_GPU_GET_GID_FLAGS,_FORMAT,_BINARY);
233
234 if (!pGpu)
235 goto err;
236
237 rmStatus = gpuGetGidInfo(pGpu, NULL, NULL, gidFlags);
238 if (rmStatus != NV_OK)
239 goto err;
240
241 if (!pGpu->gpuUuid.isInitialized)
242 goto err;
243
244 // copy the uuid from the OBJGPU uuid cache
245 os_mem_copy(pNv->nv_uuid_cache.uuid, pGpu->gpuUuid.uuid, GPU_UUID_LEN);
246 pNv->nv_uuid_cache.valid = NV_TRUE;
247
248 done:
249 if (isApiLockTaken)
250 {
251 rmapiLockRelease();
252 }
253
254 return pNv->nv_uuid_cache.uuid;
255
256 err:
257 if (isApiLockTaken)
258 {
259 rmapiLockRelease();
260 }
261
262 return NULL;
263 }
264
RmGpuUuidRawToString(const NvU8 * pGidData,char * pBuf,NvU32 bufLen)265 static NV_STATUS RmGpuUuidRawToString(
266 const NvU8 *pGidData,
267 char *pBuf,
268 NvU32 bufLen
269 )
270 {
271 NvU8 *pGidString;
272 NvU32 GidStrlen;
273 NV_STATUS rmStatus;
274 NvU32 gidFlags;
275
276 gidFlags = DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _FORMAT, _ASCII) |
277 DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1);
278
279 rmStatus = transformGidToUserFriendlyString(pGidData, RM_SHA1_GID_SIZE,
280 &pGidString, &GidStrlen,
281 gidFlags);
282 if (rmStatus != NV_OK)
283 return rmStatus;
284
285 if (bufLen >= GidStrlen)
286 portMemCopy(pBuf, bufLen, pGidString, GidStrlen);
287 else
288 rmStatus = NV_ERR_BUFFER_TOO_SMALL;
289
290 portMemFree((void *)pGidString);
291
292 return rmStatus;
293 }
294
295 // This function should be called with the API and GPU locks already acquired.
296 NV_STATUS
RmLogGpuCrash(OBJGPU * pGpu)297 RmLogGpuCrash(OBJGPU *pGpu)
298 {
299 NV_STATUS status = NV_OK;
300 NvBool bGpuIsLost, bGpuIsConnected;
301
302 if (pGpu == NULL)
303 {
304 return NV_ERR_INVALID_ARGUMENT;
305 }
306
307 //
308 // Re-evaluate whether or not the GPU is accessible. This could be called
309 // from a recovery context where the OS has re-enabled MMIO for the device.
310 // This happens during EEH processing on IBM Power + Linux, and marking
311 // the device as connected again will allow rcdbAddRmGpuDump() to collect
312 // more GPU state.
313 //
314 bGpuIsLost = pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_LOST);
315 bGpuIsConnected = pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_CONNECTED);
316 if (!bGpuIsConnected || bGpuIsLost)
317 {
318 nv_state_t *nv = NV_GET_NV_STATE(pGpu);
319 nv_priv_t *nvp = NV_GET_NV_PRIV(nv);
320 NvU32 pmcBoot0 = NV_PRIV_REG_RD32(nv->regs->map_u, NV_PMC_BOOT_0);
321 if (pmcBoot0 == nvp->pmc_boot_0)
322 {
323 pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_CONNECTED, NV_TRUE);
324 pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_LOST, NV_FALSE);
325 }
326 }
327
328 //
329 // Log the engine data to the Journal object, to be pulled out later. This
330 // will return NV_WARN_MORE_PROCESSING_REQUIRED if the dump needed to be
331 // deferred to a passive IRQL. We still log the crash dump as being created
332 // in that case since it (should) be created shortly thereafter, and
333 // there's currently not a good way to print the below notification
334 // publicly from the core RM when the DPC completes.
335 //
336 status = rcdbAddRmGpuDump(pGpu);
337 if (status != NV_OK && status != NV_WARN_MORE_PROCESSING_REQUIRED)
338 {
339 NV_PRINTF(LEVEL_ERROR,
340 "%s: failed to save GPU crash data\n", __FUNCTION__);
341 }
342 else
343 {
344 status = NV_OK;
345 nv_printf(NV_DBG_ERRORS,
346 "NVRM: A GPU crash dump has been created. If possible, please run\n"
347 "NVRM: nvidia-bug-report.sh as root to collect this data before\n"
348 "NVRM: the NVIDIA kernel module is unloaded.\n");
349 if (hypervisorIsVgxHyper())
350 {
351 nv_printf(NV_DBG_ERRORS, "NVRM: Dumping nvlogs buffers\n");
352 nvlogDumpToKernelLog(NV_FALSE);
353 }
354 }
355
356 // Restore the disconnected properties, if they were reset
357 pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_CONNECTED, bGpuIsConnected);
358 pGpu->setProperty(pGpu, PDB_PROP_GPU_IS_LOST, bGpuIsLost);
359
360 // Restore persistence mode to the way it was prior to the crash
361 osModifyGpuSwStatePersistence(pGpu->pOsGpuInfo,
362 pGpu->getProperty(pGpu, PDB_PROP_GPU_PERSISTENT_SW_STATE));
363
364 return status;
365 }
366
free_os_event_under_lock(nv_event_t * event)367 static void free_os_event_under_lock(nv_event_t *event)
368 {
369 event->active = NV_FALSE;
370
371 // If refcount > 0, event will be freed by osDereferenceObjectCount
372 // when the last associated RM event is freed.
373 if (event->refcount == 0)
374 portMemFree(event);
375 }
376
free_os_events(nv_file_private_t * nvfp,NvHandle client)377 static void free_os_events(
378 nv_file_private_t *nvfp,
379 NvHandle client
380 )
381 {
382 nv_state_t *nv = nv_get_ctl_state();
383 nv_event_t **pprev;
384
385 portSyncSpinlockAcquire(nv->event_spinlock);
386
387 pprev = &nv->event_list;
388 while (*pprev != NULL)
389 {
390 nv_event_t *cur = *pprev;
391 //
392 // XXX We must be called from either rm_client_free_os_events() or
393 // RmFreeUnusedClients() for this to work.
394 //
395 if ((cur->hParent == client) || (cur->nvfp == nvfp))
396 {
397 *pprev = cur->next;
398 free_os_event_under_lock(cur);
399 }
400 else
401 {
402 pprev = &cur->next;
403 }
404 }
405
406 portSyncSpinlockRelease(nv->event_spinlock);
407 }
408
rm_client_free_os_events(NvHandle client)409 void rm_client_free_os_events(
410 NvHandle client
411 )
412 {
413 free_os_events(NULL, client);
414 }
415
RmFreeUnusedClients(nv_state_t * nv,nv_file_private_t * nvfp)416 void RmFreeUnusedClients(
417 nv_state_t *nv,
418 nv_file_private_t *nvfp
419 )
420 {
421 NvU32 *pClientList;
422 NvU32 numClients, i;
423 NV_STATUS status;
424 RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL);
425
426 //
427 // The 'nvfp' pointer uniquely identifies an open instance in kernel space
428 // and the kernel interface layer guarantees that we are not called before
429 // the associated nvfp descriptor is closed. We can thus safely free
430 // abandoned clients with matching 'nvfp' pointers.
431 //
432 status = rmapiGetClientHandlesFromOSInfo(nvfp, &pClientList, &numClients);
433 if (status != NV_OK)
434 {
435 numClients = 0;
436 }
437
438 for (i = 0; i < numClients; ++i)
439 {
440 NV_PRINTF(LEVEL_INFO, "freeing abandoned client 0x%x\n",
441 pClientList[i]);
442
443 }
444
445 if (numClients != 0)
446 {
447 pRmApi->DisableClients(pRmApi, pClientList, numClients);
448
449 portMemFree(pClientList);
450 }
451
452 // Clean up any remaining events using this nvfp.
453 free_os_events(nvfp, 0);
454 }
455
RmUnbindLock(nv_state_t * nv)456 static void RmUnbindLock(
457 nv_state_t *nv
458 )
459 {
460 OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv);
461
462 if ((pGpu == NULL) || (gpuGetUserClientCount(pGpu) == 0))
463 {
464 nv->flags |= NV_FLAG_UNBIND_LOCK;
465 }
466 }
467
allocate_os_event(NvHandle hParent,nv_file_private_t * nvfp,NvU32 fd)468 static NV_STATUS allocate_os_event(
469 NvHandle hParent,
470 nv_file_private_t *nvfp,
471 NvU32 fd
472 )
473 {
474 nv_state_t *nv = nv_get_ctl_state();
475 NvU32 status = NV_OK;
476 nv_event_t *event;
477
478 nv_event_t *new_event = portMemAllocNonPaged(sizeof(nv_event_t));
479 if (new_event == NULL)
480 {
481 status = NV_ERR_NO_MEMORY;
482 goto done;
483 }
484
485 portSyncSpinlockAcquire(nv->event_spinlock);
486 for (event = nv->event_list; event; event = event->next)
487 {
488 // Only one event may be associated with a given fd.
489 if (event->hParent == hParent && event->fd == fd)
490 {
491 status = NV_ERR_INVALID_ARGUMENT;
492 portSyncSpinlockRelease(nv->event_spinlock);
493 goto done;
494 }
495 }
496
497 new_event->next = nv->event_list;
498 nv->event_list = new_event;
499 portSyncSpinlockRelease(nv->event_spinlock);
500
501 done:
502 if (status == NV_OK)
503 {
504 new_event->hParent = hParent;
505 new_event->nvfp = nvfp;
506 new_event->fd = fd;
507 new_event->active = NV_TRUE;
508 new_event->refcount = 0;
509
510 nvfp->bCleanupRmapi = NV_TRUE;
511
512 NV_PRINTF(LEVEL_INFO, "allocated OS event:\n");
513 NV_PRINTF(LEVEL_INFO, " hParent: 0x%x\n", hParent);
514 NV_PRINTF(LEVEL_INFO, " fd: %d\n", fd);
515 }
516 else
517 {
518 portMemFree(new_event);
519 }
520
521 return status;
522 }
523
RmAllocOsEvent(NvHandle hParent,nv_file_private_t * nvfp,NvU32 fd)524 NV_STATUS RmAllocOsEvent(
525 NvHandle hParent,
526 nv_file_private_t *nvfp,
527 NvU32 fd
528 )
529 {
530 if (NV_OK != allocate_os_event(hParent, nvfp, fd))
531 {
532 NV_PRINTF(LEVEL_ERROR, "failed to allocate OS event\n");
533 return NV_ERR_INSUFFICIENT_RESOURCES;
534 }
535 return NV_OK;
536 }
537
free_os_event(NvHandle hParent,NvU32 fd)538 static NV_STATUS free_os_event(
539 NvHandle hParent,
540 NvU32 fd
541 )
542 {
543 nv_state_t *nv = nv_get_ctl_state();
544 nv_event_t *event, *tmp;
545 NV_STATUS result;
546
547 portSyncSpinlockAcquire(nv->event_spinlock);
548 tmp = event = nv->event_list;
549 while (event)
550 {
551 if ((event->fd == fd) && (event->hParent == hParent))
552 {
553 if (event == nv->event_list)
554 nv->event_list = event->next;
555 else
556 tmp->next = event->next;
557 break;
558 }
559 tmp = event;
560 event = event->next;
561 }
562
563 if (event != NULL)
564 {
565 free_os_event_under_lock(event);
566 result = NV_OK;
567 }
568 else
569 result = NV_ERR_INVALID_EVENT;
570 portSyncSpinlockRelease(nv->event_spinlock);
571
572 if (result == NV_OK)
573 {
574 NV_PRINTF(LEVEL_INFO, "freed OS event:\n");
575 NV_PRINTF(LEVEL_INFO, " hParent: 0x%x\n", hParent);
576 NV_PRINTF(LEVEL_INFO, " fd: %d\n", fd);
577 }
578 else
579 {
580 NV_PRINTF(LEVEL_ERROR, "failed to find OS event:\n");
581 NV_PRINTF(LEVEL_ERROR, " hParent: 0x%x\n", hParent);
582 NV_PRINTF(LEVEL_ERROR, " fd: %d\n", fd);
583 }
584
585 return result;
586 }
587
RmFreeOsEvent(NvHandle hParent,NvU32 fd)588 NV_STATUS RmFreeOsEvent(
589 NvHandle hParent,
590 NvU32 fd
591 )
592 {
593 if (NV_OK != free_os_event(hParent, fd))
594 {
595 return NV_ERR_INVALID_EVENT;
596 }
597 return NV_OK;
598 }
599
RmExecuteWorkItem(void * pWorkItem)600 static void RmExecuteWorkItem(
601 void *pWorkItem
602 )
603 {
604 nv_work_item_t *pWi = (nv_work_item_t *)pWorkItem;
605 NvU32 gpuMask;
606 NvU32 releaseLocks = 0;
607
608 if (!(pWi->flags & NV_WORK_ITEM_FLAGS_REQUIRES_GPU) &&
609 ((pWi->flags & OS_QUEUE_WORKITEM_FLAGS_LOCK_GPUS_RW) ||
610 (pWi->flags & OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_DEVICE_RW) ||
611 (pWi->flags & OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_SUBDEVICE_RW) ||
612 (pWi->flags & OS_QUEUE_WORKITEM_FLAGS_FULL_GPU_SANITY)))
613 {
614 // Requesting one of the GPU locks without providing a GPU instance
615 NV_ASSERT(0);
616 goto done;
617 }
618
619 // Get locks requested by workitem
620 if (NV_OK != workItemLocksAcquire(pWi->gpuInstance, pWi->flags,
621 &releaseLocks, &gpuMask))
622 {
623 goto done;
624 }
625
626 // Some work items may not require a valid GPU instance
627 if (pWi->flags & NV_WORK_ITEM_FLAGS_REQUIRES_GPU)
628 {
629 pWi->func.pGpuFunction(pWi->gpuInstance, pWi->pData);
630 }
631 else
632 {
633 pWi->func.pSystemFunction(pWi->pData);
634 }
635
636 // Release any locks taken
637 workItemLocksRelease(releaseLocks, gpuMask);
638
639 done:
640 if ((pWi->pData != NULL) &&
641 !(pWi->flags & NV_WORK_ITEM_FLAGS_DONT_FREE_DATA))
642 {
643 portMemFree(pWi->pData);
644 }
645
646 portMemFree((void *)pWi);
647 }
648
RmGetEventData(nv_file_private_t * nvfp,NvP64 pEvent,NvU32 * MoreEvents,NvBool bUserModeArgs)649 static NV_STATUS RmGetEventData(
650 nv_file_private_t *nvfp,
651 NvP64 pEvent,
652 NvU32 *MoreEvents,
653 NvBool bUserModeArgs
654 )
655 {
656 NV_STATUS RmStatus;
657 NvUnixEvent *pKernelEvent = NULL;
658 nv_event_t nv_event;
659 RMAPI_PARAM_COPY paramCopy;
660
661 RmStatus = nv_get_event(nvfp, &nv_event, MoreEvents);
662 if (RmStatus != NV_OK)
663 return NV_ERR_OPERATING_SYSTEM;
664
665 // setup for access to client's parameters
666 RMAPI_PARAM_COPY_INIT(paramCopy, pKernelEvent, pEvent, 1, sizeof(NvUnixEvent));
667 RmStatus = rmapiParamsAcquire(¶mCopy, bUserModeArgs);
668 if (RmStatus != NV_OK)
669 return NV_ERR_OPERATING_SYSTEM;
670
671 pKernelEvent->hObject = nv_event.hObject;
672 pKernelEvent->NotifyIndex = nv_event.index;
673 pKernelEvent->info32 = nv_event.info32;
674 pKernelEvent->info16 = nv_event.info16;
675
676 // release client buffer access, with copyout as needed
677 if (rmapiParamsRelease(¶mCopy) != NV_OK)
678 return NV_ERR_OPERATING_SYSTEM;
679
680 return NV_OK;
681 }
682
RmAccessRegistry(NvHandle hClient,NvHandle hObject,NvU32 AccessType,NvP64 clientDevNodeAddress,NvU32 DevNodeLength,NvP64 clientParmStrAddress,NvU32 ParmStrLength,NvP64 clientBinaryDataAddress,NvU32 * pBinaryDataLength,NvU32 * Data,NvU32 * Entry)683 static NV_STATUS RmAccessRegistry(
684 NvHandle hClient,
685 NvHandle hObject,
686 NvU32 AccessType,
687 NvP64 clientDevNodeAddress,
688 NvU32 DevNodeLength,
689 NvP64 clientParmStrAddress,
690 NvU32 ParmStrLength,
691 NvP64 clientBinaryDataAddress,
692 NvU32 *pBinaryDataLength,
693 NvU32 *Data,
694 NvU32 *Entry
695 )
696 {
697 NvU32 gpuMask = 0, gpuInstance = 0;
698 OBJGPU *pGpu;
699 NvBool isDevice = NV_FALSE;
700 NV_STATUS RmStatus = NV_ERR_OPERATING_SYSTEM;
701 RsClient *pClient;
702 Device *pDevice;
703 Subdevice *pSubdevice;
704
705 RMAPI_PARAM_COPY devNodeParamCopy;
706 NvU8 *tmpDevNode = NULL;
707 NvU32 copyOutDevNodeLength = 0;
708
709 RMAPI_PARAM_COPY parmStrParamCopy;
710 char *tmpParmStr = NULL;
711 NvU32 copyOutParmStrLength = 0;
712
713 RMAPI_PARAM_COPY binaryDataParamCopy;
714 NvU8 *tmpBinaryData = NULL;
715 NvU32 BinaryDataLength = 0;
716 NvU32 copyOutBinaryDataLength = 0;
717
718 if (NV_OK != serverAcquireClient(&g_resServ, hClient, LOCK_ACCESS_WRITE, &pClient))
719 return NV_ERR_INVALID_CLIENT;
720
721 if (hClient == hObject)
722 {
723 pGpu = NULL;
724 }
725 else
726 {
727 RmStatus = deviceGetByHandle(pClient, hObject, &pDevice);
728 if (RmStatus != NV_OK)
729 {
730 RmStatus = subdeviceGetByHandle(pClient, hObject, &pSubdevice);
731 if (RmStatus != NV_OK)
732 goto done;
733
734 RmStatus = rmGpuGroupLockAcquire(pSubdevice->subDeviceInst,
735 GPU_LOCK_GRP_SUBDEVICE,
736 GPUS_LOCK_FLAGS_NONE,
737 RM_LOCK_MODULES_GPU,
738 &gpuMask);
739 if (RmStatus != NV_OK)
740 {
741 gpuMask = 0;
742 goto done;
743 }
744
745 GPU_RES_SET_THREAD_BC_STATE(pSubdevice);
746 pGpu = GPU_RES_GET_GPU(pSubdevice);
747 }
748 else
749 {
750 RmStatus = rmGpuGroupLockAcquire(pDevice->deviceInst,
751 GPU_LOCK_GRP_DEVICE,
752 GPUS_LOCK_FLAGS_NONE,
753 RM_LOCK_MODULES_GPU,
754 &gpuMask);
755 if (RmStatus != NV_OK)
756 {
757 gpuMask = 0;
758 goto done;
759 }
760
761 GPU_RES_SET_THREAD_BC_STATE(pDevice);
762 pGpu = GPU_RES_GET_GPU(pDevice);
763 isDevice = NV_TRUE;
764 }
765 }
766
767 if (pBinaryDataLength)
768 {
769 BinaryDataLength = *pBinaryDataLength;
770 }
771
772 // a passed-in devNode
773 if (DevNodeLength)
774 {
775 // the passed-in DevNodeLength does not account for '\0'
776 DevNodeLength++;
777
778 if (DevNodeLength > NVOS38_MAX_REGISTRY_STRING_LENGTH)
779 {
780 RmStatus = NV_ERR_INVALID_STRING_LENGTH;
781 goto done;
782 }
783
784 // get access to client's DevNode
785 RMAPI_PARAM_COPY_INIT(devNodeParamCopy, tmpDevNode, clientDevNodeAddress, DevNodeLength, 1);
786 devNodeParamCopy.flags |= RMAPI_PARAM_COPY_FLAGS_ZERO_BUFFER;
787 RmStatus = rmapiParamsAcquire(&devNodeParamCopy, NV_TRUE);
788 if (RmStatus != NV_OK)
789 {
790 RmStatus = NV_ERR_OPERATING_SYSTEM;
791 goto done;
792 }
793 }
794
795 // a passed-in parmStr
796 if (ParmStrLength)
797 {
798 // the passed-in ParmStrLength does not account for '\0'
799 ParmStrLength++;
800
801 if ((ParmStrLength == 0) || (ParmStrLength > NVOS38_MAX_REGISTRY_STRING_LENGTH))
802 {
803 RmStatus = NV_ERR_INVALID_STRING_LENGTH;
804 goto done;
805 }
806 // get access to client's parmStr
807 RMAPI_PARAM_COPY_INIT(parmStrParamCopy, tmpParmStr, clientParmStrAddress, ParmStrLength, 1);
808 RmStatus = rmapiParamsAcquire(&parmStrParamCopy, NV_TRUE);
809 if (RmStatus != NV_OK)
810 {
811 RmStatus = NV_ERR_OPERATING_SYSTEM;
812 goto done;
813 }
814 if (tmpParmStr[ParmStrLength - 1] != '\0')
815 {
816 RmStatus = NV_ERR_INVALID_ARGUMENT;
817 goto done;
818 }
819 }
820
821 if ((AccessType == NVOS38_ACCESS_TYPE_READ_BINARY) ||
822 (AccessType == NVOS38_ACCESS_TYPE_WRITE_BINARY))
823 {
824 if ((BinaryDataLength > NVOS38_MAX_REGISTRY_BINARY_LENGTH) ||
825 (BinaryDataLength == 0))
826 {
827 RmStatus = NV_ERR_INVALID_STRING_LENGTH;
828 goto done;
829 }
830
831 // get access to client's binaryData
832 RMAPI_PARAM_COPY_INIT(binaryDataParamCopy, tmpBinaryData, clientBinaryDataAddress, BinaryDataLength, 1);
833 if (AccessType == NVOS38_ACCESS_TYPE_READ_BINARY)
834 binaryDataParamCopy.flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYIN;
835 RmStatus = rmapiParamsAcquire(&binaryDataParamCopy, NV_TRUE);
836 if (RmStatus != NV_OK)
837 {
838 RmStatus = NV_ERR_OPERATING_SYSTEM;
839 goto done;
840 }
841 }
842
843 switch (AccessType)
844 {
845 case NVOS38_ACCESS_TYPE_READ_DWORD:
846 RmStatus = osReadRegistryDword(pGpu,
847 tmpParmStr, Data);
848 break;
849
850 case NVOS38_ACCESS_TYPE_WRITE_DWORD:
851 if (isDevice && osIsAdministrator())
852 {
853 while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL)
854 {
855 RmStatus = osWriteRegistryDword(pGpu,
856 tmpParmStr, *Data);
857
858 if (RmStatus != NV_OK)
859 goto done;
860 }
861 break;
862 }
863
864 RmStatus = osWriteRegistryDword(pGpu,
865 tmpParmStr, *Data);
866 break;
867
868 case NVOS38_ACCESS_TYPE_READ_BINARY:
869 RmStatus = osReadRegistryBinary(pGpu,
870 tmpParmStr, tmpBinaryData, &BinaryDataLength);
871
872 if (RmStatus != NV_OK)
873 {
874 goto done;
875 }
876
877 if (BinaryDataLength)
878 copyOutBinaryDataLength = BinaryDataLength;
879
880 break;
881
882 case NVOS38_ACCESS_TYPE_WRITE_BINARY:
883 if (isDevice && osIsAdministrator())
884 {
885 while ((pGpu = gpumgrGetNextGpu(gpuMask, &gpuInstance)) != NULL)
886 {
887 RmStatus = osWriteRegistryBinary(pGpu,
888 tmpParmStr, tmpBinaryData,
889 BinaryDataLength);
890
891 if (RmStatus != NV_OK)
892 goto done;
893 }
894 break;
895 }
896
897 RmStatus = osWriteRegistryBinary(pGpu,
898 tmpParmStr, tmpBinaryData,
899 BinaryDataLength);
900 break;
901
902 default:
903 RmStatus = NV_ERR_INVALID_ACCESS_TYPE;
904 }
905
906 done:
907 if (gpuMask != 0)
908 rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE);
909
910 if (tmpDevNode != NULL)
911 {
912 // skip copyout on error
913 if ((RmStatus != NV_OK) || (copyOutDevNodeLength == 0))
914 devNodeParamCopy.flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYOUT;
915 devNodeParamCopy.paramsSize = copyOutDevNodeLength;
916 if (NV_OK != rmapiParamsRelease(&devNodeParamCopy))
917 if (RmStatus == NV_OK)
918 RmStatus = NV_ERR_OPERATING_SYSTEM;
919 }
920 if (tmpParmStr != NULL)
921 {
922 // skip copyout on error
923 if ((RmStatus != NV_OK) || (copyOutParmStrLength == 0))
924 parmStrParamCopy.flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYOUT;
925 parmStrParamCopy.paramsSize = copyOutParmStrLength;
926 if (NV_OK != rmapiParamsRelease(&parmStrParamCopy))
927 if (RmStatus == NV_OK)
928 RmStatus = NV_ERR_OPERATING_SYSTEM;
929 }
930 if (tmpBinaryData != NULL)
931 {
932 // skip copyout on error
933 if ((RmStatus != NV_OK) || (copyOutBinaryDataLength == 0))
934 binaryDataParamCopy.flags |= RMAPI_PARAM_COPY_FLAGS_SKIP_COPYOUT;
935 binaryDataParamCopy.paramsSize = copyOutBinaryDataLength;
936 if (NV_OK != rmapiParamsRelease(&binaryDataParamCopy))
937 if (RmStatus == NV_OK)
938 RmStatus = NV_ERR_OPERATING_SYSTEM;
939 *pBinaryDataLength = copyOutBinaryDataLength;
940 }
941
942 serverReleaseClient(&g_resServ, LOCK_ACCESS_WRITE, pClient);
943 return RmStatus;
944 }
945
RmUpdateDeviceMappingInfo(NvHandle hClient,NvHandle hDevice,NvHandle hMappable,void * pOldCpuAddress,void * pNewCpuAddress)946 static NV_STATUS RmUpdateDeviceMappingInfo(
947 NvHandle hClient,
948 NvHandle hDevice,
949 NvHandle hMappable,
950 void *pOldCpuAddress,
951 void *pNewCpuAddress
952 )
953 {
954 NV_STATUS status;
955 RsClient *pClient;
956 RsResourceRef *pMappableRef;
957 RsCpuMapping *pCpuMapping;
958 Device *pDevice;
959 Subdevice *pSubdevice;
960 NvU32 gpuMask = 0;
961
962 status = serverAcquireClient(&g_resServ, hClient, LOCK_ACCESS_WRITE, &pClient);
963 if (status != NV_OK)
964 return status;
965
966 status = deviceGetByHandle(pClient, hDevice, &pDevice);
967 if (status != NV_OK)
968 {
969 status = subdeviceGetByHandle(pClient, hDevice, &pSubdevice);
970 if (status != NV_OK)
971 goto done;
972
973 status = rmGpuGroupLockAcquire(pSubdevice->subDeviceInst,
974 GPU_LOCK_GRP_SUBDEVICE,
975 GPUS_LOCK_FLAGS_NONE,
976 RM_LOCK_MODULES_GPU,
977 &gpuMask);
978 if (status != NV_OK)
979 goto done;
980
981 GPU_RES_SET_THREAD_BC_STATE(pSubdevice);
982 }
983 else
984 {
985 status = rmGpuGroupLockAcquire(pDevice->deviceInst,
986 GPU_LOCK_GRP_DEVICE,
987 GPUS_LOCK_FLAGS_NONE,
988 RM_LOCK_MODULES_GPU,
989 &gpuMask);
990 if (status != NV_OK)
991 goto done;
992
993 GPU_RES_SET_THREAD_BC_STATE(pDevice);
994 }
995
996 status = clientGetResourceRef(pClient, hMappable, &pMappableRef);
997 if (status != NV_OK)
998 goto done;
999
1000 if ((objDynamicCastById(pMappableRef->pResource, classId(Memory)) == NULL) &&
1001 (objDynamicCastById(pMappableRef->pResource, classId(KernelChannel)) == NULL))
1002 {
1003 status = NV_ERR_INVALID_OBJECT_HANDLE;
1004 goto done;
1005 }
1006
1007 status = refFindCpuMappingWithFilter(pMappableRef,
1008 NV_PTR_TO_NvP64(pOldCpuAddress),
1009 serverutilMappingFilterCurrentUserProc,
1010 &pCpuMapping);
1011 if (status != NV_OK)
1012 goto done;
1013
1014 pCpuMapping->pLinearAddress = NV_PTR_TO_NvP64(pNewCpuAddress);
1015
1016 done:
1017
1018 if (gpuMask != 0)
1019 rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE);
1020
1021 serverReleaseClient(&g_resServ, LOCK_ACCESS_WRITE, pClient);
1022 return status;
1023 }
1024
RmPerformVersionCheck(void * pData,NvU32 dataSize)1025 static NV_STATUS RmPerformVersionCheck(
1026 void *pData,
1027 NvU32 dataSize
1028 )
1029 {
1030 nv_ioctl_rm_api_version_t *pParams;
1031 char clientCh, rmCh;
1032 const char *rmStr = NV_VERSION_STRING;
1033 NvBool relaxed = NV_FALSE;
1034 NvU32 i;
1035
1036 //
1037 // rmStr (i.e., NV_VERSION_STRING) must be null-terminated and fit within
1038 // NV_RM_API_VERSION_STRING_LENGTH, so that:
1039 //
1040 // (1) If the versions don't match, we can return rmStr in
1041 // pParams->versionString.
1042 // (2) The below loop is guaranteed to not overrun rmStr.
1043 //
1044 ct_assert(sizeof(NV_VERSION_STRING) <= NV_RM_API_VERSION_STRING_LENGTH);
1045
1046 if (dataSize != sizeof(nv_ioctl_rm_api_version_t))
1047 return NV_ERR_INVALID_ARGUMENT;
1048
1049 pParams = pData;
1050
1051 //
1052 // write the reply value, so that the client knows we recognized
1053 // the request
1054 //
1055 pParams->reply = NV_RM_API_VERSION_REPLY_RECOGNIZED;
1056
1057 //
1058 // the client is just querying the version, not verifying against expected.
1059 //
1060 if (pParams->cmd == NV_RM_API_VERSION_CMD_QUERY)
1061 {
1062 os_string_copy(pParams->versionString, rmStr);
1063 return NV_OK;
1064 }
1065
1066 //
1067 // the client requested relaxed version checking; we will only
1068 // compare the strings until the first decimal point.
1069 //
1070 if (pParams->cmd == NV_RM_API_VERSION_CMD_RELAXED)
1071 {
1072 relaxed = NV_TRUE;
1073 }
1074
1075 for (i = 0; i < NV_RM_API_VERSION_STRING_LENGTH; i++)
1076 {
1077 clientCh = pParams->versionString[i];
1078 rmCh = rmStr[i];
1079
1080 //
1081 // fail if the current character is not the same
1082 //
1083 if (clientCh != rmCh)
1084 {
1085 break;
1086 }
1087
1088 //
1089 // if relaxed matching was requested, succeed when we find the
1090 // first decimal point
1091 //
1092 if ((relaxed) && (clientCh == '.'))
1093 {
1094 return NV_OK;
1095 }
1096
1097 //
1098 // we found the end of the strings: succeed
1099 //
1100 if (clientCh == '\0')
1101 {
1102 return NV_OK;
1103 }
1104 }
1105
1106 //
1107 // the version strings did not match: print an error message and
1108 // copy the RM's version string into pParams->versionString, so
1109 // that the client can report the mismatch; explicitly NULL
1110 // terminate the client's string, since we cannot trust it
1111 //
1112 pParams->versionString[NV_RM_API_VERSION_STRING_LENGTH - 1] = '\0';
1113
1114 nv_printf(NV_DBG_ERRORS,
1115 "NVRM: API mismatch: the client has the version %s, but\n"
1116 "NVRM: this kernel module has the version %s. Please\n"
1117 "NVRM: make sure that this kernel module and all NVIDIA driver\n"
1118 "NVRM: components have the same version.\n",
1119 pParams->versionString, NV_VERSION_STRING);
1120
1121 os_string_copy(pParams->versionString, rmStr);
1122
1123 return NV_ERR_GENERIC;
1124 }
1125
1126 //
1127 // Check if the NVPCF _DSM functions are implemented under
1128 // NVPCF scope or GPU device scope.
1129 // As part of RM initialisation this function checks the
1130 // support of NVPCF _DSM function implementation under
1131 // NVPCF scope, in case that fails, clear the cached DSM
1132 // support status and retry the NVPCF _DSM function under
1133 // GPU scope.
1134 //
RmCheckNvpcfDsmScope(OBJGPU * pGpu)1135 static void RmCheckNvpcfDsmScope(
1136 OBJGPU *pGpu
1137 )
1138 {
1139 NvU32 supportedFuncs = 0;
1140 NvU16 dsmDataSize = sizeof(supportedFuncs);
1141 nv_state_t *nv = NV_GET_NV_STATE(pGpu);
1142 ACPI_DSM_FUNCTION acpiDsmFunction = ACPI_DSM_FUNCTION_NVPCF_2X;
1143 NvU32 acpiDsmSubFunction = NVPCF0100_CTRL_CONFIG_DSM_2X_FUNC_GET_SUPPORTED;
1144
1145 nv->nvpcf_dsm_in_gpu_scope = NV_FALSE;
1146
1147 if ((osCallACPI_DSM(pGpu, acpiDsmFunction, acpiDsmSubFunction,
1148 &supportedFuncs, &dsmDataSize) != NV_OK) ||
1149 (FLD_TEST_DRF(PCF0100, _CTRL_CONFIG_DSM,
1150 _FUNC_GET_SUPPORTED_IS_SUPPORTED, _NO, supportedFuncs)) ||
1151 (dsmDataSize != sizeof(supportedFuncs)))
1152 {
1153 nv->nvpcf_dsm_in_gpu_scope = NV_TRUE;
1154
1155 // clear cached DSM function status
1156 uncacheDsmFuncStatus(pGpu, acpiDsmFunction, acpiDsmSubFunction);
1157 }
1158 }
1159
RmPowerSourceChangeEvent(nv_state_t * pNv,NvU32 event_val)1160 NV_STATUS RmPowerSourceChangeEvent(
1161 nv_state_t *pNv,
1162 NvU32 event_val
1163 )
1164 {
1165 NV2080_CTRL_PERF_SET_POWERSTATE_PARAMS params = {0};
1166 RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL);
1167
1168 params.powerStateInfo.powerState = event_val ? NV2080_CTRL_PERF_POWER_SOURCE_BATTERY :
1169 NV2080_CTRL_PERF_POWER_SOURCE_AC;
1170
1171 return pRmApi->Control(pRmApi, pNv->rmapi.hClient,
1172 pNv->rmapi.hSubDevice,
1173 NV2080_CTRL_CMD_PERF_SET_POWERSTATE,
1174 ¶ms, sizeof(params));
1175 }
1176
1177 /*!
1178 * @brief Function to request latest D-Notifier status from SBIOS.
1179 *
1180 * Handle certain scenarios (like a fresh boot or suspend/resume
1181 * of the system) when RM is not available to receive the Dx notifiers.
1182 * This function gets the latest D-Notifier status from SBIOS
1183 * when RM is ready to receive and handle those events.
1184 * Use GPS_FUNC_REQUESTDXSTATE subfunction to invoke current Dx state.
1185 *
1186 * @param[in] pNv nv_state_t pointer.
1187 */
RmRequestDNotifierState(nv_state_t * pNv)1188 void RmRequestDNotifierState(
1189 nv_state_t *pNv
1190 )
1191 {
1192 OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv);
1193 NvU32 supportedFuncs = 0;
1194 NvU16 dsmDataSize = sizeof(supportedFuncs);
1195 NV_STATUS status = NV_OK;
1196
1197 status = osCallACPI_DSM(pGpu, ACPI_DSM_FUNCTION_GPS_2X,
1198 GPS_FUNC_REQUESTDXSTATE, &supportedFuncs,
1199 &dsmDataSize);
1200 if (status != NV_OK)
1201 {
1202 //
1203 // Call for 'GPS_FUNC_REQUESTDXSTATE' subfunction may fail if the
1204 // SBIOS/EC does not have the corresponding implementation.
1205 //
1206 NV_PRINTF(LEVEL_INFO,
1207 "%s: Failed to request Dx event update, status 0x%x\n",
1208 __FUNCTION__, status);
1209 }
1210 }
1211
1212 /*!
1213 * @brief Deal with D-notifier events to apply a performance
1214 * level based on the requested auxiliary power-state.
1215 * Read confluence page "D-Notifiers on Linux" for more details.
1216 *
1217 * @param[in] pNv nv_state_t pointer.
1218 * @param[in] event_type NvU32 Event type.
1219 */
RmHandleDNotifierEvent(nv_state_t * pNv,NvU32 event_type)1220 static void RmHandleDNotifierEvent(
1221 nv_state_t *pNv,
1222 NvU32 event_type
1223 )
1224 {
1225 NV2080_CTRL_PERF_SET_AUX_POWER_STATE_PARAMS params = { 0 };
1226 RM_API *pRmApi;
1227 THREAD_STATE_NODE threadState;
1228 NV_STATUS rmStatus = NV_OK;
1229
1230 switch (event_type)
1231 {
1232 case ACPI_NOTIFY_POWER_LEVEL_D1:
1233 params.powerState = NV2080_CTRL_PERF_AUX_POWER_STATE_P0;
1234 break;
1235 case ACPI_NOTIFY_POWER_LEVEL_D2:
1236 params.powerState = NV2080_CTRL_PERF_AUX_POWER_STATE_P1;
1237 break;
1238 case ACPI_NOTIFY_POWER_LEVEL_D3:
1239 params.powerState = NV2080_CTRL_PERF_AUX_POWER_STATE_P2;
1240 break;
1241 case ACPI_NOTIFY_POWER_LEVEL_D4:
1242 params.powerState = NV2080_CTRL_PERF_AUX_POWER_STATE_P3;
1243 break;
1244 case ACPI_NOTIFY_POWER_LEVEL_D5:
1245 params.powerState = NV2080_CTRL_PERF_AUX_POWER_STATE_P4;
1246 break;
1247 default:
1248 return;
1249 }
1250
1251 pRmApi = RmUnixRmApiPrologue(pNv, &threadState, RM_LOCK_MODULES_ACPI);
1252 if (pRmApi == NULL)
1253 {
1254 return;
1255 }
1256
1257 rmStatus = pRmApi->Control(pRmApi, pNv->rmapi.hClient,
1258 pNv->rmapi.hSubDevice,
1259 NV2080_CTRL_CMD_PERF_SET_AUX_POWER_STATE,
1260 ¶ms, sizeof(params));
1261
1262 RmUnixRmApiEpilogue(pNv, &threadState);
1263
1264 if (rmStatus != NV_OK)
1265 {
1266 NV_PRINTF(LEVEL_ERROR,
1267 "%s: Failed to handle ACPI D-Notifier event, status=0x%x\n",
1268 __FUNCTION__, rmStatus);
1269 }
1270 }
1271
1272 static NV_STATUS
RmDmabufVerifyMemHandle(OBJGPU * pGpu,NvHandle hSrcClient,NvHandle hMemory,NvU64 offset,NvU64 size,void * pGpuInstanceInfo,MEMORY_DESCRIPTOR ** ppMemDesc)1273 RmDmabufVerifyMemHandle(
1274 OBJGPU *pGpu,
1275 NvHandle hSrcClient,
1276 NvHandle hMemory,
1277 NvU64 offset,
1278 NvU64 size,
1279 void *pGpuInstanceInfo,
1280 MEMORY_DESCRIPTOR **ppMemDesc
1281 )
1282 {
1283 NV_STATUS status;
1284 RsClient *pClient = NULL;
1285 RsResourceRef *pSrcMemoryRef = NULL;
1286 Memory *pSrcMemory = NULL;
1287 MEMORY_DESCRIPTOR *pMemDesc = NULL;
1288
1289 NV_ASSERT_OK_OR_RETURN(serverGetClientUnderLock(&g_resServ, hSrcClient, &pClient));
1290
1291 status = clientGetResourceRef(pClient, hMemory, &pSrcMemoryRef);
1292 if (status != NV_OK)
1293 {
1294 return status;
1295 }
1296
1297 pSrcMemory = dynamicCast(pSrcMemoryRef->pResource, Memory);
1298 if (pSrcMemory == NULL)
1299 {
1300 return NV_ERR_INVALID_OBJECT;
1301 }
1302
1303 pMemDesc = pSrcMemory->pMemDesc;
1304
1305 if (pGpuInstanceInfo != NULL)
1306 {
1307 KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance;
1308 pKernelMIGGpuInstance = (KERNEL_MIG_GPU_INSTANCE *) pGpuInstanceInfo;
1309
1310 if ((pKernelMIGGpuInstance->pMemoryPartitionHeap != pSrcMemory->pHeap))
1311 {
1312 return NV_ERR_INVALID_OBJECT_PARENT;
1313 }
1314 }
1315
1316 // Check if hMemory belongs to the same pGpu
1317 if ((pMemDesc->pGpu != pGpu) &&
1318 (pSrcMemory->pGpu != pGpu))
1319 {
1320 return NV_ERR_INVALID_OBJECT_PARENT;
1321 }
1322
1323 // Offset and size must be aligned to OS page-size
1324 if (!NV_IS_ALIGNED64(offset, os_page_size) ||
1325 !NV_IS_ALIGNED64(size, os_page_size))
1326 {
1327 return NV_ERR_INVALID_ARGUMENT;
1328 }
1329
1330 // Only supported for vidmem handles
1331 if (memdescGetAddressSpace(pMemDesc) != ADDR_FBMEM)
1332 {
1333 return NV_ERR_INVALID_ARGUMENT;
1334 }
1335
1336 if ((size == 0) ||
1337 (size > memdescGetSize(pMemDesc)) ||
1338 (offset > (memdescGetSize(pMemDesc) - size)))
1339 {
1340 return NV_ERR_INVALID_ARGUMENT;
1341 }
1342
1343 *ppMemDesc = pMemDesc;
1344
1345 return NV_OK;
1346 }
1347
1348 static NV_STATUS
RmDmabufGetParentDevice(OBJGPU * pGpu,NvHandle hClient,NvHandle hMemory,Device ** ppDevice)1349 RmDmabufGetParentDevice(
1350 OBJGPU *pGpu,
1351 NvHandle hClient,
1352 NvHandle hMemory,
1353 Device **ppDevice
1354 )
1355 {
1356 RsClient *pClient;
1357 RsResourceRef *pDeviceRef;
1358 RsResourceRef *pMemoryRef;
1359
1360 NV_CHECK_OK_OR_RETURN(LEVEL_ERROR,
1361 serverGetClientUnderLock(&g_resServ, hClient, &pClient));
1362
1363 NV_CHECK_OK_OR_RETURN(LEVEL_ERROR,
1364 clientGetResourceRef(pClient, hMemory, &pMemoryRef));
1365
1366 NV_CHECK_OK_OR_RETURN(LEVEL_ERROR,
1367 refFindAncestorOfType(pMemoryRef, classId(Device), &pDeviceRef));
1368
1369 *ppDevice = dynamicCast(pDeviceRef->pResource, Device);
1370
1371 return NV_OK;
1372 }
1373
1374 static NV_STATUS
RmDmabufGetClientAndDevice(OBJGPU * pGpu,NvHandle hClient,NvHandle hMemory,NvHandle * phClient,NvHandle * phDevice,NvHandle * phSubdevice,void ** ppGpuInstanceInfo)1375 RmDmabufGetClientAndDevice(
1376 OBJGPU *pGpu,
1377 NvHandle hClient,
1378 NvHandle hMemory,
1379 NvHandle *phClient,
1380 NvHandle *phDevice,
1381 NvHandle *phSubdevice,
1382 void **ppGpuInstanceInfo
1383 )
1384 {
1385 MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu);
1386
1387 if (IS_MIG_ENABLED(pGpu))
1388 {
1389 NV_STATUS status;
1390 MIG_INSTANCE_REF ref;
1391 Device *pParentDevice;
1392 KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu);
1393
1394 status = RmDmabufGetParentDevice(pGpu, hClient, hMemory,
1395 &pParentDevice);
1396 if (status != NV_OK)
1397 {
1398 return status;
1399 }
1400
1401 status = kmigmgrGetInstanceRefFromDevice(pGpu, pKernelMIGManager,
1402 pParentDevice, &ref);
1403 if (status != NV_OK)
1404 {
1405 return status;
1406 }
1407
1408 status = kmigmgrIncRefCount(ref.pKernelMIGGpuInstance->pShare);
1409 if (status != NV_OK)
1410 {
1411 return status;
1412 }
1413
1414 *phClient = ref.pKernelMIGGpuInstance->instanceHandles.hClient;
1415 *phDevice = ref.pKernelMIGGpuInstance->instanceHandles.hDevice;
1416 *phSubdevice = ref.pKernelMIGGpuInstance->instanceHandles.hSubdevice;
1417 *ppGpuInstanceInfo = (void *) ref.pKernelMIGGpuInstance;
1418
1419 return NV_OK;
1420 }
1421
1422 *phClient = pMemoryManager->hClient;
1423 *phDevice = pMemoryManager->hDevice;
1424 *phSubdevice = pMemoryManager->hSubdevice;
1425 *ppGpuInstanceInfo = NULL;
1426
1427 return NV_OK;
1428 }
1429
1430 static void
RmDmabufPutClientAndDevice(OBJGPU * pGpu,NvHandle hClient,NvHandle hDevice,NvHandle hSubdevice,void * pGpuInstanceInfo)1431 RmDmabufPutClientAndDevice(
1432 OBJGPU *pGpu,
1433 NvHandle hClient,
1434 NvHandle hDevice,
1435 NvHandle hSubdevice,
1436 void *pGpuInstanceInfo
1437 )
1438 {
1439 KERNEL_MIG_GPU_INSTANCE *pKernelMIGGpuInstance;
1440
1441 if (pGpuInstanceInfo == NULL)
1442 {
1443 return;
1444 }
1445
1446 pKernelMIGGpuInstance = (KERNEL_MIG_GPU_INSTANCE *) pGpuInstanceInfo;
1447
1448 NV_ASSERT_OK(kmigmgrDecRefCount(pKernelMIGGpuInstance->pShare));
1449 }
1450
RmP2PDmaMapPagesCoherent(nv_dma_device_t * peer,NvU64 pageSize,NvU32 pageCount,NvU64 * pDmaAddresses,void ** ppPriv)1451 static NV_STATUS RmP2PDmaMapPagesCoherent(
1452 nv_dma_device_t *peer,
1453 NvU64 pageSize,
1454 NvU32 pageCount,
1455 NvU64 *pDmaAddresses,
1456 void **ppPriv
1457 )
1458 {
1459 NV_STATUS status;
1460 NvU64 *pOsDmaAddresses = NULL;
1461 NvU32 osPagesPerP2PPage, osPageCount, count;
1462 NvBool bDmaMapped = NV_FALSE;
1463 NvU32 i, j, index;
1464
1465 NV_ASSERT_OR_RETURN((pageSize >= os_page_size), NV_ERR_INVALID_ARGUMENT);
1466
1467 if (pageSize == os_page_size)
1468 {
1469 return nv_dma_map_alloc(peer, pageCount, pDmaAddresses, NV_FALSE, ppPriv);
1470 }
1471
1472 //
1473 // If P2P page_size returned from nvidia_p2p_get_pages is bigger than
1474 // OS page size, the page array need to be inflated to correctly do the DMA mapping.
1475 // For example, if page_size = 64K and OS page size = 4K,
1476 // there are 16 OS pages to this 64K P2P page.
1477 //
1478
1479 osPagesPerP2PPage = pageSize / os_page_size;
1480 osPageCount = osPagesPerP2PPage * pageCount;
1481
1482 status = os_alloc_mem((void **)&pOsDmaAddresses,
1483 (osPageCount * sizeof(NvU64)));
1484 if (status != NV_OK)
1485 {
1486 goto failed;
1487 }
1488
1489 index = 0;
1490 for (i = 0; i < pageCount; i++)
1491 {
1492 pOsDmaAddresses[index] = pDmaAddresses[i];
1493 index++;
1494
1495 for (j = 1; j < osPagesPerP2PPage; j++)
1496 {
1497 pOsDmaAddresses[index] = pOsDmaAddresses[index - 1] + os_page_size;
1498 index++;
1499 }
1500 }
1501
1502 status = nv_dma_map_alloc(peer, osPageCount, pOsDmaAddresses, NV_FALSE, ppPriv);
1503 if (status != NV_OK)
1504 {
1505 goto failed;
1506 }
1507 bDmaMapped = NV_TRUE;
1508
1509 //
1510 // The driver breaks down the size into submaps and dma-maps those individually.
1511 // This may result in non-contiguous IOVA segments allocated to each submap.
1512 // We check for OS page contiguity within the bigger pageSize since we need to
1513 // return IOVA chunks at pageSize granularity.
1514 //
1515 count = 0;
1516 for (i = 1; i < osPageCount; i++)
1517 {
1518 count++;
1519 if (count == osPagesPerP2PPage)
1520 {
1521 count = 0;
1522 continue;
1523 }
1524
1525 if (pOsDmaAddresses[i] != (pOsDmaAddresses[i - 1] + os_page_size))
1526 {
1527 status = NV_ERR_INVALID_STATE;
1528 goto failed;
1529 }
1530 }
1531
1532 //
1533 // Fill pDmaAddresses at pageSize granularity
1534 // from expanded pOsDmaAddresses.
1535 //
1536 index = 0;
1537 for (i = 0; i < pageCount; i++)
1538 {
1539 pDmaAddresses[i] = pOsDmaAddresses[index];
1540 index += osPagesPerP2PPage;
1541 }
1542
1543 os_free_mem(pOsDmaAddresses);
1544
1545 return NV_OK;
1546
1547 failed:
1548 if (bDmaMapped)
1549 {
1550 NV_ASSERT_OK(nv_dma_unmap_alloc(peer, osPageCount,
1551 pOsDmaAddresses, ppPriv));
1552 }
1553
1554 if (pOsDmaAddresses != NULL)
1555 {
1556 os_free_mem(pOsDmaAddresses);
1557 }
1558
1559 return status;
1560 }
1561
1562 static void
RmHandleNvpcfEvents(nv_state_t * pNv)1563 RmHandleNvpcfEvents(
1564 nv_state_t *pNv
1565 )
1566 {
1567 OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv);
1568 THREAD_STATE_NODE threadState;
1569
1570 if (RmUnixRmApiPrologue(pNv, &threadState, RM_LOCK_MODULES_ACPI) == NULL)
1571 {
1572 return;
1573 }
1574
1575 gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_NVPCF_EVENTS, NULL, 0, 0, 0);
1576
1577 RmUnixRmApiEpilogue(pNv, &threadState);
1578 }
1579
1580 /*
1581 * ---------------------------------------------------------------------------
1582 *
1583 * The routines below are part of the interface between the kernel interface
1584 * layer and the kernel-agnostic portions of the resource manager.
1585 *
1586 * ---------------------------------------------------------------------------
1587 */
1588
rm_init_private_state(nvidia_stack_t * sp,nv_state_t * pNv)1589 NvBool NV_API_CALL rm_init_private_state(
1590 nvidia_stack_t *sp,
1591 nv_state_t *pNv
1592 )
1593 {
1594 NvBool retval;
1595 void *fp;
1596
1597 NV_ENTER_RM_RUNTIME(sp,fp);
1598
1599 retval = RmInitPrivateState(pNv);
1600
1601 NV_EXIT_RM_RUNTIME(sp,fp);
1602
1603 return retval;
1604 }
1605
rm_free_private_state(nvidia_stack_t * sp,nv_state_t * pNv)1606 void NV_API_CALL rm_free_private_state(
1607 nvidia_stack_t *sp,
1608 nv_state_t *pNv
1609 )
1610 {
1611 void *fp;
1612
1613 NV_ENTER_RM_RUNTIME(sp,fp);
1614
1615 RmFreePrivateState(pNv);
1616
1617 NV_EXIT_RM_RUNTIME(sp,fp);
1618 }
1619
rm_init_adapter(nvidia_stack_t * sp,nv_state_t * pNv)1620 NvBool NV_API_CALL rm_init_adapter(
1621 nvidia_stack_t *sp,
1622 nv_state_t *pNv
1623 )
1624 {
1625 THREAD_STATE_NODE threadState;
1626 NvBool retval = NV_FALSE;
1627 void *fp;
1628 NvBool bEnabled;
1629
1630 NV_ENTER_RM_RUNTIME(sp,fp);
1631 threadStateInit(&threadState, THREAD_STATE_FLAGS_DEVICE_INIT);
1632
1633 // LOCK: acquire API lock
1634 if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_INIT) == NV_OK)
1635 {
1636 if (!((gpumgrQueryGpuDrainState(pNv->gpu_id, &bEnabled, NULL) == NV_OK)
1637 && bEnabled))
1638 {
1639 if (pNv->flags & NV_FLAG_PERSISTENT_SW_STATE)
1640 {
1641 retval = RmPartiallyInitAdapter(pNv);
1642 }
1643 else
1644 {
1645 retval = RmInitAdapter(pNv);
1646 }
1647 }
1648
1649 // UNLOCK: release API lock
1650 rmapiLockRelease();
1651 }
1652
1653 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
1654 NV_EXIT_RM_RUNTIME(sp,fp);
1655
1656 return retval;
1657 }
1658
rm_disable_adapter(nvidia_stack_t * sp,nv_state_t * pNv)1659 void NV_API_CALL rm_disable_adapter(
1660 nvidia_stack_t *sp,
1661 nv_state_t *pNv
1662 )
1663 {
1664 THREAD_STATE_NODE threadState;
1665 void *fp;
1666
1667 NV_ENTER_RM_RUNTIME(sp,fp);
1668 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
1669
1670 NV_ASSERT_OK(os_flush_work_queue(pNv->queue));
1671
1672 // LOCK: acquire API lock
1673 if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DESTROY) == NV_OK)
1674 {
1675 if (pNv->flags & NV_FLAG_PERSISTENT_SW_STATE)
1676 {
1677 RmPartiallyDisableAdapter(pNv);
1678 }
1679 else
1680 {
1681 RmDisableAdapter(pNv);
1682 }
1683
1684 // UNLOCK: release API lock
1685 rmapiLockRelease();
1686 }
1687
1688 NV_ASSERT_OK(os_flush_work_queue(pNv->queue));
1689 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
1690 NV_EXIT_RM_RUNTIME(sp,fp);
1691 }
1692
rm_shutdown_adapter(nvidia_stack_t * sp,nv_state_t * pNv)1693 void NV_API_CALL rm_shutdown_adapter(
1694 nvidia_stack_t *sp,
1695 nv_state_t *pNv
1696 )
1697 {
1698 THREAD_STATE_NODE threadState;
1699 void *fp;
1700
1701 NV_ENTER_RM_RUNTIME(sp,fp);
1702 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
1703
1704 // LOCK: acquire API lock
1705 if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DESTROY) == NV_OK)
1706 {
1707 RmShutdownAdapter(pNv);
1708
1709 // UNLOCK: release API lock
1710 rmapiLockRelease();
1711 }
1712
1713 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
1714 NV_EXIT_RM_RUNTIME(sp,fp);
1715 }
1716
rm_exclude_adapter(nvidia_stack_t * sp,nv_state_t * pNv)1717 NV_STATUS NV_API_CALL rm_exclude_adapter(
1718 nvidia_stack_t *sp,
1719 nv_state_t *pNv
1720 )
1721 {
1722 NV_STATUS rmStatus;
1723 THREAD_STATE_NODE threadState;
1724 void *fp;
1725
1726 NV_ENTER_RM_RUNTIME(sp,fp);
1727 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
1728
1729 rmStatus = RmExcludeAdapter(pNv);
1730
1731 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
1732 NV_EXIT_RM_RUNTIME(sp,fp);
1733
1734 return rmStatus;
1735 }
1736
rm_acquire_api_lock(nvidia_stack_t * sp)1737 NV_STATUS NV_API_CALL rm_acquire_api_lock(
1738 nvidia_stack_t *sp
1739 )
1740 {
1741 THREAD_STATE_NODE threadState;
1742 NV_STATUS rmStatus;
1743 void *fp;
1744
1745 NV_ENTER_RM_RUNTIME(sp,fp);
1746 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
1747
1748 // LOCK: acquire API lock
1749 rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI);
1750
1751 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
1752 NV_EXIT_RM_RUNTIME(sp,fp);
1753
1754 return rmStatus;
1755 }
1756
rm_release_api_lock(nvidia_stack_t * sp)1757 NV_STATUS NV_API_CALL rm_release_api_lock(
1758 nvidia_stack_t *sp
1759 )
1760 {
1761 THREAD_STATE_NODE threadState;
1762 void *fp;
1763
1764 NV_ENTER_RM_RUNTIME(sp,fp);
1765 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
1766
1767 // UNLOCK: release API lock
1768 rmapiLockRelease();
1769
1770 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
1771 NV_EXIT_RM_RUNTIME(sp,fp);
1772
1773 return NV_OK;
1774 }
1775
rm_acquire_gpu_lock(nvidia_stack_t * sp,nv_state_t * nv)1776 NV_STATUS NV_API_CALL rm_acquire_gpu_lock(
1777 nvidia_stack_t *sp,
1778 nv_state_t *nv
1779 )
1780 {
1781 THREAD_STATE_NODE threadState;
1782 NV_STATUS rmStatus;
1783 void *fp;
1784
1785 NV_ENTER_RM_RUNTIME(sp,fp);
1786 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
1787
1788 // LOCK: acquire GPU lock
1789 rmStatus = rmDeviceGpuLocksAcquire(NV_GET_NV_PRIV_PGPU(nv),
1790 GPUS_LOCK_FLAGS_NONE,
1791 RM_LOCK_MODULES_OSAPI);
1792
1793 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
1794 NV_EXIT_RM_RUNTIME(sp,fp);
1795
1796 return rmStatus;
1797 }
1798
rm_release_gpu_lock(nvidia_stack_t * sp,nv_state_t * nv)1799 NV_STATUS NV_API_CALL rm_release_gpu_lock(
1800 nvidia_stack_t *sp,
1801 nv_state_t *nv
1802 )
1803 {
1804 THREAD_STATE_NODE threadState;
1805 void *fp;
1806
1807 NV_ENTER_RM_RUNTIME(sp,fp);
1808 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
1809
1810 // UNLOCK: release GPU lock
1811 rmDeviceGpuLocksRelease(NV_GET_NV_PRIV_PGPU(nv), GPUS_LOCK_FLAGS_NONE, NULL);
1812
1813 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
1814 NV_EXIT_RM_RUNTIME(sp,fp);
1815
1816 return NV_OK;
1817 }
1818
rm_acquire_all_gpus_lock(nvidia_stack_t * sp)1819 NV_STATUS NV_API_CALL rm_acquire_all_gpus_lock(
1820 nvidia_stack_t *sp
1821 )
1822 {
1823 THREAD_STATE_NODE threadState;
1824 NV_STATUS rmStatus;
1825 void *fp;
1826
1827 NV_ENTER_RM_RUNTIME(sp,fp);
1828 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
1829
1830 // LOCK: acquire all GPUs lock
1831 rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI);
1832
1833 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
1834 NV_EXIT_RM_RUNTIME(sp,fp);
1835
1836 return rmStatus;
1837 }
1838
rm_release_all_gpus_lock(nvidia_stack_t * sp)1839 NV_STATUS NV_API_CALL rm_release_all_gpus_lock(
1840 nvidia_stack_t *sp
1841 )
1842 {
1843 THREAD_STATE_NODE threadState;
1844 void *fp;
1845
1846 NV_ENTER_RM_RUNTIME(sp,fp);
1847 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
1848
1849 // UNLOCK: release all GPUs lock
1850 rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL);
1851
1852 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
1853 NV_EXIT_RM_RUNTIME(sp,fp);
1854
1855 return NV_OK;
1856 }
1857
1858 /*!
1859 * @brief Handle ACPI_NOTIFY_GPS_STATUS_CHANGE event.
1860 *
1861 * This function is called for GPS when SBIOS trigger
1862 * gps STATUS_CHANGE event, which calls rm control call
1863 * NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL to init the GPS
1864 * data from SBIOS.
1865 */
RmHandleGPSStatusChange(nv_state_t * pNv)1866 static void RmHandleGPSStatusChange
1867 (
1868 nv_state_t *pNv
1869 )
1870 {
1871 NV_STATUS rmStatus;
1872 RM_API *pRmApi;
1873 THREAD_STATE_NODE threadState;
1874 NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS gpsControl = { 0 };
1875
1876 pRmApi = RmUnixRmApiPrologue(pNv, &threadState, RM_LOCK_MODULES_ACPI);
1877 if (pRmApi == NULL)
1878 {
1879 return;
1880 }
1881
1882 gpsControl.command = NV0000_CTRL_CMD_SYSTEM_GPS_DATA_INIT_USING_SBIOS_AND_ACK;
1883 gpsControl.locale = NV0000_CTRL_CMD_SYSTEM_GPS_LOCALE_SYSTEM;
1884
1885 //
1886 // NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL is not a subdevice command.
1887 // But, Inside GPS module, the first GPU, which has GPS
1888 // enabled will be grabbed with GPU manager. The RMAPI_API_LOCK_INTERNAL
1889 // will internally grab the GPU locks and wake-up all the GPUs. Ideally
1890 // this control call should be GPU specific command, if internally
1891 // it uses the GPU.
1892 //
1893 rmStatus = pRmApi->Control(pRmApi,
1894 pNv->rmapi.hClient,
1895 pNv->rmapi.hClient,
1896 NV0000_CTRL_CMD_SYSTEM_GPS_CONTROL,
1897 (void *)&gpsControl,
1898 sizeof(NV0000_CTRL_SYSTEM_GPS_CONTROL_PARAMS));
1899
1900 RmUnixRmApiEpilogue(pNv, &threadState);
1901
1902 if (rmStatus != NV_OK)
1903 {
1904 NV_PRINTF(LEVEL_ERROR,
1905 "%s: Failed to handle ACPI GPS status change event, status=0x%x\n",
1906 __FUNCTION__, rmStatus);
1907 }
1908 }
1909
1910 /*!
1911 * @brief Function to handle device specific ACPI events.
1912 *
1913 * @param[in] sp nvidia_stack_t pointer.
1914 * @param[in] nv nv_state_t pointer.
1915 * @param[in] event_type NvU32 Event type.
1916 */
rm_acpi_notify(nvidia_stack_t * sp,nv_state_t * nv,NvU32 event_type)1917 void NV_API_CALL rm_acpi_notify(
1918 nvidia_stack_t *sp,
1919 nv_state_t *nv,
1920 NvU32 event_type
1921 )
1922 {
1923 void *fp;
1924 NV_ENTER_RM_RUNTIME(sp,fp);
1925
1926 switch (event_type)
1927 {
1928 case ACPI_VIDEO_NOTIFY_PROBE:
1929 {
1930 THREAD_STATE_NODE threadState;
1931
1932 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
1933 RmHandleDisplayChange(sp, nv);
1934 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
1935 break;
1936 }
1937
1938 case ACPI_NOTIFY_GPS_STATUS_CHANGE:
1939 RmHandleGPSStatusChange(nv);
1940 break;
1941
1942 case ACPI_NOTIFY_POWER_LEVEL_D1: /* fallthrough */
1943 case ACPI_NOTIFY_POWER_LEVEL_D2: /* fallthrough */
1944 case ACPI_NOTIFY_POWER_LEVEL_D3: /* fallthrough */
1945 case ACPI_NOTIFY_POWER_LEVEL_D4: /* fallthrough */
1946 case ACPI_NOTIFY_POWER_LEVEL_D5:
1947 RmHandleDNotifierEvent(nv, event_type);
1948 break;
1949
1950 default:
1951 NV_PRINTF(LEVEL_INFO, "No support for 0x%x event\n", event_type);
1952 NV_ASSERT(0);
1953 break;
1954 }
1955
1956 NV_EXIT_RM_RUNTIME(sp,fp);
1957 }
1958
nv_align_mmap_offset_length(nv_usermap_access_params_t * nvuap)1959 static void nv_align_mmap_offset_length(
1960 nv_usermap_access_params_t *nvuap)
1961 {
1962 NvU64 page_size = os_page_size;
1963 NvU64 end = nvuap->size + (nvuap->addr & (page_size - 1));
1964
1965 nvuap->mmap_start = NV_ALIGN_DOWN(nvuap->addr, page_size);
1966 nvuap->mmap_size = NV_ALIGN_UP(end, page_size);
1967 nvuap->offset = NV_ALIGN_DOWN(nvuap->offset, page_size);
1968 }
1969
RmGetArrayMinMax(NvU64 * array,NvU64 count,NvU64 * min,NvU64 * max)1970 static inline NV_STATUS RmGetArrayMinMax(
1971 NvU64 *array,
1972 NvU64 count,
1973 NvU64 *min,
1974 NvU64 *max
1975 )
1976 {
1977 NvU64 i;
1978
1979 if (array == NULL)
1980 {
1981 return NV_ERR_INVALID_ARGUMENT;
1982 }
1983
1984 *min = array[0];
1985 *max = array[0];
1986
1987 if (count == 1)
1988 return NV_OK;
1989
1990 for (i = 1; i < count; i++)
1991 {
1992 if (array[i] > *max)
1993 *max = array[i];
1994
1995 if (array[i] < *min)
1996 *min = array[i];
1997 }
1998
1999 return NV_OK;
2000 }
2001
RmSetUserMapAccessRange(nv_usermap_access_params_t * nvuap)2002 static NV_STATUS RmSetUserMapAccessRange(
2003 nv_usermap_access_params_t *nvuap
2004 )
2005 {
2006 NV_STATUS status = NV_OK;
2007
2008 if (nvuap->contig)
2009 {
2010 nvuap->access_start = nvuap->mmap_start;
2011 nvuap->access_size = nvuap->mmap_size;
2012 }
2013 else
2014 {
2015 NvU64 highest_address_mapped;
2016 NvU64 lowest_address_mapped;
2017
2018 status = RmGetArrayMinMax(nvuap->page_array, nvuap->num_pages,
2019 &lowest_address_mapped,
2020 &highest_address_mapped);
2021 if (status != NV_OK)
2022 {
2023 return status;
2024 }
2025
2026 nvuap->access_start = lowest_address_mapped;
2027 nvuap->access_size = (highest_address_mapped + os_page_size) - lowest_address_mapped;
2028 }
2029
2030 return status;
2031 }
2032
2033 static NV_STATUS RmGetAllocPrivate(RmClient *, NvU32, NvU64, NvU64, NvU32 *, void **,
2034 NvU64 *);
2035 static NV_STATUS RmValidateMmapRequest(nv_state_t *, NvU64, NvU64, NvU32 *);
2036
RmGetMmapPteArray(KernelMemorySystem * pKernelMemorySystem,RsClient * pClient,NvHandle hMemory,nv_usermap_access_params_t * nvuap)2037 static NV_STATUS RmGetMmapPteArray(
2038 KernelMemorySystem *pKernelMemorySystem,
2039 RsClient *pClient,
2040 NvHandle hMemory,
2041 nv_usermap_access_params_t *nvuap
2042 )
2043 {
2044 NV_STATUS status = NV_OK;
2045 NvU64 pages = 0;
2046 Memory *pMemory = NULL;
2047 PMEMORY_DESCRIPTOR pMemDesc = NULL;
2048 RsResourceRef *pResourceRef;
2049 NvU64 i;
2050 NvU64 *pteArray;
2051 NvU64 index;
2052
2053 if (nvuap == NULL)
2054 {
2055 return NV_ERR_INVALID_ARGUMENT;
2056 }
2057
2058 //
2059 // If we're mapping a memory handle, we can get the data from the
2060 // descriptor (required if the allocation being mapped is discontiguous).
2061 //
2062 if (clientGetResourceRef(pClient, hMemory, &pResourceRef) == NV_OK)
2063 {
2064 pMemory = dynamicCast(pResourceRef->pResource, Memory);
2065 if (pMemory != NULL)
2066 {
2067 pMemDesc = pMemory->pMemDesc;
2068 nvuap->contig = memdescGetContiguity(pMemDesc, AT_CPU);
2069 }
2070 }
2071
2072 //
2073 // In the discontiguous case, the page array needs to be large enough to hold
2074 // the 4K-page-sized addresses that we will then deflate to OS page addresses.
2075 // For the contiguous case, we can create the OS-page-sized addresses
2076 // directly in the array.
2077 //
2078 if (nvuap->contig)
2079 {
2080 pages = nvuap->mmap_size / os_page_size;
2081 }
2082 else
2083 {
2084 pages = nvuap->mmap_size / NV_RM_PAGE_SIZE;
2085 }
2086
2087 NV_ASSERT_OR_RETURN(pages != 0, NV_ERR_INVALID_ARGUMENT);
2088
2089 status = os_alloc_mem((void **)&nvuap->page_array, (pages * sizeof(NvU64)));
2090 if (status != NV_OK)
2091 {
2092 return status;
2093 }
2094
2095 if (!nvuap->contig)
2096 {
2097 pteArray = memdescGetPteArray(pMemDesc, AT_CPU);
2098 index = nvuap->offset / NV_RM_PAGE_SIZE;
2099
2100 //
2101 // We're guaranteed to have a MEMORY_DESCRIPTOR in the discontiguous
2102 // case. Copy over the addresses now.
2103 //
2104 portMemCopy((void *)nvuap->page_array,
2105 pages * sizeof(NvU64), (void *)&pteArray[index],
2106 pages * sizeof(NvU64));
2107
2108 if (NV_RM_PAGE_SIZE < os_page_size)
2109 {
2110 RmDeflateRmToOsPageArray(nvuap->page_array, pages);
2111 pages = NV_RM_PAGES_TO_OS_PAGES(pages);
2112 }
2113
2114 //
2115 // Convert the GPU physical addresses to system physical addresses,
2116 // if applicable.
2117 //
2118 for (i = 0; i < pages; i++)
2119 {
2120 nvuap->page_array[i] += pKernelMemorySystem->coherentCpuFbBase;
2121 }
2122 }
2123 else
2124 {
2125 // Offset is accounted in mmap_start.
2126 for (nvuap->page_array[0] = nvuap->mmap_start, i = 1;
2127 i < pages; i++)
2128 {
2129 nvuap->page_array[i] = nvuap->page_array[i-1] + os_page_size;
2130 }
2131 }
2132
2133 nvuap->num_pages = pages;
2134
2135 return status;
2136 }
2137
2138 /* Must be called with the API lock and the GPU locks */
RmCreateMmapContextLocked(RmClient * pRmClient,NvHandle hDevice,NvHandle hMemory,NvP64 address,NvU64 size,NvU64 offset,NvU32 cachingType,NvU32 fd)2139 static NV_STATUS RmCreateMmapContextLocked(
2140 RmClient *pRmClient,
2141 NvHandle hDevice,
2142 NvHandle hMemory,
2143 NvP64 address,
2144 NvU64 size,
2145 NvU64 offset,
2146 NvU32 cachingType,
2147 NvU32 fd
2148 )
2149 {
2150 NV_STATUS status = NV_OK;
2151 void *pAllocPriv = NULL;
2152 OBJGPU *pGpu = NULL;
2153 RsClient *pClient = staticCast(pRmClient, RsClient);
2154 KernelMemorySystem *pKernelMemorySystem = NULL;
2155 NvBool bCoherentAtsCpuOffset = NV_FALSE;
2156 NvBool bSriovHostCoherentFbOffset = NV_FALSE;
2157 nv_state_t *pNv = NULL;
2158 NvU64 addr = (NvU64)address;
2159 NvU32 prot = 0;
2160 NvU64 pageIndex = 0;
2161 nv_usermap_access_params_t *nvuap = NULL;
2162 NvBool bClientMap = (pClient->hClient == hDevice);
2163
2164 if (!bClientMap)
2165 {
2166 if (CliSetGpuContext(pClient->hClient, hDevice, &pGpu, NULL) != NV_OK)
2167 {
2168 Subdevice *pSubdevice;
2169
2170 status = subdeviceGetByHandle(pClient, hDevice, &pSubdevice);
2171 if (status != NV_OK)
2172 return status;
2173
2174 pGpu = GPU_RES_GET_GPU(pSubdevice);
2175
2176 GPU_RES_SET_THREAD_BC_STATE(pSubdevice);
2177 }
2178 }
2179
2180 status = os_alloc_mem((void**)&nvuap, sizeof(nv_usermap_access_params_t));
2181 if (status != NV_OK)
2182 {
2183 return status;
2184 }
2185
2186 portMemSet(nvuap, 0, sizeof(nv_usermap_access_params_t));
2187 nvuap->addr = addr;
2188 nvuap->size = size;
2189 nvuap->offset = offset;
2190 nvuap->caching = cachingType;
2191
2192 //
2193 // Assume the allocation is contiguous until RmGetMmapPteArray
2194 // determines otherwise.
2195 //
2196 nvuap->contig = NV_TRUE;
2197 nv_align_mmap_offset_length(nvuap);
2198
2199 if (pGpu != NULL)
2200 {
2201 pNv = NV_GET_NV_STATE(pGpu);
2202 pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu);
2203 bCoherentAtsCpuOffset = IS_COHERENT_CPU_ATS_OFFSET(pKernelMemorySystem, addr, size);
2204 bSriovHostCoherentFbOffset = os_is_vgx_hyper() &&
2205 IS_COHERENT_FB_OFFSET(pKernelMemorySystem, addr, size);
2206 }
2207
2208 //
2209 // If no device is given, or the address isn't in the given device's BARs,
2210 // validate this as a system memory mapping and associate it with the
2211 // control device.
2212 //
2213 if ((pNv == NULL) ||
2214 (!IS_REG_OFFSET(pNv, addr, size) &&
2215 !IS_FB_OFFSET(pNv, addr, size) &&
2216 !(bCoherentAtsCpuOffset || bSriovHostCoherentFbOffset) &&
2217 !IS_IMEM_OFFSET(pNv, addr, size)))
2218 {
2219 pNv = nv_get_ctl_state();
2220
2221 //
2222 // Validate the mapping request by looking up the underlying sysmem
2223 // allocation.
2224 //
2225 status = RmGetAllocPrivate(pRmClient, hMemory, addr, size, &prot, &pAllocPriv,
2226 &pageIndex);
2227
2228 if (status != NV_OK)
2229 {
2230 goto done;
2231 }
2232 }
2233 else
2234 {
2235 //
2236 // Validate the mapping request for ATS and get pteArray
2237 //
2238 if (bCoherentAtsCpuOffset)
2239 {
2240 status = RmGetMmapPteArray(pKernelMemorySystem, pClient, hMemory, nvuap);
2241 if (status != NV_OK)
2242 {
2243 goto done;
2244 }
2245 }
2246 else if (bSriovHostCoherentFbOffset)
2247 {
2248 status = RmGetMmapPteArray(pKernelMemorySystem, pClient, hMemory, nvuap);
2249 if (status != NV_OK)
2250 {
2251 goto done;
2252 }
2253
2254 //
2255 // nvuap->page_array(allocated in RmGetMmapPteArray) is not assigned
2256 // to nvamc->page_array if onlining status is false(which is the case with
2257 // bSriovHostCoherentFbOffset) and so doesn't get freed if not done here.
2258 // The call to RmGetMmapPteArray is for getting the contig and num
2259 // pages of the allocation.
2260 //
2261 os_free_mem(nvuap->page_array);
2262 nvuap->page_array = NULL;
2263
2264 //
2265 // This path is taken in the case of self-hosted SRIOV host where
2266 // the coherent GPU memory is not onlined but the CPU mapping to
2267 // the coherent GPU memory is done via C2C(instead of BAR1) and so
2268 // only contig can be supported for now.
2269 //
2270 if (!nvuap->contig && (nvuap->num_pages > 1))
2271 {
2272 NV_PRINTF(LEVEL_ERROR, "Mapping of Non-contig allocation for "
2273 "not onlined coherent GPU memory not supported\n");
2274 status = NV_ERR_NOT_SUPPORTED;
2275 goto done;
2276 }
2277 }
2278
2279 if (RmSetUserMapAccessRange(nvuap) != NV_OK)
2280 {
2281 goto done;
2282 }
2283
2284 status = nv_get_usermap_access_params(pNv, nvuap);
2285 if (status != NV_OK)
2286 {
2287 goto done;
2288 }
2289
2290 // Validate the mapping request for BAR's.
2291 status = RmValidateMmapRequest(pNv, nvuap->access_start,
2292 nvuap->access_size, &prot);
2293 if (status != NV_OK)
2294 {
2295 goto done;
2296 }
2297 }
2298
2299 status = nv_add_mapping_context_to_file(pNv, nvuap, prot, pAllocPriv,
2300 pageIndex, fd);
2301
2302 done:
2303 os_free_mem(nvuap);
2304 return status;
2305 }
2306
2307 // TODO: Bug 1802250: [uvm8] Use an alt stack in all functions in unix/src/osapi.c
rm_create_mmap_context(NvHandle hClient,NvHandle hDevice,NvHandle hMemory,NvP64 address,NvU64 size,NvU64 offset,NvU32 cachingType,NvU32 fd)2308 NV_STATUS rm_create_mmap_context(
2309 NvHandle hClient,
2310 NvHandle hDevice,
2311 NvHandle hMemory,
2312 NvP64 address,
2313 NvU64 size,
2314 NvU64 offset,
2315 NvU32 cachingType,
2316 NvU32 fd
2317 )
2318 {
2319 NV_STATUS rmStatus = NV_OK;
2320 // LOCK: acquire API lock
2321 if ((rmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_OSAPI)) == NV_OK)
2322 {
2323 RmClient *pRmClient;
2324
2325 if (NV_OK != serverutilAcquireClient(hClient, LOCK_ACCESS_READ, &pRmClient))
2326 {
2327 // UNLOCK: release API lock
2328 rmapiLockRelease();
2329 return NV_ERR_INVALID_CLIENT;
2330 }
2331
2332 if (pRmClient->ProcID != osGetCurrentProcess())
2333 {
2334 rmStatus = NV_ERR_INVALID_CLIENT;
2335 }
2336 // LOCK: acquire GPUs lock
2337 else if ((rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) == NV_OK)
2338 {
2339 rmStatus = RmCreateMmapContextLocked(pRmClient, hDevice,
2340 hMemory, address, size, offset,
2341 cachingType, fd);
2342 // UNLOCK: release GPUs lock
2343 rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL);
2344 }
2345
2346 serverutilReleaseClient(LOCK_ACCESS_READ, pRmClient);
2347
2348 // UNLOCK: release API lock
2349 rmapiLockRelease();
2350 }
2351
2352 return rmStatus;
2353 }
2354
RmGetAllocPrivate(RmClient * pRmClient,NvU32 hMemory,NvU64 offset,NvU64 length,NvU32 * pProtection,void ** ppPrivate,NvU64 * pPageIndex)2355 static NV_STATUS RmGetAllocPrivate(
2356 RmClient *pRmClient,
2357 NvU32 hMemory,
2358 NvU64 offset,
2359 NvU64 length,
2360 NvU32 *pProtection,
2361 void **ppPrivate,
2362 NvU64 *pPageIndex
2363 )
2364 {
2365 NV_STATUS rmStatus;
2366 PMEMORY_DESCRIPTOR pMemDesc;
2367 NvU32 pageOffset;
2368 NvU64 pageCount;
2369 NvU64 endingOffset;
2370 RsResourceRef *pResourceRef;
2371 RmResource *pRmResource;
2372 void *pMemData;
2373 NvBool bPeerIoMem;
2374 NvBool bReadOnlyMem;
2375 *pProtection = NV_PROTECT_READ_WRITE;
2376 *ppPrivate = NULL;
2377
2378 pageOffset = (offset & ~os_page_mask);
2379 offset &= os_page_mask;
2380
2381 NV_ASSERT_OR_RETURN(rmapiLockIsOwner(), NV_ERR_INVALID_LOCK_STATE);
2382
2383 rmStatus = clientGetResourceRef(staticCast(pRmClient, RsClient),
2384 hMemory, &pResourceRef);
2385 if (rmStatus != NV_OK)
2386 goto done;
2387
2388 pRmResource = dynamicCast(pResourceRef->pResource, RmResource);
2389 if (!pRmResource)
2390 {
2391 rmStatus = NV_ERR_INVALID_OBJECT;
2392 goto done;
2393 }
2394
2395 rmStatus = rmresGetMemoryMappingDescriptor(pRmResource, &pMemDesc);
2396 if (rmStatus != NV_OK)
2397 goto done;
2398
2399 bReadOnlyMem = memdescGetFlag(pMemDesc, MEMDESC_FLAGS_USER_READ_ONLY);
2400 bPeerIoMem = memdescGetFlag(pMemDesc, MEMDESC_FLAGS_PEER_IO_MEM);
2401
2402 if (!(pMemDesc->Allocated || bPeerIoMem))
2403 {
2404 rmStatus = NV_ERR_OBJECT_NOT_FOUND;
2405 goto done;
2406 }
2407
2408 switch (memdescGetAddressSpace(pMemDesc))
2409 {
2410 case ADDR_SYSMEM:
2411 case ADDR_EGM:
2412 break;
2413 default:
2414 rmStatus = NV_ERR_OBJECT_NOT_FOUND;
2415 goto done;
2416 }
2417
2418 pMemData = memdescGetMemData(pMemDesc);
2419 if (pMemData == NULL)
2420 {
2421 rmStatus = NV_ERR_OBJECT_NOT_FOUND;
2422 goto done;
2423 }
2424
2425 rmStatus = os_match_mmap_offset(pMemData, offset, pPageIndex);
2426 if (rmStatus != NV_OK)
2427 goto done;
2428
2429 if (!portSafeAddU64(pageOffset, length, &endingOffset))
2430 {
2431 rmStatus = NV_ERR_INVALID_ARGUMENT;
2432 goto done;
2433 }
2434
2435 pageCount = (endingOffset / os_page_size);
2436
2437 if (!portSafeAddU64(*pPageIndex + ((endingOffset % os_page_size) ? 1 : 0),
2438 pageCount, &pageCount))
2439 {
2440 rmStatus = NV_ERR_INVALID_ARGUMENT;
2441 goto done;
2442 }
2443
2444 if (pageCount > NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount))
2445 {
2446 rmStatus = NV_ERR_INVALID_ARGUMENT;
2447 goto done;
2448 }
2449
2450 if (bReadOnlyMem)
2451 *pProtection = NV_PROTECT_READABLE;
2452
2453 *ppPrivate = pMemData;
2454
2455 done:
2456 return rmStatus;
2457 }
2458
RmValidateMmapRequest(nv_state_t * pNv,NvU64 offset,NvU64 length,NvU32 * pProtection)2459 static NV_STATUS RmValidateMmapRequest(
2460 nv_state_t *pNv,
2461 NvU64 offset,
2462 NvU64 length,
2463 NvU32 *pProtection
2464 )
2465 {
2466 NV2080_CTRL_GPU_VALIDATE_MEM_MAP_REQUEST_PARAMS params = { 0 };
2467 RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL);
2468 NV_STATUS status;
2469
2470 if (osIsAdministrator())
2471 {
2472 *pProtection = NV_PROTECT_READ_WRITE;
2473 return NV_OK;
2474 }
2475
2476 params.addressStart = offset;
2477 params.addressLength = length;
2478
2479 status = pRmApi->Control(pRmApi, pNv->rmapi.hClient,
2480 pNv->rmapi.hSubDevice,
2481 NV2080_CTRL_CMD_GPU_VALIDATE_MEM_MAP_REQUEST,
2482 ¶ms, sizeof(params));
2483
2484 if (status == NV_OK)
2485 {
2486 *pProtection = params.protection;
2487 }
2488
2489 return status;
2490 }
2491
rm_get_adapter_status(nv_state_t * pNv,NvU32 * pStatus)2492 NV_STATUS rm_get_adapter_status(
2493 nv_state_t *pNv,
2494 NvU32 *pStatus
2495 )
2496 {
2497 NV_STATUS rmStatus = NV_ERR_OPERATING_SYSTEM;
2498
2499 // LOCK: acquire API lock
2500 if (rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_OSAPI) == NV_OK)
2501 {
2502 rmStatus = RmGetAdapterStatus(pNv, pStatus);
2503
2504 // UNLOCK: release API lock
2505 rmapiLockRelease();
2506 }
2507
2508 return rmStatus;
2509 }
2510
rm_get_adapter_status_external(nvidia_stack_t * sp,nv_state_t * pNv)2511 NV_STATUS NV_API_CALL rm_get_adapter_status_external(
2512 nvidia_stack_t *sp,
2513 nv_state_t *pNv
2514 )
2515 {
2516 NV_STATUS rmStatus;
2517 void *fp;
2518
2519 NV_ENTER_RM_RUNTIME(sp,fp);
2520
2521 if (rm_get_adapter_status(pNv, &rmStatus) != NV_OK)
2522 {
2523 rmStatus = NV_ERR_OPERATING_SYSTEM;
2524 }
2525
2526 NV_EXIT_RM_RUNTIME(sp,fp);
2527
2528 return rmStatus;
2529 }
2530
rm_init_rm(nvidia_stack_t * sp)2531 NvBool NV_API_CALL rm_init_rm(
2532 nvidia_stack_t *sp
2533 )
2534 {
2535 NvBool retval;
2536 void *fp;
2537
2538 NV_ENTER_RM_RUNTIME(sp,fp);
2539
2540 retval = RmInitRm();
2541
2542 NV_EXIT_RM_RUNTIME(sp,fp);
2543
2544 return retval;
2545 }
2546
rm_shutdown_rm(nvidia_stack_t * sp)2547 void NV_API_CALL rm_shutdown_rm(
2548 nvidia_stack_t *sp
2549 )
2550 {
2551 void *fp;
2552
2553 NV_ENTER_RM_RUNTIME(sp,fp);
2554
2555 RmShutdownRm();
2556
2557 NV_EXIT_RM_RUNTIME(sp,fp);
2558 }
2559
rm_init_event_locks(nvidia_stack_t * sp,nv_state_t * pNv)2560 NvBool NV_API_CALL rm_init_event_locks(
2561 nvidia_stack_t *sp,
2562 nv_state_t *pNv
2563 )
2564 {
2565 void *fp;
2566 NvBool ret;
2567
2568 NV_ENTER_RM_RUNTIME(sp,fp);
2569
2570 pNv->event_spinlock = portSyncSpinlockCreate(portMemAllocatorGetGlobalNonPaged());
2571 ret = (pNv->event_spinlock != NULL);
2572
2573 NV_EXIT_RM_RUNTIME(sp,fp);
2574 return ret;
2575 }
2576
rm_destroy_event_locks(nvidia_stack_t * sp,nv_state_t * pNv)2577 void NV_API_CALL rm_destroy_event_locks(
2578 nvidia_stack_t *sp,
2579 nv_state_t *pNv
2580 )
2581 {
2582 void *fp;
2583
2584 NV_ENTER_RM_RUNTIME(sp,fp);
2585
2586 if (pNv && pNv->event_spinlock)
2587 portSyncSpinlockDestroy(pNv->event_spinlock);
2588
2589 NV_EXIT_RM_RUNTIME(sp,fp);
2590 }
2591
rm_get_vbios_version(nvidia_stack_t * sp,nv_state_t * pNv,char * vbiosString)2592 void NV_API_CALL rm_get_vbios_version(
2593 nvidia_stack_t *sp,
2594 nv_state_t *pNv,
2595 char *vbiosString
2596 )
2597 {
2598 void *fp;
2599 NV2080_CTRL_BIOS_GET_INFO_V2_PARAMS *params;
2600 RM_API *pRmApi;
2601 THREAD_STATE_NODE threadState;
2602 const size_t vbiosStringLen = 15; // "xx.xx.xx.xx.xx"
2603
2604 os_snprintf(vbiosString, vbiosStringLen, "??.??.??.??.??");
2605
2606 NV_ENTER_RM_RUNTIME(sp,fp);
2607
2608 params = portMemAllocNonPaged(sizeof(*params));
2609 if (params == NULL)
2610 {
2611 NV_EXIT_RM_RUNTIME(sp,fp);
2612 return;
2613 }
2614
2615 portMemSet(params, 0, sizeof(*params));
2616
2617 params->biosInfoList[0].index = NV2080_CTRL_BIOS_INFO_INDEX_REVISION;
2618 params->biosInfoList[1].index = NV2080_CTRL_BIOS_INFO_INDEX_OEM_REVISION;
2619 params->biosInfoListSize = 2;
2620
2621 pRmApi = RmUnixRmApiPrologue(pNv, &threadState, RM_LOCK_MODULES_VBIOS);
2622 if (pRmApi != NULL)
2623 {
2624 NV_STATUS rmStatus;
2625
2626 rmStatus = pRmApi->Control(pRmApi,
2627 pNv->rmapi.hClient,
2628 pNv->rmapi.hSubDevice,
2629 NV2080_CTRL_CMD_BIOS_GET_INFO_V2,
2630 params,
2631 sizeof(*params));
2632
2633 if (rmStatus == NV_OK)
2634 {
2635 const NvU32 biosRevision = params->biosInfoList[0].data;
2636 const NvU32 biosOEMRevision = params->biosInfoList[1].data;
2637
2638 os_snprintf(vbiosString, vbiosStringLen,
2639 "%02x.%02x.%02x.%02x.%02x",
2640 (biosRevision & 0xff000000) >> 24,
2641 (biosRevision & 0x00ff0000) >> 16,
2642 (biosRevision & 0x0000ff00) >> 8,
2643 (biosRevision & 0x000000ff) >> 0,
2644 biosOEMRevision);
2645 }
2646
2647 RmUnixRmApiEpilogue(pNv, &threadState);
2648 }
2649
2650 portMemFree(params);
2651
2652 NV_EXIT_RM_RUNTIME(sp,fp);
2653 }
2654
rm_stop_user_channels(nvidia_stack_t * sp,nv_state_t * pNv)2655 NV_STATUS NV_API_CALL rm_stop_user_channels(
2656 nvidia_stack_t *sp,
2657 nv_state_t *pNv
2658 )
2659 {
2660 NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS params = { 0 };
2661 RM_API *pRmApi;
2662 THREAD_STATE_NODE threadState;
2663 NV_STATUS rmStatus = NV_ERR_INVALID_STATE;
2664 void *fp;
2665
2666 NV_ENTER_RM_RUNTIME(sp,fp);
2667
2668 pRmApi = RmUnixRmApiPrologue(pNv, &threadState, RM_LOCK_MODULES_FIFO);
2669 if (pRmApi != NULL)
2670 {
2671 params.bDisable = NV_TRUE;
2672 rmStatus = pRmApi->Control(pRmApi, pNv->rmapi.hClient,
2673 pNv->rmapi.hSubDevice,
2674 NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS,
2675 ¶ms, sizeof(params));
2676
2677 RmUnixRmApiEpilogue(pNv, &threadState);
2678 }
2679
2680 NV_EXIT_RM_RUNTIME(sp,fp);
2681
2682 return rmStatus;
2683 }
2684
rm_restart_user_channels(nvidia_stack_t * sp,nv_state_t * pNv)2685 NV_STATUS NV_API_CALL rm_restart_user_channels(
2686 nvidia_stack_t *sp,
2687 nv_state_t *pNv
2688 )
2689 {
2690 NV2080_CTRL_FIFO_DISABLE_USERMODE_CHANNELS_PARAMS params = { 0 };
2691 RM_API *pRmApi;
2692 THREAD_STATE_NODE threadState;
2693 NV_STATUS rmStatus = NV_ERR_INVALID_STATE;
2694 void *fp;
2695
2696 NV_ENTER_RM_RUNTIME(sp,fp);
2697
2698 pRmApi = RmUnixRmApiPrologue(pNv, &threadState, RM_LOCK_MODULES_FIFO);
2699 if (pRmApi != NULL)
2700 {
2701 params.bDisable = NV_FALSE;
2702 rmStatus = pRmApi->Control(pRmApi, pNv->rmapi.hClient, pNv->rmapi.hSubDevice,
2703 NV2080_CTRL_CMD_FIFO_DISABLE_USERMODE_CHANNELS,
2704 ¶ms, sizeof(params));
2705
2706 RmUnixRmApiEpilogue(pNv, &threadState);
2707 }
2708
2709 NV_EXIT_RM_RUNTIME(sp,fp);
2710
2711 return rmStatus;
2712 }
2713
2714 //
2715 // Use this call to check if the chipset is io coherent
2716 //
rm_is_chipset_io_coherent(nvidia_stack_t * sp)2717 NvBool NV_API_CALL rm_is_chipset_io_coherent(
2718 nvidia_stack_t *sp)
2719 {
2720 void *fp;
2721 OBJSYS *pSys;
2722 OBJCL *pCl;
2723 NvBool bIoCoherent = NV_FALSE;
2724
2725 NV_ENTER_RM_RUNTIME(sp,fp);
2726
2727 pSys = SYS_GET_INSTANCE();
2728 pCl = SYS_GET_CL(pSys);
2729 if (pCl == NULL)
2730 {
2731 NV_PRINTF(LEVEL_ERROR,
2732 "%s: no CL object found, setting io coherent by default\n",
2733 __FUNCTION__);
2734 goto done;
2735 }
2736
2737 bIoCoherent = pCl->getProperty(pCl, PDB_PROP_CL_IS_CHIPSET_IO_COHERENT);
2738
2739 done:
2740 NV_EXIT_RM_RUNTIME(sp,fp);
2741
2742 return bIoCoherent;
2743 }
2744
rm_ioctl(nvidia_stack_t * sp,nv_state_t * pNv,nv_file_private_t * nvfp,NvU32 Command,void * pData,NvU32 dataSize)2745 NV_STATUS NV_API_CALL rm_ioctl(
2746 nvidia_stack_t *sp,
2747 nv_state_t *pNv,
2748 nv_file_private_t *nvfp,
2749 NvU32 Command,
2750 void *pData,
2751 NvU32 dataSize
2752 )
2753 {
2754 NV_STATUS rmStatus;
2755 THREAD_STATE_NODE threadState;
2756 void *fp;
2757
2758 NV_ENTER_RM_RUNTIME(sp,fp);
2759 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
2760
2761 rmStatus = RmIoctl(pNv, nvfp, Command, pData, dataSize);
2762
2763 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
2764 NV_EXIT_RM_RUNTIME(sp,fp);
2765
2766 return rmStatus;
2767 }
2768
_deferredClientListFreeCallback(void * unused)2769 static void _deferredClientListFreeCallback(void *unused)
2770 {
2771 OBJSYS *pSys = SYS_GET_INSTANCE();
2772 NV_STATUS status = serverFreeDisabledClients(&g_resServ, 0, pSys->clientListDeferredFreeLimit);
2773 //
2774 // Possible return values:
2775 // NV_WARN_MORE_PROCESSING_REQUIRED - Iteration limit reached, need to call again
2776 // NV_ERR_IN_USE - Already running on another thread, try again later
2777 // In both cases, schedule a worker to clean up anything that remains
2778 //
2779 if (status != NV_OK)
2780 {
2781 status = osQueueSystemWorkItem(_deferredClientListFreeCallback, unused);
2782 if (status != NV_OK)
2783 {
2784 NV_PRINTF(LEVEL_NOTICE, "Failed to schedule deferred free callback. Freeing immediately.\n");
2785 serverFreeDisabledClients(&g_resServ, 0, 0);
2786 }
2787 }
2788 }
2789
rm_cleanup_file_private(nvidia_stack_t * sp,nv_state_t * pNv,nv_file_private_t * nvfp)2790 void NV_API_CALL rm_cleanup_file_private(
2791 nvidia_stack_t *sp,
2792 nv_state_t *pNv,
2793 nv_file_private_t *nvfp
2794 )
2795 {
2796 THREAD_STATE_NODE threadState;
2797 void *fp;
2798 RM_API *pRmApi;
2799 RM_API_CONTEXT rmApiContext = {0};
2800 NvU32 i;
2801 OBJSYS *pSys = SYS_GET_INSTANCE();
2802
2803 NV_ENTER_RM_RUNTIME(sp,fp);
2804
2805 //
2806 // Skip cleaning up this fd if:
2807 // - no RMAPI clients and events were ever allocated on this fd
2808 // - no RMAPI object handles were exported on this fd
2809 // Access nvfp->handles without locking as fd cleanup is synchronised by the kernel
2810 //
2811 if (!nvfp->bCleanupRmapi && nvfp->handles == NULL)
2812 goto done;
2813
2814 pRmApi = rmapiGetInterface(RMAPI_EXTERNAL);
2815 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
2816 threadStateSetTimeoutOverride(&threadState, 10 * 1000);
2817
2818 if (rmapiPrologue(pRmApi, &rmApiContext) != NV_OK) {
2819 NV_EXIT_RM_RUNTIME(sp,fp);
2820 return;
2821 }
2822
2823 // LOCK: acquire API lock. Low priority so cleanup doesn't block active threads
2824 if (rmapiLockAcquire(RMAPI_LOCK_FLAGS_LOW_PRIORITY, RM_LOCK_MODULES_OSAPI) == NV_OK)
2825 {
2826 // Unref any object which was exported on this file.
2827 if (nvfp->handles != NULL)
2828 {
2829 for (i = 0; i < nvfp->maxHandles; i++)
2830 {
2831 if (nvfp->handles[i] == 0)
2832 {
2833 continue;
2834 }
2835
2836 RmFreeObjExportHandle(nvfp->handles[i]);
2837 nvfp->handles[i] = 0;
2838 }
2839
2840 os_free_mem(nvfp->handles);
2841 nvfp->handles = NULL;
2842 nvfp->maxHandles = 0;
2843 }
2844
2845 // Disable any RM clients associated with this file.
2846 RmFreeUnusedClients(pNv, nvfp);
2847
2848 // Unless configured otherwise, immediately free all disabled clients
2849 if (!pSys->bUseDeferredClientListFree)
2850 serverFreeDisabledClients(&g_resServ, RM_LOCK_STATES_API_LOCK_ACQUIRED, 0);
2851
2852 // UNLOCK: release API lock
2853 rmapiLockRelease();
2854 }
2855
2856 // Start the deferred free callback if necessary
2857 if (pSys->bUseDeferredClientListFree)
2858 _deferredClientListFreeCallback(NULL);
2859
2860 rmapiEpilogue(pRmApi, &rmApiContext);
2861 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
2862
2863 done:
2864 if (nvfp->ctl_nvfp != NULL)
2865 {
2866 nv_put_file_private(nvfp->ctl_nvfp_priv);
2867 nvfp->ctl_nvfp = NULL;
2868 nvfp->ctl_nvfp_priv = NULL;
2869 }
2870
2871 NV_EXIT_RM_RUNTIME(sp,fp);
2872 }
2873
rm_unbind_lock(nvidia_stack_t * sp,nv_state_t * pNv)2874 void NV_API_CALL rm_unbind_lock(
2875 nvidia_stack_t *sp,
2876 nv_state_t *pNv
2877 )
2878 {
2879 THREAD_STATE_NODE threadState;
2880 void *fp;
2881
2882 NV_ENTER_RM_RUNTIME(sp,fp);
2883 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
2884
2885 // LOCK: acquire API lock
2886 if (rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI) == NV_OK)
2887 {
2888 RmUnbindLock(pNv);
2889
2890 // UNLOCK: release API lock
2891 rmapiLockRelease();
2892 }
2893
2894 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
2895 NV_EXIT_RM_RUNTIME(sp,fp);
2896 }
2897
rm_alloc_os_event(NvHandle hClient,nv_file_private_t * nvfp,NvU32 fd)2898 NV_STATUS rm_alloc_os_event(
2899 NvHandle hClient,
2900 nv_file_private_t *nvfp,
2901 NvU32 fd
2902 )
2903 {
2904 NV_STATUS RmStatus;
2905
2906 // LOCK: acquire API lock
2907 if ((RmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_EVENT)) == NV_OK)
2908 {
2909 RmStatus = RmAllocOsEvent(hClient, nvfp, fd);
2910
2911 // UNLOCK: release API lock
2912 rmapiLockRelease();
2913 }
2914
2915 return RmStatus;
2916 }
2917
rm_free_os_event(NvHandle hClient,NvU32 fd)2918 NV_STATUS rm_free_os_event(
2919 NvHandle hClient,
2920 NvU32 fd
2921 )
2922 {
2923 NV_STATUS RmStatus;
2924
2925 // LOCK: acquire API lock
2926 if ((RmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_EVENT)) == NV_OK)
2927 {
2928 RmStatus = RmFreeOsEvent(hClient, fd);
2929
2930 // UNLOCK: release API lock
2931 rmapiLockRelease();
2932 }
2933
2934 return RmStatus;
2935 }
2936
rm_get_event_data(nv_file_private_t * nvfp,NvP64 pEvent,NvU32 * MoreEvents)2937 NV_STATUS rm_get_event_data(
2938 nv_file_private_t *nvfp,
2939 NvP64 pEvent,
2940 NvU32 *MoreEvents
2941 )
2942 {
2943 NV_STATUS RmStatus;
2944
2945 // LOCK: acquire API lock
2946 if ((RmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_EVENT)) == NV_OK)
2947 {
2948 RmStatus = RmGetEventData(nvfp, pEvent, MoreEvents, NV_TRUE);
2949
2950 // UNLOCK: release API lock
2951 rmapiLockRelease();
2952 }
2953
2954 return RmStatus;
2955 }
2956
rm_read_registry_dword(nvidia_stack_t * sp,nv_state_t * nv,const char * regParmStr,NvU32 * Data)2957 NV_STATUS NV_API_CALL rm_read_registry_dword(
2958 nvidia_stack_t *sp,
2959 nv_state_t *nv,
2960 const char *regParmStr,
2961 NvU32 *Data
2962 )
2963 {
2964 OBJGPU *pGpu = NULL;
2965 NV_STATUS RmStatus;
2966 void *fp;
2967 NvBool isApiLockTaken = NV_FALSE;
2968
2969 NV_ENTER_RM_RUNTIME(sp,fp);
2970
2971 //
2972 // We can be called from different contexts:
2973 //
2974 // 1) early initialization without device state.
2975 // 2) from outside the RM API (without the lock held)
2976 //
2977 // In context 1)the API lock is not needed and
2978 // in context 2), it needs to be acquired.
2979 //
2980 if (nv != NULL)
2981 {
2982 // LOCK: acquire API lock
2983 if ((RmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_OSAPI)) != NV_OK)
2984 {
2985 NV_EXIT_RM_RUNTIME(sp,fp);
2986 return RmStatus;
2987 }
2988
2989 isApiLockTaken = NV_TRUE;
2990 }
2991
2992 pGpu = NV_GET_NV_PRIV_PGPU(nv);
2993
2994 // Skipping the NULL check as osReadRegistryDword takes care of it.
2995 RmStatus = osReadRegistryDword(pGpu, regParmStr, Data);
2996
2997 if (isApiLockTaken == NV_TRUE)
2998 {
2999 // UNLOCK: release API lock
3000 rmapiLockRelease();
3001 }
3002
3003 NV_EXIT_RM_RUNTIME(sp,fp);
3004
3005 return RmStatus;
3006 }
3007
rm_write_registry_dword(nvidia_stack_t * sp,nv_state_t * nv,const char * regParmStr,NvU32 Data)3008 NV_STATUS NV_API_CALL rm_write_registry_dword(
3009 nvidia_stack_t *sp,
3010 nv_state_t *nv,
3011 const char *regParmStr,
3012 NvU32 Data
3013 )
3014 {
3015 NV_STATUS RmStatus;
3016 void *fp;
3017 NvBool isApiLockTaken = NV_FALSE;
3018
3019 NV_ENTER_RM_RUNTIME(sp,fp);
3020
3021 if (nv != NULL)
3022 {
3023 // LOCK: acquire API lock
3024 if ((RmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) != NV_OK)
3025 {
3026 NV_EXIT_RM_RUNTIME(sp,fp);
3027 return RmStatus;
3028 }
3029
3030 isApiLockTaken = NV_TRUE;
3031 }
3032
3033 RmStatus = RmWriteRegistryDword(nv, regParmStr, Data);
3034
3035 if (isApiLockTaken == NV_TRUE)
3036 {
3037 // UNLOCK: release API lock
3038 rmapiLockRelease();
3039 }
3040
3041 NV_EXIT_RM_RUNTIME(sp,fp);
3042
3043 return RmStatus;
3044 }
3045
rm_write_registry_binary(nvidia_stack_t * sp,nv_state_t * nv,const char * regParmStr,NvU8 * Data,NvU32 cbLen)3046 NV_STATUS NV_API_CALL rm_write_registry_binary(
3047 nvidia_stack_t *sp,
3048 nv_state_t *nv,
3049 const char *regParmStr,
3050 NvU8 *Data,
3051 NvU32 cbLen
3052 )
3053 {
3054 NV_STATUS RmStatus;
3055 void *fp;
3056 NvBool isApiLockTaken = NV_FALSE;
3057
3058 NV_ENTER_RM_RUNTIME(sp,fp);
3059
3060 if (nv != NULL)
3061 {
3062 // LOCK: acquire API lock
3063 if ((RmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) != NV_OK)
3064 {
3065 NV_EXIT_RM_RUNTIME(sp,fp);
3066 return RmStatus;
3067 }
3068
3069 isApiLockTaken = NV_TRUE;
3070 }
3071
3072 RmStatus = RmWriteRegistryBinary(nv, regParmStr, Data, cbLen);
3073
3074 if (isApiLockTaken == NV_TRUE)
3075 {
3076 // UNLOCK: release API lock
3077 rmapiLockRelease();
3078 }
3079
3080 NV_EXIT_RM_RUNTIME(sp,fp);
3081
3082 return RmStatus;
3083 }
3084
rm_write_registry_string(nvidia_stack_t * sp,nv_state_t * nv,const char * regParmStr,const char * string,NvU32 stringLength)3085 NV_STATUS NV_API_CALL rm_write_registry_string(
3086 nvidia_stack_t *sp,
3087 nv_state_t *nv,
3088 const char *regParmStr,
3089 const char *string,
3090 NvU32 stringLength
3091 )
3092 {
3093 NV_STATUS rmStatus;
3094 void *fp;
3095 NvBool isApiLockTaken = NV_FALSE;
3096
3097 NV_ENTER_RM_RUNTIME(sp,fp);
3098
3099 if (nv != NULL)
3100 {
3101 // LOCK: acquire API lock
3102 if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI)) != NV_OK)
3103 {
3104 NV_EXIT_RM_RUNTIME(sp,fp);
3105 return rmStatus;
3106 }
3107
3108 isApiLockTaken = NV_TRUE;
3109 }
3110
3111 rmStatus = RmWriteRegistryString(nv, regParmStr, string, (stringLength + 1));
3112
3113 if (isApiLockTaken == NV_TRUE)
3114 {
3115 // UNLOCK: release API lock
3116 rmapiLockRelease();
3117 }
3118
3119 NV_EXIT_RM_RUNTIME(sp,fp);
3120
3121 return rmStatus;
3122 }
3123
rm_is_space(const char ch)3124 static NvBool NV_API_CALL rm_is_space(const char ch)
3125 {
3126 //
3127 // return true if it is a:
3128 // ' ' : (space - decimal 32.)
3129 // '\t' : (TAB - decimal 9)
3130 // 'LF' : (Line feed, new line - decimal 10)
3131 // 'VT' : (Vertical TAB - decimal 11)
3132 // 'FF' : (Form feed, new page - decimal 12)
3133 // '\r' : (carriage return - decimal 13)
3134 //
3135 return ((ch == ' ') || ((ch >= '\t') && (ch <= '\r')));
3136 }
3137
rm_remove_spaces(const char * in)3138 char* NV_API_CALL rm_remove_spaces(const char *in)
3139 {
3140 unsigned int len = os_string_length(in) + 1;
3141 const char *in_ptr;
3142 char *out, *out_ptr;
3143
3144 if (os_alloc_mem((void **)&out, len) != NV_OK)
3145 return NULL;
3146
3147 in_ptr = in;
3148 out_ptr = out;
3149
3150 while (*in_ptr != '\0')
3151 {
3152 if (!rm_is_space(*in_ptr))
3153 *out_ptr++ = *in_ptr;
3154 in_ptr++;
3155 }
3156 *out_ptr = '\0';
3157
3158 return out;
3159 }
3160
rm_string_token(char ** strp,const char delim)3161 char* NV_API_CALL rm_string_token(char **strp, const char delim)
3162 {
3163 char *s, *token;
3164
3165 if ((strp == NULL) || (*strp == NULL))
3166 return NULL;
3167
3168 s = token = *strp;
3169 *strp = NULL;
3170
3171 for (; *s != '\0'; s++) {
3172 if (*s == delim) {
3173 *s = '\0';
3174 *strp = ++s;
3175 break;
3176 }
3177 }
3178
3179 return token;
3180 }
3181
3182 // Parse string passed in NVRM as module parameter.
rm_parse_option_string(nvidia_stack_t * sp,const char * nvRegistryDwords)3183 void NV_API_CALL rm_parse_option_string(nvidia_stack_t *sp, const char *nvRegistryDwords)
3184 {
3185 unsigned int i;
3186 nv_parm_t *entry;
3187 char *option_string = NULL;
3188 char *ptr, *token;
3189 char *name, *value;
3190 NvU32 data;
3191
3192 if (nvRegistryDwords != NULL)
3193 {
3194 if ((option_string = rm_remove_spaces(nvRegistryDwords)) == NULL)
3195 {
3196 return;
3197 }
3198
3199 ptr = option_string;
3200
3201 while ((token = rm_string_token(&ptr, ';')) != NULL)
3202 {
3203 if (!(name = rm_string_token(&token, '=')) || !os_string_length(name))
3204 {
3205 continue;
3206 }
3207
3208 if (!(value = rm_string_token(&token, '=')) || !os_string_length(value))
3209 {
3210 continue;
3211 }
3212
3213 if (rm_string_token(&token, '=') != NULL)
3214 {
3215 continue;
3216 }
3217
3218 data = os_strtoul(value, NULL, 0);
3219
3220 for (i = 0; (entry = &nv_parms[i])->name != NULL; i++)
3221 {
3222 if (os_string_compare(entry->name, name) == 0)
3223 break;
3224 }
3225
3226 if (!entry->name)
3227 rm_write_registry_dword(sp, NULL, name, data);
3228 else
3229 *entry->data = data;
3230 }
3231
3232 // Free the memory allocated by rm_remove_spaces()
3233 os_free_mem(option_string);
3234 }
3235 }
3236
rm_run_rc_callback(nvidia_stack_t * sp,nv_state_t * nv)3237 NV_STATUS NV_API_CALL rm_run_rc_callback(
3238 nvidia_stack_t *sp,
3239 nv_state_t *nv
3240 )
3241 {
3242 OBJGPU *pGpu;
3243 void *fp;
3244
3245 /* make sure our timer's not still running when it shouldn't be */
3246 if (nv == NULL)
3247 return NV_ERR_GENERIC;
3248
3249 pGpu = NV_GET_NV_PRIV_PGPU(nv);
3250 if (pGpu == NULL)
3251 return NV_ERR_GENERIC;
3252
3253 if (nv->rc_timer_enabled == 0)
3254 return NV_ERR_GENERIC;
3255
3256 if (!FULL_GPU_SANITY_CHECK(pGpu))
3257 {
3258 return NV_ERR_GENERIC;
3259 }
3260
3261 NV_ENTER_RM_RUNTIME(sp,fp);
3262
3263 osRun1HzCallbacksNow(pGpu);
3264
3265 NV_EXIT_RM_RUNTIME(sp,fp);
3266
3267 return NV_OK;
3268 }
3269
RmRunNanoTimerCallback(OBJGPU * pGpu,void * pTmrEvent)3270 static NV_STATUS RmRunNanoTimerCallback(
3271 OBJGPU *pGpu,
3272 void *pTmrEvent
3273 )
3274 {
3275 OBJTMR *pTmr = GPU_GET_TIMER(pGpu);
3276 THREAD_STATE_NODE threadState;
3277 NV_STATUS status = NV_OK;
3278 // LOCK: try to acquire GPUs lock
3279 if ((status = rmGpuLocksAcquire(GPU_LOCK_FLAGS_COND_ACQUIRE, RM_LOCK_MODULES_TMR)) != NV_OK)
3280 {
3281 TMR_EVENT *pEvent = (TMR_EVENT *)pTmrEvent;
3282 NvU64 timeNs = pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_RESUME_CODEPATH) ?
3283 TIMER_RESCHED_TIME_DURING_PM_RESUME_NS :
3284 osGetTickResolution();
3285
3286 //
3287 // We failed to acquire the lock - depending on what's holding it,
3288 // the lock could be held for a while, so try again soon, but not too
3289 // soon to prevent the owner from making forward progress indefinitely.
3290 //
3291 return osStartNanoTimer(pGpu->pOsGpuInfo, pEvent->pOSTmrCBdata, timeNs);
3292 }
3293
3294 threadStateInitISRAndDeferredIntHandler(&threadState, pGpu,
3295 THREAD_STATE_FLAGS_IS_DEFERRED_INT_HANDLER);
3296
3297 // Call timer event service
3298 status = tmrEventServiceTimer(pGpu, pTmr, (PTMR_EVENT)pTmrEvent);
3299
3300 // Out of conflicting thread
3301 threadStateFreeISRAndDeferredIntHandler(&threadState,
3302 pGpu, THREAD_STATE_FLAGS_IS_DEFERRED_INT_HANDLER);
3303
3304 // UNLOCK: release GPUs lock
3305 rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, pGpu);
3306
3307 return status;
3308 }
3309
rm_run_nano_timer_callback(nvidia_stack_t * sp,nv_state_t * nv,void * pTmrEvent)3310 NV_STATUS NV_API_CALL rm_run_nano_timer_callback
3311 (
3312 nvidia_stack_t *sp,
3313 nv_state_t *nv,
3314 void *pTmrEvent
3315 )
3316 {
3317 NV_STATUS status;
3318 OBJGPU *pGpu = NULL;
3319 void *fp;
3320
3321 if (nv == NULL)
3322 return NV_ERR_GENERIC;
3323
3324 pGpu = NV_GET_NV_PRIV_PGPU(nv);
3325 if (pGpu == NULL)
3326 return NV_ERR_GENERIC;
3327
3328 if (!FULL_GPU_SANITY_FOR_PM_RESUME(pGpu))
3329 {
3330 return NV_ERR_GENERIC;
3331 }
3332
3333 NV_ENTER_RM_RUNTIME(sp,fp);
3334
3335 status = RmRunNanoTimerCallback(pGpu, pTmrEvent);
3336
3337 NV_EXIT_RM_RUNTIME(sp,fp);
3338
3339 return status;
3340 }
3341
rm_execute_work_item(nvidia_stack_t * sp,void * pNvWorkItem)3342 void NV_API_CALL rm_execute_work_item(
3343 nvidia_stack_t *sp,
3344 void *pNvWorkItem
3345 )
3346 {
3347 void *fp;
3348 THREAD_STATE_NODE threadState;
3349
3350 NV_ENTER_RM_RUNTIME(sp, fp);
3351 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
3352
3353 RmExecuteWorkItem(pNvWorkItem);
3354
3355 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
3356 NV_EXIT_RM_RUNTIME(sp, fp);
3357 }
3358
rm_get_device_name(NvU16 device,NvU16 subsystem_vendor,NvU16 subsystem_device)3359 const char* NV_API_CALL rm_get_device_name(
3360 NvU16 device,
3361 NvU16 subsystem_vendor,
3362 NvU16 subsystem_device
3363 )
3364 {
3365 unsigned int i;
3366 const char *tmpName = NULL;
3367
3368 for (i = 0; i < NV_ARRAY_ELEMENTS(sChipsReleased); i++)
3369 {
3370 // if the device ID doesn't match, go to the next entry
3371 if (device != sChipsReleased[i].devID)
3372 {
3373 continue;
3374 }
3375
3376 // if the entry has 0 for the subsystem IDs, then the device
3377 // ID match is sufficient, but continue scanning through
3378 // sChipsReleased[] in case there is a subsystem ID match later
3379 // in the table
3380 if (sChipsReleased[i].subSystemVendorID == 0 &&
3381 sChipsReleased[i].subSystemID == 0)
3382 {
3383 tmpName = sChipsReleased[i].name;
3384 continue;
3385 }
3386
3387 if (subsystem_vendor == sChipsReleased[i].subSystemVendorID &&
3388 subsystem_device == sChipsReleased[i].subSystemID)
3389 {
3390 tmpName = sChipsReleased[i].name;
3391 break;
3392 }
3393 }
3394
3395 return (tmpName != NULL) ? tmpName : "Unknown";
3396 }
3397
rm_access_registry(NvHandle hClient,NvHandle hObject,NvU32 AccessType,NvP64 clientDevNodeAddress,NvU32 DevNodeLength,NvP64 clientParmStrAddress,NvU32 ParmStrLength,NvP64 clientBinaryDataAddress,NvU32 * pBinaryDataLength,NvU32 * Data,NvU32 * Entry)3398 NV_STATUS rm_access_registry(
3399 NvHandle hClient,
3400 NvHandle hObject,
3401 NvU32 AccessType,
3402 NvP64 clientDevNodeAddress,
3403 NvU32 DevNodeLength,
3404 NvP64 clientParmStrAddress,
3405 NvU32 ParmStrLength,
3406 NvP64 clientBinaryDataAddress,
3407 NvU32 *pBinaryDataLength,
3408 NvU32 *Data,
3409 NvU32 *Entry
3410 )
3411 {
3412 NV_STATUS RmStatus;
3413 NvBool bReadOnly = (AccessType == NVOS38_ACCESS_TYPE_READ_DWORD) ||
3414 (AccessType == NVOS38_ACCESS_TYPE_READ_BINARY);
3415
3416 // LOCK: acquire API lock
3417 if ((RmStatus = rmapiLockAcquire(bReadOnly ? RMAPI_LOCK_FLAGS_READ : RMAPI_LOCK_FLAGS_NONE,
3418 RM_LOCK_MODULES_OSAPI)) == NV_OK)
3419 {
3420 RmStatus = RmAccessRegistry(hClient,
3421 hObject,
3422 AccessType,
3423 clientDevNodeAddress,
3424 DevNodeLength,
3425 clientParmStrAddress,
3426 ParmStrLength,
3427 clientBinaryDataAddress,
3428 pBinaryDataLength,
3429 Data,
3430 Entry);
3431
3432 // UNLOCK: release API lock
3433 rmapiLockRelease();
3434 }
3435
3436 return RmStatus;
3437 }
3438
rm_update_device_mapping_info(NvHandle hClient,NvHandle hDevice,NvHandle hMemory,void * pOldCpuAddress,void * pNewCpuAddress)3439 NV_STATUS rm_update_device_mapping_info(
3440 NvHandle hClient,
3441 NvHandle hDevice,
3442 NvHandle hMemory,
3443 void *pOldCpuAddress,
3444 void *pNewCpuAddress
3445 )
3446 {
3447 NV_STATUS RmStatus;
3448
3449 // LOCK: acquire API lock
3450 if ((RmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU)) == NV_OK)
3451 {
3452 RmStatus = RmUpdateDeviceMappingInfo(hClient,
3453 hDevice,
3454 hMemory,
3455 pOldCpuAddress,
3456 pNewCpuAddress);
3457
3458 // UNLOCK: release API lock
3459 rmapiLockRelease();
3460 }
3461
3462 return RmStatus;
3463 }
3464
rm_is_legacy_device(NvU16 device_id,NvU16 subsystem_vendor,NvU16 subsystem_device,NvBool print_warning)3465 static NvBool NV_API_CALL rm_is_legacy_device(
3466 NvU16 device_id,
3467 NvU16 subsystem_vendor,
3468 NvU16 subsystem_device,
3469 NvBool print_warning
3470 )
3471 {
3472 return NV_FALSE;
3473 }
3474
rm_is_legacy_arch(NvU32 pmc_boot_0,NvU32 pmc_boot_42)3475 static NvBool NV_API_CALL rm_is_legacy_arch(
3476 NvU32 pmc_boot_0,
3477 NvU32 pmc_boot_42
3478 )
3479 {
3480 NvBool legacy = NV_FALSE;
3481
3482 return legacy;
3483 }
3484
rm_is_supported_device(nvidia_stack_t * sp,nv_state_t * pNv)3485 NV_STATUS NV_API_CALL rm_is_supported_device(
3486 nvidia_stack_t *sp,
3487 nv_state_t *pNv
3488 )
3489 {
3490 THREAD_STATE_NODE threadState;
3491 NV_STATUS rmStatus;
3492 OBJSYS *pSys;
3493 OBJHALMGR *pHalMgr;
3494 GPUHWREG *reg_mapping;
3495 NvU32 myHalPublicID;
3496 void *fp;
3497 NvU32 pmc_boot_0;
3498 NvU32 pmc_boot_42;
3499
3500 NV_ENTER_RM_RUNTIME(sp,fp);
3501 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
3502
3503 pSys = SYS_GET_INSTANCE();
3504 pHalMgr = SYS_GET_HALMGR(pSys);
3505
3506 reg_mapping = osMapKernelSpace(pNv->regs->cpu_address,
3507 os_page_size,
3508 NV_MEMORY_UNCACHED,
3509 NV_PROTECT_READABLE);
3510
3511 if (reg_mapping == NULL)
3512 {
3513 nv_printf(NV_DBG_ERRORS, "NVRM: failed to map registers!\n");
3514 rmStatus = NV_ERR_OPERATING_SYSTEM;
3515 goto threadfree;
3516 }
3517 NvU32 pmc_boot_1 = NV_PRIV_REG_RD32(reg_mapping, NV_PMC_BOOT_1);
3518 pmc_boot_0 = NV_PRIV_REG_RD32(reg_mapping, NV_PMC_BOOT_0);
3519 pmc_boot_42 = NV_PRIV_REG_RD32(reg_mapping, NV_PMC_BOOT_42);
3520
3521 osUnmapKernelSpace(reg_mapping, os_page_size);
3522
3523 if ((pmc_boot_0 == 0xFFFFFFFF) && (pmc_boot_42 == 0xFFFFFFFF))
3524 {
3525 nv_printf(NV_DBG_ERRORS,
3526 "NVRM: The NVIDIA GPU %04x:%02x:%02x.%x\n"
3527 "NVRM: (PCI ID: %04x:%04x) installed in this system has\n"
3528 "NVRM: fallen off the bus and is not responding to commands.\n",
3529 pNv->pci_info.domain, pNv->pci_info.bus, pNv->pci_info.slot,
3530 pNv->pci_info.function, pNv->pci_info.vendor_id,
3531 pNv->pci_info.device_id);
3532 rmStatus = NV_ERR_GPU_IS_LOST;
3533 goto threadfree;
3534 }
3535
3536 /*
3537 * For legacy architectures, rm_is_legacy_arch() prints "legacy" message.
3538 * We do not want to print "unsupported" message for legacy architectures
3539 * to avoid confusion. Also, the probe should not continue for legacy
3540 * architectures. Hence, we set rmStatus to NV_ERR_NOT_SUPPORTED and
3541 * goto threadfree.
3542 */
3543 if (rm_is_legacy_arch(pmc_boot_0, pmc_boot_42))
3544 {
3545 rmStatus = NV_ERR_NOT_SUPPORTED;
3546 goto threadfree;
3547 }
3548
3549 rmStatus = halmgrGetHalForGpu(pHalMgr, pmc_boot_0, pmc_boot_42, &myHalPublicID);
3550
3551 if (rmStatus != NV_OK)
3552 {
3553 NvBool bIsFirmwareCapable;
3554
3555 bIsFirmwareCapable = gpumgrIsDeviceRmFirmwareCapable(pNv->pci_info.device_id,
3556 pmc_boot_42,
3557 NV_IS_SOC_DISPLAY_DEVICE(pNv),
3558 NULL);
3559 if (!bIsFirmwareCapable)
3560 {
3561 if (hypervisorIsVgxHyper())
3562 {
3563 nv_printf(NV_DBG_ERRORS,
3564 "NVRM: The NVIDIA GPU %04x:%02x:%02x.%x (PCI ID: %04x:%04x)\n"
3565 "NVRM: installed in this vGPU host system is not supported by\n"
3566 "NVRM: open nvidia.ko.\n"
3567 "NVRM: Please see the 'Open Linux Kernel Modules' and 'GSP\n"
3568 "NVRM: Firmware' sections in the NVIDIA Virtual GPU (vGPU)\n"
3569 "NVRM: Software documentation, available at docs.nvidia.com.\n",
3570 pNv->pci_info.domain, pNv->pci_info.bus, pNv->pci_info.slot,
3571 pNv->pci_info.function, pNv->pci_info.vendor_id,
3572 pNv->pci_info.device_id, NV_VERSION_STRING);
3573 }
3574 else
3575 {
3576 nv_printf(NV_DBG_ERRORS,
3577 "NVRM: The NVIDIA GPU %04x:%02x:%02x.%x (PCI ID: %04x:%04x)\n"
3578 "NVRM: installed in this system is not supported by open\n"
3579 "NVRM: nvidia.ko because it does not include the required GPU\n"
3580 "NVRM: System Processor (GSP).\n"
3581 "NVRM: Please see the 'Open Linux Kernel Modules' and 'GSP\n"
3582 "NVRM: Firmware' sections in the driver README, available on\n"
3583 "NVRM: the Linux graphics driver download page at\n"
3584 "NVRM: www.nvidia.com.\n",
3585 pNv->pci_info.domain, pNv->pci_info.bus, pNv->pci_info.slot,
3586 pNv->pci_info.function, pNv->pci_info.vendor_id,
3587 pNv->pci_info.device_id, NV_VERSION_STRING);
3588 }
3589 goto threadfree;
3590 }
3591 goto print_unsupported;
3592 }
3593
3594 rmStatus = rm_is_vgpu_supported_device(pNv, pmc_boot_1, pmc_boot_42);
3595
3596 if (rmStatus != NV_OK)
3597 {
3598 nv_printf(NV_DBG_ERRORS,
3599 "NVRM: The NVIDIA vGPU %04x:%02x:%02x.%x (PCI ID: %04x:%04x)\n"
3600 "NVRM: installed in this system is not supported by open\n"
3601 "NVRM: nvidia.ko.\n"
3602 "NVRM: Please see the 'Open Linux Kernel Modules' and 'GSP\n"
3603 "NVRM: Firmware' sections in the NVIDIA Virtual GPU (vGPU)\n"
3604 "NVRM: Software documentation, available at docs.nvidia.com.\n",
3605 pNv->pci_info.domain, pNv->pci_info.bus, pNv->pci_info.slot,
3606 pNv->pci_info.function, pNv->pci_info.vendor_id,
3607 pNv->pci_info.device_id, NV_VERSION_STRING);
3608 goto threadfree;
3609 }
3610 goto threadfree;
3611
3612 print_unsupported:
3613 nv_printf(NV_DBG_ERRORS,
3614 "NVRM: The NVIDIA GPU %04x:%02x:%02x.%x (PCI ID: %04x:%04x)\n"
3615 "NVRM: installed in this system is not supported by the\n"
3616 "NVRM: NVIDIA %s driver release.\n"
3617 "NVRM: Please see 'Appendix A - Supported NVIDIA GPU Products'\n"
3618 "NVRM: in this release's README, available on the operating system\n"
3619 "NVRM: specific graphics driver download page at www.nvidia.com.\n",
3620 pNv->pci_info.domain, pNv->pci_info.bus, pNv->pci_info.slot,
3621 pNv->pci_info.function, pNv->pci_info.vendor_id,
3622 pNv->pci_info.device_id, NV_VERSION_STRING);
3623
3624 threadfree:
3625 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
3626 NV_EXIT_RM_RUNTIME(sp,fp);
3627
3628 return rmStatus;
3629 }
3630
rm_is_supported_pci_device(NvU8 pci_class,NvU8 pci_subclass,NvU16 vendor,NvU16 device,NvU16 subsystem_vendor,NvU16 subsystem_device,NvBool print_legacy_warning)3631 NvBool NV_API_CALL rm_is_supported_pci_device(
3632 NvU8 pci_class,
3633 NvU8 pci_subclass,
3634 NvU16 vendor,
3635 NvU16 device,
3636 NvU16 subsystem_vendor,
3637 NvU16 subsystem_device,
3638 NvBool print_legacy_warning
3639 )
3640 {
3641 const NvU16 nv_pci_vendor_id = 0x10DE;
3642 const NvU16 nv_pci_id_riva_tnt = 0x0020;
3643 const NvU8 nv_pci_class_display = 0x03;
3644 const NvU8 nv_pci_subclass_display_vga = 0x00;
3645 const NvU8 nv_pci_subclass_display_3d = 0x02;
3646
3647 if (pci_class != nv_pci_class_display)
3648 {
3649 return NV_FALSE;
3650 }
3651
3652 if ((pci_subclass != nv_pci_subclass_display_vga) &&
3653 (pci_subclass != nv_pci_subclass_display_3d))
3654 {
3655 return NV_FALSE;
3656 }
3657
3658 if (vendor != nv_pci_vendor_id)
3659 {
3660 return NV_FALSE;
3661 }
3662
3663 if (device < nv_pci_id_riva_tnt)
3664 {
3665 return NV_FALSE;
3666 }
3667
3668 if (rm_is_legacy_device(
3669 device,
3670 subsystem_vendor,
3671 subsystem_device,
3672 print_legacy_warning))
3673 {
3674 return NV_FALSE;
3675 }
3676
3677 return NV_TRUE;
3678 }
3679
3680 /*
3681 * Performs the I2C transfers which are related with DP AUX channel
3682 */
RmDpAuxI2CTransfer(nv_state_t * pNv,NvU32 displayId,NvU8 addr,NvU32 len,NvU8 * pData,NvBool bWrite)3683 static NV_STATUS RmDpAuxI2CTransfer
3684 (
3685 nv_state_t *pNv,
3686 NvU32 displayId,
3687 NvU8 addr,
3688 NvU32 len,
3689 NvU8 *pData,
3690 NvBool bWrite
3691 )
3692 {
3693 NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_CTRL_PARAMS *pParams;
3694 RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL);
3695 NV_STATUS status;
3696
3697 if (len > NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_MAX_DATA_SIZE)
3698 {
3699 NV_PRINTF(LEVEL_ERROR,
3700 "%s: requested I2C transfer length %u is greater than maximum supported length %u\n",
3701 __FUNCTION__, len, NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_MAX_DATA_SIZE);
3702 return NV_ERR_NOT_SUPPORTED;
3703 }
3704
3705 pParams = portMemAllocNonPaged(sizeof(*pParams));
3706 if (pParams == NULL)
3707 {
3708 return NV_ERR_NO_MEMORY;
3709 }
3710
3711 portMemSet(pParams, 0, sizeof(*pParams));
3712
3713 pParams->subDeviceInstance = 0;
3714 pParams->displayId = displayId;
3715 pParams->addr = addr;
3716 pParams->size = len;
3717 pParams->bWrite = bWrite;
3718
3719 if (bWrite)
3720 {
3721 portMemCopy(pParams->data, NV0073_CTRL_DP_AUXCH_I2C_TRANSFER_MAX_DATA_SIZE,
3722 pData, len);
3723 }
3724
3725 status = pRmApi->Control(pRmApi, pNv->rmapi.hClient, pNv->rmapi.hDisp,
3726 NV0073_CTRL_CMD_DP_AUXCH_I2C_TRANSFER_CTRL,
3727 pParams, sizeof(*pParams));
3728
3729 if ((status == NV_OK) && !bWrite)
3730 {
3731 portMemCopy(pData, len, pParams->data, pParams->size);
3732 }
3733
3734 portMemFree(pParams);
3735
3736 return status;
3737 }
3738
3739 /*
3740 * Performs the I2C transfers which are not related with DP AUX channel
3741 */
RmNonDPAuxI2CTransfer(nv_state_t * pNv,NvU8 portId,nv_i2c_cmd_t type,NvU8 addr,NvU8 command,NvU32 len,NvU8 * pData)3742 static NV_STATUS RmNonDPAuxI2CTransfer
3743 (
3744 nv_state_t *pNv,
3745 NvU8 portId,
3746 nv_i2c_cmd_t type,
3747 NvU8 addr,
3748 NvU8 command,
3749 NvU32 len,
3750 NvU8 *pData
3751 )
3752 {
3753 NV402C_CTRL_I2C_TRANSACTION_PARAMS *params;
3754 RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL);
3755 NV_STATUS rmStatus = NV_OK;
3756
3757 params = portMemAllocNonPaged(sizeof(*params));
3758 if (params == NULL)
3759 {
3760 return NV_ERR_NO_MEMORY;
3761 }
3762
3763 portMemSet(params, 0, sizeof(*params));
3764
3765 params->portId = portId;
3766 // precondition our address (our stack requires this)
3767 params->deviceAddress = addr << 1;
3768
3769 switch (type)
3770 {
3771 case NV_I2C_CMD_WRITE:
3772 params->transData.i2cBlockData.bWrite = NV_TRUE;
3773 /* fall through*/
3774
3775 case NV_I2C_CMD_READ:
3776 params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BLOCK_RW;
3777 params->transData.i2cBlockData.messageLength = len;
3778 params->transData.i2cBlockData.pMessage = pData;
3779 break;
3780
3781 case NV_I2C_CMD_SMBUS_WRITE:
3782 if (len == 2)
3783 {
3784 params->transData.smbusWordData.bWrite = NV_TRUE;
3785 }
3786 else
3787 {
3788 params->transData.smbusByteData.bWrite = NV_TRUE;
3789 }
3790 /* fall through*/
3791
3792 case NV_I2C_CMD_SMBUS_READ:
3793 if (len == 2)
3794 {
3795 params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_WORD_RW;
3796 params->transData.smbusWordData.message = pData[0] | ((NvU16)pData[1] << 8);
3797 params->transData.smbusWordData.registerAddress = command;
3798 }
3799 else
3800 {
3801 params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BYTE_RW;
3802 params->transData.smbusByteData.message = pData[0];
3803 params->transData.smbusByteData.registerAddress = command;
3804 }
3805 break;
3806
3807 case NV_I2C_CMD_SMBUS_BLOCK_WRITE:
3808 params->transData.smbusBlockData.bWrite = NV_TRUE;
3809 /* fall through*/
3810
3811 case NV_I2C_CMD_SMBUS_BLOCK_READ:
3812 params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_BLOCK_RW;
3813 params->transData.smbusBlockData.registerAddress = command;
3814 params->transData.smbusBlockData.messageLength = len;
3815 params->transData.smbusBlockData.pMessage = pData;
3816 break;
3817
3818 case NV_I2C_CMD_SMBUS_QUICK_WRITE:
3819 params->transData.smbusQuickData.bWrite = NV_TRUE;
3820 /* fall through*/
3821
3822 case NV_I2C_CMD_SMBUS_QUICK_READ:
3823 params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_SMBUS_QUICK_RW;
3824 break;
3825
3826 case NV_I2C_CMD_BLOCK_WRITE:
3827 params->transData.i2cBufferData.bWrite = NV_TRUE;
3828 /* fall through */
3829
3830 case NV_I2C_CMD_BLOCK_READ:
3831 params->transType = NV402C_CTRL_I2C_TRANSACTION_TYPE_I2C_BUFFER_RW;
3832 params->transData.i2cBufferData.registerAddress = command;
3833 params->transData.i2cBufferData.messageLength = len;
3834 params->transData.i2cBufferData.pMessage = pData;
3835 break;
3836
3837 default:
3838 portMemFree(params);
3839 return NV_ERR_INVALID_ARGUMENT;
3840 }
3841
3842 rmStatus = pRmApi->Control(pRmApi, pNv->rmapi.hClient,
3843 pNv->rmapi.hI2C,
3844 NV402C_CTRL_CMD_I2C_TRANSACTION,
3845 params, sizeof(*params));
3846
3847 //
3848 // For NV_I2C_CMD_SMBUS_READ, copy the read data to original
3849 // data buffer.
3850 //
3851 if (rmStatus == NV_OK && type == NV_I2C_CMD_SMBUS_READ)
3852 {
3853 if (len == 2)
3854 {
3855 pData[0] = (params->transData.smbusWordData.message & 0xff);
3856 pData[1] = params->transData.smbusWordData.message >> 8;
3857 }
3858 else
3859 {
3860 pData[0] = params->transData.smbusByteData.message;
3861 }
3862 }
3863
3864 portMemFree(params);
3865
3866 return rmStatus;
3867 }
3868
rm_i2c_transfer(nvidia_stack_t * sp,nv_state_t * pNv,void * pI2cAdapter,nv_i2c_cmd_t type,NvU8 addr,NvU8 command,NvU32 len,NvU8 * pData)3869 NV_STATUS NV_API_CALL rm_i2c_transfer(
3870 nvidia_stack_t *sp,
3871 nv_state_t *pNv,
3872 void *pI2cAdapter,
3873 nv_i2c_cmd_t type,
3874 NvU8 addr,
3875 NvU8 command,
3876 NvU32 len,
3877 NvU8 *pData
3878 )
3879 {
3880 THREAD_STATE_NODE threadState;
3881 nv_priv_t *pNvp = NV_GET_NV_PRIV(pNv);
3882 NV_STATUS rmStatus = NV_OK;
3883 OBJGPU *pGpu = NULL;
3884 NvBool unlockApi = NV_FALSE;
3885 NvBool unlockGpu = NV_FALSE;
3886 NvU32 x;
3887 void *fp;
3888 NvU32 numDispId = 0;
3889
3890 NV_ENTER_RM_RUNTIME(sp,fp);
3891 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
3892
3893 if (pNvp->flags & NV_INIT_FLAG_PUBLIC_I2C)
3894 {
3895 // LOCK: acquire API lock
3896 if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_I2C)) != NV_OK)
3897 goto finish;
3898
3899 unlockApi = NV_TRUE;
3900
3901 // LOCK: acquire GPUs lock
3902 if ((rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_I2C)) != NV_OK)
3903 goto finish;
3904
3905 unlockGpu = NV_TRUE;
3906 }
3907
3908 pGpu = NV_GET_NV_PRIV_PGPU(pNv);
3909
3910 if (!pGpu)
3911 {
3912 rmStatus = NV_ERR_GENERIC;
3913 goto finish;
3914 }
3915
3916 for (x = 0; x < MAX_I2C_ADAPTERS; x++)
3917 {
3918 if (pNvp->i2c_adapters[x].pOsAdapter == pI2cAdapter)
3919 {
3920 break;
3921 }
3922 }
3923
3924 if (x == MAX_I2C_ADAPTERS)
3925 {
3926 rmStatus = NV_ERR_GENERIC;
3927 goto finish;
3928 }
3929
3930 for (numDispId = 0; numDispId < MAX_DISP_ID_PER_ADAPTER; numDispId++)
3931 {
3932 NvU32 displayId = pNvp->i2c_adapters[x].displayId[numDispId];
3933
3934 if (displayId == INVALID_DISP_ID)
3935 {
3936 continue;
3937 }
3938
3939 // Handle i2c-over-DpAux adapters separately from regular i2c adapters
3940 if (displayId == 0)
3941 {
3942 rmStatus = RmNonDPAuxI2CTransfer(pNv, pNvp->i2c_adapters[x].port,
3943 type, addr, command, len, pData);
3944 }
3945 else
3946 {
3947 if ((type != NV_I2C_CMD_READ) && (type != NV_I2C_CMD_WRITE))
3948 {
3949 rmStatus = NV_ERR_NOT_SUPPORTED;
3950 goto semafinish;
3951 }
3952
3953 rmStatus = RmDpAuxI2CTransfer(pNv, displayId, addr, len, pData,
3954 type == NV_I2C_CMD_WRITE);
3955 }
3956 semafinish:
3957 if (rmStatus == NV_OK)
3958 {
3959 break;
3960 }
3961 }
3962
3963 finish:
3964 if (unlockGpu)
3965 {
3966 // UNLOCK: release GPU lock
3967 rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL);
3968 }
3969
3970 if (unlockApi)
3971 {
3972 // UNLOCK: release API lock
3973 rmapiLockRelease();
3974 }
3975
3976 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
3977 NV_EXIT_RM_RUNTIME(sp,fp);
3978
3979 return rmStatus;
3980 }
3981
rm_i2c_add_adapter(nv_state_t * pNv,NvU32 port,NvU32 displayId)3982 static void rm_i2c_add_adapter(
3983 nv_state_t *pNv,
3984 NvU32 port,
3985 NvU32 displayId
3986 )
3987 {
3988 NvU32 y, free;
3989 nv_priv_t *pNvp = NV_GET_NV_PRIV(pNv);
3990 NvU32 numDispId = 0;
3991
3992 for (y = 0, free = MAX_I2C_ADAPTERS; y < MAX_I2C_ADAPTERS; y++)
3993 {
3994 if (pNvp->i2c_adapters[y].pOsAdapter == NULL)
3995 {
3996 // Only find the first free entry, and ignore the rest
3997 if (free == MAX_I2C_ADAPTERS)
3998 {
3999 free = y;
4000 }
4001 }
4002 else if (pNvp->i2c_adapters[y].port == port)
4003 {
4004 break;
4005 }
4006 }
4007
4008 if (y < MAX_I2C_ADAPTERS)
4009 {
4010 for (numDispId = 0; numDispId < MAX_DISP_ID_PER_ADAPTER; numDispId++)
4011 {
4012 if (pNvp->i2c_adapters[y].displayId[numDispId] == INVALID_DISP_ID)
4013 {
4014 pNvp->i2c_adapters[y].displayId[numDispId] = displayId;
4015 break;
4016 }
4017 else
4018 {
4019 NV_PRINTF(LEVEL_INFO,
4020 "%s: adapter already exists (port=0x%x, displayId=0x%x)\n",
4021 __FUNCTION__, port,
4022 pNvp->i2c_adapters[y].displayId[numDispId]);
4023 }
4024 }
4025
4026 if (numDispId == MAX_DISP_ID_PER_ADAPTER)
4027 {
4028 NV_PRINTF(LEVEL_ERROR,
4029 "%s: no more free display Id entries in adapter\n",
4030 __FUNCTION__);
4031 }
4032
4033 return;
4034 }
4035
4036 if (free == MAX_I2C_ADAPTERS)
4037 {
4038 NV_PRINTF(LEVEL_ERROR, "%s: no more free adapter entries exist\n",
4039 __FUNCTION__);
4040 return;
4041 }
4042
4043 pNvp->i2c_adapters[free].pOsAdapter = nv_i2c_add_adapter(pNv, port);
4044 pNvp->i2c_adapters[free].port = port;
4045 // When port is added, numDispId will be 0.
4046 pNvp->i2c_adapters[free].displayId[numDispId] = displayId;
4047 }
4048
RmI2cAddGpuPorts(nv_state_t * pNv)4049 void RmI2cAddGpuPorts(nv_state_t * pNv)
4050 {
4051 NvU32 x = 0;
4052 nv_priv_t *pNvp = NV_GET_NV_PRIV(pNv);
4053 RM_API *pRmApi = rmapiGetInterface(RMAPI_API_LOCK_INTERNAL);
4054 NvU32 displayMask;
4055 NV_STATUS status;
4056 OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv);
4057 NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS systemGetSupportedParams = { 0 };
4058
4059 if (IS_VIRTUAL(pGpu))
4060 return;
4061
4062 // Make displayId as Invalid.
4063 for (x = 0; x < MAX_I2C_ADAPTERS; x++)
4064 {
4065 NvU32 numDispId;
4066
4067 for (numDispId = 0; numDispId < MAX_DISP_ID_PER_ADAPTER; numDispId++)
4068 {
4069 pNvp->i2c_adapters[x].displayId[numDispId] = INVALID_DISP_ID;
4070 }
4071 }
4072
4073 // First, set up the regular i2c adapters - one per i2c port
4074 if (pNv->rmapi.hI2C != 0)
4075 {
4076 NV402C_CTRL_I2C_GET_PORT_INFO_PARAMS i2cPortInfoParams = { 0 };
4077
4078 status = pRmApi->Control(pRmApi, pNv->rmapi.hClient, pNv->rmapi.hI2C,
4079 NV402C_CTRL_CMD_I2C_GET_PORT_INFO,
4080 &i2cPortInfoParams, sizeof(i2cPortInfoParams));
4081
4082 if (status == NV_OK)
4083 {
4084 for (x = 0; x < NV_ARRAY_ELEMENTS(i2cPortInfoParams.info); x++)
4085 {
4086 //
4087 // Check if this port is implemented and RM I2C framework has
4088 // validated this port. Only limited amount of ports can
4089 // be added to the OS framework.
4090 //
4091 if (FLD_TEST_DRF(402C_CTRL, _I2C_GET_PORT_INFO, _IMPLEMENTED,
4092 _YES, i2cPortInfoParams.info[x]) &&
4093 FLD_TEST_DRF(402C_CTRL, _I2C_GET_PORT_INFO, _VALID,
4094 _YES, i2cPortInfoParams.info[x]))
4095 {
4096 rm_i2c_add_adapter(pNv, x, 0);
4097 }
4098 }
4099 }
4100 }
4101
4102 //
4103 // Now set up the i2c-over-DpAux adapters - one per DP OD
4104 //
4105 // 1. Perform NV0073_CTRL_SYSTEM_GET_SUPPORTED_PARAMS RM control which
4106 // will return the mask for all the display ID's.
4107 // 2. Loop for all the display ID's and do
4108 // NV0073_CTRL_CMD_SPECIFIC_OR_GET_INFO RM control call. For each
4109 // output resource, check for the following requirements:
4110 // a. It must be DisplayPort.
4111 // b. It must be internal to the GPU (ie, not on the board)
4112 // c. It must be directly connected to the physical connector (ie, no DP
4113 // 1.2 multistream ODs).
4114 // 3. Perform NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID RM control for
4115 // getting the I2C port data.
4116 //
4117 // With these restrictions, we should only end up with at most one OD
4118 // per DP connector.
4119 //
4120
4121 if (pNv->rmapi.hDisp == 0)
4122 {
4123 return;
4124 }
4125
4126 systemGetSupportedParams.subDeviceInstance = 0;
4127 status = pRmApi->Control(pRmApi, pNv->rmapi.hClient, pNv->rmapi.hDisp,
4128 NV0073_CTRL_CMD_SYSTEM_GET_SUPPORTED,
4129 &systemGetSupportedParams, sizeof(systemGetSupportedParams));
4130
4131 if (status != NV_OK)
4132 {
4133 return;
4134 }
4135
4136 for (displayMask = systemGetSupportedParams.displayMask;
4137 displayMask != 0;
4138 displayMask &= ~LOWESTBIT(displayMask))
4139 {
4140 NV0073_CTRL_SPECIFIC_OR_GET_INFO_PARAMS orInfoParams = { 0 };
4141 NvU32 displayId = LOWESTBIT(displayMask);
4142
4143 orInfoParams.subDeviceInstance = 0;
4144 orInfoParams.displayId = displayId;
4145
4146 status = pRmApi->Control(pRmApi, pNv->rmapi.hClient, pNv->rmapi.hDisp,
4147 NV0073_CTRL_CMD_SPECIFIC_OR_GET_INFO,
4148 &orInfoParams, sizeof(orInfoParams));
4149
4150 if ((status == NV_OK) &&
4151 (orInfoParams.type == NV0073_CTRL_SPECIFIC_OR_TYPE_SOR) &&
4152 ((orInfoParams.protocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_A) ||
4153 (orInfoParams.protocol == NV0073_CTRL_SPECIFIC_OR_PROTOCOL_SOR_DP_B)) &&
4154 (orInfoParams.location == NV0073_CTRL_SPECIFIC_OR_LOCATION_CHIP) &&
4155 (!orInfoParams.bIsDispDynamic))
4156 {
4157 NV0073_CTRL_SPECIFIC_GET_I2C_PORTID_PARAMS i2cPortIdParams = { 0 };
4158
4159 i2cPortIdParams.subDeviceInstance = 0;
4160 i2cPortIdParams.displayId = displayId;
4161
4162 status = pRmApi->Control(pRmApi,
4163 pNv->rmapi.hClient,
4164 pNv->rmapi.hDisp,
4165 NV0073_CTRL_CMD_SPECIFIC_GET_I2C_PORTID,
4166 &i2cPortIdParams,
4167 sizeof(i2cPortIdParams));
4168
4169 if ((status == NV_OK) &&
4170 (i2cPortIdParams.ddcPortId != NV0073_CTRL_SPECIFIC_I2C_PORT_NONE))
4171 {
4172 rm_i2c_add_adapter(pNv, i2cPortIdParams.ddcPortId - 1, displayId);
4173 }
4174 }
4175 }
4176 }
4177
rm_i2c_remove_adapters(nvidia_stack_t * sp,nv_state_t * pNv)4178 void NV_API_CALL rm_i2c_remove_adapters(
4179 nvidia_stack_t *sp,
4180 nv_state_t *pNv
4181 )
4182 {
4183 //
4184 // Cycle through all adapter entries, and first remove the adapter
4185 // from the list from the kernel, then remove the i2c adapter
4186 // list once that is completed. This should only be used from exit
4187 // module time. Otherwise it could fail to remove some of the
4188 // kernel adapters and subsequent transfer requests would result
4189 // in crashes.
4190 //
4191 NvU32 x = 0;
4192 nv_priv_t *pNvp = NV_GET_NV_PRIV(pNv);
4193 NvU32 numDispId;
4194
4195 for (x = 0; x < MAX_I2C_ADAPTERS; x++)
4196 {
4197 if (pNvp->i2c_adapters[x].pOsAdapter != NULL)
4198 {
4199 nv_i2c_del_adapter(pNv, pNvp->i2c_adapters[x].pOsAdapter);
4200
4201 pNvp->i2c_adapters[x].pOsAdapter = NULL;
4202 pNvp->i2c_adapters[x].port = 0;
4203 for (numDispId = 0; numDispId < MAX_DISP_ID_PER_ADAPTER; numDispId++)
4204 {
4205 pNvp->i2c_adapters[x].displayId[numDispId] = INVALID_DISP_ID;
4206 }
4207 }
4208 }
4209 }
4210
rm_i2c_is_smbus_capable(nvidia_stack_t * sp,nv_state_t * pNv,void * pI2cAdapter)4211 NvBool NV_API_CALL rm_i2c_is_smbus_capable(
4212 nvidia_stack_t *sp,
4213 nv_state_t *pNv,
4214 void *pI2cAdapter
4215 )
4216 {
4217 THREAD_STATE_NODE threadState;
4218 nv_priv_t *pNvp = NV_GET_NV_PRIV(pNv);
4219 NV_STATUS rmStatus = NV_OK;
4220 OBJGPU *pGpu = NULL;
4221 NvBool unlock = NV_FALSE;
4222 NvU32 x;
4223 NvBool ret = NV_FALSE;
4224 void *fp;
4225 NvU32 numDispId = 0;
4226
4227 NV_ENTER_RM_RUNTIME(sp,fp);
4228 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
4229
4230 if (pNvp->flags & NV_INIT_FLAG_PUBLIC_I2C)
4231 {
4232 // LOCK: acquire API lock
4233 if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_I2C)) != NV_OK)
4234 goto semafinish;
4235
4236 unlock = NV_TRUE;
4237 }
4238
4239 pGpu = NV_GET_NV_PRIV_PGPU(pNv);
4240
4241 if (!pGpu)
4242 {
4243 goto semafinish;
4244 }
4245
4246 for (x = 0; x < MAX_I2C_ADAPTERS; x++)
4247 {
4248 if (pNvp->i2c_adapters[x].pOsAdapter == pI2cAdapter)
4249 {
4250 break;
4251 }
4252 }
4253
4254 if (x == MAX_I2C_ADAPTERS)
4255 {
4256 goto semafinish;
4257 }
4258
4259 // we do not support smbus functions on i2c-over-DPAUX
4260 for (numDispId = 0; numDispId < MAX_DISP_ID_PER_ADAPTER; numDispId++)
4261 {
4262 if (pNvp->i2c_adapters[x].displayId[numDispId] == 0x0)
4263 {
4264 ret = NV_TRUE;
4265 }
4266 }
4267
4268 semafinish:
4269 if (unlock)
4270 {
4271 // UNLOCK: release API lock
4272 rmapiLockRelease();
4273 }
4274
4275 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
4276 NV_EXIT_RM_RUNTIME(sp,fp);
4277
4278 return ret;
4279 }
4280
rm_perform_version_check(nvidia_stack_t * sp,void * pData,NvU32 dataSize)4281 NV_STATUS NV_API_CALL rm_perform_version_check(
4282 nvidia_stack_t *sp,
4283 void *pData,
4284 NvU32 dataSize
4285 )
4286 {
4287 THREAD_STATE_NODE threadState;
4288 NV_STATUS rmStatus;
4289 void *fp;
4290
4291 NV_ENTER_RM_RUNTIME(sp,fp);
4292 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
4293
4294 rmStatus = RmPerformVersionCheck(pData, dataSize);
4295
4296 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
4297 NV_EXIT_RM_RUNTIME(sp,fp);
4298
4299 return rmStatus;
4300 }
4301
4302 //
4303 // Handles the Power Source Change event(AC/DC) for Notebooks.
4304 // Notebooks from Maxwell have only one Gpu, so this functions grabs first Gpu
4305 // from GpuMgr and call subdevice RmControl.
4306 //
rm_power_source_change_event(nvidia_stack_t * sp,NvU32 event_val)4307 void NV_API_CALL rm_power_source_change_event(
4308 nvidia_stack_t *sp,
4309 NvU32 event_val
4310 )
4311 {
4312 THREAD_STATE_NODE threadState;
4313 void *fp;
4314 nv_state_t *nv;
4315 OBJGPU *pGpu = gpumgrGetGpu(0);
4316 NV_STATUS rmStatus = NV_OK;
4317
4318 NV_ENTER_RM_RUNTIME(sp,fp);
4319 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
4320
4321 // LOCK: acquire API lock
4322 if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_EVENT)) == NV_OK)
4323 {
4324 if (pGpu != NULL)
4325 {
4326 nv = NV_GET_NV_STATE(pGpu);
4327 if ((rmStatus = os_ref_dynamic_power(nv, NV_DYNAMIC_PM_FINE)) ==
4328 NV_OK)
4329 {
4330 // LOCK: acquire GPU lock
4331 if ((rmStatus = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_EVENT)) ==
4332 NV_OK)
4333 {
4334 rmStatus = RmPowerSourceChangeEvent(nv, event_val);
4335
4336 // UNLOCK: release GPU lock
4337 rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL);
4338 }
4339 os_unref_dynamic_power(nv, NV_DYNAMIC_PM_FINE);
4340 }
4341 // UNLOCK: release API lock
4342 rmapiLockRelease();
4343 }
4344 }
4345
4346 if (rmStatus != NV_OK)
4347 {
4348 NV_PRINTF(LEVEL_ERROR,
4349 "%s: Failed to handle Power Source change event, status=0x%x\n",
4350 __FUNCTION__, rmStatus);
4351 }
4352
4353 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
4354 NV_EXIT_RM_RUNTIME(sp,fp);
4355 }
4356
rm_request_dnotifier_state(nv_stack_t * sp,nv_state_t * pNv)4357 void NV_API_CALL rm_request_dnotifier_state(
4358 nv_stack_t *sp,
4359 nv_state_t *pNv
4360 )
4361 {
4362 nv_priv_t *nvp = NV_GET_NV_PRIV(pNv);
4363
4364 if (nvp->b_mobile_config_enabled)
4365 {
4366 THREAD_STATE_NODE threadState;
4367 void *fp;
4368 GPU_MASK gpuMask;
4369
4370 NV_ENTER_RM_RUNTIME(sp,fp);
4371 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
4372
4373 // LOCK: acquire API lock
4374 if ((rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_ACPI)) == NV_OK)
4375 {
4376 OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(pNv);
4377
4378 // LOCK: acquire per device lock
4379 if ((pGpu != NULL) &&
4380 ((rmGpuGroupLockAcquire(pGpu->gpuInstance, GPU_LOCK_GRP_SUBDEVICE,
4381 GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_ACPI,
4382 &gpuMask)) == NV_OK))
4383 {
4384 RmRequestDNotifierState(pNv);
4385
4386 // UNLOCK: release per device lock
4387 rmGpuGroupLockRelease(gpuMask, GPUS_LOCK_FLAGS_NONE);
4388 }
4389
4390 // UNLOCK: release API lock
4391 rmapiLockRelease();
4392 }
4393
4394 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
4395 NV_EXIT_RM_RUNTIME(sp,fp);
4396 }
4397 }
4398
rm_p2p_dma_map_pages(nvidia_stack_t * sp,nv_dma_device_t * peer,NvU8 * pGpuUuid,NvU64 pageSize,NvU32 pageCount,NvU64 * pDmaAddresses,void ** ppPriv)4399 NV_STATUS NV_API_CALL rm_p2p_dma_map_pages(
4400 nvidia_stack_t *sp,
4401 nv_dma_device_t *peer,
4402 NvU8 *pGpuUuid,
4403 NvU64 pageSize,
4404 NvU32 pageCount,
4405 NvU64 *pDmaAddresses,
4406 void **ppPriv
4407 )
4408 {
4409 THREAD_STATE_NODE threadState;
4410 NV_STATUS rmStatus;
4411 void *fp;
4412
4413 if (ppPriv == NULL)
4414 {
4415 return NV_ERR_INVALID_ARGUMENT;
4416 }
4417
4418 *ppPriv = NULL;
4419
4420 NV_ENTER_RM_RUNTIME(sp,fp);
4421 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
4422
4423 if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK)
4424 {
4425 OBJGPU *pGpu = gpumgrGetGpuFromUuid(pGpuUuid,
4426 DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _TYPE, _SHA1) |
4427 DRF_DEF(2080_GPU_CMD, _GPU_GET_GID_FLAGS, _FORMAT, _BINARY));
4428 if (pGpu == NULL)
4429 {
4430 rmStatus = NV_ERR_INVALID_ARGUMENT;
4431 }
4432 else
4433 {
4434 NvU32 i;
4435
4436 if (pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING))
4437 {
4438 rmStatus = RmP2PDmaMapPagesCoherent(peer, pageSize, pageCount,
4439 pDmaAddresses, ppPriv);
4440 }
4441 else
4442 {
4443 nv_state_t *nv = NV_GET_NV_STATE(pGpu);
4444 for (i = 0; i < pageCount; i++)
4445 {
4446 // Peer mappings through this API are always via BAR1
4447 rmStatus = nv_dma_map_peer(peer, nv->dma_dev, 0x1,
4448 pageSize / os_page_size,
4449 &pDmaAddresses[i]);
4450 if ((rmStatus != NV_OK) && (i > 0))
4451 {
4452 NvU32 j;
4453 for (j = i - 1; j < pageCount; j--)
4454 {
4455 nv_dma_unmap_peer(peer, pageSize / os_page_size,
4456 pDmaAddresses[j]);
4457 }
4458 }
4459 }
4460 }
4461 }
4462
4463 rmapiLockRelease();
4464 }
4465
4466 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
4467 NV_EXIT_RM_RUNTIME(sp,fp);
4468
4469 return rmStatus;
4470 }
4471
rm_p2p_get_gpu_info(nvidia_stack_t * sp,NvU64 gpuVirtualAddress,NvU64 length,NvU8 ** ppGpuUuid,void ** ppGpuInfo)4472 NV_STATUS NV_API_CALL rm_p2p_get_gpu_info(
4473 nvidia_stack_t *sp,
4474 NvU64 gpuVirtualAddress,
4475 NvU64 length,
4476 NvU8 **ppGpuUuid,
4477 void **ppGpuInfo
4478 )
4479 {
4480 THREAD_STATE_NODE threadState;
4481 NV_STATUS rmStatus;
4482 void *fp;
4483
4484 NV_ENTER_RM_RUNTIME(sp,fp);
4485 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
4486
4487 // LOCK: acquire API lock
4488 rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P);
4489 if (rmStatus == NV_OK)
4490 {
4491 OBJGPU *pGpu;
4492 rmStatus = RmP2PGetGpuByAddress(gpuVirtualAddress,
4493 length,
4494 &pGpu);
4495 if (rmStatus == NV_OK)
4496 {
4497 nv_state_t *nv = NV_GET_NV_STATE(pGpu);
4498 const NvU8 *pGid;
4499
4500 pGid = RmGetGpuUuidRaw(nv);
4501 if (pGid == NULL)
4502 {
4503 rmStatus = NV_ERR_GPU_UUID_NOT_FOUND;
4504 }
4505 else
4506 {
4507 rmStatus = os_alloc_mem((void **)ppGpuUuid, GPU_UUID_LEN);
4508 if (rmStatus == NV_OK)
4509 {
4510 os_mem_copy(*ppGpuUuid, pGid, GPU_UUID_LEN);
4511 }
4512 }
4513
4514 *ppGpuInfo = (void *) pGpu;
4515 }
4516
4517 // UNLOCK: release API lock
4518 rmapiLockRelease();
4519 }
4520
4521 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
4522 NV_EXIT_RM_RUNTIME(sp,fp);
4523
4524 return rmStatus;
4525 }
4526
rm_p2p_get_pages_persistent(nvidia_stack_t * sp,NvU64 gpuVirtualAddress,NvU64 length,void ** p2pObject,NvU64 * pPhysicalAddresses,NvU32 * pEntries,void * pPlatformData,void * pGpuInfo)4527 NV_STATUS NV_API_CALL rm_p2p_get_pages_persistent(
4528 nvidia_stack_t *sp,
4529 NvU64 gpuVirtualAddress,
4530 NvU64 length,
4531 void **p2pObject,
4532 NvU64 *pPhysicalAddresses,
4533 NvU32 *pEntries,
4534 void *pPlatformData,
4535 void *pGpuInfo
4536 )
4537 {
4538 THREAD_STATE_NODE threadState;
4539 NV_STATUS rmStatus;
4540 void *fp;
4541
4542 NV_ENTER_RM_RUNTIME(sp,fp);
4543 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
4544
4545 // LOCK: acquire API lock
4546 if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK)
4547 {
4548 rmStatus = RmP2PGetPagesPersistent(gpuVirtualAddress,
4549 length,
4550 p2pObject,
4551 pPhysicalAddresses,
4552 pEntries,
4553 pPlatformData,
4554 pGpuInfo);
4555 // UNLOCK: release API lock
4556 rmapiLockRelease();
4557 }
4558
4559 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
4560 NV_EXIT_RM_RUNTIME(sp,fp);
4561
4562 return rmStatus;
4563 }
4564
rm_p2p_get_pages(nvidia_stack_t * sp,NvU64 p2pToken,NvU32 vaSpaceToken,NvU64 gpuVirtualAddress,NvU64 length,NvU64 * pPhysicalAddresses,NvU32 * pWreqMbH,NvU32 * pRreqMbH,NvU32 * pEntries,NvU8 ** ppGpuUuid,void * pPlatformData)4565 NV_STATUS NV_API_CALL rm_p2p_get_pages(
4566 nvidia_stack_t *sp,
4567 NvU64 p2pToken,
4568 NvU32 vaSpaceToken,
4569 NvU64 gpuVirtualAddress,
4570 NvU64 length,
4571 NvU64 *pPhysicalAddresses,
4572 NvU32 *pWreqMbH,
4573 NvU32 *pRreqMbH,
4574 NvU32 *pEntries,
4575 NvU8 **ppGpuUuid,
4576 void *pPlatformData
4577 )
4578 {
4579 THREAD_STATE_NODE threadState;
4580 NV_STATUS rmStatus;
4581 void *fp;
4582
4583 NV_ENTER_RM_RUNTIME(sp,fp);
4584 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
4585
4586 // LOCK: acquire API lock
4587 if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK)
4588 {
4589 OBJGPU *pGpu;
4590 rmStatus = RmP2PGetPagesWithoutCallbackRegistration(p2pToken,
4591 vaSpaceToken,
4592 gpuVirtualAddress,
4593 length,
4594 pPhysicalAddresses,
4595 pWreqMbH,
4596 pRreqMbH,
4597 pEntries,
4598 &pGpu,
4599 pPlatformData);
4600 if (rmStatus == NV_OK)
4601 {
4602 nv_state_t *nv = NV_GET_NV_STATE(pGpu);
4603 const NvU8 *pGid;
4604
4605 pGid = RmGetGpuUuidRaw(nv);
4606 if (pGid == NULL)
4607 {
4608 NV_ASSERT_OK(RmP2PPutPages(p2pToken, vaSpaceToken,
4609 gpuVirtualAddress,
4610 pPlatformData));
4611 rmStatus = NV_ERR_GENERIC;
4612 }
4613 else
4614 {
4615 rmStatus = os_alloc_mem((void **)ppGpuUuid, GPU_UUID_LEN);
4616 if (rmStatus == NV_OK)
4617 os_mem_copy(*ppGpuUuid, pGid, GPU_UUID_LEN);
4618 }
4619 }
4620
4621 // UNLOCK: release API lock
4622 rmapiLockRelease();
4623 }
4624
4625 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
4626 NV_EXIT_RM_RUNTIME(sp,fp);
4627
4628 return rmStatus;
4629 }
4630
rm_p2p_register_callback(nvidia_stack_t * sp,NvU64 p2pToken,NvU64 gpuVirtualAddress,NvU64 length,void * pPlatformData,void (* pFreeCallback)(void * pData),void * pData)4631 NV_STATUS NV_API_CALL rm_p2p_register_callback(
4632 nvidia_stack_t *sp,
4633 NvU64 p2pToken,
4634 NvU64 gpuVirtualAddress,
4635 NvU64 length,
4636 void *pPlatformData,
4637 void (*pFreeCallback)(void *pData),
4638 void *pData
4639 )
4640 {
4641 THREAD_STATE_NODE threadState;
4642 NV_STATUS rmStatus;
4643 void *fp;
4644
4645 NV_ENTER_RM_RUNTIME(sp,fp);
4646 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
4647
4648 // LOCK: acquire API lock
4649 if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK)
4650 {
4651 rmStatus = RmP2PRegisterCallback(p2pToken, gpuVirtualAddress, length,
4652 pPlatformData, pFreeCallback, pData);
4653
4654 // UNLOCK: release API lock
4655 rmapiLockRelease();
4656 }
4657
4658 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
4659 NV_EXIT_RM_RUNTIME(sp,fp);
4660
4661 return rmStatus;
4662 }
4663
rm_p2p_put_pages_persistent(nvidia_stack_t * sp,void * p2pObject,void * pKey)4664 NV_STATUS NV_API_CALL rm_p2p_put_pages_persistent(
4665 nvidia_stack_t *sp,
4666 void *p2pObject,
4667 void *pKey
4668 )
4669 {
4670 THREAD_STATE_NODE threadState;
4671 NV_STATUS rmStatus;
4672 void *fp;
4673
4674 NV_ENTER_RM_RUNTIME(sp,fp);
4675 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
4676
4677 // LOCK: acquire API lock
4678 if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK)
4679 {
4680 rmStatus = RmP2PPutPagesPersistent(p2pObject, pKey);
4681
4682 // UNLOCK: release API lock
4683 rmapiLockRelease();
4684 }
4685
4686 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
4687 NV_EXIT_RM_RUNTIME(sp,fp);
4688
4689 return rmStatus;
4690 }
4691
rm_p2p_put_pages(nvidia_stack_t * sp,NvU64 p2pToken,NvU32 vaSpaceToken,NvU64 gpuVirtualAddress,void * pKey)4692 NV_STATUS NV_API_CALL rm_p2p_put_pages(
4693 nvidia_stack_t *sp,
4694 NvU64 p2pToken,
4695 NvU32 vaSpaceToken,
4696 NvU64 gpuVirtualAddress,
4697 void *pKey
4698 )
4699 {
4700 THREAD_STATE_NODE threadState;
4701 NV_STATUS rmStatus;
4702 void *fp;
4703
4704 NV_ENTER_RM_RUNTIME(sp,fp);
4705 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
4706
4707 // LOCK: acquire API lock
4708 if ((rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_P2P)) == NV_OK)
4709 {
4710 rmStatus = RmP2PPutPages(p2pToken,
4711 vaSpaceToken,
4712 gpuVirtualAddress,
4713 pKey);
4714
4715 // UNLOCK: release API lock
4716 rmapiLockRelease();
4717 }
4718
4719 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
4720 NV_EXIT_RM_RUNTIME(sp,fp);
4721
4722 return rmStatus;
4723 }
4724
rm_get_gpu_uuid(nvidia_stack_t * sp,nv_state_t * nv)4725 char* NV_API_CALL rm_get_gpu_uuid(
4726 nvidia_stack_t *sp,
4727 nv_state_t *nv
4728 )
4729 {
4730 NV_STATUS rmStatus;
4731 const NvU8 *pGid;
4732 char *pGidString;
4733
4734 THREAD_STATE_NODE threadState;
4735 void *fp;
4736
4737 NV_ENTER_RM_RUNTIME(sp,fp);
4738 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
4739
4740 // Allocate space for the ASCII string
4741 rmStatus = os_alloc_mem((void **)&pGidString, GPU_UUID_ASCII_LEN);
4742 if (rmStatus != NV_OK)
4743 {
4744 pGidString = NULL;
4745 goto done;
4746 }
4747
4748 // Get the raw UUID; note the pGid is cached, so we do not need to free it
4749 pGid = RmGetGpuUuidRaw(nv);
4750
4751 if (pGid != NULL)
4752 {
4753 // Convert the raw UUID to ASCII
4754 rmStatus = RmGpuUuidRawToString(pGid, pGidString, GPU_UUID_ASCII_LEN);
4755 if (rmStatus != NV_OK)
4756 {
4757 os_free_mem(pGidString);
4758 pGidString = NULL;
4759 }
4760 }
4761 else
4762 {
4763 const char *pTmpString = "GPU-???????\?-???\?-???\?-???\?-????????????";
4764
4765 portStringCopy(pGidString, GPU_UUID_ASCII_LEN, pTmpString,
4766 portStringLength(pTmpString) + 1);
4767 }
4768
4769 done:
4770 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
4771 NV_EXIT_RM_RUNTIME(sp,fp);
4772
4773 return pGidString;
4774 }
4775
4776 //
4777 // This function will return the UUID in the binary format
4778 //
rm_get_gpu_uuid_raw(nvidia_stack_t * sp,nv_state_t * nv)4779 const NvU8 * NV_API_CALL rm_get_gpu_uuid_raw(
4780 nvidia_stack_t *sp,
4781 nv_state_t *nv)
4782 {
4783 THREAD_STATE_NODE threadState;
4784 void *fp;
4785 const NvU8 *pGid;
4786
4787 NV_ENTER_RM_RUNTIME(sp,fp);
4788 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
4789
4790 pGid = RmGetGpuUuidRaw(nv);
4791
4792 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
4793 NV_EXIT_RM_RUNTIME(sp,fp);
4794
4795 return pGid;
4796 }
4797
rm_set_firmware_logs(nvidia_stack_t * sp,nv_state_t * nv)4798 static void rm_set_firmware_logs(
4799 nvidia_stack_t *sp,
4800 nv_state_t *nv
4801 )
4802 {
4803 void *fp;
4804 NvU32 enableFirmwareLogsRegVal = NV_REG_ENABLE_GPU_FIRMWARE_LOGS_ENABLE_ON_DEBUG;
4805
4806 NV_ENTER_RM_RUNTIME(sp,fp);
4807
4808 (void) RmReadRegistryDword(nv, NV_REG_ENABLE_GPU_FIRMWARE_LOGS,
4809 &enableFirmwareLogsRegVal);
4810 nv->enable_firmware_logs = gpumgrGetRmFirmwareLogsEnabled(enableFirmwareLogsRegVal);
4811 NV_EXIT_RM_RUNTIME(sp,fp);
4812 }
4813
rm_get_is_gsp_capable_vgpu(nvidia_stack_t * sp,nv_state_t * nv)4814 static NvBool rm_get_is_gsp_capable_vgpu(
4815 nvidia_stack_t *sp,
4816 nv_state_t *nv
4817 )
4818 {
4819 void *fp;
4820 THREAD_STATE_NODE threadState;
4821 NvBool isVgpu = NV_FALSE;
4822 OBJSYS *pSys = SYS_GET_INSTANCE();
4823 OBJHYPERVISOR *pHypervisor = SYS_GET_HYPERVISOR(pSys);
4824
4825 NV_ENTER_RM_RUNTIME(sp,fp);
4826 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
4827
4828 if ((pHypervisor != NULL) && pHypervisor->bIsHVMGuest)
4829 {
4830 GPUHWREG *reg_mapping;
4831 reg_mapping = osMapKernelSpace(nv->regs->cpu_address,
4832 os_page_size,
4833 NV_MEMORY_UNCACHED,
4834 NV_PROTECT_READABLE);
4835
4836 if (reg_mapping != NULL)
4837 {
4838 NvU32 pmc_boot_1 = NV_PRIV_REG_RD32(reg_mapping, NV_PMC_BOOT_1);
4839 NvU32 pmc_boot_42 = NV_PRIV_REG_RD32(reg_mapping, NV_PMC_BOOT_42);
4840
4841 osUnmapKernelSpace(reg_mapping, os_page_size);
4842
4843 if (FLD_TEST_DRF(_PMC, _BOOT_1, _VGPU, _VF, pmc_boot_1) &&
4844 gpumgrIsVgxRmFirmwareCapableChip(pmc_boot_42))
4845 {
4846 isVgpu = NV_TRUE;
4847 }
4848 }
4849 }
4850 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
4851 NV_EXIT_RM_RUNTIME(sp,fp);
4852 return isVgpu;
4853 }
4854
rm_set_rm_firmware_requested(nvidia_stack_t * sp,nv_state_t * nv)4855 void NV_API_CALL rm_set_rm_firmware_requested(
4856 nvidia_stack_t *sp,
4857 nv_state_t *nv
4858 )
4859 {
4860 nv->request_firmware = NV_TRUE;
4861 nv->allow_fallback_to_monolithic_rm = NV_FALSE;
4862 if (rm_get_is_gsp_capable_vgpu(sp, nv))
4863 {
4864 nv->request_firmware = NV_FALSE;
4865 }
4866
4867 // Check if we want firmware logs
4868 if (nv->request_firmware)
4869 rm_set_firmware_logs(sp, nv);
4870 }
4871
4872 //
4873 // This function will be called by nv_procfs_read_gpu_info().
4874 // nv_procfs_read_gpu_info() will not print the 'GPU Firmware:' field at
4875 // all if the 'version' string is empty.
4876 //
4877 // If GSP is enabled (firmware was requested), this function needs to return
4878 // the firmware version or "NA" in case of any errors.
4879 //
4880 // If GSP is not enabled (firmware was not requested), this function needs to
4881 // return the empty string, regardless of error cases.
4882 //
rm_get_firmware_version(nvidia_stack_t * sp,nv_state_t * nv,char * version,NvLength version_length)4883 void NV_API_CALL rm_get_firmware_version(
4884 nvidia_stack_t *sp,
4885 nv_state_t *nv,
4886 char *version,
4887 NvLength version_length
4888 )
4889 {
4890 NV2080_CTRL_GSP_GET_FEATURES_PARAMS params = { 0 };
4891 RM_API *pRmApi;
4892 THREAD_STATE_NODE threadState;
4893 NV_STATUS rmStatus = NV_OK;
4894 void *fp;
4895
4896 NV_ENTER_RM_RUNTIME(sp,fp);
4897
4898 pRmApi = RmUnixRmApiPrologue(nv, &threadState, RM_LOCK_MODULES_GPU);
4899 if (pRmApi != NULL)
4900 {
4901 rmStatus = pRmApi->Control(pRmApi,
4902 nv->rmapi.hClient,
4903 nv->rmapi.hSubDevice,
4904 NV2080_CTRL_CMD_GSP_GET_FEATURES,
4905 ¶ms,
4906 sizeof(params));
4907
4908 RmUnixRmApiEpilogue(nv, &threadState);
4909 }
4910 else
4911 {
4912 rmStatus = NV_ERR_INVALID_STATE;
4913 }
4914
4915 if (rmStatus != NV_OK)
4916 {
4917 if (RMCFG_FEATURE_GSP_CLIENT_RM && nv->request_firmware)
4918 {
4919 const char *pTmpString = "N/A";
4920 portStringCopy(version, version_length, pTmpString, portStringLength(pTmpString) + 1);
4921 }
4922 NV_PRINTF(LEVEL_INFO,
4923 "%s: Failed to query gpu build versions, status=0x%x\n",
4924 __FUNCTION__,
4925 rmStatus);
4926 goto finish;
4927 }
4928 portMemCopy(version, version_length, params.firmwareVersion, sizeof(params.firmwareVersion));
4929
4930 finish:
4931 NV_EXIT_RM_RUNTIME(sp,fp);
4932 }
4933
4934 //
4935 // disable GPU SW state persistence
4936 //
4937
rm_disable_gpu_state_persistence(nvidia_stack_t * sp,nv_state_t * nv)4938 void NV_API_CALL rm_disable_gpu_state_persistence(nvidia_stack_t *sp, nv_state_t *nv)
4939 {
4940 THREAD_STATE_NODE threadState;
4941 OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv);
4942 void *fp;
4943
4944 NV_ENTER_RM_RUNTIME(sp,fp);
4945 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
4946
4947 pGpu->setProperty(pGpu, PDB_PROP_GPU_PERSISTENT_SW_STATE, NV_FALSE);
4948 osModifyGpuSwStatePersistence(pGpu->pOsGpuInfo, NV_FALSE);
4949
4950 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
4951 NV_EXIT_RM_RUNTIME(sp,fp);
4952 }
4953
rm_log_gpu_crash(nv_stack_t * sp,nv_state_t * nv)4954 NV_STATUS NV_API_CALL rm_log_gpu_crash(
4955 nv_stack_t *sp,
4956 nv_state_t *nv
4957 )
4958 {
4959 THREAD_STATE_NODE threadState;
4960 NV_STATUS status;
4961 void *fp;
4962
4963 NV_ENTER_RM_RUNTIME(sp,fp);
4964 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
4965
4966 if ((status = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DIAG)) == NV_OK)
4967 {
4968 OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv);
4969
4970 if ((pGpu != NULL) &&
4971 ((status = rmGpuLocksAcquire(GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_DIAG)) == NV_OK))
4972 {
4973 status = RmLogGpuCrash(pGpu);
4974
4975 rmGpuLocksRelease(GPUS_LOCK_FLAGS_NONE, NULL);
4976 }
4977 rmapiLockRelease();
4978 }
4979
4980 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
4981 NV_EXIT_RM_RUNTIME(sp,fp);
4982
4983 return status;
4984 }
4985
rm_kernel_rmapi_op(nvidia_stack_t * sp,void * ops_cmd)4986 void NV_API_CALL rm_kernel_rmapi_op(nvidia_stack_t *sp, void *ops_cmd)
4987 {
4988 nvidia_kernel_rmapi_ops_t *ops = ops_cmd;
4989 void *fp;
4990
4991 NV_ENTER_RM_RUNTIME(sp,fp);
4992
4993 switch (ops->op)
4994 {
4995 case NV01_FREE:
4996 Nv01FreeKernel(&ops->params.free);
4997 break;
4998
4999 case NV01_ALLOC_MEMORY:
5000 Nv01AllocMemoryKernel(&ops->params.allocMemory64);
5001 break;
5002
5003 case NV04_ALLOC:
5004 Nv04AllocKernel(&ops->params.alloc);
5005 break;
5006
5007 case NV04_VID_HEAP_CONTROL:
5008 Nv04VidHeapControlKernel(ops->params.pVidHeapControl);
5009 break;
5010
5011 case NV04_MAP_MEMORY:
5012 Nv04MapMemoryKernel(&ops->params.mapMemory);
5013 break;
5014
5015 case NV04_UNMAP_MEMORY:
5016 Nv04UnmapMemoryKernel(&ops->params.unmapMemory);
5017 break;
5018
5019 case NV04_ALLOC_CONTEXT_DMA:
5020 Nv04AllocContextDmaKernel(&ops->params.allocContextDma2);
5021 break;
5022
5023 case NV04_MAP_MEMORY_DMA:
5024 Nv04MapMemoryDmaKernel(&ops->params.mapMemoryDma);
5025 break;
5026
5027 case NV04_UNMAP_MEMORY_DMA:
5028 Nv04UnmapMemoryDmaKernel(&ops->params.unmapMemoryDma);
5029 break;
5030
5031 case NV04_BIND_CONTEXT_DMA:
5032 Nv04BindContextDmaKernel(&ops->params.bindContextDma);
5033 break;
5034
5035 case NV04_CONTROL:
5036 Nv04ControlKernel(&ops->params.control);
5037 break;
5038
5039 case NV04_DUP_OBJECT:
5040 Nv04DupObjectKernel(&ops->params.dupObject);
5041 break;
5042
5043 case NV04_SHARE:
5044 Nv04ShareKernel(&ops->params.share);
5045 break;
5046
5047 case NV04_ADD_VBLANK_CALLBACK:
5048 Nv04AddVblankCallbackKernel(&ops->params.addVblankCallback);
5049 break;
5050 }
5051
5052 NV_EXIT_RM_RUNTIME(sp,fp);
5053 }
5054
5055 //
5056 // ACPI method (NVIF/_DSM/WMMX/MXM*/etc.) initialization
5057 //
RmInitAcpiMethods(OBJOS * pOS,OBJSYS * pSys,OBJGPU * pGpu)5058 void RmInitAcpiMethods(OBJOS *pOS, OBJSYS *pSys, OBJGPU *pGpu)
5059 {
5060 NvU32 handlesPresent;
5061
5062 if (pSys->getProperty(pSys, PDB_PROP_SYS_NVIF_INIT_DONE))
5063 return;
5064
5065 nv_acpi_methods_init(&handlesPresent);
5066
5067 // Check if NVPCF _DSM functions are implemented under NVPCF or GPU device scope.
5068 RmCheckNvpcfDsmScope(pGpu);
5069 acpiDsmInit(pGpu);
5070 }
5071
5072 //
5073 // ACPI method (NVIF/_DSM/WMMX/MXM*/etc.) teardown
5074 //
RmUnInitAcpiMethods(OBJSYS * pSys)5075 void RmUnInitAcpiMethods(OBJSYS *pSys)
5076 {
5077 pSys->setProperty(pSys, PDB_PROP_SYS_NVIF_INIT_DONE, NV_FALSE);
5078
5079 nv_acpi_methods_uninit();
5080 }
5081
5082 //
5083 // Converts an array of OS page address to an array of RM page addresses.This
5084 // assumes that:
5085 // (1) The pteArray is at least pageCount entries large,
5086 // (2) The pageCount is given in RM pages, and
5087 // (3) The OS page entries start at index 0.
5088 //
RmInflateOsToRmPageArray(RmPhysAddr * pteArray,NvU64 pageCount)5089 void RmInflateOsToRmPageArray(RmPhysAddr *pteArray, NvU64 pageCount)
5090 {
5091 NvUPtr osPageIdx, osPageOffset;
5092 NvU64 i;
5093
5094 //
5095 // We can do the translation in place by moving backwards, since there
5096 // will always be more RM pages than OS pages
5097 //
5098 for (i = pageCount - 1; i != NV_U64_MAX; i--)
5099 {
5100 osPageIdx = i >> NV_RM_TO_OS_PAGE_SHIFT;
5101 osPageOffset = (i & ((1 << NV_RM_TO_OS_PAGE_SHIFT) - 1)) *
5102 NV_RM_PAGE_SIZE;
5103 pteArray[i] = pteArray[osPageIdx] + osPageOffset;
5104 }
5105 }
5106
RmDeflateRmToOsPageArray(RmPhysAddr * pteArray,NvU64 pageCount)5107 void RmDeflateRmToOsPageArray(RmPhysAddr *pteArray, NvU64 pageCount)
5108 {
5109 NvU64 i;
5110
5111 for (i = 0; i < NV_RM_PAGES_TO_OS_PAGES(pageCount); i++)
5112 {
5113 pteArray[i] = pteArray[(i << NV_RM_TO_OS_PAGE_SHIFT)];
5114 }
5115
5116 // Zero out the rest of the addresses, which are now invalid
5117 portMemSet(pteArray + i, 0, sizeof(*pteArray) * (pageCount - i));
5118 }
5119
5120 NvBool NV_API_CALL
rm_get_device_remove_flag(nvidia_stack_t * sp,NvU32 gpu_id)5121 rm_get_device_remove_flag
5122 (
5123 nvidia_stack_t * sp,
5124 NvU32 gpu_id
5125 )
5126 {
5127 THREAD_STATE_NODE threadState;
5128 void *fp;
5129 NvBool bRemove;
5130
5131 NV_ENTER_RM_RUNTIME(sp,fp);
5132 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
5133
5134 if (gpumgrQueryGpuDrainState(gpu_id, NULL, &bRemove) != NV_OK)
5135 {
5136 bRemove = NV_FALSE;
5137 }
5138
5139 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
5140 NV_EXIT_RM_RUNTIME(sp,fp);
5141 return bRemove;
5142 }
5143
5144 NvBool NV_API_CALL
rm_gpu_need_4k_page_isolation(nv_state_t * nv)5145 rm_gpu_need_4k_page_isolation
5146 (
5147 nv_state_t *nv
5148 )
5149 {
5150 nv_priv_t *nvp = NV_GET_NV_PRIV(nv);
5151
5152 return nvp->b_4k_page_isolation_required;
5153 }
5154
5155 //
5156 // This API updates only the following fields in nv_ioctl_numa_info_t:
5157 // - nid
5158 // - numa_mem_addr
5159 // - numa_mem_size
5160 // - offline_addresses
5161 //
5162 // Rest of the fields should be updated by caller.
rm_get_gpu_numa_info(nvidia_stack_t * sp,nv_state_t * nv,nv_ioctl_numa_info_t * numa_info)5163 NV_STATUS NV_API_CALL rm_get_gpu_numa_info(
5164 nvidia_stack_t *sp,
5165 nv_state_t *nv,
5166 nv_ioctl_numa_info_t *numa_info
5167 )
5168 {
5169 NV2080_CTRL_FB_GET_NUMA_INFO_PARAMS *pParams;
5170 RM_API *pRmApi;
5171 THREAD_STATE_NODE threadState;
5172 void *fp;
5173 NV_STATUS status = NV_OK;
5174
5175 ct_assert(NV_ARRAY_ELEMENTS(numa_info->offline_addresses.addresses) >=
5176 NV_ARRAY_ELEMENTS(pParams->numaOfflineAddresses));
5177
5178 if ((numa_info == NULL) ||
5179 (numa_info->offline_addresses.numEntries >
5180 NV_ARRAY_ELEMENTS(pParams->numaOfflineAddresses)))
5181 {
5182 return NV_ERR_INVALID_ARGUMENT;
5183 }
5184
5185 NV_ENTER_RM_RUNTIME(sp,fp);
5186
5187 pParams = portMemAllocNonPaged(sizeof(*pParams));
5188 if (pParams == NULL)
5189 {
5190 NV_EXIT_RM_RUNTIME(sp,fp);
5191 return NV_ERR_NO_MEMORY;
5192 }
5193
5194 portMemSet(pParams, 0, sizeof(*pParams));
5195 pParams->numaOfflineAddressesCount =
5196 numa_info->offline_addresses.numEntries;
5197
5198 pRmApi = RmUnixRmApiPrologue(nv, &threadState, RM_LOCK_MODULES_MEM);
5199 if (pRmApi == NULL)
5200 {
5201 status = NV_ERR_INVALID_STATE;
5202 goto finish;
5203 }
5204
5205 status = pRmApi->Control(pRmApi, nv->rmapi.hClient, nv->rmapi.hSubDevice,
5206 NV2080_CTRL_CMD_FB_GET_NUMA_INFO,
5207 pParams, sizeof(*pParams));
5208
5209 RmUnixRmApiEpilogue(nv, &threadState);
5210
5211 if (status == NV_OK)
5212 {
5213 NvU32 i;
5214
5215 numa_info->nid = pParams->numaNodeId;
5216 numa_info->numa_mem_addr = pParams->numaMemAddr;
5217 numa_info->numa_mem_size = pParams->numaMemSize;
5218 numa_info->offline_addresses.numEntries =
5219 pParams->numaOfflineAddressesCount;
5220
5221 for (i = 0; i < pParams->numaOfflineAddressesCount; i++)
5222 {
5223 numa_info->offline_addresses.addresses[i] =
5224 pParams->numaOfflineAddresses[i];
5225 }
5226 }
5227
5228 finish:
5229 portMemFree(pParams);
5230
5231 NV_EXIT_RM_RUNTIME(sp,fp);
5232
5233 return status;
5234 }
5235
rm_gpu_numa_online(nvidia_stack_t * sp,nv_state_t * nv)5236 NV_STATUS NV_API_CALL rm_gpu_numa_online(
5237 nvidia_stack_t *sp,
5238 nv_state_t *nv
5239 )
5240 {
5241 NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS params = { 0 };
5242 RM_API *pRmApi;
5243 THREAD_STATE_NODE threadState;
5244 void *fp;
5245 NV_STATUS status = NV_OK;
5246
5247 NV_ENTER_RM_RUNTIME(sp,fp);
5248
5249 pRmApi = RmUnixRmApiPrologue(nv, &threadState, RM_LOCK_MODULES_MEM);
5250 if (pRmApi == NULL)
5251 {
5252 status = NV_ERR_INVALID_STATE;
5253 goto finish;
5254 }
5255
5256 params.bOnline = NV_TRUE;
5257
5258 status = pRmApi->Control(pRmApi, nv->rmapi.hClient, nv->rmapi.hSubDevice,
5259 NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS,
5260 ¶ms, sizeof(params));
5261
5262 RmUnixRmApiEpilogue(nv, &threadState);
5263
5264 finish:
5265 NV_EXIT_RM_RUNTIME(sp,fp);
5266
5267 return status;
5268 }
5269
5270
rm_gpu_numa_offline(nvidia_stack_t * sp,nv_state_t * nv)5271 NV_STATUS NV_API_CALL rm_gpu_numa_offline(
5272 nvidia_stack_t *sp,
5273 nv_state_t *nv
5274 )
5275 {
5276 NV2080_CTRL_FB_UPDATE_NUMA_STATUS_PARAMS params = { 0 };
5277 RM_API *pRmApi;
5278 THREAD_STATE_NODE threadState;
5279 void *fp;
5280 NV_STATUS status = NV_OK;
5281
5282 NV_ENTER_RM_RUNTIME(sp,fp);
5283
5284 pRmApi = RmUnixRmApiPrologue(nv, &threadState, RM_LOCK_MODULES_MEM);
5285 if (pRmApi == NULL)
5286 {
5287 status = NV_ERR_INVALID_STATE;
5288 goto finish;
5289 }
5290
5291 params.bOnline = NV_FALSE;
5292
5293 status = pRmApi->Control(pRmApi, nv->rmapi.hClient,
5294 nv->rmapi.hSubDevice,
5295 NV2080_CTRL_CMD_FB_UPDATE_NUMA_STATUS,
5296 ¶ms, sizeof(params));
5297
5298 RmUnixRmApiEpilogue(nv, &threadState);
5299
5300 finish:
5301 NV_EXIT_RM_RUNTIME(sp,fp);
5302
5303 return status;
5304 }
5305
5306 //
5307 // A device is considered "sequestered" if it has drain state enabled for it.
5308 // The kernel interface layer can use this to check the drain state of a device
5309 // in paths outside of initialization, e.g., when clients attempt to reference
5310 // count the device.
5311 //
rm_is_device_sequestered(nvidia_stack_t * sp,nv_state_t * pNv)5312 NvBool NV_API_CALL rm_is_device_sequestered(
5313 nvidia_stack_t *sp,
5314 nv_state_t *pNv
5315 )
5316 {
5317 THREAD_STATE_NODE threadState;
5318 void *fp;
5319 NvBool bDrain = NV_FALSE;
5320
5321 NV_ENTER_RM_RUNTIME(sp,fp);
5322 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
5323
5324 if (rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU) == NV_OK)
5325 {
5326 //
5327 // If gpumgrQueryGpuDrainState succeeds, bDrain will be set as needed.
5328 // If gpumgrQueryGpuDrainState fails, bDrain will stay false; we assume
5329 // that if core RM can't tell us the drain state, it must not be
5330 // attached and the "sequestered" question is not relevant.
5331 //
5332 (void) gpumgrQueryGpuDrainState(pNv->gpu_id, &bDrain, NULL);
5333
5334 rmapiLockRelease();
5335 }
5336
5337 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
5338 NV_EXIT_RM_RUNTIME(sp,fp);
5339 return bDrain;
5340 }
5341
rm_check_for_gpu_surprise_removal(nvidia_stack_t * sp,nv_state_t * nv)5342 void NV_API_CALL rm_check_for_gpu_surprise_removal(
5343 nvidia_stack_t *sp,
5344 nv_state_t *nv
5345 )
5346 {
5347 THREAD_STATE_NODE threadState;
5348 void *fp;
5349 NV_STATUS rmStatus;
5350
5351 NV_ENTER_RM_RUNTIME(sp,fp);
5352 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
5353
5354 // LOCK: acquire API lock.
5355 if ((rmStatus = rmapiLockAcquire(RMAPI_LOCK_FLAGS_READ, RM_LOCK_MODULES_GPU)) == NV_OK)
5356 {
5357 OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv);
5358
5359 if ((rmStatus = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_GPU)) == NV_OK)
5360 {
5361 osHandleGpuLost(pGpu);
5362 rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL);
5363 }
5364
5365 // UNLOCK: release api lock
5366 rmapiLockRelease();
5367 }
5368
5369 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
5370 NV_EXIT_RM_RUNTIME(sp,fp);
5371 }
5372
rm_set_external_kernel_client_count(nvidia_stack_t * sp,nv_state_t * pNv,NvBool bIncr)5373 NV_STATUS NV_API_CALL rm_set_external_kernel_client_count(
5374 nvidia_stack_t *sp,
5375 nv_state_t *pNv,
5376 NvBool bIncr
5377 )
5378 {
5379 THREAD_STATE_NODE threadState;
5380 void *fp;
5381 OBJGPU *pGpu;
5382 NV_STATUS rmStatus = NV_OK;
5383
5384 NV_ENTER_RM_RUNTIME(sp,fp);
5385 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
5386
5387 pGpu = NV_GET_NV_PRIV_PGPU(pNv);
5388
5389 if (pGpu != NULL)
5390 {
5391 rmStatus = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE,
5392 RM_LOCK_MODULES_GPU);
5393 if (rmStatus == NV_OK)
5394 {
5395 rmStatus = gpuSetExternalKernelClientCount(pGpu, bIncr);
5396 rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL);
5397 }
5398 }
5399
5400 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
5401 NV_EXIT_RM_RUNTIME(sp,fp);
5402
5403 return rmStatus;
5404 }
5405
rm_get_uefi_console_status(nv_state_t * nv)5406 NvBool rm_get_uefi_console_status(
5407 nv_state_t *nv
5408 )
5409 {
5410 NvU32 fbWidth, fbHeight, fbDepth, fbPitch;
5411 NvU64 fbSize;
5412 NvU64 fbBaseAddress = 0;
5413 NvBool bConsoleDevice = NV_FALSE;
5414
5415 //
5416 // nv_get_screen_info() will return dimensions and an address for
5417 // any fbdev driver (e.g., efifb, vesafb, etc).
5418 //
5419 nv_get_screen_info(nv, &fbBaseAddress, &fbWidth, &fbHeight, &fbDepth, &fbPitch, &fbSize);
5420
5421 bConsoleDevice = (fbSize != 0);
5422
5423 return bConsoleDevice;
5424 }
5425
rm_get_uefi_console_size(nv_state_t * nv,NvU64 * pFbBaseAddress)5426 NvU64 rm_get_uefi_console_size(
5427 nv_state_t *nv,
5428 NvU64 *pFbBaseAddress
5429 )
5430 {
5431 NvU32 fbWidth, fbHeight, fbDepth, fbPitch;
5432 NvU64 fbSize;
5433
5434 fbSize = fbWidth = fbHeight = fbDepth = fbPitch = 0;
5435
5436 //
5437 // nv_get_screen_info() will return dimensions and an address for
5438 // any fbdev driver (e.g., efifb, vesafb, etc).
5439 //
5440 nv_get_screen_info(nv, pFbBaseAddress, &fbWidth, &fbHeight, &fbDepth, &fbPitch, &fbSize);
5441
5442 return fbSize;
5443 }
5444
5445 /*
5446 * IOMMU needs to be present on the server to support SR-IOV vGPU, unless
5447 * we have SR-IOV enabled for remote GPU.
5448 */
5449
rm_is_iommu_needed_for_sriov(nvidia_stack_t * sp,nv_state_t * nv)5450 NvBool NV_API_CALL rm_is_iommu_needed_for_sriov(
5451 nvidia_stack_t *sp,
5452 nv_state_t * nv
5453 )
5454 {
5455 OBJGPU *pGpu;
5456 NvU32 data;
5457 NvBool ret = NV_TRUE;
5458 void *fp;
5459
5460 NV_ENTER_RM_RUNTIME(sp,fp);
5461
5462 pGpu = NV_GET_NV_PRIV_PGPU(nv);
5463 if (osReadRegistryDword(pGpu, NV_REG_STR_RM_REMOTE_GPU, &data) == NV_OK)
5464 {
5465 if (data == NV_REG_STR_RM_REMOTE_GPU_ENABLE)
5466 ret = NV_FALSE;
5467 }
5468
5469 NV_EXIT_RM_RUNTIME(sp,fp);
5470
5471 return ret;
5472 }
5473
rm_disable_iomap_wc(void)5474 NvBool NV_API_CALL rm_disable_iomap_wc(void)
5475 {
5476 OBJSYS *pSys = SYS_GET_INSTANCE();
5477 OBJCL *pCl = pSys->pCl;
5478 return pCl->getProperty(pCl, PDB_PROP_CL_DISABLE_IOMAP_WC) == NV_TRUE;
5479 }
5480
5481 //
5482 // Verifies the handle, offset and size and dups hMemory.
5483 // Must be called with API lock and GPU lock held.
5484 //
rm_dma_buf_dup_mem_handle(nvidia_stack_t * sp,nv_state_t * nv,NvHandle hSrcClient,NvHandle hDstClient,NvHandle hDevice,NvHandle hSubdevice,void * pGpuInstanceInfo,NvHandle hMemory,NvU64 offset,NvU64 size,NvHandle * phMemoryDuped,void ** ppStaticMemInfo)5485 NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle(
5486 nvidia_stack_t *sp,
5487 nv_state_t *nv,
5488 NvHandle hSrcClient,
5489 NvHandle hDstClient,
5490 NvHandle hDevice,
5491 NvHandle hSubdevice,
5492 void *pGpuInstanceInfo,
5493 NvHandle hMemory,
5494 NvU64 offset,
5495 NvU64 size,
5496 NvHandle *phMemoryDuped,
5497 void **ppStaticMemInfo
5498 )
5499 {
5500 MEMORY_DESCRIPTOR *pMemDesc;
5501 THREAD_STATE_NODE threadState;
5502 NV_STATUS rmStatus;
5503 OBJGPU *pGpu;
5504 void *fp;
5505
5506 NV_ENTER_RM_RUNTIME(sp,fp);
5507 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
5508
5509 pGpu = NV_GET_NV_PRIV_PGPU(nv);
5510
5511 NV_ASSERT(rmapiLockIsOwner());
5512
5513 NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu)));
5514
5515 rmStatus = RmDmabufVerifyMemHandle(pGpu, hSrcClient, hMemory,
5516 offset, size, pGpuInstanceInfo,
5517 &pMemDesc);
5518 if (rmStatus == NV_OK)
5519 {
5520 RM_API *pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL);
5521 NvHandle hMemoryDuped = 0;
5522
5523 rmStatus = pRmApi->DupObject(pRmApi,
5524 hDstClient,
5525 hDevice,
5526 &hMemoryDuped,
5527 hSrcClient,
5528 hMemory,
5529 0);
5530 if (rmStatus == NV_OK)
5531 {
5532 *phMemoryDuped = hMemoryDuped;
5533 }
5534 else if (rmStatus == NV_ERR_INVALID_OBJECT_PARENT)
5535 {
5536 hMemoryDuped = 0;
5537
5538 // If duping under Device fails, try duping under Subdevice
5539 rmStatus = pRmApi->DupObject(pRmApi,
5540 hDstClient,
5541 hSubdevice,
5542 &hMemoryDuped,
5543 hSrcClient,
5544 hMemory,
5545 0);
5546 if (rmStatus == NV_OK)
5547 {
5548 *phMemoryDuped = hMemoryDuped;
5549 }
5550 }
5551 *ppStaticMemInfo = (void *) pMemDesc;
5552 }
5553
5554 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
5555 NV_EXIT_RM_RUNTIME(sp,fp);
5556
5557 return rmStatus;
5558 }
5559
5560 //
5561 // Frees dup'd hMemory.
5562 // Must be called with API lock and GPU lock held.
5563 //
rm_dma_buf_undup_mem_handle(nvidia_stack_t * sp,nv_state_t * nv,NvHandle hClient,NvHandle hMemory)5564 void NV_API_CALL rm_dma_buf_undup_mem_handle(
5565 nvidia_stack_t *sp,
5566 nv_state_t *nv,
5567 NvHandle hClient,
5568 NvHandle hMemory
5569 )
5570 {
5571 THREAD_STATE_NODE threadState;
5572 RM_API *pRmApi;
5573 OBJGPU *pGpu;
5574 void *fp;
5575
5576 NV_ENTER_RM_RUNTIME(sp,fp);
5577 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
5578
5579 pGpu = NV_GET_NV_PRIV_PGPU(nv);
5580
5581 NV_ASSERT(rmapiLockIsOwner());
5582
5583 NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu)));
5584
5585 pRmApi = rmapiGetInterface(RMAPI_GPU_LOCK_INTERNAL);
5586
5587 pRmApi->Free(pRmApi, hClient, hMemory);
5588
5589 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
5590 NV_EXIT_RM_RUNTIME(sp,fp);
5591 }
5592
rm_dma_buf_map_mem_handle(nvidia_stack_t * sp,nv_state_t * nv,NvHandle hClient,NvHandle hMemory,NvU64 offset,NvU64 size,void * pStaticMemInfo,nv_phys_addr_range_t ** ppRanges,NvU32 * pRangeCount)5593 NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle(
5594 nvidia_stack_t *sp,
5595 nv_state_t *nv,
5596 NvHandle hClient,
5597 NvHandle hMemory,
5598 NvU64 offset,
5599 NvU64 size,
5600 void *pStaticMemInfo,
5601 nv_phys_addr_range_t **ppRanges,
5602 NvU32 *pRangeCount
5603 )
5604 {
5605 THREAD_STATE_NODE threadState;
5606 NV_STATUS rmStatus = NV_ERR_INVALID_ARGUMENT;
5607 OBJGPU *pGpu;
5608 void *fp;
5609
5610 NV_ENTER_RM_RUNTIME(sp,fp);
5611 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
5612
5613 NV_ASSERT_OR_GOTO(((ppRanges != NULL) &&
5614 (pRangeCount != NULL) &&
5615 (pStaticMemInfo != NULL)), Done);
5616
5617 pGpu = NV_GET_NV_PRIV_PGPU(nv);
5618
5619 if (pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING))
5620 {
5621 KernelMemorySystem *pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu);
5622 MEMORY_DESCRIPTOR *pMemDesc = (MEMORY_DESCRIPTOR *) pStaticMemInfo;
5623 NvU32 memdescPageSize = memdescGetPageSize(pMemDesc, AT_GPU);
5624 NvU64 prologueOffset = offset;
5625 NvU64 prologueSize = 0;
5626 NvU64 epilogueOffset = offset;
5627 NvU64 epilogueSize = 0;
5628 NvU64 mainOffset = offset;
5629 NvU64 mainSize = 0;
5630 NvU32 mainPageCount = 0;
5631 NvU64 alignedOffset;
5632 NvU32 pageCount = 0;
5633 NvU32 index = 0;
5634
5635 alignedOffset = NV_ALIGN_UP64(offset, memdescPageSize);
5636
5637 if ((size > 0) && offset != alignedOffset)
5638 {
5639 prologueOffset = offset;
5640 prologueSize = NV_MIN(alignedOffset - offset, size);
5641 pageCount++;
5642
5643 size -= prologueSize;
5644 }
5645
5646 if (size > 0)
5647 {
5648 mainOffset = prologueOffset + prologueSize;
5649 mainSize = NV_ALIGN_DOWN64(size, memdescPageSize);
5650 mainPageCount = mainSize / memdescPageSize;
5651 pageCount += mainPageCount;
5652
5653 size -= mainSize;
5654 }
5655
5656 if (size > 0)
5657 {
5658 epilogueOffset = mainOffset + mainSize;
5659 epilogueSize = size;
5660 pageCount++;
5661
5662 size -= epilogueSize;
5663 }
5664
5665 if ((pageCount == 0) || (size != 0))
5666 {
5667 NV_ASSERT(0);
5668 rmStatus = NV_ERR_INVALID_STATE;
5669 goto Done;
5670 }
5671
5672 rmStatus = os_alloc_mem((void **) ppRanges,
5673 pageCount * sizeof(nv_phys_addr_range_t));
5674 if (rmStatus != NV_OK)
5675 {
5676 goto Done;
5677 }
5678
5679 // Fill the first unaligned segment
5680 if (prologueSize > 0)
5681 {
5682 NvU64 physAddr = memdescGetPhysAddr(pMemDesc, AT_CPU, prologueOffset);
5683 (*ppRanges)[0].addr = pKernelMemorySystem->coherentCpuFbBase + physAddr;
5684 (*ppRanges)[0].len = prologueSize;
5685
5686 index = 1;
5687 }
5688
5689 // Fill the aligned segments between first and last entries
5690 while (mainPageCount != 0)
5691 {
5692 NvU64 physAddr = memdescGetPhysAddr(pMemDesc, AT_CPU, alignedOffset);
5693 (*ppRanges)[index].addr = pKernelMemorySystem->coherentCpuFbBase + physAddr;
5694 (*ppRanges)[index].len = memdescPageSize;
5695 index++;
5696
5697 alignedOffset += memdescPageSize;
5698 mainPageCount--;
5699 }
5700
5701 // Fill the last unaligned segment
5702 if (epilogueSize > 0)
5703 {
5704 NvU64 physAddr = memdescGetPhysAddr(pMemDesc, AT_CPU, epilogueOffset);
5705 (*ppRanges)[index].addr = pKernelMemorySystem->coherentCpuFbBase + physAddr;
5706 (*ppRanges)[index].len = epilogueSize;
5707 index++;
5708 }
5709
5710 NV_ASSERT(index == pageCount);
5711
5712 *pRangeCount = pageCount;
5713 }
5714 else
5715 {
5716 Device *pDevice;
5717 RsClient *pClient;
5718 KernelBus *pKernelBus;
5719 NvU64 bar1Va;
5720
5721 NV_ASSERT(rmapiLockIsOwner());
5722 NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu)));
5723
5724 NV_ASSERT_OK_OR_GOTO(rmStatus,
5725 serverGetClientUnderLock(&g_resServ, hClient, &pClient),
5726 Done);
5727
5728 NV_ASSERT_OK_OR_GOTO(rmStatus,
5729 deviceGetByGpu(pClient, pGpu, NV_TRUE, &pDevice),
5730 Done);
5731
5732 pKernelBus = GPU_GET_KERNEL_BUS(pGpu);
5733
5734 rmStatus = kbusMapFbApertureByHandle(pGpu, pKernelBus, hClient,
5735 hMemory, offset, size, &bar1Va,
5736 pDevice);
5737 if (rmStatus != NV_OK)
5738 {
5739 goto Done;
5740 }
5741
5742 // Adjust this alloc when discontiguous BAR1 is supported
5743 rmStatus = os_alloc_mem((void **) ppRanges,
5744 sizeof(nv_phys_addr_range_t));
5745 if (rmStatus != NV_OK)
5746 {
5747 kbusUnmapFbApertureByHandle(pGpu, pKernelBus, hClient,
5748 hMemory, bar1Va);
5749 goto Done;
5750 }
5751 (*ppRanges)[0].addr = bar1Va;
5752 (*ppRanges)[0].len = size;
5753 *pRangeCount = 1;
5754 }
5755
5756 Done:
5757 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
5758 NV_EXIT_RM_RUNTIME(sp,fp);
5759
5760 return rmStatus;
5761 }
5762
5763 //
5764 // Unmaps a handle from BAR1.
5765 // Must be called with API lock and GPU lock held.
5766 //
rm_dma_buf_unmap_mem_handle(nvidia_stack_t * sp,nv_state_t * nv,NvHandle hClient,NvHandle hMemory,NvU64 size,nv_phys_addr_range_t ** ppRanges,NvU32 rangeCount)5767 void NV_API_CALL rm_dma_buf_unmap_mem_handle(
5768 nvidia_stack_t *sp,
5769 nv_state_t *nv,
5770 NvHandle hClient,
5771 NvHandle hMemory,
5772 NvU64 size,
5773 nv_phys_addr_range_t **ppRanges,
5774 NvU32 rangeCount
5775 )
5776 {
5777 THREAD_STATE_NODE threadState;
5778 NV_STATUS rmStatus = NV_OK;
5779 OBJGPU *pGpu;
5780 NvU32 i;
5781 void *fp;
5782
5783 NV_ENTER_RM_RUNTIME(sp,fp);
5784 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
5785
5786 NV_ASSERT_OR_GOTO(((ppRanges != NULL) && (rangeCount != 0)), Done);
5787
5788 pGpu = NV_GET_NV_PRIV_PGPU(nv);
5789
5790 if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_COHERENT_CPU_MAPPING))
5791 {
5792 KernelBus *pKernelBus;
5793
5794 NV_ASSERT(rmapiLockIsOwner());
5795 NV_ASSERT(rmDeviceGpuLockIsOwner(gpuGetInstance(pGpu)));
5796
5797 pKernelBus = GPU_GET_KERNEL_BUS(pGpu);
5798
5799 for (i = 0; i < rangeCount; i++)
5800 {
5801 rmStatus = kbusUnmapFbApertureByHandle(pGpu, pKernelBus, hClient,
5802 hMemory, (*ppRanges)[i].addr);
5803 NV_ASSERT_OK(rmStatus);
5804 }
5805 }
5806
5807 os_free_mem(*ppRanges);
5808 *ppRanges = NULL;
5809
5810 Done:
5811 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
5812 NV_EXIT_RM_RUNTIME(sp,fp);
5813 }
5814
rm_dma_buf_get_client_and_device(nvidia_stack_t * sp,nv_state_t * nv,NvHandle hClient,NvHandle hMemory,NvHandle * phClient,NvHandle * phDevice,NvHandle * phSubdevice,void ** ppGpuInstanceInfo,NvBool * pbStaticPhysAddrs)5815 NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device(
5816 nvidia_stack_t *sp,
5817 nv_state_t *nv,
5818 NvHandle hClient,
5819 NvHandle hMemory,
5820 NvHandle *phClient,
5821 NvHandle *phDevice,
5822 NvHandle *phSubdevice,
5823 void **ppGpuInstanceInfo,
5824 NvBool *pbStaticPhysAddrs
5825 )
5826 {
5827 THREAD_STATE_NODE threadState;
5828 NV_STATUS rmStatus;
5829 void *fp;
5830
5831 NV_ENTER_RM_RUNTIME(sp,fp);
5832 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
5833
5834 // LOCK: acquire API lock
5835 rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI);
5836 if (rmStatus == NV_OK)
5837 {
5838 OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv);
5839
5840 rmStatus = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI);
5841 if (rmStatus == NV_OK)
5842 {
5843 rmStatus = RmDmabufGetClientAndDevice(pGpu, hClient, hMemory,
5844 phClient, phDevice,
5845 phSubdevice, ppGpuInstanceInfo);
5846 if (rmStatus == NV_OK)
5847 {
5848 // Note: revisit this when BAR1 static map is supported.
5849 *pbStaticPhysAddrs = pGpu->getProperty(pGpu,
5850 PDB_PROP_GPU_COHERENT_CPU_MAPPING);
5851 }
5852
5853 rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL);
5854 }
5855
5856 // UNLOCK: release API lock
5857 rmapiLockRelease();
5858 }
5859
5860 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
5861 NV_EXIT_RM_RUNTIME(sp,fp);
5862
5863 return rmStatus;
5864 }
5865
rm_dma_buf_put_client_and_device(nvidia_stack_t * sp,nv_state_t * nv,NvHandle hClient,NvHandle hDevice,NvHandle hSubdevice,void * pGpuInstanceInfo)5866 void NV_API_CALL rm_dma_buf_put_client_and_device(
5867 nvidia_stack_t *sp,
5868 nv_state_t *nv,
5869 NvHandle hClient,
5870 NvHandle hDevice,
5871 NvHandle hSubdevice,
5872 void *pGpuInstanceInfo
5873 )
5874 {
5875 THREAD_STATE_NODE threadState;
5876 NV_STATUS rmStatus;
5877 void *fp;
5878
5879 NV_ENTER_RM_RUNTIME(sp,fp);
5880 threadStateInit(&threadState, THREAD_STATE_FLAGS_NONE);
5881
5882 // LOCK: acquire API lock
5883 rmStatus = rmapiLockAcquire(API_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI);
5884 if (rmStatus == NV_OK)
5885 {
5886 OBJGPU *pGpu = NV_GET_NV_PRIV_PGPU(nv);
5887
5888 rmStatus = rmDeviceGpuLocksAcquire(pGpu, GPUS_LOCK_FLAGS_NONE, RM_LOCK_MODULES_OSAPI);
5889 if (rmStatus == NV_OK)
5890 {
5891 RmDmabufPutClientAndDevice(pGpu, hClient, hDevice, hSubdevice,
5892 pGpuInstanceInfo);
5893
5894 rmDeviceGpuLocksRelease(pGpu, GPUS_LOCK_FLAGS_NONE, NULL);
5895 }
5896
5897 // UNLOCK: release API lock
5898 rmapiLockRelease();
5899 }
5900 NV_ASSERT_OK(rmStatus);
5901
5902 threadStateFree(&threadState, THREAD_STATE_FLAGS_NONE);
5903 NV_EXIT_RM_RUNTIME(sp,fp);
5904 }
5905
5906 //
5907 // Fetches GSP ucode data for usage during RM Init
5908 // NOTE: Used only on VMWware
5909 //
5910
rm_vgpu_vfio_set_driver_vm(nvidia_stack_t * sp,NvBool is_driver_vm)5911 void NV_API_CALL rm_vgpu_vfio_set_driver_vm(
5912 nvidia_stack_t *sp,
5913 NvBool is_driver_vm
5914 )
5915 {
5916 OBJSYS *pSys;
5917 OBJHYPERVISOR *pHypervisor;
5918 void *fp;
5919
5920 NV_ENTER_RM_RUNTIME(sp,fp);
5921
5922 pSys = SYS_GET_INSTANCE();
5923 pHypervisor = SYS_GET_HYPERVISOR(pSys);
5924
5925 pHypervisor->setProperty(pHypervisor, PDB_PROP_HYPERVISOR_DRIVERVM_ENABLED, is_driver_vm);
5926
5927 NV_EXIT_RM_RUNTIME(sp,fp);
5928 }
5929
rm_is_altstack_in_use(void)5930 NvBool NV_API_CALL rm_is_altstack_in_use(void)
5931 {
5932 #if defined(__use_altstack__)
5933 return NV_TRUE;
5934 #else
5935 return NV_FALSE;
5936 #endif
5937 }
5938
rm_acpi_nvpcf_notify(nvidia_stack_t * sp)5939 void NV_API_CALL rm_acpi_nvpcf_notify(
5940 nvidia_stack_t *sp
5941 )
5942 {
5943 void *fp;
5944 OBJGPU *pGpu = gpumgrGetGpu(0);
5945
5946 NV_ENTER_RM_RUNTIME(sp,fp);
5947
5948 if (pGpu != NULL)
5949 {
5950 nv_state_t *nv = NV_GET_NV_STATE(pGpu);
5951 RmHandleNvpcfEvents(nv);
5952 }
5953
5954 NV_EXIT_RM_RUNTIME(sp,fp);
5955 }
5956