| /dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue98/ |
| H A D | test_load.vhdl | 8 rst_i : in std_ulogic; port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/ |
| H A D | xwb_lm32.vhd | 50 rst_i : in std_logic; port in xwb_lm32.rtl.lm32_top_minimal
85 rst_i : in std_logic; port in xwb_lm32.rtl.lm32_top_medium
120 rst_i : in std_logic; port in xwb_lm32.rtl.lm32_top_medium_icache
155 rst_i : in std_logic; port in xwb_lm32.rtl.lm32_top_medium_debug
190 rst_i : in std_logic; port in xwb_lm32.rtl.lm32_top_medium_icache_debug
225 rst_i : in std_logic; port in xwb_lm32.rtl.lm32_top_full
260 rst_i : in std_logic; port in xwb_lm32.rtl.lm32_top_full_debug
295 rst_i : in std_logic; port in xwb_lm32.rtl.lm32_top_wr_node
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/sdr_lib/ |
| H A D | integrate.v | 24 input rst_i, port
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/synth/issue1426/ |
| H A D | bar.vhdl | 12 rst_i : in std_logic; port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/src/ |
| H A D | lm32_dp_ram.vhd | 16 rst_i : in std_logic; port
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| H A D | lm32_shifter.v | 53 input rst_i; // Reset port
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue1346/ |
| H A D | memory_map.vhd | 23 alias rst_i : std_ulogic is p_i.dmn.rst; alias
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/sdr_lib/ |
| H A D | atr_delay.v | 24 input rst_i; port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/timing/ |
| H A D | timer.v | 21 (input wb_clk_i, input rst_i, port
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| H A D | time_sync.v | 21 (input wb_clk_i, input rst_i, port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/control_lib/ |
| H A D | settings_bus_crossclock.v | 26 (input clk_i, input rst_i, input set_stb_i, input [7:0] set_addr_i, input [31:0] set_data_i, port
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| H A D | atr_controller.v | 24 (input clk_i, input rst_i, port
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| H A D | atr_controller16.v | 24 (input clk_i, input rst_i, port
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| H A D | nsgpio.v | 39 (input clk_i, input rst_i, port
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| H A D | nsgpio16LE.v | 39 (input clk_i, input rst_i, port
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| H A D | pic.v | 95 (input clk_i, input rst_i, input cyc_i, input stb_i, port
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| H A D | simple_uart.v | 23 (input clk_i, input rst_i, port
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| H A D | quad_uart.v | 22 (input clk_i, input rst_i, port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/ |
| H A D | lm32_multiplier.v | 52 input rst_i; // Reset port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/opencores/simple_gpio/rtl/ |
| H A D | simple_gpio.v | 108 input rst_i; // reset (asynchronous active low) port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/ |
| H A D | file_sink.v | 14 input rst_i, port
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/wishbone/ |
| H A D | simple_uart.v | 12 (input clk_i, input rst_i, port
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| H A D | i2c_master_top.v | 153 wire rst_i = arst_i ^ ARST_LVL; net
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/opencores/simple_pic/rtl/ |
| H A D | simple_pic.v | 105 input rst_i; // reset (asynchronous active low) port
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/bug24065/ |
| H A D | cic_up.vhd | 15 rst_i : in std_logic; port
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