1 /* $OpenBSD: rt2860.c,v 1.104 2024/09/20 02:00:46 jsg Exp $ */
2
3 /*-
4 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 /*-
20 * Ralink Technology RT2860/RT3090/RT3290/RT3390/RT3562/RT5390/
21 * RT5392 chipset driver
22 * http://www.ralinktech.com/
23 */
24
25 #include "bpfilter.h"
26
27 #include <sys/param.h>
28 #include <sys/sockio.h>
29 #include <sys/mbuf.h>
30 #include <sys/kernel.h>
31 #include <sys/socket.h>
32 #include <sys/systm.h>
33 #include <sys/malloc.h>
34 #include <sys/queue.h>
35 #include <sys/timeout.h>
36 #include <sys/conf.h>
37 #include <sys/device.h>
38 #include <sys/endian.h>
39
40 #include <machine/bus.h>
41 #include <machine/intr.h>
42
43 #if NBPFILTER > 0
44 #include <net/bpf.h>
45 #endif
46 #include <net/if.h>
47 #include <net/if_dl.h>
48 #include <net/if_media.h>
49
50 #include <netinet/in.h>
51 #include <netinet/if_ether.h>
52
53 #include <net80211/ieee80211_var.h>
54 #include <net80211/ieee80211_amrr.h>
55 #include <net80211/ieee80211_radiotap.h>
56
57 #include <dev/ic/rt2860var.h>
58 #include <dev/ic/rt2860reg.h>
59
60 #include <dev/pci/pcidevs.h>
61
62 #ifdef RAL_DEBUG
63 #define DPRINTF(x) do { if (rt2860_debug > 0) printf x; } while (0)
64 #define DPRINTFN(n, x) do { if (rt2860_debug >= (n)) printf x; } while (0)
65 int rt2860_debug = 0;
66 #else
67 #define DPRINTF(x)
68 #define DPRINTFN(n, x)
69 #endif
70
71 void rt2860_attachhook(struct device *);
72 int rt2860_alloc_tx_ring(struct rt2860_softc *,
73 struct rt2860_tx_ring *);
74 void rt2860_reset_tx_ring(struct rt2860_softc *,
75 struct rt2860_tx_ring *);
76 void rt2860_free_tx_ring(struct rt2860_softc *,
77 struct rt2860_tx_ring *);
78 int rt2860_alloc_tx_pool(struct rt2860_softc *);
79 void rt2860_free_tx_pool(struct rt2860_softc *);
80 int rt2860_alloc_rx_ring(struct rt2860_softc *,
81 struct rt2860_rx_ring *);
82 void rt2860_reset_rx_ring(struct rt2860_softc *,
83 struct rt2860_rx_ring *);
84 void rt2860_free_rx_ring(struct rt2860_softc *,
85 struct rt2860_rx_ring *);
86 struct ieee80211_node *rt2860_node_alloc(struct ieee80211com *);
87 int rt2860_media_change(struct ifnet *);
88 void rt2860_iter_func(void *, struct ieee80211_node *);
89 void rt2860_updatestats(struct rt2860_softc *);
90 void rt2860_newassoc(struct ieee80211com *, struct ieee80211_node *,
91 int);
92 void rt2860_node_leave(struct ieee80211com *,
93 struct ieee80211_node *);
94 int rt2860_ampdu_rx_start(struct ieee80211com *,
95 struct ieee80211_node *, uint8_t);
96 void rt2860_ampdu_rx_stop(struct ieee80211com *,
97 struct ieee80211_node *, uint8_t);
98 int rt2860_newstate(struct ieee80211com *, enum ieee80211_state,
99 int);
100 uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t);
101 uint16_t rt3290_efuse_read_2(struct rt2860_softc *, uint16_t);
102 uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t);
103 void rt2860_intr_coherent(struct rt2860_softc *);
104 void rt2860_drain_stats_fifo(struct rt2860_softc *);
105 void rt2860_tx_intr(struct rt2860_softc *, int);
106 void rt2860_rx_intr(struct rt2860_softc *);
107 void rt2860_tbtt_intr(struct rt2860_softc *);
108 void rt2860_gp_intr(struct rt2860_softc *);
109 int rt2860_tx(struct rt2860_softc *, struct mbuf *,
110 struct ieee80211_node *);
111 void rt2860_start(struct ifnet *);
112 void rt2860_watchdog(struct ifnet *);
113 int rt2860_ioctl(struct ifnet *, u_long, caddr_t);
114 void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t);
115 uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t);
116 void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t);
117 uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t);
118 void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t);
119 int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int);
120 void rt2860_enable_mrr(struct rt2860_softc *);
121 void rt2860_set_txpreamble(struct rt2860_softc *);
122 void rt2860_set_basicrates(struct rt2860_softc *);
123 void rt2860_select_chan_group(struct rt2860_softc *, int);
124 void rt2860_set_chan(struct rt2860_softc *, u_int);
125 void rt3090_set_chan(struct rt2860_softc *, u_int);
126 void rt5390_set_chan(struct rt2860_softc *, u_int);
127 int rt3090_rf_init(struct rt2860_softc *);
128 void rt5390_rf_init(struct rt2860_softc *);
129 void rt3090_rf_wakeup(struct rt2860_softc *);
130 void rt5390_rf_wakeup(struct rt2860_softc *);
131 int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t,
132 uint8_t *);
133 void rt3090_rf_setup(struct rt2860_softc *);
134 void rt2860_set_leds(struct rt2860_softc *, uint16_t);
135 void rt2860_set_gp_timer(struct rt2860_softc *, int);
136 void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *);
137 void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *);
138 void rt2860_updateslot(struct ieee80211com *);
139 void rt2860_updateprot(struct ieee80211com *);
140 void rt2860_updateedca(struct ieee80211com *);
141 int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *,
142 struct ieee80211_key *);
143 void rt2860_delete_key(struct ieee80211com *,
144 struct ieee80211_node *, struct ieee80211_key *);
145 #if NBPFILTER > 0
146 int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t);
147 #endif
148 const char * rt2860_get_rf(uint16_t);
149 int rt2860_read_eeprom(struct rt2860_softc *);
150 int rt2860_bbp_init(struct rt2860_softc *);
151 void rt5390_bbp_init(struct rt2860_softc *);
152 int rt3290_wlan_enable(struct rt2860_softc *);
153 int rt2860_txrx_enable(struct rt2860_softc *);
154 int rt2860_init(struct ifnet *);
155 void rt2860_stop(struct ifnet *, int);
156 int rt2860_load_microcode(struct rt2860_softc *);
157 void rt2860_calib(struct rt2860_softc *);
158 void rt3090_set_rx_antenna(struct rt2860_softc *, int);
159 void rt2860_switch_chan(struct rt2860_softc *,
160 struct ieee80211_channel *);
161 #ifndef IEEE80211_STA_ONLY
162 int rt2860_setup_beacon(struct rt2860_softc *);
163 #endif
164 void rt2860_enable_tsf_sync(struct rt2860_softc *);
165
166 static const struct {
167 uint32_t reg;
168 uint32_t val;
169 } rt2860_def_mac[] = {
170 RT2860_DEF_MAC
171 };
172
173 static const struct {
174 uint8_t reg;
175 uint8_t val;
176 } rt2860_def_bbp[] = {
177 RT2860_DEF_BBP
178 },rt3290_def_bbp[] = {
179 RT3290_DEF_BBP
180 },rt5390_def_bbp[] = {
181 RT5390_DEF_BBP
182 };
183
184 static const struct rfprog {
185 uint8_t chan;
186 uint32_t r1, r2, r3, r4;
187 } rt2860_rf2850[] = {
188 RT2860_RF2850
189 };
190
191 struct {
192 uint8_t n, r, k;
193 } rt3090_freqs[] = {
194 RT3070_RF3052
195 };
196
197 static const struct {
198 uint8_t reg;
199 uint8_t val;
200 } rt3090_def_rf[] = {
201 RT3070_DEF_RF
202 }, rt3290_def_rf[] = {
203 RT3290_DEF_RF
204 }, rt3572_def_rf[] = {
205 RT3572_DEF_RF
206 }, rt5390_def_rf[] = {
207 RT5390_DEF_RF
208 }, rt5392_def_rf[] = {
209 RT5392_DEF_RF
210 };
211
212 int
rt2860_attach(void * xsc,int id)213 rt2860_attach(void *xsc, int id)
214 {
215 struct rt2860_softc *sc = xsc;
216 struct ieee80211com *ic = &sc->sc_ic;
217 int qid, ntries, error;
218 uint32_t tmp, reg;
219
220 sc->amrr.amrr_min_success_threshold = 1;
221 sc->amrr.amrr_max_success_threshold = 15;
222
223 if (id == PCI_PRODUCT_RALINK_RT3290)
224 reg = RT2860_PCI_CFG;
225 else
226 reg = RT2860_ASIC_VER_ID;
227
228 /* wait for NIC to initialize */
229 for (ntries = 0; ntries < 100; ntries++) {
230 tmp = RAL_READ(sc, reg);
231 if (tmp != 0 && tmp != 0xffffffff)
232 break;
233 DELAY(10);
234 }
235 if (ntries == 100) {
236 printf("%s: timeout waiting for NIC to initialize\n",
237 sc->sc_dev.dv_xname);
238 return ETIMEDOUT;
239 }
240 sc->mac_ver = tmp >> 16;
241 sc->mac_rev = tmp & 0xffff;
242
243 if (sc->mac_ver != 0x2860 &&
244 (id == PCI_PRODUCT_RALINK_RT2890 ||
245 id == PCI_PRODUCT_RALINK_RT2790 ||
246 id == PCI_PRODUCT_AWT_RT2890))
247 sc->sc_flags |= RT2860_ADVANCED_PS;
248
249 /* retrieve RF rev. no and various other things from EEPROM */
250 rt2860_read_eeprom(sc);
251 printf(", address %s\n", ether_sprintf(ic->ic_myaddr));
252 printf("%s: MAC/BBP RT%X (rev 0x%04X), RF %s (MIMO %dT%dR)\n",
253 sc->sc_dev.dv_xname, sc->mac_ver, sc->mac_rev,
254 rt2860_get_rf(sc->rf_rev), sc->ntxchains, sc->nrxchains);
255
256 /*
257 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings.
258 */
259 for (qid = 0; qid < 6; qid++) {
260 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) {
261 printf("%s: could not allocate Tx ring %d\n",
262 sc->sc_dev.dv_xname, qid);
263 goto fail1;
264 }
265 }
266
267 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) {
268 printf("%s: could not allocate Rx ring\n",
269 sc->sc_dev.dv_xname);
270 goto fail1;
271 }
272
273 if ((error = rt2860_alloc_tx_pool(sc)) != 0) {
274 printf("%s: could not allocate Tx pool\n",
275 sc->sc_dev.dv_xname);
276 goto fail2;
277 }
278
279 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */
280 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ?
281 EDCA_AC_VO : 5;
282
283 config_mountroot(xsc, rt2860_attachhook);
284
285 return 0;
286
287 fail2: rt2860_free_rx_ring(sc, &sc->rxq);
288 fail1: while (--qid >= 0)
289 rt2860_free_tx_ring(sc, &sc->txq[qid]);
290 return error;
291 }
292
293 void
rt2860_attachhook(struct device * self)294 rt2860_attachhook(struct device *self)
295 {
296 struct rt2860_softc *sc = (struct rt2860_softc *)self;
297 struct ieee80211com *ic = &sc->sc_ic;
298 struct ifnet *ifp = &ic->ic_if;
299 int i, error;
300
301 if (sc->mac_ver == 0x3290) {
302 error = loadfirmware("ral-rt3290", &sc->ucode, &sc->ucsize);
303 } else {
304 error = loadfirmware("ral-rt2860", &sc->ucode, &sc->ucsize);
305 }
306 if (error != 0) {
307 printf("%s: error %d, could not read firmware file %s\n",
308 sc->sc_dev.dv_xname, error, "ral-rt2860");
309 return;
310 }
311
312 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
313 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
314 ic->ic_state = IEEE80211_S_INIT;
315
316 /* set device capabilities */
317 ic->ic_caps =
318 IEEE80211_C_MONITOR | /* monitor mode supported */
319 #ifndef IEEE80211_STA_ONLY
320 IEEE80211_C_IBSS | /* IBSS mode supported */
321 IEEE80211_C_HOSTAP | /* HostAP mode supported */
322 IEEE80211_C_APPMGT | /* HostAP power management */
323 #endif
324 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
325 IEEE80211_C_SHSLOT | /* short slot time supported */
326 IEEE80211_C_WEP | /* s/w WEP */
327 IEEE80211_C_RSN; /* WPA/RSN */
328
329 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) {
330 /* set supported .11a rates */
331 ic->ic_sup_rates[IEEE80211_MODE_11A] =
332 ieee80211_std_rateset_11a;
333
334 /* set supported .11a channels */
335 for (i = 14; i < nitems(rt2860_rf2850); i++) {
336 uint8_t chan = rt2860_rf2850[i].chan;
337 ic->ic_channels[chan].ic_freq =
338 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ);
339 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A;
340 }
341 }
342
343 /* set supported .11b and .11g rates */
344 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b;
345 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g;
346
347 /* set supported .11b and .11g channels (1 through 14) */
348 for (i = 1; i <= 14; i++) {
349 ic->ic_channels[i].ic_freq =
350 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
351 ic->ic_channels[i].ic_flags =
352 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
353 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
354 }
355
356 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */
357 ic->ic_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX);
358
359 ifp->if_softc = sc;
360 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
361 ifp->if_ioctl = rt2860_ioctl;
362 ifp->if_start = rt2860_start;
363 ifp->if_watchdog = rt2860_watchdog;
364 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ);
365
366 if_attach(ifp);
367 ieee80211_ifattach(ifp);
368 ic->ic_node_alloc = rt2860_node_alloc;
369 ic->ic_newassoc = rt2860_newassoc;
370 #ifndef IEEE80211_STA_ONLY
371 ic->ic_node_leave = rt2860_node_leave;
372 #endif
373 ic->ic_ampdu_rx_start = rt2860_ampdu_rx_start;
374 ic->ic_ampdu_rx_stop = rt2860_ampdu_rx_stop;
375 ic->ic_updateslot = rt2860_updateslot;
376 ic->ic_updateedca = rt2860_updateedca;
377 ic->ic_set_key = rt2860_set_key;
378 ic->ic_delete_key = rt2860_delete_key;
379 /* override state transition machine */
380 sc->sc_newstate = ic->ic_newstate;
381 ic->ic_newstate = rt2860_newstate;
382 ieee80211_media_init(ifp, rt2860_media_change, ieee80211_media_status);
383
384 #if NBPFILTER > 0
385 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO,
386 sizeof (struct ieee80211_frame) + 64);
387
388 sc->sc_rxtap_len = sizeof sc->sc_rxtapu;
389 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len);
390 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2860_RX_RADIOTAP_PRESENT);
391
392 sc->sc_txtap_len = sizeof sc->sc_txtapu;
393 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len);
394 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2860_TX_RADIOTAP_PRESENT);
395 #endif
396 }
397
398 int
rt2860_detach(void * xsc)399 rt2860_detach(void *xsc)
400 {
401 struct rt2860_softc *sc = xsc;
402 struct ifnet *ifp = &sc->sc_ic.ic_if;
403 int qid;
404
405 ieee80211_ifdetach(ifp); /* free all nodes */
406 if_detach(ifp);
407
408 for (qid = 0; qid < 6; qid++)
409 rt2860_free_tx_ring(sc, &sc->txq[qid]);
410 rt2860_free_rx_ring(sc, &sc->rxq);
411 rt2860_free_tx_pool(sc);
412
413 if (sc->ucode != NULL)
414 free(sc->ucode, M_DEVBUF, sc->ucsize);
415
416 return 0;
417 }
418
419 void
rt2860_suspend(void * xsc)420 rt2860_suspend(void *xsc)
421 {
422 struct rt2860_softc *sc = xsc;
423 struct ifnet *ifp = &sc->sc_ic.ic_if;
424
425 if (ifp->if_flags & IFF_RUNNING)
426 rt2860_stop(ifp, 1);
427 }
428
429 void
rt2860_wakeup(void * xsc)430 rt2860_wakeup(void *xsc)
431 {
432 struct rt2860_softc *sc = xsc;
433 struct ifnet *ifp = &sc->sc_ic.ic_if;
434
435 if (ifp->if_flags & IFF_UP)
436 rt2860_init(ifp);
437 }
438
439 int
rt2860_alloc_tx_ring(struct rt2860_softc * sc,struct rt2860_tx_ring * ring)440 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
441 {
442 int nsegs, size, error;
443
444 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd);
445
446 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
447 BUS_DMA_NOWAIT, &ring->map);
448 if (error != 0) {
449 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname);
450 goto fail;
451 }
452
453 /* Tx rings must be 4-DWORD aligned */
454 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1,
455 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO);
456 if (error != 0) {
457 printf("%s: could not allocate DMA memory\n",
458 sc->sc_dev.dv_xname);
459 goto fail;
460 }
461
462 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size,
463 (caddr_t *)&ring->txd, BUS_DMA_NOWAIT);
464 if (error != 0) {
465 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname);
466 goto fail;
467 }
468
469 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->txd, size, NULL,
470 BUS_DMA_NOWAIT);
471 if (error != 0) {
472 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname);
473 goto fail;
474 }
475
476 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE);
477
478 ring->paddr = ring->map->dm_segs[0].ds_addr;
479
480 return 0;
481
482 fail: rt2860_free_tx_ring(sc, ring);
483 return error;
484 }
485
486 void
rt2860_reset_tx_ring(struct rt2860_softc * sc,struct rt2860_tx_ring * ring)487 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
488 {
489 struct rt2860_tx_data *data;
490 int i;
491
492 for (i = 0; i < RT2860_TX_RING_COUNT; i++) {
493 if ((data = ring->data[i]) == NULL)
494 continue; /* nothing mapped in this slot */
495
496 bus_dmamap_sync(sc->sc_dmat, data->map, 0,
497 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
498 bus_dmamap_unload(sc->sc_dmat, data->map);
499 m_freem(data->m);
500 data->m= NULL;
501 data->ni = NULL; /* node already freed */
502
503 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
504 ring->data[i] = NULL;
505 }
506
507 ring->queued = 0;
508 ring->cur = ring->next = 0;
509 }
510
511 void
rt2860_free_tx_ring(struct rt2860_softc * sc,struct rt2860_tx_ring * ring)512 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
513 {
514 struct rt2860_tx_data *data;
515 int i;
516
517 if (ring->txd != NULL) {
518 bus_dmamap_sync(sc->sc_dmat, ring->map, 0,
519 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
520 bus_dmamap_unload(sc->sc_dmat, ring->map);
521 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->txd,
522 RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd));
523 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1);
524 }
525 if (ring->map != NULL)
526 bus_dmamap_destroy(sc->sc_dmat, ring->map);
527
528 for (i = 0; i < RT2860_TX_RING_COUNT; i++) {
529 if ((data = ring->data[i]) == NULL)
530 continue; /* nothing mapped in this slot */
531
532 bus_dmamap_sync(sc->sc_dmat, data->map, 0,
533 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
534 bus_dmamap_unload(sc->sc_dmat, data->map);
535 m_freem(data->m);
536
537 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
538 }
539 }
540
541 /*
542 * Allocate a pool of TX Wireless Information blocks.
543 */
544 int
rt2860_alloc_tx_pool(struct rt2860_softc * sc)545 rt2860_alloc_tx_pool(struct rt2860_softc *sc)
546 {
547 caddr_t vaddr;
548 bus_addr_t paddr;
549 int i, nsegs, size, error;
550
551 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ;
552
553 /* init data_pool early in case of failure.. */
554 SLIST_INIT(&sc->data_pool);
555
556 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
557 BUS_DMA_NOWAIT, &sc->txwi_map);
558 if (error != 0) {
559 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname);
560 goto fail;
561 }
562
563 error = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0,
564 &sc->txwi_seg, 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO);
565 if (error != 0) {
566 printf("%s: could not allocate DMA memory\n",
567 sc->sc_dev.dv_xname);
568 goto fail;
569 }
570
571 error = bus_dmamem_map(sc->sc_dmat, &sc->txwi_seg, nsegs, size,
572 &sc->txwi_vaddr, BUS_DMA_NOWAIT);
573 if (error != 0) {
574 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname);
575 goto fail;
576 }
577
578 error = bus_dmamap_load(sc->sc_dmat, sc->txwi_map, sc->txwi_vaddr,
579 size, NULL, BUS_DMA_NOWAIT);
580 if (error != 0) {
581 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname);
582 goto fail;
583 }
584
585 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0, size,
586 BUS_DMASYNC_PREWRITE);
587
588 vaddr = sc->txwi_vaddr;
589 paddr = sc->txwi_map->dm_segs[0].ds_addr;
590 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) {
591 struct rt2860_tx_data *data = &sc->data[i];
592
593 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
594 RT2860_MAX_SCATTER, MCLBYTES, 0, BUS_DMA_NOWAIT,
595 &data->map); /* <0> */
596 if (error != 0) {
597 printf("%s: could not create DMA map\n",
598 sc->sc_dev.dv_xname);
599 goto fail;
600 }
601 data->txwi = (struct rt2860_txwi *)vaddr;
602 data->paddr = paddr;
603 vaddr += RT2860_TXWI_DMASZ;
604 paddr += RT2860_TXWI_DMASZ;
605
606 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
607 }
608
609 return 0;
610
611 fail: rt2860_free_tx_pool(sc);
612 return error;
613 }
614
615 void
rt2860_free_tx_pool(struct rt2860_softc * sc)616 rt2860_free_tx_pool(struct rt2860_softc *sc)
617 {
618 if (sc->txwi_vaddr != NULL) {
619 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map, 0,
620 sc->txwi_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
621 bus_dmamap_unload(sc->sc_dmat, sc->txwi_map);
622 bus_dmamem_unmap(sc->sc_dmat, sc->txwi_vaddr,
623 RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ);
624 bus_dmamem_free(sc->sc_dmat, &sc->txwi_seg, 1);
625 }
626 if (sc->txwi_map != NULL)
627 bus_dmamap_destroy(sc->sc_dmat, sc->txwi_map);
628
629 while (!SLIST_EMPTY(&sc->data_pool)) {
630 struct rt2860_tx_data *data;
631 data = SLIST_FIRST(&sc->data_pool);
632 bus_dmamap_destroy(sc->sc_dmat, data->map);
633 SLIST_REMOVE_HEAD(&sc->data_pool, next);
634 }
635 }
636
637 int
rt2860_alloc_rx_ring(struct rt2860_softc * sc,struct rt2860_rx_ring * ring)638 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
639 {
640 int i, nsegs, size, error;
641
642 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd);
643
644 error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
645 BUS_DMA_NOWAIT, &ring->map);
646 if (error != 0) {
647 printf("%s: could not create DMA map\n", sc->sc_dev.dv_xname);
648 goto fail;
649 }
650
651 /* Rx ring must be 4-DWORD aligned */
652 error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, &ring->seg, 1,
653 &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO);
654 if (error != 0) {
655 printf("%s: could not allocate DMA memory\n",
656 sc->sc_dev.dv_xname);
657 goto fail;
658 }
659
660 error = bus_dmamem_map(sc->sc_dmat, &ring->seg, nsegs, size,
661 (caddr_t *)&ring->rxd, BUS_DMA_NOWAIT);
662 if (error != 0) {
663 printf("%s: can't map DMA memory\n", sc->sc_dev.dv_xname);
664 goto fail;
665 }
666
667 error = bus_dmamap_load(sc->sc_dmat, ring->map, ring->rxd, size, NULL,
668 BUS_DMA_NOWAIT);
669 if (error != 0) {
670 printf("%s: could not load DMA map\n", sc->sc_dev.dv_xname);
671 goto fail;
672 }
673
674 ring->paddr = ring->map->dm_segs[0].ds_addr;
675
676 for (i = 0; i < RT2860_RX_RING_COUNT; i++) {
677 struct rt2860_rx_data *data = &ring->data[i];
678 struct rt2860_rxd *rxd = &ring->rxd[i];
679
680 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
681 0, BUS_DMA_NOWAIT, &data->map);
682 if (error != 0) {
683 printf("%s: could not create DMA map\n",
684 sc->sc_dev.dv_xname);
685 goto fail;
686 }
687
688 data->m = MCLGETL(NULL, M_DONTWAIT, MCLBYTES);
689 if (data->m == NULL) {
690 printf("%s: could not allocate Rx mbuf\n",
691 sc->sc_dev.dv_xname);
692 error = ENOBUFS;
693 goto fail;
694 }
695
696 error = bus_dmamap_load(sc->sc_dmat, data->map,
697 mtod(data->m, void *), MCLBYTES, NULL,
698 BUS_DMA_READ | BUS_DMA_NOWAIT);
699 if (error != 0) {
700 printf("%s: could not load DMA map\n",
701 sc->sc_dev.dv_xname);
702 goto fail;
703 }
704
705 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr);
706 rxd->sdl0 = htole16(MCLBYTES);
707 }
708
709 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, size, BUS_DMASYNC_PREWRITE);
710
711 return 0;
712
713 fail: rt2860_free_rx_ring(sc, ring);
714 return error;
715 }
716
717 void
rt2860_reset_rx_ring(struct rt2860_softc * sc,struct rt2860_rx_ring * ring)718 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
719 {
720 int i;
721
722 for (i = 0; i < RT2860_RX_RING_COUNT; i++)
723 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE);
724
725 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize,
726 BUS_DMASYNC_PREWRITE);
727
728 ring->cur = 0;
729 }
730
731 void
rt2860_free_rx_ring(struct rt2860_softc * sc,struct rt2860_rx_ring * ring)732 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
733 {
734 int i;
735
736 if (ring->rxd != NULL) {
737 bus_dmamap_sync(sc->sc_dmat, ring->map, 0,
738 ring->map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
739 bus_dmamap_unload(sc->sc_dmat, ring->map);
740 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)ring->rxd,
741 RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd));
742 bus_dmamem_free(sc->sc_dmat, &ring->seg, 1);
743 }
744 if (ring->map != NULL)
745 bus_dmamap_destroy(sc->sc_dmat, ring->map);
746
747 for (i = 0; i < RT2860_RX_RING_COUNT; i++) {
748 struct rt2860_rx_data *data = &ring->data[i];
749
750 if (data->m != NULL) {
751 bus_dmamap_sync(sc->sc_dmat, data->map, 0,
752 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD);
753 bus_dmamap_unload(sc->sc_dmat, data->map);
754 m_freem(data->m);
755 }
756 if (data->map != NULL)
757 bus_dmamap_destroy(sc->sc_dmat, data->map);
758 }
759 }
760
761 struct ieee80211_node *
rt2860_node_alloc(struct ieee80211com * ic)762 rt2860_node_alloc(struct ieee80211com *ic)
763 {
764 return malloc(sizeof (struct rt2860_node), M_DEVBUF,
765 M_NOWAIT | M_ZERO);
766 }
767
768 int
rt2860_media_change(struct ifnet * ifp)769 rt2860_media_change(struct ifnet *ifp)
770 {
771 struct rt2860_softc *sc = ifp->if_softc;
772 struct ieee80211com *ic = &sc->sc_ic;
773 uint8_t rate, ridx;
774 int error;
775
776 error = ieee80211_media_change(ifp);
777 if (error != ENETRESET)
778 return error;
779
780 if (ic->ic_fixed_rate != -1) {
781 rate = ic->ic_sup_rates[ic->ic_curmode].
782 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL;
783 for (ridx = 0; ridx <= RT2860_RIDX_MAX; ridx++)
784 if (rt2860_rates[ridx].rate == rate)
785 break;
786 sc->fixed_ridx = ridx;
787 }
788
789 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
790 (IFF_UP | IFF_RUNNING)) {
791 rt2860_stop(ifp, 0);
792 rt2860_init(ifp);
793 }
794 return 0;
795 }
796
797 void
rt2860_iter_func(void * arg,struct ieee80211_node * ni)798 rt2860_iter_func(void *arg, struct ieee80211_node *ni)
799 {
800 struct rt2860_softc *sc = arg;
801 uint8_t wcid = ((struct rt2860_node *)ni)->wcid;
802
803 ieee80211_amrr_choose(&sc->amrr, ni, &sc->amn[wcid]);
804 }
805
806 void
rt2860_updatestats(struct rt2860_softc * sc)807 rt2860_updatestats(struct rt2860_softc *sc)
808 {
809 struct ieee80211com *ic = &sc->sc_ic;
810
811 #ifndef IEEE80211_STA_ONLY
812 /*
813 * In IBSS or HostAP modes (when the hardware sends beacons), the
814 * MAC can run into a livelock and start sending CTS-to-self frames
815 * like crazy if protection is enabled. Fortunately, we can detect
816 * when such a situation occurs and reset the MAC.
817 */
818 if (ic->ic_curmode != IEEE80211_M_STA) {
819 /* check if we're in a livelock situation.. */
820 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG);
821 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) {
822 /* ..and reset MAC/BBP for a while.. */
823 DPRINTF(("CTS-to-self livelock detected\n"));
824 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST);
825 RAL_BARRIER_WRITE(sc);
826 DELAY(1);
827 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL,
828 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
829 }
830 }
831 #endif
832 if (ic->ic_opmode == IEEE80211_M_STA)
833 rt2860_iter_func(sc, ic->ic_bss);
834 #ifndef IEEE80211_STA_ONLY
835 else
836 ieee80211_iterate_nodes(ic, rt2860_iter_func, sc);
837 #endif
838 }
839
840 void
rt2860_newassoc(struct ieee80211com * ic,struct ieee80211_node * ni,int isnew)841 rt2860_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew)
842 {
843 struct rt2860_softc *sc = ic->ic_softc;
844 struct rt2860_node *rn = (void *)ni;
845 struct ieee80211_rateset *rs = &ni->ni_rates;
846 uint8_t rate, wcid = 0;
847 int ridx, i, j;
848
849 if (isnew && ni->ni_associd != 0) {
850 /* only interested in true associations */
851 wcid = rn->wcid = IEEE80211_AID(ni->ni_associd);
852
853 /* init WCID table entry */
854 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid),
855 ni->ni_macaddr, IEEE80211_ADDR_LEN);
856 }
857 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n",
858 isnew, ether_sprintf(ni->ni_macaddr), wcid));
859
860 ieee80211_amrr_node_init(&sc->amrr, &sc->amn[wcid]);
861 /* start at lowest available bit-rate, AMRR will raise */
862 ni->ni_txrate = 0;
863
864 for (i = 0; i < rs->rs_nrates; i++) {
865 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL;
866 /* convert 802.11 rate to hardware rate index */
867 for (ridx = 0; ridx < RT2860_RIDX_MAX; ridx++)
868 if (rt2860_rates[ridx].rate == rate)
869 break;
870 rn->ridx[i] = ridx;
871 /* determine rate of control response frames */
872 for (j = i; j >= 0; j--) {
873 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC) &&
874 rt2860_rates[rn->ridx[i]].phy ==
875 rt2860_rates[rn->ridx[j]].phy)
876 break;
877 }
878 if (j >= 0) {
879 rn->ctl_ridx[i] = rn->ridx[j];
880 } else {
881 /* no basic rate found, use mandatory one */
882 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx;
883 }
884 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n",
885 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i]));
886 }
887 }
888
889 #ifndef IEEE80211_STA_ONLY
890 void
rt2860_node_leave(struct ieee80211com * ic,struct ieee80211_node * ni)891 rt2860_node_leave(struct ieee80211com *ic, struct ieee80211_node *ni)
892 {
893 struct rt2860_softc *sc = ic->ic_softc;
894 uint8_t wcid = ((struct rt2860_node *)ni)->wcid;
895
896 /* clear Rx WCID search table entry */
897 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2);
898 }
899 #endif
900
901 int
rt2860_ampdu_rx_start(struct ieee80211com * ic,struct ieee80211_node * ni,uint8_t tid)902 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni,
903 uint8_t tid)
904 {
905 struct rt2860_softc *sc = ic->ic_softc;
906 uint8_t wcid = ((struct rt2860_node *)ni)->wcid;
907 uint32_t tmp;
908
909 /* update BA session mask */
910 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4);
911 tmp |= (1 << tid) << 16;
912 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp);
913 return 0;
914 }
915
916 void
rt2860_ampdu_rx_stop(struct ieee80211com * ic,struct ieee80211_node * ni,uint8_t tid)917 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni,
918 uint8_t tid)
919 {
920 struct rt2860_softc *sc = ic->ic_softc;
921 uint8_t wcid = ((struct rt2860_node *)ni)->wcid;
922 uint32_t tmp;
923
924 /* update BA session mask */
925 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4);
926 tmp &= ~((1 << tid) << 16);
927 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp);
928 }
929
930 int
rt2860_newstate(struct ieee80211com * ic,enum ieee80211_state nstate,int arg)931 rt2860_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
932 {
933 struct rt2860_softc *sc = ic->ic_if.if_softc;
934 enum ieee80211_state ostate;
935 uint32_t tmp;
936
937 ostate = ic->ic_state;
938
939 if (ostate == IEEE80211_S_RUN) {
940 /* turn link LED off */
941 rt2860_set_leds(sc, RT2860_LED_RADIO);
942 }
943
944 switch (nstate) {
945 case IEEE80211_S_INIT:
946 if (ostate == IEEE80211_S_RUN) {
947 /* abort TSF synchronization */
948 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG);
949 RAL_WRITE(sc, RT2860_BCN_TIME_CFG,
950 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |
951 RT2860_TBTT_TIMER_EN));
952 }
953 rt2860_set_gp_timer(sc, 0);
954 break;
955
956 case IEEE80211_S_SCAN:
957 rt2860_switch_chan(sc, ic->ic_bss->ni_chan);
958 if (ostate != IEEE80211_S_SCAN)
959 rt2860_set_gp_timer(sc, 150);
960 break;
961
962 case IEEE80211_S_AUTH:
963 case IEEE80211_S_ASSOC:
964 rt2860_set_gp_timer(sc, 0);
965 rt2860_switch_chan(sc, ic->ic_bss->ni_chan);
966 break;
967
968 case IEEE80211_S_RUN:
969 rt2860_set_gp_timer(sc, 0);
970 rt2860_switch_chan(sc, ic->ic_bss->ni_chan);
971
972 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
973 rt2860_updateslot(ic);
974 rt2860_enable_mrr(sc);
975 rt2860_set_txpreamble(sc);
976 rt2860_set_basicrates(sc);
977 rt2860_set_bssid(sc, ic->ic_bss->ni_bssid);
978 }
979
980 #ifndef IEEE80211_STA_ONLY
981 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
982 ic->ic_opmode == IEEE80211_M_IBSS)
983 (void)rt2860_setup_beacon(sc);
984 #endif
985
986 if (ic->ic_opmode == IEEE80211_M_STA) {
987 /* fake a join to init the tx rate */
988 rt2860_newassoc(ic, ic->ic_bss, 1);
989 }
990
991 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
992 rt2860_enable_tsf_sync(sc);
993 rt2860_set_gp_timer(sc, 500);
994 }
995
996 /* turn link LED on */
997 rt2860_set_leds(sc, RT2860_LED_RADIO |
998 (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan) ?
999 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ));
1000 break;
1001 }
1002
1003 return sc->sc_newstate(ic, nstate, arg);
1004 }
1005
1006 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */
1007 uint16_t
rt3090_efuse_read_2(struct rt2860_softc * sc,uint16_t addr)1008 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr)
1009 {
1010 uint32_t tmp;
1011 uint16_t reg;
1012 int ntries;
1013
1014 addr *= 2;
1015 /*-
1016 * Read one 16-byte block into registers EFUSE_DATA[0-3]:
1017 * DATA0: F E D C
1018 * DATA1: B A 9 8
1019 * DATA2: 7 6 5 4
1020 * DATA3: 3 2 1 0
1021 */
1022 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL);
1023 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK);
1024 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK;
1025 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp);
1026 for (ntries = 0; ntries < 500; ntries++) {
1027 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL);
1028 if (!(tmp & RT3070_EFSROM_KICK))
1029 break;
1030 DELAY(2);
1031 }
1032 if (ntries == 500)
1033 return 0xffff;
1034
1035 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK)
1036 return 0xffff; /* address not found */
1037
1038 /* determine to which 32-bit register our 16-bit word belongs */
1039 reg = RT3070_EFUSE_DATA3 - (addr & 0xc);
1040 tmp = RAL_READ(sc, reg);
1041
1042 return (addr & 2) ? tmp >> 16 : tmp & 0xffff;
1043 }
1044
1045 /* Read 16 bits from eFUSE ROM (RT3290 only) */
1046 uint16_t
rt3290_efuse_read_2(struct rt2860_softc * sc,uint16_t addr)1047 rt3290_efuse_read_2(struct rt2860_softc *sc, uint16_t addr)
1048 {
1049 uint32_t tmp;
1050 uint16_t reg;
1051 int ntries;
1052
1053 addr *= 2;
1054 /*-
1055 * Read one 16-byte block into registers EFUSE_DATA[0-3]:
1056 * DATA3: 3 2 1 0
1057 * DATA2: 7 6 5 4
1058 * DATA1: B A 9 8
1059 * DATA0: F E D C
1060 */
1061 tmp = RAL_READ(sc, RT3290_EFUSE_CTRL);
1062 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK);
1063 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK;
1064 RAL_WRITE(sc, RT3290_EFUSE_CTRL, tmp);
1065 for (ntries = 0; ntries < 500; ntries++) {
1066 tmp = RAL_READ(sc, RT3290_EFUSE_CTRL);
1067 if (!(tmp & RT3070_EFSROM_KICK))
1068 break;
1069 DELAY(2);
1070 }
1071 if (ntries == 500)
1072 return 0xffff;
1073
1074 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK)
1075 return 0xffff; /* address not found */
1076
1077 /* determine to which 32-bit register our 16-bit word belongs */
1078 reg = RT3290_EFUSE_DATA3 + (addr & 0xc);
1079 tmp = RAL_READ(sc, reg);
1080
1081 return (addr & 2) ? tmp >> 16 : tmp & 0xffff;
1082 }
1083
1084 /*
1085 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46,
1086 * 93C66 or 93C86).
1087 */
1088 uint16_t
rt2860_eeprom_read_2(struct rt2860_softc * sc,uint16_t addr)1089 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr)
1090 {
1091 uint32_t tmp;
1092 uint16_t val;
1093 int n;
1094
1095 /* clock C once before the first command */
1096 RT2860_EEPROM_CTL(sc, 0);
1097
1098 RT2860_EEPROM_CTL(sc, RT2860_S);
1099 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
1100 RT2860_EEPROM_CTL(sc, RT2860_S);
1101
1102 /* write start bit (1) */
1103 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D);
1104 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C);
1105
1106 /* write READ opcode (10) */
1107 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D);
1108 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C);
1109 RT2860_EEPROM_CTL(sc, RT2860_S);
1110 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
1111
1112 /* write address (A5-A0 or A7-A0) */
1113 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7;
1114 for (; n >= 0; n--) {
1115 RT2860_EEPROM_CTL(sc, RT2860_S |
1116 (((addr >> n) & 1) << RT2860_SHIFT_D));
1117 RT2860_EEPROM_CTL(sc, RT2860_S |
1118 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C);
1119 }
1120
1121 RT2860_EEPROM_CTL(sc, RT2860_S);
1122
1123 /* read data Q15-Q0 */
1124 val = 0;
1125 for (n = 15; n >= 0; n--) {
1126 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
1127 tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
1128 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n;
1129 RT2860_EEPROM_CTL(sc, RT2860_S);
1130 }
1131
1132 RT2860_EEPROM_CTL(sc, 0);
1133
1134 /* clear Chip Select and clock C */
1135 RT2860_EEPROM_CTL(sc, RT2860_S);
1136 RT2860_EEPROM_CTL(sc, 0);
1137 RT2860_EEPROM_CTL(sc, RT2860_C);
1138
1139 return val;
1140 }
1141
1142 static __inline uint16_t
rt2860_srom_read(struct rt2860_softc * sc,uint8_t addr)1143 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr)
1144 {
1145 /* either eFUSE ROM or EEPROM */
1146 return sc->sc_srom_read(sc, addr);
1147 }
1148
1149 void
rt2860_intr_coherent(struct rt2860_softc * sc)1150 rt2860_intr_coherent(struct rt2860_softc *sc)
1151 {
1152 uint32_t tmp;
1153
1154 /* DMA finds data coherent event when checking the DDONE bit */
1155
1156 DPRINTF(("Tx/Rx Coherent interrupt\n"));
1157
1158 /* restart DMA engine */
1159 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
1160 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN);
1161 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
1162
1163 (void)rt2860_txrx_enable(sc);
1164 }
1165
1166 void
rt2860_drain_stats_fifo(struct rt2860_softc * sc)1167 rt2860_drain_stats_fifo(struct rt2860_softc *sc)
1168 {
1169 struct ifnet *ifp = &sc->sc_ic.ic_if;
1170 struct ieee80211_amrr_node *amn;
1171 uint32_t stat;
1172 uint8_t wcid, mcs, pid;
1173
1174 /* drain Tx status FIFO (maxsize = 16) */
1175 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) {
1176 DPRINTFN(4, ("tx stat 0x%08x\n", stat));
1177
1178 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff;
1179
1180 /* if no ACK was requested, no feedback is available */
1181 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff)
1182 continue;
1183
1184 /* update per-STA AMRR stats */
1185 amn = &sc->amn[wcid];
1186 amn->amn_txcnt++;
1187 if (stat & RT2860_TXQ_OK) {
1188 /*
1189 * Check if there were retries, ie if the Tx success
1190 * rate is different from the requested rate. Note
1191 * that it works only because we do not allow rate
1192 * fallback from OFDM to CCK.
1193 */
1194 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f;
1195 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf;
1196 if (mcs + 1 != pid)
1197 amn->amn_retrycnt++;
1198 } else {
1199 amn->amn_retrycnt++;
1200 ifp->if_oerrors++;
1201 }
1202 }
1203 }
1204
1205 void
rt2860_tx_intr(struct rt2860_softc * sc,int qid)1206 rt2860_tx_intr(struct rt2860_softc *sc, int qid)
1207 {
1208 struct ieee80211com *ic = &sc->sc_ic;
1209 struct ifnet *ifp = &ic->ic_if;
1210 struct rt2860_tx_ring *ring = &sc->txq[qid];
1211 uint32_t hw;
1212
1213 rt2860_drain_stats_fifo(sc);
1214
1215 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid));
1216 while (ring->next != hw) {
1217 struct rt2860_tx_data *data = ring->data[ring->next];
1218
1219 if (data != NULL) {
1220 bus_dmamap_sync(sc->sc_dmat, data->map, 0,
1221 data->map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1222 bus_dmamap_unload(sc->sc_dmat, data->map);
1223 m_freem(data->m);
1224 data->m= NULL;
1225 ieee80211_release_node(ic, data->ni);
1226 data->ni = NULL;
1227
1228 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
1229 ring->data[ring->next] = NULL;
1230 }
1231 ring->queued--;
1232 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT;
1233 }
1234
1235 sc->sc_tx_timer = 0;
1236 if (ring->queued <= RT2860_TX_RING_ONEMORE)
1237 sc->qfullmsk &= ~(1 << qid);
1238 ifq_clr_oactive(&ifp->if_snd);
1239 rt2860_start(ifp);
1240 }
1241
1242 /*
1243 * Return the Rx chain with the highest RSSI for a given frame.
1244 */
1245 static __inline uint8_t
rt2860_maxrssi_chain(struct rt2860_softc * sc,const struct rt2860_rxwi * rxwi)1246 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi)
1247 {
1248 uint8_t rxchain = 0;
1249
1250 if (sc->nrxchains > 1) {
1251 if (rxwi->rssi[1] > rxwi->rssi[rxchain])
1252 rxchain = 1;
1253 if (sc->nrxchains > 2)
1254 if (rxwi->rssi[2] > rxwi->rssi[rxchain])
1255 rxchain = 2;
1256 }
1257 return rxchain;
1258 }
1259
1260 void
rt2860_rx_intr(struct rt2860_softc * sc)1261 rt2860_rx_intr(struct rt2860_softc *sc)
1262 {
1263 struct mbuf_list ml = MBUF_LIST_INITIALIZER();
1264 struct ieee80211com *ic = &sc->sc_ic;
1265 struct ifnet *ifp = &ic->ic_if;
1266 struct ieee80211_frame *wh;
1267 struct ieee80211_rxinfo rxi;
1268 struct ieee80211_node *ni;
1269 struct mbuf *m, *m1;
1270 uint32_t hw;
1271 uint8_t ant, rssi;
1272 int error;
1273 #if NBPFILTER > 0
1274 struct rt2860_rx_radiotap_header *tap;
1275 uint16_t phy;
1276 #endif
1277
1278 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff;
1279 while (sc->rxq.cur != hw) {
1280 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur];
1281 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur];
1282 struct rt2860_rxwi *rxwi;
1283
1284 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map,
1285 sc->rxq.cur * sizeof (struct rt2860_rxd),
1286 sizeof (struct rt2860_rxd), BUS_DMASYNC_POSTREAD);
1287
1288 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) {
1289 DPRINTF(("RXD DDONE bit not set!\n"));
1290 break; /* should not happen */
1291 }
1292
1293 if (__predict_false(rxd->flags &
1294 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) {
1295 ifp->if_ierrors++;
1296 goto skip;
1297 }
1298
1299 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) {
1300 /* report MIC failures to net80211 for TKIP */
1301 ic->ic_stats.is_rx_locmicfail++;
1302 ieee80211_michael_mic_failure(ic, 0/* XXX */);
1303 ifp->if_ierrors++;
1304 goto skip;
1305 }
1306
1307 m1 = MCLGETL(NULL, M_DONTWAIT, MCLBYTES);
1308 if (__predict_false(m1 == NULL)) {
1309 ifp->if_ierrors++;
1310 goto skip;
1311 }
1312
1313 bus_dmamap_sync(sc->sc_dmat, data->map, 0,
1314 data->map->dm_mapsize, BUS_DMASYNC_POSTREAD);
1315 bus_dmamap_unload(sc->sc_dmat, data->map);
1316
1317 error = bus_dmamap_load(sc->sc_dmat, data->map,
1318 mtod(m1, void *), MCLBYTES, NULL,
1319 BUS_DMA_READ | BUS_DMA_NOWAIT);
1320 if (__predict_false(error != 0)) {
1321 m_freem(m1);
1322
1323 /* try to reload the old mbuf */
1324 error = bus_dmamap_load(sc->sc_dmat, data->map,
1325 mtod(data->m, void *), MCLBYTES, NULL,
1326 BUS_DMA_READ | BUS_DMA_NOWAIT);
1327 if (__predict_false(error != 0)) {
1328 panic("%s: could not load old rx mbuf",
1329 sc->sc_dev.dv_xname);
1330 }
1331 /* physical address may have changed */
1332 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr);
1333 ifp->if_ierrors++;
1334 goto skip;
1335 }
1336
1337 /*
1338 * New mbuf successfully loaded, update Rx ring and continue
1339 * processing.
1340 */
1341 m = data->m;
1342 data->m = m1;
1343 rxd->sdp0 = htole32(data->map->dm_segs[0].ds_addr);
1344
1345 rxwi = mtod(m, struct rt2860_rxwi *);
1346
1347 /* finalize mbuf */
1348 m->m_data = (caddr_t)(rxwi + 1);
1349 m->m_pkthdr.len = m->m_len = letoh16(rxwi->len) & 0xfff;
1350
1351 wh = mtod(m, struct ieee80211_frame *);
1352 memset(&rxi, 0, sizeof(rxi));
1353 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1354 /* frame is decrypted by hardware */
1355 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED;
1356 rxi.rxi_flags |= IEEE80211_RXI_HWDEC;
1357 }
1358
1359 /* HW may insert 2 padding bytes after 802.11 header */
1360 if (rxd->flags & htole32(RT2860_RX_L2PAD)) {
1361 u_int hdrlen = ieee80211_get_hdrlen(wh);
1362 memmove((caddr_t)wh + 2, wh, hdrlen);
1363 m->m_data += 2;
1364 wh = mtod(m, struct ieee80211_frame *);
1365 }
1366
1367 ant = rt2860_maxrssi_chain(sc, rxwi);
1368 rssi = rxwi->rssi[ant];
1369
1370 #if NBPFILTER > 0
1371 if (__predict_true(sc->sc_drvbpf == NULL))
1372 goto skipbpf;
1373
1374 tap = &sc->sc_rxtap;
1375 tap->wr_flags = 0;
1376 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq);
1377 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags);
1378 tap->wr_antsignal = rssi;
1379 tap->wr_antenna = ant;
1380 tap->wr_dbm_antsignal = rt2860_rssi2dbm(sc, rssi, ant);
1381 tap->wr_rate = 2; /* in case it can't be found below */
1382 phy = letoh16(rxwi->phy);
1383 switch (phy & RT2860_PHY_MODE) {
1384 case RT2860_PHY_CCK:
1385 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) {
1386 case 0: tap->wr_rate = 2; break;
1387 case 1: tap->wr_rate = 4; break;
1388 case 2: tap->wr_rate = 11; break;
1389 case 3: tap->wr_rate = 22; break;
1390 }
1391 if (phy & RT2860_PHY_SHPRE)
1392 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
1393 break;
1394 case RT2860_PHY_OFDM:
1395 switch (phy & RT2860_PHY_MCS) {
1396 case 0: tap->wr_rate = 12; break;
1397 case 1: tap->wr_rate = 18; break;
1398 case 2: tap->wr_rate = 24; break;
1399 case 3: tap->wr_rate = 36; break;
1400 case 4: tap->wr_rate = 48; break;
1401 case 5: tap->wr_rate = 72; break;
1402 case 6: tap->wr_rate = 96; break;
1403 case 7: tap->wr_rate = 108; break;
1404 }
1405 break;
1406 }
1407 bpf_mtap_hdr(sc->sc_drvbpf, tap, sc->sc_rxtap_len, m,
1408 BPF_DIRECTION_IN);
1409 skipbpf:
1410 #endif
1411 /* grab a reference to the source node */
1412 ni = ieee80211_find_rxnode(ic, wh);
1413
1414 /* send the frame to the 802.11 layer */
1415 rxi.rxi_rssi = rssi;
1416 ieee80211_inputm(ifp, m, ni, &rxi, &ml);
1417
1418 /* node is no longer needed */
1419 ieee80211_release_node(ic, ni);
1420
1421 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE);
1422
1423 bus_dmamap_sync(sc->sc_dmat, sc->rxq.map,
1424 sc->rxq.cur * sizeof (struct rt2860_rxd),
1425 sizeof (struct rt2860_rxd), BUS_DMASYNC_PREWRITE);
1426
1427 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT;
1428 }
1429 if_input(ifp, &ml);
1430
1431 /* tell HW what we have processed */
1432 RAL_WRITE(sc, RT2860_RX_CALC_IDX,
1433 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT);
1434 }
1435
1436 void
rt2860_tbtt_intr(struct rt2860_softc * sc)1437 rt2860_tbtt_intr(struct rt2860_softc *sc)
1438 {
1439 struct ieee80211com *ic = &sc->sc_ic;
1440
1441 #ifndef IEEE80211_STA_ONLY
1442 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
1443 /* one less beacon until next DTIM */
1444 if (ic->ic_dtim_count == 0)
1445 ic->ic_dtim_count = ic->ic_dtim_period - 1;
1446 else
1447 ic->ic_dtim_count--;
1448
1449 /* update dynamic parts of beacon */
1450 rt2860_setup_beacon(sc);
1451
1452 /* flush buffered multicast frames */
1453 if (ic->ic_dtim_count == 0)
1454 ieee80211_notify_dtim(ic);
1455 }
1456 #endif
1457 /* check if protection mode has changed */
1458 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) {
1459 rt2860_updateprot(ic);
1460 sc->sc_ic_flags = ic->ic_flags;
1461 }
1462 }
1463
1464 void
rt2860_gp_intr(struct rt2860_softc * sc)1465 rt2860_gp_intr(struct rt2860_softc *sc)
1466 {
1467 struct ieee80211com *ic = &sc->sc_ic;
1468
1469 DPRINTFN(2, ("GP timeout state=%d\n", ic->ic_state));
1470
1471 if (ic->ic_state == IEEE80211_S_SCAN)
1472 ieee80211_next_scan(&ic->ic_if);
1473 else if (ic->ic_state == IEEE80211_S_RUN)
1474 rt2860_updatestats(sc);
1475 }
1476
1477 int
rt2860_intr(void * arg)1478 rt2860_intr(void *arg)
1479 {
1480 struct rt2860_softc *sc = arg;
1481 uint32_t r;
1482
1483 r = RAL_READ(sc, RT2860_INT_STATUS);
1484 if (__predict_false(r == 0xffffffff))
1485 return 0; /* device likely went away */
1486 if (r == 0)
1487 return 0; /* not for us */
1488
1489 /* acknowledge interrupts */
1490 RAL_WRITE(sc, RT2860_INT_STATUS, r);
1491
1492 if (r & RT2860_TX_RX_COHERENT)
1493 rt2860_intr_coherent(sc);
1494
1495 if (r & RT2860_MAC_INT_2) /* TX status */
1496 rt2860_drain_stats_fifo(sc);
1497
1498 if (r & RT2860_TX_DONE_INT5)
1499 rt2860_tx_intr(sc, 5);
1500
1501 if (r & RT2860_RX_DONE_INT)
1502 rt2860_rx_intr(sc);
1503
1504 if (r & RT2860_TX_DONE_INT4)
1505 rt2860_tx_intr(sc, 4);
1506
1507 if (r & RT2860_TX_DONE_INT3)
1508 rt2860_tx_intr(sc, 3);
1509
1510 if (r & RT2860_TX_DONE_INT2)
1511 rt2860_tx_intr(sc, 2);
1512
1513 if (r & RT2860_TX_DONE_INT1)
1514 rt2860_tx_intr(sc, 1);
1515
1516 if (r & RT2860_TX_DONE_INT0)
1517 rt2860_tx_intr(sc, 0);
1518
1519 if (r & RT2860_MAC_INT_0) /* TBTT */
1520 rt2860_tbtt_intr(sc);
1521
1522 if (r & RT2860_MAC_INT_3) /* Auto wakeup */
1523 /* TBD wakeup */;
1524
1525 if (r & RT2860_MAC_INT_4) /* GP timer */
1526 rt2860_gp_intr(sc);
1527
1528 return 1;
1529 }
1530
1531 int
rt2860_tx(struct rt2860_softc * sc,struct mbuf * m,struct ieee80211_node * ni)1532 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
1533 {
1534 struct ieee80211com *ic = &sc->sc_ic;
1535 struct rt2860_node *rn = (void *)ni;
1536 struct rt2860_tx_ring *ring;
1537 struct rt2860_tx_data *data;
1538 struct rt2860_txd *txd;
1539 struct rt2860_txwi *txwi;
1540 struct ieee80211_frame *wh;
1541 bus_dma_segment_t *seg;
1542 u_int hdrlen;
1543 uint16_t qos, dur;
1544 uint8_t type, qsel, mcs, pid, tid, qid;
1545 int nsegs, hasqos, ridx, ctl_ridx;
1546
1547 /* the data pool contains at least one element, pick the first */
1548 data = SLIST_FIRST(&sc->data_pool);
1549
1550 wh = mtod(m, struct ieee80211_frame *);
1551 hdrlen = ieee80211_get_hdrlen(wh);
1552 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1553
1554 if ((hasqos = ieee80211_has_qos(wh))) {
1555 qos = ieee80211_get_qos(wh);
1556 tid = qos & IEEE80211_QOS_TID;
1557 qid = ieee80211_up_to_ac(ic, tid);
1558 } else {
1559 qos = 0;
1560 tid = 0;
1561 qid = (type == IEEE80211_FC0_TYPE_MGT) ?
1562 sc->mgtqid : EDCA_AC_BE;
1563 }
1564 ring = &sc->txq[qid];
1565
1566 /* pickup a rate index */
1567 if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
1568 type != IEEE80211_FC0_TYPE_DATA) {
1569 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ?
1570 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1;
1571 ctl_ridx = rt2860_rates[ridx].ctl_ridx;
1572 } else if (ic->ic_fixed_rate != -1) {
1573 ridx = sc->fixed_ridx;
1574 ctl_ridx = rt2860_rates[ridx].ctl_ridx;
1575 } else {
1576 ridx = rn->ridx[ni->ni_txrate];
1577 ctl_ridx = rn->ctl_ridx[ni->ni_txrate];
1578 }
1579
1580 /* get MCS code from rate index */
1581 mcs = rt2860_rates[ridx].mcs;
1582
1583 /* setup TX Wireless Information */
1584 txwi = data->txwi;
1585 txwi->flags = 0;
1586 /* let HW generate seq numbers for non-QoS frames */
1587 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ;
1588 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA) ? rn->wcid : 0xff;
1589 txwi->len = htole16(m->m_pkthdr.len);
1590 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) {
1591 txwi->phy = htole16(RT2860_PHY_CCK);
1592 if (ridx != RT2860_RIDX_CCK1 &&
1593 (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1594 mcs |= RT2860_PHY_SHPRE;
1595 } else
1596 txwi->phy = htole16(RT2860_PHY_OFDM);
1597 txwi->phy |= htole16(mcs);
1598
1599 /*
1600 * We store the MCS code into the driver-private PacketID field.
1601 * The PacketID is latched into TX_STAT_FIFO when Tx completes so
1602 * that we know at which initial rate the frame was transmitted.
1603 * We add 1 to the MCS code because setting the PacketID field to
1604 * 0 means that we don't want feedback in TX_STAT_FIFO.
1605 */
1606 pid = (mcs + 1) & 0xf;
1607 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT);
1608
1609 /* check if RTS/CTS or CTS-to-self protection is required */
1610 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1611 (m->m_pkthdr.len + IEEE80211_CRC_LEN > ic->ic_rtsthreshold ||
1612 ((ic->ic_flags & IEEE80211_F_USEPROT) &&
1613 rt2860_rates[ridx].phy == IEEE80211_T_OFDM)))
1614 txwi->txop = RT2860_TX_TXOP_HT;
1615 else
1616 txwi->txop = RT2860_TX_TXOP_BACKOFF;
1617
1618 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1619 (!hasqos || (qos & IEEE80211_QOS_ACK_POLICY_MASK) !=
1620 IEEE80211_QOS_ACK_POLICY_NOACK)) {
1621 txwi->xflags |= RT2860_TX_ACK;
1622
1623 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
1624 dur = rt2860_rates[ctl_ridx].sp_ack_dur;
1625 else
1626 dur = rt2860_rates[ctl_ridx].lp_ack_dur;
1627 *(uint16_t *)wh->i_dur = htole16(dur);
1628 }
1629 #ifndef IEEE80211_STA_ONLY
1630 /* ask MAC to insert timestamp into probe responses */
1631 if ((wh->i_fc[0] &
1632 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
1633 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP))
1634 /* NOTE: beacons do not pass through tx_data() */
1635 txwi->flags |= RT2860_TX_TS;
1636 #endif
1637
1638 #if NBPFILTER > 0
1639 if (__predict_false(sc->sc_drvbpf != NULL)) {
1640 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap;
1641
1642 tap->wt_flags = 0;
1643 tap->wt_rate = rt2860_rates[ridx].rate;
1644 tap->wt_chan_freq = htole16(ic->ic_ibss_chan->ic_freq);
1645 tap->wt_chan_flags = htole16(ic->ic_ibss_chan->ic_flags);
1646 if (mcs & RT2860_PHY_SHPRE)
1647 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
1648
1649 bpf_mtap_hdr(sc->sc_drvbpf, tap, sc->sc_txtap_len, m,
1650 BPF_DIRECTION_OUT);
1651 }
1652 #endif
1653
1654 /* copy and trim 802.11 header */
1655 memcpy(txwi + 1, wh, hdrlen);
1656 m_adj(m, hdrlen);
1657
1658 KASSERT (ring->queued <= RT2860_TX_RING_ONEMORE); /* <1> */
1659
1660 if (bus_dmamap_load_mbuf(sc->sc_dmat, data->map, m, BUS_DMA_NOWAIT)) {
1661 if (m_defrag(m, M_DONTWAIT))
1662 return (ENOBUFS);
1663 if (bus_dmamap_load_mbuf(sc->sc_dmat,
1664 data->map, m, BUS_DMA_NOWAIT))
1665 return (EFBIG);
1666 }
1667
1668 /* The map will fit into the tx ring: (a "full" ring may have a few
1669 * unused descriptors, at most (txds(MAX_SCATTER) - 1))
1670 *
1671 * ring->queued + txds(data->map->nsegs)
1672 * <= { <0> data->map->nsegs <= MAX_SCATTER }
1673 * ring->queued + txds(MAX_SCATTER)
1674 * <= { <1> ring->queued <= TX_RING_MAX - txds(MAX_SCATTER) }
1675 * TX_RING_MAX - txds(MAX_SCATTER) + txds(MAX_SCATTER)
1676 * <= { arithmetic }
1677 * TX_RING_MAX
1678 */
1679
1680 qsel = (qid < EDCA_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT;
1681
1682 /* first segment is TXWI + 802.11 header */
1683 txd = &ring->txd[ring->cur];
1684 txd->sdp0 = htole32(data->paddr);
1685 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + hdrlen);
1686 txd->flags = qsel;
1687
1688 /* setup payload segments */
1689 seg = data->map->dm_segs;
1690 for (nsegs = data->map->dm_nsegs; nsegs >= 2; nsegs -= 2) {
1691 txd->sdp1 = htole32(seg->ds_addr);
1692 txd->sdl1 = htole16(seg->ds_len);
1693 seg++;
1694 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1695 /* grab a new Tx descriptor */
1696 txd = &ring->txd[ring->cur];
1697 txd->sdp0 = htole32(seg->ds_addr);
1698 txd->sdl0 = htole16(seg->ds_len);
1699 txd->flags = qsel;
1700 seg++;
1701 }
1702 /* finalize last segment */
1703 if (nsegs > 0) {
1704 txd->sdp1 = htole32(seg->ds_addr);
1705 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1);
1706 } else {
1707 txd->sdl0 |= htole16(RT2860_TX_LS0);
1708 txd->sdl1 = 0;
1709 }
1710
1711 /* remove from the free pool and link it into the SW Tx slot */
1712 SLIST_REMOVE_HEAD(&sc->data_pool, next);
1713 data->m = m;
1714 data->ni = ni;
1715 ring->data[ring->cur] = data;
1716
1717 bus_dmamap_sync(sc->sc_dmat, sc->txwi_map,
1718 (caddr_t)txwi - sc->txwi_vaddr, RT2860_TXWI_DMASZ,
1719 BUS_DMASYNC_PREWRITE);
1720 bus_dmamap_sync(sc->sc_dmat, data->map, 0, data->map->dm_mapsize,
1721 BUS_DMASYNC_PREWRITE);
1722 bus_dmamap_sync(sc->sc_dmat, ring->map, 0, ring->map->dm_mapsize,
1723 BUS_DMASYNC_PREWRITE);
1724
1725 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n",
1726 qid, txwi->wcid, data->map->dm_nsegs, ridx));
1727
1728 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1729 ring->queued += 1 + (data->map->dm_nsegs / 2);
1730 if (ring->queued > RT2860_TX_RING_ONEMORE)
1731 sc->qfullmsk |= 1 << qid;
1732
1733 /* kick Tx */
1734 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur);
1735
1736 return 0;
1737 }
1738
1739 void
rt2860_start(struct ifnet * ifp)1740 rt2860_start(struct ifnet *ifp)
1741 {
1742 struct rt2860_softc *sc = ifp->if_softc;
1743 struct ieee80211com *ic = &sc->sc_ic;
1744 struct ieee80211_node *ni;
1745 struct mbuf *m;
1746
1747 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd))
1748 return;
1749
1750 for (;;) {
1751 if (SLIST_EMPTY(&sc->data_pool) || sc->qfullmsk != 0) {
1752 ifq_set_oactive(&ifp->if_snd);
1753 break;
1754 }
1755 /* send pending management frames first */
1756 m = mq_dequeue(&ic->ic_mgtq);
1757 if (m != NULL) {
1758 ni = m->m_pkthdr.ph_cookie;
1759 goto sendit;
1760 }
1761 if (ic->ic_state != IEEE80211_S_RUN)
1762 break;
1763
1764 /* send buffered frames for power-save mode */
1765 m = mq_dequeue(&ic->ic_pwrsaveq);
1766 if (m != NULL) {
1767 ni = m->m_pkthdr.ph_cookie;
1768 goto sendit;
1769 }
1770
1771 /* encapsulate and send data frames */
1772 m = ifq_dequeue(&ifp->if_snd);
1773 if (m == NULL)
1774 break;
1775 #if NBPFILTER > 0
1776 if (ifp->if_bpf != NULL)
1777 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT);
1778 #endif
1779 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL)
1780 continue;
1781 sendit:
1782 #if NBPFILTER > 0
1783 if (ic->ic_rawbpf != NULL)
1784 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT);
1785 #endif
1786 if (rt2860_tx(sc, m, ni) != 0) {
1787 m_freem(m);
1788 ieee80211_release_node(ic, ni);
1789 ifp->if_oerrors++;
1790 continue;
1791 }
1792
1793 sc->sc_tx_timer = 5;
1794 ifp->if_timer = 1;
1795 }
1796 }
1797
1798 void
rt2860_watchdog(struct ifnet * ifp)1799 rt2860_watchdog(struct ifnet *ifp)
1800 {
1801 struct rt2860_softc *sc = ifp->if_softc;
1802
1803 ifp->if_timer = 0;
1804
1805 if (sc->sc_tx_timer > 0) {
1806 if (--sc->sc_tx_timer == 0) {
1807 printf("%s: device timeout\n", sc->sc_dev.dv_xname);
1808 rt2860_stop(ifp, 0);
1809 rt2860_init(ifp);
1810 ifp->if_oerrors++;
1811 return;
1812 }
1813 ifp->if_timer = 1;
1814 }
1815
1816 ieee80211_watchdog(ifp);
1817 }
1818
1819 int
rt2860_ioctl(struct ifnet * ifp,u_long cmd,caddr_t data)1820 rt2860_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1821 {
1822 struct rt2860_softc *sc = ifp->if_softc;
1823 struct ieee80211com *ic = &sc->sc_ic;
1824 int s, error = 0;
1825
1826 s = splnet();
1827
1828 switch (cmd) {
1829 case SIOCSIFADDR:
1830 ifp->if_flags |= IFF_UP;
1831 /* FALLTHROUGH */
1832 case SIOCSIFFLAGS:
1833 if (ifp->if_flags & IFF_UP) {
1834 if (!(ifp->if_flags & IFF_RUNNING))
1835 rt2860_init(ifp);
1836 } else {
1837 if (ifp->if_flags & IFF_RUNNING)
1838 rt2860_stop(ifp, 1);
1839 }
1840 break;
1841
1842 case SIOCS80211CHANNEL:
1843 /*
1844 * This allows for fast channel switching in monitor mode
1845 * (used by kismet). In IBSS mode, we must explicitly reset
1846 * the interface to generate a new beacon frame.
1847 */
1848 error = ieee80211_ioctl(ifp, cmd, data);
1849 if (error == ENETRESET &&
1850 ic->ic_opmode == IEEE80211_M_MONITOR) {
1851 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1852 (IFF_UP | IFF_RUNNING))
1853 rt2860_switch_chan(sc, ic->ic_ibss_chan);
1854 error = 0;
1855 }
1856 break;
1857
1858 default:
1859 error = ieee80211_ioctl(ifp, cmd, data);
1860 }
1861
1862 if (error == ENETRESET) {
1863 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1864 (IFF_UP | IFF_RUNNING)) {
1865 rt2860_stop(ifp, 0);
1866 rt2860_init(ifp);
1867 }
1868 error = 0;
1869 }
1870
1871 splx(s);
1872
1873 return error;
1874 }
1875
1876 /*
1877 * Reading and writing from/to the BBP is different from RT2560 and RT2661.
1878 * We access the BBP through the 8051 microcontroller unit which means that
1879 * the microcode must be loaded first.
1880 */
1881 void
rt2860_mcu_bbp_write(struct rt2860_softc * sc,uint8_t reg,uint8_t val)1882 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)
1883 {
1884 int ntries;
1885
1886 for (ntries = 0; ntries < 100; ntries++) {
1887 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK))
1888 break;
1889 DELAY(1);
1890 }
1891 if (ntries == 100) {
1892 printf("%s: could not write to BBP through MCU\n",
1893 sc->sc_dev.dv_xname);
1894 return;
1895 }
1896
1897 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL |
1898 RT2860_BBP_CSR_KICK | reg << 8 | val);
1899 RAL_BARRIER_WRITE(sc);
1900
1901 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0);
1902 DELAY(1000);
1903 }
1904
1905 uint8_t
rt2860_mcu_bbp_read(struct rt2860_softc * sc,uint8_t reg)1906 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg)
1907 {
1908 uint32_t val;
1909 int ntries;
1910
1911 for (ntries = 0; ntries < 100; ntries++) {
1912 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK))
1913 break;
1914 DELAY(1);
1915 }
1916 if (ntries == 100) {
1917 printf("%s: could not read from BBP through MCU\n",
1918 sc->sc_dev.dv_xname);
1919 return 0;
1920 }
1921
1922 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL |
1923 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8);
1924 RAL_BARRIER_WRITE(sc);
1925
1926 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0);
1927 DELAY(1000);
1928
1929 for (ntries = 0; ntries < 100; ntries++) {
1930 val = RAL_READ(sc, RT2860_H2M_BBPAGENT);
1931 if (!(val & RT2860_BBP_CSR_KICK))
1932 return val & 0xff;
1933 DELAY(1);
1934 }
1935 printf("%s: could not read from BBP through MCU\n",
1936 sc->sc_dev.dv_xname);
1937
1938 return 0;
1939 }
1940
1941 /*
1942 * Write to one of the 4 programmable 24-bit RF registers.
1943 */
1944 void
rt2860_rf_write(struct rt2860_softc * sc,uint8_t reg,uint32_t val)1945 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val)
1946 {
1947 uint32_t tmp;
1948 int ntries;
1949
1950 for (ntries = 0; ntries < 100; ntries++) {
1951 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL))
1952 break;
1953 DELAY(1);
1954 }
1955 if (ntries == 100) {
1956 printf("%s: could not write to RF\n", sc->sc_dev.dv_xname);
1957 return;
1958 }
1959
1960 /* RF registers are 24-bit on the RT2860 */
1961 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT |
1962 (val & 0x3fffff) << 2 | (reg & 3);
1963 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp);
1964 }
1965
1966 uint8_t
rt3090_rf_read(struct rt2860_softc * sc,uint8_t reg)1967 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg)
1968 {
1969 uint32_t tmp;
1970 int ntries;
1971
1972 for (ntries = 0; ntries < 100; ntries++) {
1973 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK))
1974 break;
1975 DELAY(1);
1976 }
1977 if (ntries == 100) {
1978 printf("%s: could not read RF register\n",
1979 sc->sc_dev.dv_xname);
1980 return 0xff;
1981 }
1982 tmp = RT3070_RF_KICK | reg << 8;
1983 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp);
1984
1985 for (ntries = 0; ntries < 100; ntries++) {
1986 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG);
1987 if (!(tmp & RT3070_RF_KICK))
1988 break;
1989 DELAY(1);
1990 }
1991 if (ntries == 100) {
1992 printf("%s: could not read RF register\n",
1993 sc->sc_dev.dv_xname);
1994 return 0xff;
1995 }
1996 return tmp & 0xff;
1997 }
1998
1999 void
rt3090_rf_write(struct rt2860_softc * sc,uint8_t reg,uint8_t val)2000 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)
2001 {
2002 uint32_t tmp;
2003 int ntries;
2004
2005 for (ntries = 0; ntries < 10; ntries++) {
2006 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK))
2007 break;
2008 DELAY(10);
2009 }
2010 if (ntries == 10) {
2011 printf("%s: could not write to RF\n", sc->sc_dev.dv_xname);
2012 return;
2013 }
2014
2015 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val;
2016 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp);
2017 }
2018
2019 /*
2020 * Send a command to the 8051 microcontroller unit.
2021 */
2022 int
rt2860_mcu_cmd(struct rt2860_softc * sc,uint8_t cmd,uint16_t arg,int wait)2023 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait)
2024 {
2025 int slot, ntries;
2026 uint32_t tmp;
2027 uint8_t cid;
2028
2029 for (ntries = 0; ntries < 100; ntries++) {
2030 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY))
2031 break;
2032 DELAY(2);
2033 }
2034 if (ntries == 100)
2035 return EIO;
2036
2037 cid = wait ? cmd : RT2860_TOKEN_NO_INTR;
2038 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg);
2039 RAL_BARRIER_WRITE(sc);
2040 RAL_WRITE(sc, RT2860_HOST_CMD, cmd);
2041
2042 if (!wait)
2043 return 0;
2044 /* wait for the command to complete */
2045 for (ntries = 0; ntries < 200; ntries++) {
2046 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID);
2047 /* find the command slot */
2048 for (slot = 0; slot < 4; slot++, tmp >>= 8)
2049 if ((tmp & 0xff) == cid)
2050 break;
2051 if (slot < 4)
2052 break;
2053 DELAY(100);
2054 }
2055 if (ntries == 200) {
2056 /* clear command and status */
2057 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff);
2058 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff);
2059 return ETIMEDOUT;
2060 }
2061 /* get command status (1 means success) */
2062 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS);
2063 tmp = (tmp >> (slot * 8)) & 0xff;
2064 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n",
2065 cmd, slot, tmp));
2066 /* clear command and status */
2067 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff);
2068 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff);
2069 return (tmp == 1) ? 0 : EIO;
2070 }
2071
2072 void
rt2860_enable_mrr(struct rt2860_softc * sc)2073 rt2860_enable_mrr(struct rt2860_softc *sc)
2074 {
2075 #define CCK(mcs) (mcs)
2076 #define OFDM(mcs) (1 << 3 | (mcs))
2077 RAL_WRITE(sc, RT2860_LG_FBK_CFG0,
2078 OFDM(6) << 28 | /* 54->48 */
2079 OFDM(5) << 24 | /* 48->36 */
2080 OFDM(4) << 20 | /* 36->24 */
2081 OFDM(3) << 16 | /* 24->18 */
2082 OFDM(2) << 12 | /* 18->12 */
2083 OFDM(1) << 8 | /* 12-> 9 */
2084 OFDM(0) << 4 | /* 9-> 6 */
2085 OFDM(0)); /* 6-> 6 */
2086
2087 RAL_WRITE(sc, RT2860_LG_FBK_CFG1,
2088 CCK(2) << 12 | /* 11->5.5 */
2089 CCK(1) << 8 | /* 5.5-> 2 */
2090 CCK(0) << 4 | /* 2-> 1 */
2091 CCK(0)); /* 1-> 1 */
2092 #undef OFDM
2093 #undef CCK
2094 }
2095
2096 void
rt2860_set_txpreamble(struct rt2860_softc * sc)2097 rt2860_set_txpreamble(struct rt2860_softc *sc)
2098 {
2099 uint32_t tmp;
2100
2101 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG);
2102 tmp &= ~RT2860_CCK_SHORT_EN;
2103 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE)
2104 tmp |= RT2860_CCK_SHORT_EN;
2105 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp);
2106 }
2107
2108 void
rt2860_set_basicrates(struct rt2860_softc * sc)2109 rt2860_set_basicrates(struct rt2860_softc *sc)
2110 {
2111 struct ieee80211com *ic = &sc->sc_ic;
2112
2113 /* set basic rates mask */
2114 if (ic->ic_curmode == IEEE80211_MODE_11B)
2115 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x003);
2116 else if (ic->ic_curmode == IEEE80211_MODE_11A)
2117 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x150);
2118 else /* 11g */
2119 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x15f);
2120 }
2121
2122 void
rt2860_select_chan_group(struct rt2860_softc * sc,int group)2123 rt2860_select_chan_group(struct rt2860_softc *sc, int group)
2124 {
2125 uint32_t tmp;
2126 uint8_t agc;
2127
2128 /* Wait for BBP to settle */
2129 DELAY(1000);
2130
2131 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]);
2132 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]);
2133 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]);
2134 rt2860_mcu_bbp_write(sc, 86, 0x00);
2135
2136 if (group == 0) {
2137 if (sc->ext_2ghz_lna) {
2138 rt2860_mcu_bbp_write(sc, 82, 0x62);
2139 rt2860_mcu_bbp_write(sc, 75, 0x46);
2140 } else {
2141 rt2860_mcu_bbp_write(sc, 82, 0x84);
2142 rt2860_mcu_bbp_write(sc, 75, 0x50);
2143 }
2144 } else {
2145 if (sc->mac_ver == 0x3572)
2146 rt2860_mcu_bbp_write(sc, 82, 0x94);
2147 else
2148 rt2860_mcu_bbp_write(sc, 82, 0xf2);
2149
2150 if (sc->ext_5ghz_lna)
2151 rt2860_mcu_bbp_write(sc, 75, 0x46);
2152 else
2153 rt2860_mcu_bbp_write(sc, 75, 0x50);
2154 }
2155
2156 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG);
2157 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P);
2158 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P;
2159 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp);
2160
2161 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */
2162 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN;
2163 if (sc->nrxchains > 1)
2164 tmp |= RT2860_LNA_PE1_EN;
2165 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2)
2166 tmp |= RT3593_LNA_PE2_EN;
2167 if (group == 0) { /* 2GHz */
2168 tmp |= RT2860_PA_PE_G0_EN;
2169 if (sc->ntxchains > 1)
2170 tmp |= RT2860_PA_PE_G1_EN;
2171 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2)
2172 tmp |= RT3593_PA_PE_G2_EN;
2173 } else { /* 5GHz */
2174 tmp |= RT2860_PA_PE_A0_EN;
2175 if (sc->ntxchains > 1)
2176 tmp |= RT2860_PA_PE_A1_EN;
2177 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2)
2178 tmp |= RT3593_PA_PE_A2_EN;
2179 }
2180 if (sc->mac_ver == 0x3572) {
2181 rt3090_rf_write(sc, 8, 0x00);
2182 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp);
2183 rt3090_rf_write(sc, 8, 0x80);
2184 } else
2185 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp);
2186
2187 if (sc->mac_ver == 0x3593) {
2188 tmp = RAL_READ(sc, RT2860_GPIO_CTRL);
2189 if (sc->sc_flags & RT2860_PCIE) {
2190 tmp &= ~0x01010000;
2191 if (group == 0)
2192 tmp |= 0x00010000;
2193 } else {
2194 tmp &= ~0x00008080;
2195 if (group == 0)
2196 tmp |= 0x00000080;
2197 }
2198 tmp = (tmp & ~0x00001000) | 0x00000010;
2199 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp);
2200 }
2201
2202 /* set initial AGC value */
2203 if (group == 0) { /* 2GHz band */
2204 if (sc->mac_ver >= 0x3071)
2205 agc = 0x1c + sc->lna[0] * 2;
2206 else
2207 agc = 0x2e + sc->lna[0];
2208 } else { /* 5GHz band */
2209 if (sc->mac_ver == 0x3572)
2210 agc = 0x22 + (sc->lna[group] * 5) / 3;
2211 else
2212 agc = 0x32 + (sc->lna[group] * 5) / 3;
2213 }
2214 rt2860_mcu_bbp_write(sc, 66, agc);
2215
2216 DELAY(1000);
2217 }
2218
2219 void
rt2860_set_chan(struct rt2860_softc * sc,u_int chan)2220 rt2860_set_chan(struct rt2860_softc *sc, u_int chan)
2221 {
2222 const struct rfprog *rfprog = rt2860_rf2850;
2223 uint32_t r2, r3, r4;
2224 int8_t txpow1, txpow2;
2225 u_int i;
2226
2227 /* find the settings for this channel (we know it exists) */
2228 for (i = 0; rfprog[i].chan != chan; i++)
2229 ;
2230
2231 r2 = rfprog[i].r2;
2232 if (sc->ntxchains == 1)
2233 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */
2234 if (sc->nrxchains == 1)
2235 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */
2236 else if (sc->nrxchains == 2)
2237 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */
2238
2239 /* use Tx power values from EEPROM */
2240 txpow1 = sc->txpow1[i];
2241 txpow2 = sc->txpow2[i];
2242 if (chan > 14) {
2243 if (txpow1 >= 0)
2244 txpow1 = txpow1 << 1 | 1;
2245 else
2246 txpow1 = (7 + txpow1) << 1;
2247 if (txpow2 >= 0)
2248 txpow2 = txpow2 << 1 | 1;
2249 else
2250 txpow2 = (7 + txpow2) << 1;
2251 }
2252 r3 = rfprog[i].r3 | txpow1 << 7;
2253 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4;
2254
2255 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1);
2256 rt2860_rf_write(sc, RT2860_RF2, r2);
2257 rt2860_rf_write(sc, RT2860_RF3, r3);
2258 rt2860_rf_write(sc, RT2860_RF4, r4);
2259
2260 DELAY(200);
2261
2262 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1);
2263 rt2860_rf_write(sc, RT2860_RF2, r2);
2264 rt2860_rf_write(sc, RT2860_RF3, r3 | 1);
2265 rt2860_rf_write(sc, RT2860_RF4, r4);
2266
2267 DELAY(200);
2268
2269 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1);
2270 rt2860_rf_write(sc, RT2860_RF2, r2);
2271 rt2860_rf_write(sc, RT2860_RF3, r3);
2272 rt2860_rf_write(sc, RT2860_RF4, r4);
2273 }
2274
2275 void
rt3090_set_chan(struct rt2860_softc * sc,u_int chan)2276 rt3090_set_chan(struct rt2860_softc *sc, u_int chan)
2277 {
2278 int8_t txpow1, txpow2;
2279 uint8_t rf;
2280 int i;
2281
2282 KASSERT(chan >= 1 && chan <= 14); /* RT3090 is 2GHz only */
2283
2284 /* find the settings for this channel (we know it exists) */
2285 for (i = 0; rt2860_rf2850[i].chan != chan; i++)
2286 ;
2287
2288 /* use Tx power values from EEPROM */
2289 txpow1 = sc->txpow1[i];
2290 txpow2 = sc->txpow2[i];
2291
2292 rt3090_rf_write(sc, 2, rt3090_freqs[i].n);
2293 rf = rt3090_rf_read(sc, 3);
2294 rf = (rf & ~0x0f) | rt3090_freqs[i].k;
2295 rt3090_rf_write(sc, 3, rf);
2296 rf = rt3090_rf_read(sc, 6);
2297 rf = (rf & ~0x03) | rt3090_freqs[i].r;
2298 rt3090_rf_write(sc, 6, rf);
2299
2300 /* set Tx0 power */
2301 rf = rt3090_rf_read(sc, 12);
2302 rf = (rf & ~0x1f) | txpow1;
2303 rt3090_rf_write(sc, 12, rf);
2304
2305 /* set Tx1 power */
2306 rf = rt3090_rf_read(sc, 13);
2307 rf = (rf & ~0x1f) | txpow2;
2308 rt3090_rf_write(sc, 13, rf);
2309
2310 rf = rt3090_rf_read(sc, 1);
2311 rf &= ~0xfc;
2312 if (sc->ntxchains == 1)
2313 rf |= RT3070_TX1_PD | RT3070_TX2_PD;
2314 else if (sc->ntxchains == 2)
2315 rf |= RT3070_TX2_PD;
2316 if (sc->nrxchains == 1)
2317 rf |= RT3070_RX1_PD | RT3070_RX2_PD;
2318 else if (sc->nrxchains == 2)
2319 rf |= RT3070_RX2_PD;
2320 rt3090_rf_write(sc, 1, rf);
2321
2322 /* set RF offset */
2323 rf = rt3090_rf_read(sc, 23);
2324 rf = (rf & ~0x7f) | sc->freq;
2325 rt3090_rf_write(sc, 23, rf);
2326
2327 /* program RF filter */
2328 rf = rt3090_rf_read(sc, 24); /* Tx */
2329 rf = (rf & ~0x3f) | sc->rf24_20mhz;
2330 rt3090_rf_write(sc, 24, rf);
2331 rf = rt3090_rf_read(sc, 31); /* Rx */
2332 rf = (rf & ~0x3f) | sc->rf24_20mhz;
2333 rt3090_rf_write(sc, 31, rf);
2334
2335 /* enable RF tuning */
2336 rf = rt3090_rf_read(sc, 7);
2337 rt3090_rf_write(sc, 7, rf | RT3070_TUNE);
2338 }
2339
2340 void
rt5390_set_chan(struct rt2860_softc * sc,u_int chan)2341 rt5390_set_chan(struct rt2860_softc *sc, u_int chan)
2342 {
2343 uint8_t h20mhz, rf, tmp;
2344 int8_t txpow1, txpow2;
2345 int i;
2346
2347 /* RT5390 is 2GHz only */
2348 KASSERT(chan >= 1 && chan <= 14);
2349
2350 /* find the settings for this channel (we know it exists) */
2351 for (i = 0; rt2860_rf2850[i].chan != chan; i++)
2352 ;
2353
2354 /* use Tx power values from EEPROM */
2355 txpow1 = sc->txpow1[i];
2356 txpow2 = sc->txpow2[i];
2357
2358 rt3090_rf_write(sc, 8, rt3090_freqs[i].n);
2359 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f);
2360 rf = rt3090_rf_read(sc, 11);
2361 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03);
2362 rt3090_rf_write(sc, 11, rf);
2363
2364 rf = rt3090_rf_read(sc, 49);
2365 rf = (rf & ~0x3f) | (txpow1 & 0x3f);
2366 /* the valid range of the RF R49 is 0x00~0x27 */
2367 if ((rf & 0x3f) > 0x27)
2368 rf = (rf & ~0x3f) | 0x27;
2369 rt3090_rf_write(sc, 49, rf);
2370 if (sc->mac_ver == 0x5392) {
2371 rf = rt3090_rf_read(sc, 50);
2372 rf = (rf & ~0x3f) | (txpow2 & 0x3f);
2373 /* the valid range of the RF R50 is 0x00~0x27 */
2374 if ((rf & 0x3f) > 0x27)
2375 rf = (rf & ~0x3f) | 0x27;
2376 rt3090_rf_write(sc, 50, rf);
2377 }
2378
2379 rf = rt3090_rf_read(sc, 1);
2380 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD;
2381 if (sc->mac_ver == 0x5392)
2382 rf |= RT3070_RX1_PD | RT3070_TX1_PD;
2383 rt3090_rf_write(sc, 1, rf);
2384
2385 rf = rt3090_rf_read(sc, 2);
2386 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL);
2387 DELAY(1000);
2388 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL);
2389
2390 rf = rt3090_rf_read(sc, 17);
2391 tmp = rf;
2392 rf = (rf & ~0x7f) | (sc->freq & 0x7f);
2393 rf = MIN(rf, 0x5f);
2394 if (tmp != rf)
2395 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0);
2396
2397 if (sc->mac_ver == 0x5390) {
2398 if (chan <= 4)
2399 rf = 0x73;
2400 else if (chan >= 5 && chan <= 6)
2401 rf = 0x63;
2402 else if (chan >= 7 && chan <= 10)
2403 rf = 0x53;
2404 else
2405 rf = 43;
2406 rt3090_rf_write(sc, 55, rf);
2407
2408 if (chan == 1)
2409 rf = 0x0c;
2410 else if (chan == 2)
2411 rf = 0x0b;
2412 else if (chan == 3)
2413 rf = 0x0a;
2414 else if (chan >= 4 && chan <= 6)
2415 rf = 0x09;
2416 else if (chan >= 7 && chan <= 12)
2417 rf = 0x08;
2418 else if (chan == 13)
2419 rf = 0x07;
2420 else
2421 rf = 0x06;
2422 rt3090_rf_write(sc, 59, rf);
2423 } else if (sc->mac_ver == 0x3290) {
2424 if (chan == 6)
2425 rt2860_mcu_bbp_write(sc, 68, 0x0c);
2426 else
2427 rt2860_mcu_bbp_write(sc, 68, 0x0b);
2428
2429 if (chan >= 1 && chan < 6)
2430 rf = 0x0f;
2431 else if (chan >= 7 && chan <= 11)
2432 rf = 0x0e;
2433 else if (chan >= 12 && chan <= 14)
2434 rf = 0x0d;
2435 rt3090_rf_write(sc, 59, rf);
2436 }
2437
2438 /* Tx/Rx h20M */
2439 h20mhz = (sc->rf24_20mhz & 0x20) >> 5;
2440 rf = rt3090_rf_read(sc, 30);
2441 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2);
2442 rt3090_rf_write(sc, 30, rf);
2443
2444 /* Rx BB filter VCM */
2445 rf = rt3090_rf_read(sc, 30);
2446 rf = (rf & ~0x18) | 0x10;
2447 rt3090_rf_write(sc, 30, rf);
2448
2449 /* Initiate VCO calibration. */
2450 rf = rt3090_rf_read(sc, 3);
2451 rf |= RT3593_VCOCAL;
2452 rt3090_rf_write(sc, 3, rf);
2453 }
2454
2455 int
rt3090_rf_init(struct rt2860_softc * sc)2456 rt3090_rf_init(struct rt2860_softc *sc)
2457 {
2458 uint32_t tmp;
2459 uint8_t rf, bbp;
2460 int i;
2461
2462 rf = rt3090_rf_read(sc, 30);
2463 /* toggle RF R30 bit 7 */
2464 rt3090_rf_write(sc, 30, rf | 0x80);
2465 DELAY(1000);
2466 rt3090_rf_write(sc, 30, rf & ~0x80);
2467
2468 tmp = RAL_READ(sc, RT3070_LDO_CFG0);
2469 tmp &= ~0x1f000000;
2470 if (sc->patch_dac && sc->mac_rev < 0x0211)
2471 tmp |= 0x0d000000; /* 1.35V */
2472 else
2473 tmp |= 0x01000000; /* 1.2V */
2474 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp);
2475
2476 /* patch LNA_PE_G1 */
2477 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH);
2478 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20);
2479
2480 /* initialize RF registers to default value */
2481 if (sc->mac_ver == 0x3572) {
2482 for (i = 0; i < nitems(rt3572_def_rf); i++) {
2483 rt3090_rf_write(sc, rt3572_def_rf[i].reg,
2484 rt3572_def_rf[i].val);
2485 }
2486 } else {
2487 for (i = 0; i < nitems(rt3090_def_rf); i++) {
2488 rt3090_rf_write(sc, rt3090_def_rf[i].reg,
2489 rt3090_def_rf[i].val);
2490 }
2491 }
2492
2493 /* select 20MHz bandwidth */
2494 rt3090_rf_write(sc, 31, 0x14);
2495
2496 rf = rt3090_rf_read(sc, 6);
2497 rt3090_rf_write(sc, 6, rf | 0x40);
2498
2499 if (sc->mac_ver != 0x3593) {
2500 /* calibrate filter for 20MHz bandwidth */
2501 sc->rf24_20mhz = 0x1f; /* default value */
2502 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz);
2503
2504 /* select 40MHz bandwidth */
2505 bbp = rt2860_mcu_bbp_read(sc, 4);
2506 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10);
2507 rf = rt3090_rf_read(sc, 31);
2508 rt3090_rf_write(sc, 31, rf | 0x20);
2509
2510 /* calibrate filter for 40MHz bandwidth */
2511 sc->rf24_40mhz = 0x2f; /* default value */
2512 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz);
2513
2514 /* go back to 20MHz bandwidth */
2515 bbp = rt2860_mcu_bbp_read(sc, 4);
2516 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18);
2517 }
2518 if (sc->mac_rev < 0x0211)
2519 rt3090_rf_write(sc, 27, 0x03);
2520
2521 tmp = RAL_READ(sc, RT3070_OPT_14);
2522 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1);
2523
2524 if (sc->rf_rev == RT3070_RF_3020)
2525 rt3090_set_rx_antenna(sc, 0);
2526
2527 bbp = rt2860_mcu_bbp_read(sc, 138);
2528 if (sc->mac_ver == 0x3593) {
2529 if (sc->ntxchains == 1)
2530 bbp |= 0x60; /* turn off DAC1 and DAC2 */
2531 else if (sc->ntxchains == 2)
2532 bbp |= 0x40; /* turn off DAC2 */
2533 if (sc->nrxchains == 1)
2534 bbp &= ~0x06; /* turn off ADC1 and ADC2 */
2535 else if (sc->nrxchains == 2)
2536 bbp &= ~0x04; /* turn off ADC2 */
2537 } else {
2538 if (sc->ntxchains == 1)
2539 bbp |= 0x20; /* turn off DAC1 */
2540 if (sc->nrxchains == 1)
2541 bbp &= ~0x02; /* turn off ADC1 */
2542 }
2543 rt2860_mcu_bbp_write(sc, 138, bbp);
2544
2545 rf = rt3090_rf_read(sc, 1);
2546 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD);
2547 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD;
2548 rt3090_rf_write(sc, 1, rf);
2549
2550 rf = rt3090_rf_read(sc, 15);
2551 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2);
2552
2553 rf = rt3090_rf_read(sc, 17);
2554 rf &= ~RT3070_TX_LO1;
2555 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna)
2556 rf |= 0x20; /* fix for long range Rx issue */
2557 if (sc->txmixgain_2ghz >= 2)
2558 rf = (rf & ~0x7) | sc->txmixgain_2ghz;
2559 rt3090_rf_write(sc, 17, rf);
2560
2561 rf = rt3090_rf_read(sc, 20);
2562 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1);
2563
2564 rf = rt3090_rf_read(sc, 21);
2565 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2);
2566
2567 return 0;
2568 }
2569
2570 void
rt5390_rf_init(struct rt2860_softc * sc)2571 rt5390_rf_init(struct rt2860_softc *sc)
2572 {
2573 uint8_t rf, bbp;
2574 int i;
2575
2576 rf = rt3090_rf_read(sc, 2);
2577 /* Toggle RF R2 bit 7. */
2578 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL);
2579 DELAY(1000);
2580 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL);
2581
2582 /* Initialize RF registers to default value. */
2583 if (sc->mac_ver == 0x5392) {
2584 for (i = 0; i < nitems(rt5392_def_rf); i++) {
2585 rt3090_rf_write(sc, rt5392_def_rf[i].reg,
2586 rt5392_def_rf[i].val);
2587 }
2588 } else if (sc->mac_ver == 0x3290) {
2589 for (i = 0; i < nitems(rt3290_def_rf); i++) {
2590 rt3090_rf_write(sc, rt3290_def_rf[i].reg,
2591 rt3290_def_rf[i].val);
2592 }
2593 } else {
2594 for (i = 0; i < nitems(rt5390_def_rf); i++) {
2595 rt3090_rf_write(sc, rt5390_def_rf[i].reg,
2596 rt5390_def_rf[i].val);
2597 }
2598 }
2599
2600 sc->rf24_20mhz = 0x1f;
2601 sc->rf24_40mhz = 0x2f;
2602
2603 if (sc->mac_rev < 0x0211)
2604 rt3090_rf_write(sc, 27, 0x03);
2605
2606 /* Set led open drain enable. */
2607 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1);
2608
2609 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0);
2610 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0);
2611
2612 if (sc->mac_ver == 0x3290 ||
2613 sc->mac_ver == 0x5390)
2614 rt3090_set_rx_antenna(sc, 0);
2615
2616 /* Patch RSSI inaccurate issue. */
2617 rt2860_mcu_bbp_write(sc, 79, 0x13);
2618 rt2860_mcu_bbp_write(sc, 80, 0x05);
2619 rt2860_mcu_bbp_write(sc, 81, 0x33);
2620
2621 /* Enable DC filter. */
2622 if (sc->mac_rev >= 0x0211 ||
2623 sc->mac_ver == 0x3290)
2624 rt2860_mcu_bbp_write(sc, 103, 0xc0);
2625
2626 bbp = rt2860_mcu_bbp_read(sc, 138);
2627 if (sc->ntxchains == 1)
2628 bbp |= 0x20; /* Turn off DAC1. */
2629 if (sc->nrxchains == 1)
2630 bbp &= ~0x02; /* Turn off ADC1. */
2631 rt2860_mcu_bbp_write(sc, 138, bbp);
2632
2633 /* Enable RX LO1 and LO2. */
2634 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1);
2635 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2);
2636
2637 /* Avoid data lost and CRC error. */
2638 rt2860_mcu_bbp_write(sc, 4,
2639 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL);
2640
2641 rf = rt3090_rf_read(sc, 30);
2642 rf = (rf & ~0x18) | 0x10;
2643 rt3090_rf_write(sc, 30, rf);
2644
2645 /* Disable hardware antenna diversity. */
2646 if (sc->mac_ver == 0x5390)
2647 rt2860_mcu_bbp_write(sc, 154, 0);
2648 }
2649
2650 void
rt3090_rf_wakeup(struct rt2860_softc * sc)2651 rt3090_rf_wakeup(struct rt2860_softc *sc)
2652 {
2653 uint32_t tmp;
2654 uint8_t rf;
2655
2656 if (sc->mac_ver == 0x3593) {
2657 /* enable VCO */
2658 rf = rt3090_rf_read(sc, 1);
2659 rt3090_rf_write(sc, 1, rf | RT3593_VCO);
2660
2661 /* initiate VCO calibration */
2662 rf = rt3090_rf_read(sc, 3);
2663 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL);
2664
2665 /* enable VCO bias current control */
2666 rf = rt3090_rf_read(sc, 6);
2667 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC);
2668
2669 /* initiate res calibration */
2670 rf = rt3090_rf_read(sc, 2);
2671 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL);
2672
2673 /* set reference current control to 0.33 mA */
2674 rf = rt3090_rf_read(sc, 22);
2675 rf &= ~RT3593_CP_IC_MASK;
2676 rf |= 1 << RT3593_CP_IC_SHIFT;
2677 rt3090_rf_write(sc, 22, rf);
2678
2679 /* enable RX CTB */
2680 rf = rt3090_rf_read(sc, 46);
2681 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB);
2682
2683 rf = rt3090_rf_read(sc, 20);
2684 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK);
2685 rt3090_rf_write(sc, 20, rf);
2686 } else {
2687 /* enable RF block */
2688 rf = rt3090_rf_read(sc, 1);
2689 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK);
2690
2691 /* enable VCO bias current control */
2692 rf = rt3090_rf_read(sc, 7);
2693 rt3090_rf_write(sc, 7, rf | 0x30);
2694
2695 rf = rt3090_rf_read(sc, 9);
2696 rt3090_rf_write(sc, 9, rf | 0x0e);
2697
2698 /* enable RX CTB */
2699 rf = rt3090_rf_read(sc, 21);
2700 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB);
2701
2702 /* fix Tx to Rx IQ glitch by raising RF voltage */
2703 rf = rt3090_rf_read(sc, 27);
2704 rf &= ~0x77;
2705 if (sc->mac_rev < 0x0211)
2706 rf |= 0x03;
2707 rt3090_rf_write(sc, 27, rf);
2708 }
2709 if (sc->patch_dac && sc->mac_rev < 0x0211) {
2710 tmp = RAL_READ(sc, RT3070_LDO_CFG0);
2711 tmp = (tmp & ~0x1f000000) | 0x0d000000;
2712 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp);
2713 }
2714 }
2715
2716 void
rt5390_rf_wakeup(struct rt2860_softc * sc)2717 rt5390_rf_wakeup(struct rt2860_softc *sc)
2718 {
2719 uint32_t tmp;
2720 uint8_t rf;
2721
2722 rf = rt3090_rf_read(sc, 1);
2723 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD |
2724 RT3070_TX0_PD;
2725 if (sc->mac_ver == 0x5392)
2726 rf |= RT3070_RX1_PD | RT3070_TX1_PD;
2727 rt3090_rf_write(sc, 1, rf);
2728
2729 rf = rt3090_rf_read(sc, 6);
2730 rf |= RT3593_VCO_IC | RT3593_VCOCAL;
2731 if (sc->mac_ver == 0x5390)
2732 rf &= ~RT3593_VCO_IC;
2733 rt3090_rf_write(sc, 6, rf);
2734
2735 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL);
2736
2737 rf = rt3090_rf_read(sc, 22);
2738 rf = (rf & ~0xe0) | 0x20;
2739 rt3090_rf_write(sc, 22, rf);
2740
2741 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB);
2742 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77);
2743 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL);
2744
2745 if (sc->patch_dac && sc->mac_rev < 0x0211) {
2746 tmp = RAL_READ(sc, RT3070_LDO_CFG0);
2747 tmp = (tmp & ~0x1f000000) | 0x0d000000;
2748 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp);
2749 }
2750 }
2751
2752 int
rt3090_filter_calib(struct rt2860_softc * sc,uint8_t init,uint8_t target,uint8_t * val)2753 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target,
2754 uint8_t *val)
2755 {
2756 uint8_t rf22, rf24;
2757 uint8_t bbp55_pb, bbp55_sb, delta;
2758 int ntries;
2759
2760 /* program filter */
2761 rf24 = rt3090_rf_read(sc, 24);
2762 rf24 = (rf24 & 0xc0) | init; /* initial filter value */
2763 rt3090_rf_write(sc, 24, rf24);
2764
2765 /* enable baseband loopback mode */
2766 rf22 = rt3090_rf_read(sc, 22);
2767 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK);
2768
2769 /* set power and frequency of passband test tone */
2770 rt2860_mcu_bbp_write(sc, 24, 0x00);
2771 for (ntries = 0; ntries < 100; ntries++) {
2772 /* transmit test tone */
2773 rt2860_mcu_bbp_write(sc, 25, 0x90);
2774 DELAY(1000);
2775 /* read received power */
2776 bbp55_pb = rt2860_mcu_bbp_read(sc, 55);
2777 if (bbp55_pb != 0)
2778 break;
2779 }
2780 if (ntries == 100)
2781 return ETIMEDOUT;
2782
2783 /* set power and frequency of stopband test tone */
2784 rt2860_mcu_bbp_write(sc, 24, 0x06);
2785 for (ntries = 0; ntries < 100; ntries++) {
2786 /* transmit test tone */
2787 rt2860_mcu_bbp_write(sc, 25, 0x90);
2788 DELAY(1000);
2789 /* read received power */
2790 bbp55_sb = rt2860_mcu_bbp_read(sc, 55);
2791
2792 delta = bbp55_pb - bbp55_sb;
2793 if (delta > target)
2794 break;
2795
2796 /* reprogram filter */
2797 rf24++;
2798 rt3090_rf_write(sc, 24, rf24);
2799 }
2800 if (ntries < 100) {
2801 if (rf24 != init)
2802 rf24--; /* backtrack */
2803 *val = rf24;
2804 rt3090_rf_write(sc, 24, rf24);
2805 }
2806
2807 /* restore initial state */
2808 rt2860_mcu_bbp_write(sc, 24, 0x00);
2809
2810 /* disable baseband loopback mode */
2811 rf22 = rt3090_rf_read(sc, 22);
2812 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK);
2813
2814 return 0;
2815 }
2816
2817 void
rt3090_rf_setup(struct rt2860_softc * sc)2818 rt3090_rf_setup(struct rt2860_softc *sc)
2819 {
2820 uint8_t bbp;
2821 int i;
2822
2823 if (sc->mac_rev >= 0x0211) {
2824 /* enable DC filter */
2825 rt2860_mcu_bbp_write(sc, 103, 0xc0);
2826
2827 /* improve power consumption */
2828 bbp = rt2860_mcu_bbp_read(sc, 31);
2829 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03);
2830 }
2831
2832 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0);
2833 if (sc->mac_rev < 0x0211) {
2834 RAL_WRITE(sc, RT2860_TX_SW_CFG2,
2835 sc->patch_dac ? 0x2c : 0x0f);
2836 } else
2837 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0);
2838
2839 /* initialize RF registers from ROM */
2840 if (sc->mac_ver < 0x5390) {
2841 for (i = 0; i < 10; i++) {
2842 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff)
2843 continue;
2844 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val);
2845 }
2846 }
2847 }
2848
2849 void
rt2860_set_leds(struct rt2860_softc * sc,uint16_t which)2850 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which)
2851 {
2852 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS,
2853 which | (sc->leds & 0x7f), 0);
2854 }
2855
2856 /*
2857 * Hardware has a general-purpose programmable timer interrupt that can
2858 * periodically raise MAC_INT_4.
2859 */
2860 void
rt2860_set_gp_timer(struct rt2860_softc * sc,int ms)2861 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms)
2862 {
2863 uint32_t tmp;
2864
2865 /* disable GP timer before reprogramming it */
2866 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN);
2867 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN);
2868
2869 if (ms == 0)
2870 return;
2871
2872 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG);
2873 ms *= 16; /* Unit: 64us */
2874 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT;
2875 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp);
2876
2877 /* enable GP timer */
2878 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN);
2879 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN);
2880 }
2881
2882 void
rt2860_set_bssid(struct rt2860_softc * sc,const uint8_t * bssid)2883 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid)
2884 {
2885 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0,
2886 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24);
2887 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1,
2888 bssid[4] | bssid[5] << 8);
2889 }
2890
2891 void
rt2860_set_macaddr(struct rt2860_softc * sc,const uint8_t * addr)2892 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr)
2893 {
2894 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0,
2895 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
2896 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1,
2897 addr[4] | addr[5] << 8 | 0xff << 16);
2898 }
2899
2900 void
rt2860_updateslot(struct ieee80211com * ic)2901 rt2860_updateslot(struct ieee80211com *ic)
2902 {
2903 struct rt2860_softc *sc = ic->ic_softc;
2904 uint32_t tmp;
2905
2906 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG);
2907 tmp &= ~0xff;
2908 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ?
2909 IEEE80211_DUR_DS_SHSLOT : IEEE80211_DUR_DS_SLOT;
2910 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp);
2911 }
2912
2913 void
rt2860_updateprot(struct ieee80211com * ic)2914 rt2860_updateprot(struct ieee80211com *ic)
2915 {
2916 struct rt2860_softc *sc = ic->ic_softc;
2917 uint32_t tmp;
2918
2919 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL;
2920 /* setup protection frame rate (MCS code) */
2921 tmp |= (ic->ic_curmode == IEEE80211_MODE_11A) ?
2922 rt2860_rates[RT2860_RIDX_OFDM6].mcs :
2923 rt2860_rates[RT2860_RIDX_CCK11].mcs;
2924
2925 /* CCK frames don't require protection */
2926 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp);
2927
2928 if (ic->ic_flags & IEEE80211_F_USEPROT) {
2929 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
2930 tmp |= RT2860_PROT_CTRL_RTS_CTS;
2931 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
2932 tmp |= RT2860_PROT_CTRL_CTS;
2933 }
2934 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp);
2935 }
2936
2937 void
rt2860_updateedca(struct ieee80211com * ic)2938 rt2860_updateedca(struct ieee80211com *ic)
2939 {
2940 struct rt2860_softc *sc = ic->ic_softc;
2941 int aci;
2942
2943 /* update MAC TX configuration registers */
2944 for (aci = 0; aci < EDCA_NUM_AC; aci++) {
2945 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci),
2946 ic->ic_edca_ac[aci].ac_ecwmax << 16 |
2947 ic->ic_edca_ac[aci].ac_ecwmin << 12 |
2948 ic->ic_edca_ac[aci].ac_aifsn << 8 |
2949 ic->ic_edca_ac[aci].ac_txoplimit);
2950 }
2951
2952 /* update SCH/DMA registers too */
2953 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG,
2954 ic->ic_edca_ac[EDCA_AC_VO].ac_aifsn << 12 |
2955 ic->ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 |
2956 ic->ic_edca_ac[EDCA_AC_BK].ac_aifsn << 4 |
2957 ic->ic_edca_ac[EDCA_AC_BE].ac_aifsn);
2958 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG,
2959 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmin << 12 |
2960 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 |
2961 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmin << 4 |
2962 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmin);
2963 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG,
2964 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmax << 12 |
2965 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 |
2966 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmax << 4 |
2967 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmax);
2968 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG,
2969 ic->ic_edca_ac[EDCA_AC_BK].ac_txoplimit << 16 |
2970 ic->ic_edca_ac[EDCA_AC_BE].ac_txoplimit);
2971 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG,
2972 ic->ic_edca_ac[EDCA_AC_VO].ac_txoplimit << 16 |
2973 ic->ic_edca_ac[EDCA_AC_VI].ac_txoplimit);
2974 }
2975
2976 int
rt2860_set_key(struct ieee80211com * ic,struct ieee80211_node * ni,struct ieee80211_key * k)2977 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni,
2978 struct ieee80211_key *k)
2979 {
2980 struct rt2860_softc *sc = ic->ic_softc;
2981 bus_size_t base;
2982 uint32_t attr;
2983 uint8_t mode, wcid, iv[8];
2984
2985 /* defer setting of WEP keys until interface is brought up */
2986 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) !=
2987 (IFF_UP | IFF_RUNNING))
2988 return 0;
2989
2990 /* map net80211 cipher to RT2860 security mode */
2991 switch (k->k_cipher) {
2992 case IEEE80211_CIPHER_WEP40:
2993 mode = RT2860_MODE_WEP40;
2994 break;
2995 case IEEE80211_CIPHER_WEP104:
2996 mode = RT2860_MODE_WEP104;
2997 break;
2998 case IEEE80211_CIPHER_TKIP:
2999 mode = RT2860_MODE_TKIP;
3000 break;
3001 case IEEE80211_CIPHER_CCMP:
3002 mode = RT2860_MODE_AES_CCMP;
3003 break;
3004 default:
3005 return EINVAL;
3006 }
3007
3008 if (k->k_flags & IEEE80211_KEY_GROUP) {
3009 wcid = 0; /* NB: update WCID0 for group keys */
3010 base = RT2860_SKEY(0, k->k_id);
3011 } else {
3012 wcid = ((struct rt2860_node *)ni)->wcid;
3013 base = RT2860_PKEY(wcid);
3014 }
3015
3016 if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
3017 RAL_WRITE_REGION_1(sc, base, k->k_key, 16);
3018 #ifndef IEEE80211_STA_ONLY
3019 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
3020 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8);
3021 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8);
3022 } else
3023 #endif
3024 {
3025 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8);
3026 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8);
3027 }
3028 } else
3029 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len);
3030
3031 if (!(k->k_flags & IEEE80211_KEY_GROUP) ||
3032 (k->k_flags & IEEE80211_KEY_TX)) {
3033 /* set initial packet number in IV+EIV */
3034 if (k->k_cipher == IEEE80211_CIPHER_WEP40 ||
3035 k->k_cipher == IEEE80211_CIPHER_WEP104) {
3036 uint32_t val = arc4random();
3037 /* skip weak IVs from Fluhrer/Mantin/Shamir */
3038 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00)
3039 val += 0x000100;
3040 iv[0] = val;
3041 iv[1] = val >> 8;
3042 iv[2] = val >> 16;
3043 iv[3] = k->k_id << 6;
3044 iv[4] = iv[5] = iv[6] = iv[7] = 0;
3045 } else {
3046 if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
3047 iv[0] = k->k_tsc >> 8;
3048 iv[1] = (iv[0] | 0x20) & 0x7f;
3049 iv[2] = k->k_tsc;
3050 } else /* CCMP */ {
3051 iv[0] = k->k_tsc;
3052 iv[1] = k->k_tsc >> 8;
3053 iv[2] = 0;
3054 }
3055 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV;
3056 iv[4] = k->k_tsc >> 16;
3057 iv[5] = k->k_tsc >> 24;
3058 iv[6] = k->k_tsc >> 32;
3059 iv[7] = k->k_tsc >> 40;
3060 }
3061 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8);
3062 }
3063
3064 if (k->k_flags & IEEE80211_KEY_GROUP) {
3065 /* install group key */
3066 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7);
3067 attr &= ~(0xf << (k->k_id * 4));
3068 attr |= mode << (k->k_id * 4);
3069 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr);
3070 } else {
3071 /* install pairwise key */
3072 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid));
3073 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN;
3074 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr);
3075 }
3076 return 0;
3077 }
3078
3079 void
rt2860_delete_key(struct ieee80211com * ic,struct ieee80211_node * ni,struct ieee80211_key * k)3080 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni,
3081 struct ieee80211_key *k)
3082 {
3083 struct rt2860_softc *sc = ic->ic_softc;
3084 uint32_t attr;
3085 uint8_t wcid;
3086
3087 if (k->k_flags & IEEE80211_KEY_GROUP) {
3088 /* remove group key */
3089 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7);
3090 attr &= ~(0xf << (k->k_id * 4));
3091 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr);
3092
3093 } else {
3094 /* remove pairwise key */
3095 wcid = ((struct rt2860_node *)ni)->wcid;
3096 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid));
3097 attr &= ~0xf;
3098 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr);
3099 }
3100 }
3101
3102 #if NBPFILTER > 0
3103 int8_t
rt2860_rssi2dbm(struct rt2860_softc * sc,uint8_t rssi,uint8_t rxchain)3104 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain)
3105 {
3106 struct ieee80211com *ic = &sc->sc_ic;
3107 struct ieee80211_channel *c = ic->ic_ibss_chan;
3108 int delta;
3109
3110 if (IEEE80211_IS_CHAN_5GHZ(c)) {
3111 u_int chan = ieee80211_chan2ieee(ic, c);
3112 delta = sc->rssi_5ghz[rxchain];
3113
3114 /* determine channel group */
3115 if (chan <= 64)
3116 delta -= sc->lna[1];
3117 else if (chan <= 128)
3118 delta -= sc->lna[2];
3119 else
3120 delta -= sc->lna[3];
3121 } else
3122 delta = sc->rssi_2ghz[rxchain] - sc->lna[0];
3123
3124 return -12 - delta - rssi;
3125 }
3126 #endif
3127
3128 /*
3129 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word.
3130 * Used to adjust per-rate Tx power registers.
3131 */
3132 static __inline uint32_t
b4inc(uint32_t b32,int8_t delta)3133 b4inc(uint32_t b32, int8_t delta)
3134 {
3135 int8_t i, b4;
3136
3137 for (i = 0; i < 8; i++) {
3138 b4 = b32 & 0xf;
3139 b4 += delta;
3140 if (b4 < 0)
3141 b4 = 0;
3142 else if (b4 > 0xf)
3143 b4 = 0xf;
3144 b32 = b32 >> 4 | b4 << 28;
3145 }
3146 return b32;
3147 }
3148
3149 const char *
rt2860_get_rf(uint16_t rev)3150 rt2860_get_rf(uint16_t rev)
3151 {
3152 switch (rev) {
3153 case RT2860_RF_2820: return "RT2820";
3154 case RT2860_RF_2850: return "RT2850";
3155 case RT2860_RF_2720: return "RT2720";
3156 case RT2860_RF_2750: return "RT2750";
3157 case RT3070_RF_3020: return "RT3020";
3158 case RT3070_RF_2020: return "RT2020";
3159 case RT3070_RF_3021: return "RT3021";
3160 case RT3070_RF_3022: return "RT3022";
3161 case RT3070_RF_3052: return "RT3052";
3162 case RT3070_RF_3320: return "RT3320";
3163 case RT3070_RF_3053: return "RT3053";
3164 case RT3290_RF_3290: return "RT3290";
3165 case RT5390_RF_5360: return "RT5360";
3166 case RT5390_RF_5390: return "RT5390";
3167 case RT5390_RF_5392: return "RT5392";
3168 default: return "unknown";
3169 }
3170 }
3171
3172 int
rt2860_read_eeprom(struct rt2860_softc * sc)3173 rt2860_read_eeprom(struct rt2860_softc *sc)
3174 {
3175 struct ieee80211com *ic = &sc->sc_ic;
3176 int8_t delta_2ghz, delta_5ghz;
3177 uint32_t tmp;
3178 uint16_t val;
3179 int ridx, ant, i;
3180
3181 /* check whether the ROM is eFUSE ROM or EEPROM */
3182 sc->sc_srom_read = rt2860_eeprom_read_2;
3183 if (sc->mac_ver == 0x3290) {
3184 tmp = RAL_READ(sc, RT3290_EFUSE_CTRL);
3185 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp));
3186 if (tmp & RT3070_SEL_EFUSE)
3187 sc->sc_srom_read = rt3290_efuse_read_2;
3188 } else if (sc->mac_ver >= 0x3071) {
3189 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL);
3190 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp));
3191 if (tmp & RT3070_SEL_EFUSE)
3192 sc->sc_srom_read = rt3090_efuse_read_2;
3193 }
3194
3195 /* read EEPROM version */
3196 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION);
3197 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8));
3198
3199 /* read MAC address */
3200 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01);
3201 ic->ic_myaddr[0] = val & 0xff;
3202 ic->ic_myaddr[1] = val >> 8;
3203 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23);
3204 ic->ic_myaddr[2] = val & 0xff;
3205 ic->ic_myaddr[3] = val >> 8;
3206 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45);
3207 ic->ic_myaddr[4] = val & 0xff;
3208 ic->ic_myaddr[5] = val >> 8;
3209
3210 /* read country code */
3211 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY);
3212 DPRINTF(("EEPROM region code=0x%04x\n", val));
3213
3214 /* read vendor BBP settings */
3215 for (i = 0; i < 8; i++) {
3216 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i);
3217 sc->bbp[i].val = val & 0xff;
3218 sc->bbp[i].reg = val >> 8;
3219 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val));
3220 }
3221 if (sc->mac_ver >= 0x3071) {
3222 /* read vendor RF settings */
3223 for (i = 0; i < 10; i++) {
3224 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i);
3225 sc->rf[i].val = val & 0xff;
3226 sc->rf[i].reg = val >> 8;
3227 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg,
3228 sc->rf[i].val));
3229 }
3230 }
3231
3232 /* read RF frequency offset from EEPROM */
3233 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS);
3234 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0;
3235 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff));
3236 if ((val >> 8) != 0xff) {
3237 /* read LEDs operating mode */
3238 sc->leds = val >> 8;
3239 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1);
3240 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2);
3241 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3);
3242 } else {
3243 /* broken EEPROM, use default settings */
3244 sc->leds = 0x01;
3245 sc->led[0] = 0x5555;
3246 sc->led[1] = 0x2221;
3247 sc->led[2] = 0xa9f8;
3248 }
3249 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n",
3250 sc->leds, sc->led[0], sc->led[1], sc->led[2]));
3251
3252 /* read RF information */
3253 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA);
3254 DPRINTF(("EEPROM ANT 0x%04x\n", val));
3255 if (sc->mac_ver >= 0x5390 || sc->mac_ver == 0x3290)
3256 sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID);
3257 else
3258 sc->rf_rev = (val >> 8) & 0xf;
3259 sc->ntxchains = (val >> 4) & 0xf;
3260 sc->nrxchains = val & 0xf;
3261 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n",
3262 sc->rf_rev, sc->ntxchains, sc->nrxchains));
3263
3264 /* check if RF supports automatic Tx access gain control */
3265 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG);
3266 DPRINTF(("EEPROM CFG 0x%04x\n", val));
3267 /* check if driver should patch the DAC issue */
3268 if ((val >> 8) != 0xff)
3269 sc->patch_dac = (val >> 15) & 1;
3270 if ((val & 0xff) != 0xff) {
3271 sc->ext_5ghz_lna = (val >> 3) & 1;
3272 sc->ext_2ghz_lna = (val >> 2) & 1;
3273 /* check if RF supports automatic Tx access gain control */
3274 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */
3275 /* check if we have a hardware radio switch */
3276 sc->rfswitch = val & 1;
3277 }
3278 if (sc->sc_flags & RT2860_ADVANCED_PS) {
3279 /* read PCIe power save level */
3280 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL);
3281 if ((val & 0xff) != 0xff) {
3282 sc->pslevel = val & 0x3;
3283 val = rt2860_srom_read(sc, RT2860_EEPROM_REV);
3284 if ((val & 0xff80) != 0x9280)
3285 sc->pslevel = MIN(sc->pslevel, 1);
3286 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel));
3287 }
3288 }
3289
3290 /* read power settings for 2GHz channels */
3291 for (i = 0; i < 14; i += 2) {
3292 val = rt2860_srom_read(sc,
3293 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2);
3294 sc->txpow1[i + 0] = (int8_t)(val & 0xff);
3295 sc->txpow1[i + 1] = (int8_t)(val >> 8);
3296
3297 if (sc->mac_ver != 0x5390) {
3298 val = rt2860_srom_read(sc,
3299 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2);
3300 sc->txpow2[i + 0] = (int8_t)(val & 0xff);
3301 sc->txpow2[i + 1] = (int8_t)(val >> 8);
3302 }
3303 }
3304 /* fix broken Tx power entries */
3305 for (i = 0; i < 14; i++) {
3306 if (sc->txpow1[i] < 0 ||
3307 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31))
3308 sc->txpow1[i] = 5;
3309 if (sc->mac_ver != 0x5390) {
3310 if (sc->txpow2[i] < 0 ||
3311 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31))
3312 sc->txpow2[i] = 5;
3313 }
3314 DPRINTF(("chan %d: power1=%d, power2=%d\n",
3315 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i]));
3316 }
3317 /* read power settings for 5GHz channels */
3318 for (i = 0; i < 40; i += 2) {
3319 val = rt2860_srom_read(sc,
3320 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2);
3321 sc->txpow1[i + 14] = (int8_t)(val & 0xff);
3322 sc->txpow1[i + 15] = (int8_t)(val >> 8);
3323
3324 val = rt2860_srom_read(sc,
3325 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2);
3326 sc->txpow2[i + 14] = (int8_t)(val & 0xff);
3327 sc->txpow2[i + 15] = (int8_t)(val >> 8);
3328 }
3329 /* fix broken Tx power entries */
3330 for (i = 0; i < 40; i++) {
3331 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15)
3332 sc->txpow1[14 + i] = 5;
3333 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15)
3334 sc->txpow2[14 + i] = 5;
3335 DPRINTF(("chan %d: power1=%d, power2=%d\n",
3336 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i],
3337 sc->txpow2[14 + i]));
3338 }
3339
3340 /* read Tx power compensation for each Tx rate */
3341 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR);
3342 delta_2ghz = delta_5ghz = 0;
3343 if ((val & 0xff) != 0xff && (val & 0x80)) {
3344 delta_2ghz = val & 0xf;
3345 if (!(val & 0x40)) /* negative number */
3346 delta_2ghz = -delta_2ghz;
3347 }
3348 val >>= 8;
3349 if ((val & 0xff) != 0xff && (val & 0x80)) {
3350 delta_5ghz = val & 0xf;
3351 if (!(val & 0x40)) /* negative number */
3352 delta_5ghz = -delta_5ghz;
3353 }
3354 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n",
3355 delta_2ghz, delta_5ghz));
3356
3357 for (ridx = 0; ridx < 5; ridx++) {
3358 uint32_t reg;
3359
3360 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2);
3361 reg = val;
3362 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1);
3363 reg |= (uint32_t)val << 16;
3364
3365 sc->txpow20mhz[ridx] = reg;
3366 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);
3367 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);
3368
3369 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, "
3370 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx],
3371 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx]));
3372 }
3373
3374 /* read factory-calibrated samples for temperature compensation */
3375 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ);
3376 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */
3377 sc->tssi_2ghz[1] = val >> 8; /* [-3] */
3378 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ);
3379 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */
3380 sc->tssi_2ghz[3] = val >> 8; /* [-1] */
3381 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ);
3382 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */
3383 sc->tssi_2ghz[5] = val >> 8; /* [+1] */
3384 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ);
3385 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */
3386 sc->tssi_2ghz[7] = val >> 8; /* [+3] */
3387 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ);
3388 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */
3389 sc->step_2ghz = val >> 8;
3390 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x "
3391 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1],
3392 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4],
3393 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7],
3394 sc->tssi_2ghz[8], sc->step_2ghz));
3395 /* check that ref value is correct, otherwise disable calibration */
3396 if (sc->tssi_2ghz[4] == 0xff)
3397 sc->calib_2ghz = 0;
3398
3399 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ);
3400 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */
3401 sc->tssi_5ghz[1] = val >> 8; /* [-3] */
3402 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ);
3403 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */
3404 sc->tssi_5ghz[3] = val >> 8; /* [-1] */
3405 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ);
3406 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */
3407 sc->tssi_5ghz[5] = val >> 8; /* [+1] */
3408 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ);
3409 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */
3410 sc->tssi_5ghz[7] = val >> 8; /* [+3] */
3411 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ);
3412 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */
3413 sc->step_5ghz = val >> 8;
3414 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x "
3415 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1],
3416 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4],
3417 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7],
3418 sc->tssi_5ghz[8], sc->step_5ghz));
3419 /* check that ref value is correct, otherwise disable calibration */
3420 if (sc->tssi_5ghz[4] == 0xff)
3421 sc->calib_5ghz = 0;
3422
3423 /* read RSSI offsets and LNA gains from EEPROM */
3424 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ);
3425 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */
3426 sc->rssi_2ghz[1] = val >> 8; /* Ant B */
3427 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ);
3428 if (sc->mac_ver >= 0x3071) {
3429 /*
3430 * On RT3090 chips (limited to 2 Rx chains), this ROM
3431 * field contains the Tx mixer gain for the 2GHz band.
3432 */
3433 if ((val & 0xff) != 0xff)
3434 sc->txmixgain_2ghz = val & 0x7;
3435 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz));
3436 } else
3437 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */
3438 sc->lna[2] = val >> 8; /* channel group 2 */
3439
3440 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ);
3441 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */
3442 sc->rssi_5ghz[1] = val >> 8; /* Ant B */
3443 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ);
3444 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */
3445 sc->lna[3] = val >> 8; /* channel group 3 */
3446
3447 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA);
3448 if (sc->mac_ver >= 0x3071)
3449 sc->lna[0] = RT3090_DEF_LNA;
3450 else /* channel group 0 */
3451 sc->lna[0] = val & 0xff;
3452 sc->lna[1] = val >> 8; /* channel group 1 */
3453
3454 /* fix broken 5GHz LNA entries */
3455 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) {
3456 DPRINTF(("invalid LNA for channel group %d\n", 2));
3457 sc->lna[2] = sc->lna[1];
3458 }
3459 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) {
3460 DPRINTF(("invalid LNA for channel group %d\n", 3));
3461 sc->lna[3] = sc->lna[1];
3462 }
3463
3464 /* fix broken RSSI offset entries */
3465 for (ant = 0; ant < 3; ant++) {
3466 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) {
3467 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n",
3468 ant + 1, sc->rssi_2ghz[ant]));
3469 sc->rssi_2ghz[ant] = 0;
3470 }
3471 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) {
3472 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n",
3473 ant + 1, sc->rssi_5ghz[ant]));
3474 sc->rssi_5ghz[ant] = 0;
3475 }
3476 }
3477
3478 return 0;
3479 }
3480
3481 int
rt2860_bbp_init(struct rt2860_softc * sc)3482 rt2860_bbp_init(struct rt2860_softc *sc)
3483 {
3484 int i, ntries;
3485
3486 /* wait for BBP to wake up */
3487 for (ntries = 0; ntries < 20; ntries++) {
3488 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0);
3489 if (bbp0 != 0 && bbp0 != 0xff)
3490 break;
3491 }
3492 if (ntries == 20) {
3493 printf("%s: timeout waiting for BBP to wake up\n",
3494 sc->sc_dev.dv_xname);
3495 return ETIMEDOUT;
3496 }
3497
3498 /* initialize BBP registers to default values */
3499 if (sc->mac_ver >= 0x5390 ||
3500 sc->mac_ver == 0x3290)
3501 rt5390_bbp_init(sc);
3502 else {
3503 for (i = 0; i < nitems(rt2860_def_bbp); i++) {
3504 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg,
3505 rt2860_def_bbp[i].val);
3506 }
3507 }
3508
3509 /* fix BBP84 for RT2860E */
3510 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101)
3511 rt2860_mcu_bbp_write(sc, 84, 0x19);
3512
3513 if (sc->mac_ver >= 0x3071) {
3514 rt2860_mcu_bbp_write(sc, 79, 0x13);
3515 rt2860_mcu_bbp_write(sc, 80, 0x05);
3516 rt2860_mcu_bbp_write(sc, 81, 0x33);
3517 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) {
3518 rt2860_mcu_bbp_write(sc, 69, 0x16);
3519 rt2860_mcu_bbp_write(sc, 73, 0x12);
3520 }
3521
3522 return 0;
3523 }
3524
3525 void
rt5390_bbp_init(struct rt2860_softc * sc)3526 rt5390_bbp_init(struct rt2860_softc *sc)
3527 {
3528 uint8_t bbp;
3529 int i;
3530
3531 /* Apply maximum likelihood detection for 2 stream case. */
3532 if (sc->nrxchains > 1) {
3533 bbp = rt2860_mcu_bbp_read(sc, 105);
3534 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD);
3535 }
3536
3537 /* Avoid data lost and CRC error. */
3538 bbp = rt2860_mcu_bbp_read(sc, 4);
3539 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL);
3540 if (sc->mac_ver == 0x3290) {
3541 for (i = 0; i < nitems(rt3290_def_bbp); i++) {
3542 rt2860_mcu_bbp_write(sc, rt3290_def_bbp[i].reg,
3543 rt3290_def_bbp[i].val);
3544 }
3545 } else {
3546 for (i = 0; i < nitems(rt5390_def_bbp); i++) {
3547 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg,
3548 rt5390_def_bbp[i].val);
3549 }
3550 }
3551
3552 if (sc->mac_ver == 0x5392) {
3553 rt2860_mcu_bbp_write(sc, 84, 0x9a);
3554 rt2860_mcu_bbp_write(sc, 95, 0x9a);
3555 rt2860_mcu_bbp_write(sc, 98, 0x12);
3556 rt2860_mcu_bbp_write(sc, 106, 0x05);
3557 rt2860_mcu_bbp_write(sc, 134, 0xd0);
3558 rt2860_mcu_bbp_write(sc, 135, 0xf6);
3559 }
3560
3561 bbp = rt2860_mcu_bbp_read(sc, 152);
3562 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80);
3563
3564 /* Disable hardware antenna diversity. */
3565 if (sc->mac_ver == 0x5390)
3566 rt2860_mcu_bbp_write(sc, 154, 0);
3567 }
3568
3569 int
rt3290_wlan_enable(struct rt2860_softc * sc)3570 rt3290_wlan_enable(struct rt2860_softc *sc)
3571 {
3572 uint32_t tmp;
3573 int ntries;
3574
3575 /* enable chip and check readiness */
3576 tmp = RAL_READ(sc, RT3290_WLAN_CTRL);
3577 tmp |= RT3290_WLAN_EN | RT3290_FRC_WL_ANT_SET |
3578 RT3290_GPIO_OUT_OE_ALL;
3579 RAL_WRITE(sc, RT3290_WLAN_CTRL, tmp);
3580
3581 for (ntries = 0; ntries < 200; ntries++) {
3582 tmp = RAL_READ(sc, RT3290_CMB_CTRL);
3583 if ((tmp & RT3290_PLL_LD) &&
3584 (tmp & RT3290_XTAL_RDY))
3585 break;
3586 DELAY(20);
3587 }
3588 if (ntries == 200)
3589 return EIO;
3590
3591 /* toggle reset */
3592 tmp = RAL_READ(sc, RT3290_WLAN_CTRL);
3593 tmp |= RT3290_WLAN_RESET | RT3290_WLAN_CLK_EN;
3594 tmp &= ~RT3290_PCIE_APP0_CLK_REQ;
3595 RAL_WRITE(sc, RT3290_WLAN_CTRL, tmp);
3596 DELAY(20);
3597 tmp &= ~RT3290_WLAN_RESET;
3598 RAL_WRITE(sc, RT3290_WLAN_CTRL, tmp);
3599 DELAY(1000);
3600
3601 /* clear garbage interrupts */
3602 RAL_WRITE(sc, RT2860_INT_STATUS, 0x7fffffff);
3603
3604 return 0;
3605 }
3606
3607 int
rt2860_txrx_enable(struct rt2860_softc * sc)3608 rt2860_txrx_enable(struct rt2860_softc *sc)
3609 {
3610 uint32_t tmp;
3611 int ntries;
3612
3613 /* enable Tx/Rx DMA engine */
3614 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN);
3615 RAL_BARRIER_READ_WRITE(sc);
3616 for (ntries = 0; ntries < 200; ntries++) {
3617 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
3618 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
3619 break;
3620 DELAY(1000);
3621 }
3622 if (ntries == 200) {
3623 printf("%s: timeout waiting for DMA engine\n",
3624 sc->sc_dev.dv_xname);
3625 return ETIMEDOUT;
3626 }
3627
3628 DELAY(50);
3629
3630 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN |
3631 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT;
3632 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
3633
3634 /* set Rx filter */
3635 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR;
3636 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) {
3637 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL |
3638 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK |
3639 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV |
3640 RT2860_DROP_CFACK | RT2860_DROP_CFEND;
3641 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA)
3642 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL;
3643 }
3644 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp);
3645
3646 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL,
3647 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
3648
3649 return 0;
3650 }
3651
3652 int
rt2860_init(struct ifnet * ifp)3653 rt2860_init(struct ifnet *ifp)
3654 {
3655 struct rt2860_softc *sc = ifp->if_softc;
3656 struct ieee80211com *ic = &sc->sc_ic;
3657 uint32_t tmp;
3658 uint8_t bbp1, bbp3;
3659 int i, qid, ridx, ntries, error;
3660
3661 /* for CardBus, power on the socket */
3662 if (!(sc->sc_flags & RT2860_ENABLED)) {
3663 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) {
3664 printf("%s: could not enable device\n",
3665 sc->sc_dev.dv_xname);
3666 return EIO;
3667 }
3668 sc->sc_flags |= RT2860_ENABLED;
3669 }
3670
3671 if (sc->mac_ver == 0x3290) {
3672 if ((error = rt3290_wlan_enable(sc)) != 0) {
3673 printf("%s: could not enable wlan\n",
3674 sc->sc_dev.dv_xname);
3675 rt2860_stop(ifp, 1);
3676 return error;
3677 }
3678 }
3679
3680 if (sc->mac_ver == 0x3290 && sc->rfswitch){
3681 /* hardware has a radio switch on GPIO pin 0 */
3682 if (!(RAL_READ(sc, RT3290_WLAN_CTRL) & RT3290_RADIO_EN)) {
3683 printf("%s: radio is disabled by hardware switch\n",
3684 sc->sc_dev.dv_xname);
3685 }
3686 } else if (sc->rfswitch) {
3687 /* hardware has a radio switch on GPIO pin 2 */
3688 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) {
3689 printf("%s: radio is disabled by hardware switch\n",
3690 sc->sc_dev.dv_xname);
3691 #ifdef notyet
3692 rt2860_stop(ifp, 1);
3693 return EPERM;
3694 #endif
3695 }
3696 }
3697 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE);
3698
3699 /* disable DMA */
3700 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
3701 tmp &= 0xff0;
3702 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
3703
3704 /* PBF hardware reset */
3705 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f);
3706 RAL_BARRIER_WRITE(sc);
3707 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00);
3708
3709 if ((error = rt2860_load_microcode(sc)) != 0) {
3710 printf("%s: could not load 8051 microcode\n",
3711 sc->sc_dev.dv_xname);
3712 rt2860_stop(ifp, 1);
3713 return error;
3714 }
3715
3716 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl));
3717 rt2860_set_macaddr(sc, ic->ic_myaddr);
3718
3719 /* init Tx power for all Tx rates (from EEPROM) */
3720 for (ridx = 0; ridx < 5; ridx++) {
3721 if (sc->txpow20mhz[ridx] == 0xffffffff)
3722 continue;
3723 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]);
3724 }
3725
3726 for (ntries = 0; ntries < 100; ntries++) {
3727 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
3728 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
3729 break;
3730 DELAY(1000);
3731 }
3732 if (ntries == 100) {
3733 printf("%s: timeout waiting for DMA engine\n",
3734 sc->sc_dev.dv_xname);
3735 rt2860_stop(ifp, 1);
3736 return ETIMEDOUT;
3737 }
3738 tmp &= 0xff0;
3739 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
3740
3741 /* reset Rx ring and all 6 Tx rings */
3742 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f);
3743
3744 /* PBF hardware reset */
3745 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f);
3746 RAL_BARRIER_WRITE(sc);
3747 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00);
3748
3749 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE);
3750
3751 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST);
3752 RAL_BARRIER_WRITE(sc);
3753 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0);
3754
3755 for (i = 0; i < nitems(rt2860_def_mac); i++)
3756 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val);
3757 if (sc->mac_ver == 0x3290 ||
3758 sc->mac_ver >= 0x5390)
3759 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404);
3760 else if (sc->mac_ver >= 0x3071) {
3761 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */
3762 RAL_WRITE(sc, RT2860_TX_SW_CFG0,
3763 4 << RT2860_DLY_PAPE_EN_SHIFT);
3764 }
3765
3766 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) {
3767 sc->sc_flags |= RT2860_PCIE;
3768 /* PCIe has different clock cycle count than PCI */
3769 tmp = RAL_READ(sc, RT2860_US_CYC_CNT);
3770 tmp = (tmp & ~0xff) | 0x7d;
3771 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp);
3772 }
3773
3774 /* wait while MAC is busy */
3775 for (ntries = 0; ntries < 100; ntries++) {
3776 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) &
3777 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY)))
3778 break;
3779 DELAY(1000);
3780 }
3781 if (ntries == 100) {
3782 printf("%s: timeout waiting for MAC\n", sc->sc_dev.dv_xname);
3783 rt2860_stop(ifp, 1);
3784 return ETIMEDOUT;
3785 }
3786
3787 /* clear Host to MCU mailbox */
3788 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0);
3789 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0);
3790
3791 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0);
3792 DELAY(1000);
3793
3794 if ((error = rt2860_bbp_init(sc)) != 0) {
3795 rt2860_stop(ifp, 1);
3796 return error;
3797 }
3798
3799 /* clear RX WCID search table */
3800 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512);
3801 /* clear pairwise key table */
3802 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048);
3803 /* clear IV/EIV table */
3804 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512);
3805 /* clear WCID attribute table */
3806 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256);
3807 /* clear shared key table */
3808 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32);
3809 /* clear shared key mode */
3810 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4);
3811
3812 /* init Tx rings (4 EDCAs + HCCA + Mgt) */
3813 for (qid = 0; qid < 6; qid++) {
3814 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr);
3815 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT);
3816 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0);
3817 }
3818
3819 /* init Rx ring */
3820 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr);
3821 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT);
3822 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1);
3823
3824 /* setup maximum buffer sizes */
3825 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 |
3826 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2));
3827
3828 for (ntries = 0; ntries < 100; ntries++) {
3829 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
3830 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
3831 break;
3832 DELAY(1000);
3833 }
3834 if (ntries == 100) {
3835 printf("%s: timeout waiting for DMA engine\n",
3836 sc->sc_dev.dv_xname);
3837 rt2860_stop(ifp, 1);
3838 return ETIMEDOUT;
3839 }
3840 tmp &= 0xff0;
3841 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
3842
3843 /* disable interrupts mitigation */
3844 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0);
3845
3846 /* write vendor-specific BBP values (from EEPROM) */
3847 for (i = 0; i < 8; i++) {
3848 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)
3849 continue;
3850 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);
3851 }
3852
3853 /* select Main antenna for 1T1R devices */
3854 if (sc->rf_rev == RT3070_RF_2020 ||
3855 sc->rf_rev == RT3070_RF_3020 ||
3856 sc->rf_rev == RT3290_RF_3290 ||
3857 sc->rf_rev == RT3070_RF_3320 ||
3858 sc->rf_rev == RT5390_RF_5390)
3859 rt3090_set_rx_antenna(sc, 0);
3860
3861 /* send LEDs operating mode to microcontroller */
3862 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0);
3863 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0);
3864 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0);
3865
3866 if (sc->mac_ver == 0x3290 ||
3867 sc->mac_ver >= 0x5390)
3868 rt5390_rf_init(sc);
3869 else if (sc->mac_ver >= 0x3071)
3870 rt3090_rf_init(sc);
3871
3872 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1);
3873 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1);
3874
3875 if (sc->mac_ver == 0x3290 ||
3876 sc->mac_ver >= 0x5390)
3877 rt5390_rf_wakeup(sc);
3878 else if (sc->mac_ver >= 0x3071)
3879 rt3090_rf_wakeup(sc);
3880
3881 /* disable non-existing Rx chains */
3882 bbp3 = rt2860_mcu_bbp_read(sc, 3);
3883 bbp3 &= ~(1 << 3 | 1 << 4);
3884 if (sc->nrxchains == 2)
3885 bbp3 |= 1 << 3;
3886 else if (sc->nrxchains == 3)
3887 bbp3 |= 1 << 4;
3888 rt2860_mcu_bbp_write(sc, 3, bbp3);
3889
3890 /* disable non-existing Tx chains */
3891 bbp1 = rt2860_mcu_bbp_read(sc, 1);
3892 if (sc->ntxchains == 1)
3893 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4));
3894 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2)
3895 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3;
3896 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3)
3897 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4;
3898 rt2860_mcu_bbp_write(sc, 1, bbp1);
3899
3900 if (sc->mac_ver >= 0x3071)
3901 rt3090_rf_setup(sc);
3902
3903 /* select default channel */
3904 ic->ic_bss->ni_chan = ic->ic_ibss_chan;
3905 rt2860_switch_chan(sc, ic->ic_ibss_chan);
3906
3907 /* reset RF from MCU */
3908 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0);
3909
3910 /* set RTS threshold */
3911 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG);
3912 tmp &= ~0xffff00;
3913 tmp |= ic->ic_rtsthreshold << 8;
3914 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp);
3915
3916 /* setup initial protection mode */
3917 sc->sc_ic_flags = ic->ic_flags;
3918 rt2860_updateprot(ic);
3919
3920 /* turn radio LED on */
3921 rt2860_set_leds(sc, RT2860_LED_RADIO);
3922
3923 /* enable Tx/Rx DMA engine */
3924 if ((error = rt2860_txrx_enable(sc)) != 0) {
3925 rt2860_stop(ifp, 1);
3926 return error;
3927 }
3928
3929 /* clear pending interrupts */
3930 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff);
3931 /* enable interrupts */
3932 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc);
3933
3934 if (sc->sc_flags & RT2860_ADVANCED_PS)
3935 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0);
3936
3937 ifp->if_flags |= IFF_RUNNING;
3938 ifq_clr_oactive(&ifp->if_snd);
3939
3940 if (ic->ic_flags & IEEE80211_F_WEPON) {
3941 /* install WEP keys */
3942 for (i = 0; i < IEEE80211_WEP_NKID; i++)
3943 (void)rt2860_set_key(ic, NULL, &ic->ic_nw_keys[i]);
3944 }
3945
3946 if (ic->ic_opmode != IEEE80211_M_MONITOR)
3947 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
3948 else
3949 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
3950
3951 return 0;
3952 }
3953
3954 void
rt2860_stop(struct ifnet * ifp,int disable)3955 rt2860_stop(struct ifnet *ifp, int disable)
3956 {
3957 struct rt2860_softc *sc = ifp->if_softc;
3958 struct ieee80211com *ic = &sc->sc_ic;
3959 uint32_t tmp;
3960 int qid;
3961
3962 if (ifp->if_flags & IFF_RUNNING)
3963 rt2860_set_leds(sc, 0); /* turn all LEDs off */
3964
3965 sc->sc_tx_timer = 0;
3966 ifp->if_timer = 0;
3967 ifp->if_flags &= ~IFF_RUNNING;
3968 ifq_clr_oactive(&ifp->if_snd);
3969
3970 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* free all nodes */
3971
3972 /* disable interrupts */
3973 RAL_WRITE(sc, RT2860_INT_MASK, 0);
3974
3975 /* disable GP timer */
3976 rt2860_set_gp_timer(sc, 0);
3977
3978 /* disable Rx */
3979 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL);
3980 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
3981 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp);
3982
3983 /* reset adapter */
3984 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST);
3985 RAL_BARRIER_WRITE(sc);
3986 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0);
3987
3988 /* reset Tx and Rx rings (and reclaim TXWIs) */
3989 sc->qfullmsk = 0;
3990 for (qid = 0; qid < 6; qid++)
3991 rt2860_reset_tx_ring(sc, &sc->txq[qid]);
3992 rt2860_reset_rx_ring(sc, &sc->rxq);
3993
3994 /* for CardBus, power down the socket */
3995 if (disable && sc->sc_disable != NULL) {
3996 if (sc->sc_flags & RT2860_ENABLED) {
3997 (*sc->sc_disable)(sc);
3998 sc->sc_flags &= ~RT2860_ENABLED;
3999 }
4000 }
4001 }
4002
4003 int
rt2860_load_microcode(struct rt2860_softc * sc)4004 rt2860_load_microcode(struct rt2860_softc *sc)
4005 {
4006 int ntries;
4007
4008 /* set "host program ram write selection" bit */
4009 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL);
4010 /* write microcode image */
4011 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, sc->ucode, sc->ucsize);
4012 /* kick microcontroller unit */
4013 RAL_WRITE(sc, RT2860_SYS_CTRL, 0);
4014 RAL_BARRIER_WRITE(sc);
4015 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET);
4016
4017 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0);
4018 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0);
4019
4020 /* wait until microcontroller is ready */
4021 RAL_BARRIER_READ_WRITE(sc);
4022 for (ntries = 0; ntries < 1000; ntries++) {
4023 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY)
4024 break;
4025 DELAY(1000);
4026 }
4027 if (ntries == 1000) {
4028 printf("%s: timeout waiting for MCU to initialize\n",
4029 sc->sc_dev.dv_xname);
4030 return ETIMEDOUT;
4031 }
4032 return 0;
4033 }
4034
4035 /*
4036 * This function is called periodically to adjust Tx power based on
4037 * temperature variation.
4038 */
4039 void
rt2860_calib(struct rt2860_softc * sc)4040 rt2860_calib(struct rt2860_softc *sc)
4041 {
4042 struct ieee80211com *ic = &sc->sc_ic;
4043 const uint8_t *tssi;
4044 uint8_t step, bbp49;
4045 int8_t ridx, d;
4046
4047 /* read current temperature */
4048 bbp49 = rt2860_mcu_bbp_read(sc, 49);
4049
4050 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) {
4051 tssi = &sc->tssi_2ghz[4];
4052 step = sc->step_2ghz;
4053 } else {
4054 tssi = &sc->tssi_5ghz[4];
4055 step = sc->step_5ghz;
4056 }
4057
4058 if (bbp49 < tssi[0]) { /* lower than reference */
4059 /* use higher Tx power than default */
4060 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--)
4061 ;
4062 } else if (bbp49 > tssi[0]) { /* greater than reference */
4063 /* use lower Tx power than default */
4064 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++)
4065 ;
4066 } else {
4067 /* use default Tx power */
4068 d = 0;
4069 }
4070 d *= step;
4071
4072 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d));
4073
4074 /* write adjusted Tx power values for each Tx rate */
4075 for (ridx = 0; ridx < 5; ridx++) {
4076 if (sc->txpow20mhz[ridx] == 0xffffffff)
4077 continue;
4078 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx),
4079 b4inc(sc->txpow20mhz[ridx], d));
4080 }
4081 }
4082
4083 void
rt3090_set_rx_antenna(struct rt2860_softc * sc,int aux)4084 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux)
4085 {
4086 uint32_t tmp;
4087 if (aux) {
4088 if (sc->mac_ver == 0x5390) {
4089 rt2860_mcu_bbp_write(sc, 152,
4090 rt2860_mcu_bbp_read(sc, 152) & ~0x80);
4091 } else {
4092 tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
4093 RAL_WRITE(sc, RT2860_PCI_EECTRL,
4094 tmp & ~RT2860_C);
4095 tmp = RAL_READ(sc, RT2860_GPIO_CTRL);
4096 RAL_WRITE(sc, RT2860_GPIO_CTRL,
4097 (tmp & ~0x0808) | 0x08);
4098 }
4099 } else {
4100 if (sc->mac_ver == 0x5390) {
4101 rt2860_mcu_bbp_write(sc, 152,
4102 rt2860_mcu_bbp_read(sc, 152) | 0x80);
4103 } else {
4104 tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
4105 RAL_WRITE(sc, RT2860_PCI_EECTRL,
4106 tmp | RT2860_C);
4107 tmp = RAL_READ(sc, RT2860_GPIO_CTRL);
4108 RAL_WRITE(sc, RT2860_GPIO_CTRL,
4109 tmp & ~0x0808);
4110 }
4111 }
4112 }
4113
4114 void
rt2860_switch_chan(struct rt2860_softc * sc,struct ieee80211_channel * c)4115 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c)
4116 {
4117 struct ieee80211com *ic = &sc->sc_ic;
4118 u_int chan, group;
4119
4120 chan = ieee80211_chan2ieee(ic, c);
4121 if (chan == 0 || chan == IEEE80211_CHAN_ANY)
4122 return;
4123
4124 if (sc->mac_ver == 0x3290 ||
4125 sc->mac_ver >= 0x5390)
4126 rt5390_set_chan(sc, chan);
4127 else if (sc->mac_ver >= 0x3071)
4128 rt3090_set_chan(sc, chan);
4129 else
4130 rt2860_set_chan(sc, chan);
4131
4132 /* determine channel group */
4133 if (chan <= 14)
4134 group = 0;
4135 else if (chan <= 64)
4136 group = 1;
4137 else if (chan <= 128)
4138 group = 2;
4139 else
4140 group = 3;
4141
4142 /* XXX necessary only when group has changed! */
4143 if (sc->mac_ver <= 0x5390)
4144 rt2860_select_chan_group(sc, group);
4145
4146 DELAY(1000);
4147 }
4148
4149 #ifndef IEEE80211_STA_ONLY
4150 int
rt2860_setup_beacon(struct rt2860_softc * sc)4151 rt2860_setup_beacon(struct rt2860_softc *sc)
4152 {
4153 struct ieee80211com *ic = &sc->sc_ic;
4154 struct rt2860_txwi txwi;
4155 struct mbuf *m;
4156 int ridx;
4157
4158 if ((m = ieee80211_beacon_alloc(ic, ic->ic_bss)) == NULL)
4159 return ENOBUFS;
4160
4161 memset(&txwi, 0, sizeof txwi);
4162 txwi.wcid = 0xff;
4163 txwi.len = htole16(m->m_pkthdr.len);
4164 /* send beacons at the lowest available rate */
4165 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ?
4166 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1;
4167 txwi.phy = htole16(rt2860_rates[ridx].mcs);
4168 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM)
4169 txwi.phy |= htole16(RT2860_PHY_OFDM);
4170 txwi.txop = RT2860_TX_TXOP_HT;
4171 txwi.flags = RT2860_TX_TS;
4172 txwi.xflags = RT2860_TX_NSEQ;
4173
4174 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0),
4175 (uint8_t *)&txwi, sizeof txwi);
4176 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi,
4177 mtod(m, uint8_t *), m->m_pkthdr.len);
4178
4179 m_freem(m);
4180
4181 return 0;
4182 }
4183 #endif
4184
4185 void
rt2860_enable_tsf_sync(struct rt2860_softc * sc)4186 rt2860_enable_tsf_sync(struct rt2860_softc *sc)
4187 {
4188 struct ieee80211com *ic = &sc->sc_ic;
4189 uint32_t tmp;
4190
4191 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG);
4192
4193 tmp &= ~0x1fffff;
4194 tmp |= ic->ic_bss->ni_intval * 16;
4195 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN;
4196 if (ic->ic_opmode == IEEE80211_M_STA) {
4197 /*
4198 * Local TSF is always updated with remote TSF on beacon
4199 * reception.
4200 */
4201 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT;
4202 }
4203 #ifndef IEEE80211_STA_ONLY
4204 else if (ic->ic_opmode == IEEE80211_M_IBSS) {
4205 tmp |= RT2860_BCN_TX_EN;
4206 /*
4207 * Local TSF is updated with remote TSF on beacon reception
4208 * only if the remote TSF is greater than local TSF.
4209 */
4210 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT;
4211 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
4212 tmp |= RT2860_BCN_TX_EN;
4213 /* SYNC with nobody */
4214 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT;
4215 }
4216 #endif
4217
4218 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp);
4219 }
4220