1 /*
2 * QEMU sPAPR PCI host originated from Uninorth PCI host
3 *
4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation.
5 * Copyright (C) 2011 David Gibson, IBM Corporation.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "qapi/error.h"
28 #include "hw/irq.h"
29 #include "hw/sysbus.h"
30 #include "migration/vmstate.h"
31 #include "hw/pci/pci.h"
32 #include "hw/pci/msi.h"
33 #include "hw/pci/msix.h"
34 #include "hw/pci/pci_host.h"
35 #include "hw/ppc/spapr.h"
36 #include "hw/pci-host/spapr.h"
37 #include "exec/ram_addr.h"
38 #include <libfdt.h>
39 #include "trace.h"
40 #include "qemu/error-report.h"
41 #include "qemu/module.h"
42 #include "hw/ppc/fdt.h"
43 #include "hw/pci/pci_bridge.h"
44 #include "hw/pci/pci_bus.h"
45 #include "hw/pci/pci_ids.h"
46 #include "hw/ppc/spapr_drc.h"
47 #include "hw/qdev-properties.h"
48 #include "sysemu/device_tree.h"
49 #include "sysemu/kvm.h"
50 #include "sysemu/hostmem.h"
51 #include "sysemu/numa.h"
52 #include "hw/ppc/spapr_numa.h"
53 #include "qemu/log.h"
54
55 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */
56 #define RTAS_QUERY_FN 0
57 #define RTAS_CHANGE_FN 1
58 #define RTAS_RESET_FN 2
59 #define RTAS_CHANGE_MSI_FN 3
60 #define RTAS_CHANGE_MSIX_FN 4
61
62 /* Interrupt types to return on RTAS_CHANGE_* */
63 #define RTAS_TYPE_MSI 1
64 #define RTAS_TYPE_MSIX 2
65
spapr_pci_find_phb(SpaprMachineState * spapr,uint64_t buid)66 SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid)
67 {
68 SpaprPhbState *sphb;
69
70 QLIST_FOREACH(sphb, &spapr->phbs, list) {
71 if (sphb->buid != buid) {
72 continue;
73 }
74 return sphb;
75 }
76
77 return NULL;
78 }
79
spapr_pci_find_dev(SpaprMachineState * spapr,uint64_t buid,uint32_t config_addr)80 PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid,
81 uint32_t config_addr)
82 {
83 SpaprPhbState *sphb = spapr_pci_find_phb(spapr, buid);
84 PCIHostState *phb = PCI_HOST_BRIDGE(sphb);
85 int bus_num = (config_addr >> 16) & 0xFF;
86 int devfn = (config_addr >> 8) & 0xFF;
87
88 if (!phb) {
89 return NULL;
90 }
91
92 return pci_find_device(phb->bus, bus_num, devfn);
93 }
94
rtas_pci_cfgaddr(uint32_t arg)95 static uint32_t rtas_pci_cfgaddr(uint32_t arg)
96 {
97 /* This handles the encoding of extended config space addresses */
98 return ((arg >> 20) & 0xf00) | (arg & 0xff);
99 }
100
finish_read_pci_config(SpaprMachineState * spapr,uint64_t buid,uint32_t addr,uint32_t size,target_ulong rets)101 static void finish_read_pci_config(SpaprMachineState *spapr, uint64_t buid,
102 uint32_t addr, uint32_t size,
103 target_ulong rets)
104 {
105 PCIDevice *pci_dev;
106 uint32_t val;
107
108 if ((size != 1) && (size != 2) && (size != 4)) {
109 /* access must be 1, 2 or 4 bytes */
110 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
111 return;
112 }
113
114 pci_dev = spapr_pci_find_dev(spapr, buid, addr);
115 addr = rtas_pci_cfgaddr(addr);
116
117 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
118 /* Access must be to a valid device, within bounds and
119 * naturally aligned */
120 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
121 return;
122 }
123
124 val = pci_host_config_read_common(pci_dev, addr,
125 pci_config_size(pci_dev), size);
126
127 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
128 rtas_st(rets, 1, val);
129 }
130
rtas_ibm_read_pci_config(PowerPCCPU * cpu,SpaprMachineState * spapr,uint32_t token,uint32_t nargs,target_ulong args,uint32_t nret,target_ulong rets)131 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
132 uint32_t token, uint32_t nargs,
133 target_ulong args,
134 uint32_t nret, target_ulong rets)
135 {
136 uint64_t buid;
137 uint32_t size, addr;
138
139 if ((nargs != 4) || (nret != 2)) {
140 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
141 return;
142 }
143
144 buid = rtas_ldq(args, 1);
145 size = rtas_ld(args, 3);
146 addr = rtas_ld(args, 0);
147
148 finish_read_pci_config(spapr, buid, addr, size, rets);
149 }
150
rtas_read_pci_config(PowerPCCPU * cpu,SpaprMachineState * spapr,uint32_t token,uint32_t nargs,target_ulong args,uint32_t nret,target_ulong rets)151 static void rtas_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
152 uint32_t token, uint32_t nargs,
153 target_ulong args,
154 uint32_t nret, target_ulong rets)
155 {
156 uint32_t size, addr;
157
158 if ((nargs != 2) || (nret != 2)) {
159 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
160 return;
161 }
162
163 size = rtas_ld(args, 1);
164 addr = rtas_ld(args, 0);
165
166 finish_read_pci_config(spapr, 0, addr, size, rets);
167 }
168
finish_write_pci_config(SpaprMachineState * spapr,uint64_t buid,uint32_t addr,uint32_t size,uint32_t val,target_ulong rets)169 static void finish_write_pci_config(SpaprMachineState *spapr, uint64_t buid,
170 uint32_t addr, uint32_t size,
171 uint32_t val, target_ulong rets)
172 {
173 PCIDevice *pci_dev;
174
175 if ((size != 1) && (size != 2) && (size != 4)) {
176 /* access must be 1, 2 or 4 bytes */
177 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
178 return;
179 }
180
181 pci_dev = spapr_pci_find_dev(spapr, buid, addr);
182 addr = rtas_pci_cfgaddr(addr);
183
184 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) {
185 /* Access must be to a valid device, within bounds and
186 * naturally aligned */
187 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
188 return;
189 }
190
191 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev),
192 val, size);
193
194 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
195 }
196
rtas_ibm_write_pci_config(PowerPCCPU * cpu,SpaprMachineState * spapr,uint32_t token,uint32_t nargs,target_ulong args,uint32_t nret,target_ulong rets)197 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
198 uint32_t token, uint32_t nargs,
199 target_ulong args,
200 uint32_t nret, target_ulong rets)
201 {
202 uint64_t buid;
203 uint32_t val, size, addr;
204
205 if ((nargs != 5) || (nret != 1)) {
206 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
207 return;
208 }
209
210 buid = rtas_ldq(args, 1);
211 val = rtas_ld(args, 4);
212 size = rtas_ld(args, 3);
213 addr = rtas_ld(args, 0);
214
215 finish_write_pci_config(spapr, buid, addr, size, val, rets);
216 }
217
rtas_write_pci_config(PowerPCCPU * cpu,SpaprMachineState * spapr,uint32_t token,uint32_t nargs,target_ulong args,uint32_t nret,target_ulong rets)218 static void rtas_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr,
219 uint32_t token, uint32_t nargs,
220 target_ulong args,
221 uint32_t nret, target_ulong rets)
222 {
223 uint32_t val, size, addr;
224
225 if ((nargs != 3) || (nret != 1)) {
226 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
227 return;
228 }
229
230
231 val = rtas_ld(args, 2);
232 size = rtas_ld(args, 1);
233 addr = rtas_ld(args, 0);
234
235 finish_write_pci_config(spapr, 0, addr, size, val, rets);
236 }
237
238 /*
239 * Set MSI/MSIX message data.
240 * This is required for msi_notify()/msix_notify() which
241 * will write at the addresses via spapr_msi_write().
242 *
243 * If hwaddr == 0, all entries will have .data == first_irq i.e.
244 * table will be reset.
245 */
spapr_msi_setmsg(PCIDevice * pdev,hwaddr addr,bool msix,unsigned first_irq,unsigned req_num)246 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix,
247 unsigned first_irq, unsigned req_num)
248 {
249 unsigned i;
250 MSIMessage msg = { .address = addr, .data = first_irq };
251
252 if (!msix) {
253 msi_set_message(pdev, msg);
254 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address);
255 return;
256 }
257
258 for (i = 0; i < req_num; ++i) {
259 msix_set_message(pdev, i, msg);
260 trace_spapr_pci_msi_setup(pdev->name, i, msg.address);
261 if (addr) {
262 ++msg.data;
263 }
264 }
265 }
266
rtas_ibm_change_msi(PowerPCCPU * cpu,SpaprMachineState * spapr,uint32_t token,uint32_t nargs,target_ulong args,uint32_t nret,target_ulong rets)267 static void rtas_ibm_change_msi(PowerPCCPU *cpu, SpaprMachineState *spapr,
268 uint32_t token, uint32_t nargs,
269 target_ulong args, uint32_t nret,
270 target_ulong rets)
271 {
272 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
273 uint32_t config_addr = rtas_ld(args, 0);
274 uint64_t buid = rtas_ldq(args, 1);
275 unsigned int func = rtas_ld(args, 3);
276 unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */
277 unsigned int seq_num = rtas_ld(args, 5);
278 unsigned int ret_intr_type;
279 unsigned int irq, max_irqs = 0;
280 SpaprPhbState *phb = NULL;
281 PCIDevice *pdev = NULL;
282 SpaprPciMsi *msi;
283 int *config_addr_key;
284 Error *err = NULL;
285 int i;
286
287 /* Fins SpaprPhbState */
288 phb = spapr_pci_find_phb(spapr, buid);
289 if (phb) {
290 pdev = spapr_pci_find_dev(spapr, buid, config_addr);
291 }
292 if (!phb || !pdev) {
293 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
294 return;
295 }
296
297 switch (func) {
298 case RTAS_CHANGE_FN:
299 if (msi_present(pdev)) {
300 ret_intr_type = RTAS_TYPE_MSI;
301 } else if (msix_present(pdev)) {
302 ret_intr_type = RTAS_TYPE_MSIX;
303 } else {
304 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
305 return;
306 }
307 break;
308 case RTAS_CHANGE_MSI_FN:
309 if (msi_present(pdev)) {
310 ret_intr_type = RTAS_TYPE_MSI;
311 } else {
312 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
313 return;
314 }
315 break;
316 case RTAS_CHANGE_MSIX_FN:
317 if (msix_present(pdev)) {
318 ret_intr_type = RTAS_TYPE_MSIX;
319 } else {
320 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
321 return;
322 }
323 break;
324 default:
325 error_report("rtas_ibm_change_msi(%u) is not implemented", func);
326 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
327 return;
328 }
329
330 msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr);
331
332 /* Releasing MSIs */
333 if (!req_num) {
334 if (!msi) {
335 trace_spapr_pci_msi("Releasing wrong config", config_addr);
336 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
337 return;
338 }
339
340 if (msi_present(pdev)) {
341 spapr_msi_setmsg(pdev, 0, false, 0, 0);
342 }
343 if (msix_present(pdev)) {
344 spapr_msi_setmsg(pdev, 0, true, 0, 0);
345 }
346 g_hash_table_remove(phb->msi, &config_addr);
347
348 trace_spapr_pci_msi("Released MSIs", config_addr);
349 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
350 rtas_st(rets, 1, 0);
351 return;
352 }
353
354 /* Enabling MSI */
355
356 /* Check if the device supports as many IRQs as requested */
357 if (ret_intr_type == RTAS_TYPE_MSI) {
358 max_irqs = msi_nr_vectors_allocated(pdev);
359 } else if (ret_intr_type == RTAS_TYPE_MSIX) {
360 max_irqs = pdev->msix_entries_nr;
361 }
362 if (!max_irqs) {
363 error_report("Requested interrupt type %d is not enabled for device %x",
364 ret_intr_type, config_addr);
365 rtas_st(rets, 0, -1); /* Hardware error */
366 return;
367 }
368 /* Correct the number if the guest asked for too many */
369 if (req_num > max_irqs) {
370 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs);
371 req_num = max_irqs;
372 irq = 0; /* to avoid misleading trace */
373 goto out;
374 }
375
376 /* Allocate MSIs */
377 if (smc->legacy_irq_allocation) {
378 irq = spapr_irq_find(spapr, req_num, ret_intr_type == RTAS_TYPE_MSI,
379 &err);
380 } else {
381 irq = spapr_irq_msi_alloc(spapr, req_num,
382 ret_intr_type == RTAS_TYPE_MSI, &err);
383 }
384 if (err) {
385 error_reportf_err(err, "Can't allocate MSIs for device %x: ",
386 config_addr);
387 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
388 return;
389 }
390
391 for (i = 0; i < req_num; i++) {
392 spapr_irq_claim(spapr, irq + i, false, &err);
393 if (err) {
394 if (i) {
395 spapr_irq_free(spapr, irq, i);
396 }
397 if (!smc->legacy_irq_allocation) {
398 spapr_irq_msi_free(spapr, irq, req_num);
399 }
400 error_reportf_err(err, "Can't allocate MSIs for device %x: ",
401 config_addr);
402 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
403 return;
404 }
405 }
406
407 /* Release previous MSIs */
408 if (msi) {
409 g_hash_table_remove(phb->msi, &config_addr);
410 }
411
412 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */
413 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX,
414 irq, req_num);
415
416 /* Add MSI device to cache */
417 msi = g_new(SpaprPciMsi, 1);
418 msi->first_irq = irq;
419 msi->num = req_num;
420 config_addr_key = g_new(int, 1);
421 *config_addr_key = config_addr;
422 g_hash_table_insert(phb->msi, config_addr_key, msi);
423
424 out:
425 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
426 rtas_st(rets, 1, req_num);
427 rtas_st(rets, 2, ++seq_num);
428 if (nret > 3) {
429 rtas_st(rets, 3, ret_intr_type);
430 }
431
432 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq);
433 }
434
rtas_ibm_query_interrupt_source_number(PowerPCCPU * cpu,SpaprMachineState * spapr,uint32_t token,uint32_t nargs,target_ulong args,uint32_t nret,target_ulong rets)435 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu,
436 SpaprMachineState *spapr,
437 uint32_t token,
438 uint32_t nargs,
439 target_ulong args,
440 uint32_t nret,
441 target_ulong rets)
442 {
443 uint32_t config_addr = rtas_ld(args, 0);
444 uint64_t buid = rtas_ldq(args, 1);
445 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3);
446 SpaprPhbState *phb = NULL;
447 PCIDevice *pdev = NULL;
448 SpaprPciMsi *msi;
449
450 /* Find SpaprPhbState */
451 phb = spapr_pci_find_phb(spapr, buid);
452 if (phb) {
453 pdev = spapr_pci_find_dev(spapr, buid, config_addr);
454 }
455 if (!phb || !pdev) {
456 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
457 return;
458 }
459
460 /* Find device descriptor and start IRQ */
461 msi = (SpaprPciMsi *) g_hash_table_lookup(phb->msi, &config_addr);
462 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) {
463 trace_spapr_pci_msi("Failed to return vector", config_addr);
464 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
465 return;
466 }
467 intr_src_num = msi->first_irq + ioa_intr_num;
468 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num,
469 intr_src_num);
470
471 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
472 rtas_st(rets, 1, intr_src_num);
473 rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */
474 }
475
rtas_ibm_set_eeh_option(PowerPCCPU * cpu,SpaprMachineState * spapr,uint32_t token,uint32_t nargs,target_ulong args,uint32_t nret,target_ulong rets)476 static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu,
477 SpaprMachineState *spapr,
478 uint32_t token, uint32_t nargs,
479 target_ulong args, uint32_t nret,
480 target_ulong rets)
481 {
482 SpaprPhbState *sphb;
483 uint32_t addr, option;
484 uint64_t buid;
485 int ret;
486
487 if ((nargs != 4) || (nret != 1)) {
488 goto param_error_exit;
489 }
490
491 buid = rtas_ldq(args, 1);
492 addr = rtas_ld(args, 0);
493 option = rtas_ld(args, 3);
494
495 sphb = spapr_pci_find_phb(spapr, buid);
496 if (!sphb) {
497 goto param_error_exit;
498 }
499
500 if (!spapr_phb_eeh_available(sphb)) {
501 goto param_error_exit;
502 }
503
504 ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option);
505 rtas_st(rets, 0, ret);
506 return;
507
508 param_error_exit:
509 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
510 }
511
rtas_ibm_get_config_addr_info2(PowerPCCPU * cpu,SpaprMachineState * spapr,uint32_t token,uint32_t nargs,target_ulong args,uint32_t nret,target_ulong rets)512 static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu,
513 SpaprMachineState *spapr,
514 uint32_t token, uint32_t nargs,
515 target_ulong args, uint32_t nret,
516 target_ulong rets)
517 {
518 SpaprPhbState *sphb;
519 PCIDevice *pdev;
520 uint32_t addr, option;
521 uint64_t buid;
522
523 if ((nargs != 4) || (nret != 2)) {
524 goto param_error_exit;
525 }
526
527 buid = rtas_ldq(args, 1);
528 sphb = spapr_pci_find_phb(spapr, buid);
529 if (!sphb) {
530 goto param_error_exit;
531 }
532
533 if (!spapr_phb_eeh_available(sphb)) {
534 goto param_error_exit;
535 }
536
537 /*
538 * We always have PE address of form "00BB0001". "BB"
539 * represents the bus number of PE's primary bus.
540 */
541 option = rtas_ld(args, 3);
542 switch (option) {
543 case RTAS_GET_PE_ADDR:
544 addr = rtas_ld(args, 0);
545 pdev = spapr_pci_find_dev(spapr, buid, addr);
546 if (!pdev) {
547 goto param_error_exit;
548 }
549
550 rtas_st(rets, 1, (pci_bus_num(pci_get_bus(pdev)) << 16) + 1);
551 break;
552 case RTAS_GET_PE_MODE:
553 rtas_st(rets, 1, RTAS_PE_MODE_SHARED);
554 break;
555 default:
556 goto param_error_exit;
557 }
558
559 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
560 return;
561
562 param_error_exit:
563 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
564 }
565
rtas_ibm_read_slot_reset_state2(PowerPCCPU * cpu,SpaprMachineState * spapr,uint32_t token,uint32_t nargs,target_ulong args,uint32_t nret,target_ulong rets)566 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu,
567 SpaprMachineState *spapr,
568 uint32_t token, uint32_t nargs,
569 target_ulong args, uint32_t nret,
570 target_ulong rets)
571 {
572 SpaprPhbState *sphb;
573 uint64_t buid;
574 int state, ret;
575
576 if ((nargs != 3) || (nret != 4 && nret != 5)) {
577 goto param_error_exit;
578 }
579
580 buid = rtas_ldq(args, 1);
581 sphb = spapr_pci_find_phb(spapr, buid);
582 if (!sphb) {
583 goto param_error_exit;
584 }
585
586 if (!spapr_phb_eeh_available(sphb)) {
587 goto param_error_exit;
588 }
589
590 ret = spapr_phb_vfio_eeh_get_state(sphb, &state);
591 rtas_st(rets, 0, ret);
592 if (ret != RTAS_OUT_SUCCESS) {
593 return;
594 }
595
596 rtas_st(rets, 1, state);
597 rtas_st(rets, 2, RTAS_EEH_SUPPORT);
598 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO);
599 if (nret >= 5) {
600 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO);
601 }
602 return;
603
604 param_error_exit:
605 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
606 }
607
rtas_ibm_set_slot_reset(PowerPCCPU * cpu,SpaprMachineState * spapr,uint32_t token,uint32_t nargs,target_ulong args,uint32_t nret,target_ulong rets)608 static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu,
609 SpaprMachineState *spapr,
610 uint32_t token, uint32_t nargs,
611 target_ulong args, uint32_t nret,
612 target_ulong rets)
613 {
614 SpaprPhbState *sphb;
615 uint32_t option;
616 uint64_t buid;
617 int ret;
618
619 if ((nargs != 4) || (nret != 1)) {
620 goto param_error_exit;
621 }
622
623 buid = rtas_ldq(args, 1);
624 option = rtas_ld(args, 3);
625 sphb = spapr_pci_find_phb(spapr, buid);
626 if (!sphb) {
627 goto param_error_exit;
628 }
629
630 if (!spapr_phb_eeh_available(sphb)) {
631 goto param_error_exit;
632 }
633
634 ret = spapr_phb_vfio_eeh_reset(sphb, option);
635 rtas_st(rets, 0, ret);
636 return;
637
638 param_error_exit:
639 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
640 }
641
rtas_ibm_configure_pe(PowerPCCPU * cpu,SpaprMachineState * spapr,uint32_t token,uint32_t nargs,target_ulong args,uint32_t nret,target_ulong rets)642 static void rtas_ibm_configure_pe(PowerPCCPU *cpu,
643 SpaprMachineState *spapr,
644 uint32_t token, uint32_t nargs,
645 target_ulong args, uint32_t nret,
646 target_ulong rets)
647 {
648 SpaprPhbState *sphb;
649 uint64_t buid;
650 int ret;
651
652 if ((nargs != 3) || (nret != 1)) {
653 goto param_error_exit;
654 }
655
656 buid = rtas_ldq(args, 1);
657 sphb = spapr_pci_find_phb(spapr, buid);
658 if (!sphb) {
659 goto param_error_exit;
660 }
661
662 if (!spapr_phb_eeh_available(sphb)) {
663 goto param_error_exit;
664 }
665
666 ret = spapr_phb_vfio_eeh_configure(sphb);
667 rtas_st(rets, 0, ret);
668 return;
669
670 param_error_exit:
671 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
672 }
673
674 /* To support it later */
rtas_ibm_slot_error_detail(PowerPCCPU * cpu,SpaprMachineState * spapr,uint32_t token,uint32_t nargs,target_ulong args,uint32_t nret,target_ulong rets)675 static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu,
676 SpaprMachineState *spapr,
677 uint32_t token, uint32_t nargs,
678 target_ulong args, uint32_t nret,
679 target_ulong rets)
680 {
681 SpaprPhbState *sphb;
682 int option;
683 uint64_t buid;
684
685 if ((nargs != 8) || (nret != 1)) {
686 goto param_error_exit;
687 }
688
689 buid = rtas_ldq(args, 1);
690 sphb = spapr_pci_find_phb(spapr, buid);
691 if (!sphb) {
692 goto param_error_exit;
693 }
694
695 if (!spapr_phb_eeh_available(sphb)) {
696 goto param_error_exit;
697 }
698
699 option = rtas_ld(args, 7);
700 switch (option) {
701 case RTAS_SLOT_TEMP_ERR_LOG:
702 case RTAS_SLOT_PERM_ERR_LOG:
703 break;
704 default:
705 goto param_error_exit;
706 }
707
708 /* We don't have error log yet */
709 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND);
710 return;
711
712 param_error_exit:
713 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
714 }
715
pci_spapr_set_irq(void * opaque,int irq_num,int level)716 static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
717 {
718 /*
719 * Here we use the number returned by pci_swizzle_map_irq_fn to find a
720 * corresponding qemu_irq.
721 */
722 SpaprPhbState *phb = opaque;
723 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
724
725 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq);
726 qemu_set_irq(spapr_qirq(spapr, phb->lsi_table[irq_num].irq), level);
727 }
728
spapr_route_intx_pin_to_irq(void * opaque,int pin)729 static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin)
730 {
731 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque);
732 PCIINTxRoute route;
733
734 route.mode = PCI_INTX_ENABLED;
735 route.irq = sphb->lsi_table[pin].irq;
736
737 return route;
738 }
739
spapr_msi_read(void * opaque,hwaddr addr,unsigned size)740 static uint64_t spapr_msi_read(void *opaque, hwaddr addr, unsigned size)
741 {
742 qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid access\n", __func__);
743 return 0;
744 }
745
746 /*
747 * MSI/MSIX memory region implementation.
748 * The handler handles both MSI and MSIX.
749 * The vector number is encoded in least bits in data.
750 */
spapr_msi_write(void * opaque,hwaddr addr,uint64_t data,unsigned size)751 static void spapr_msi_write(void *opaque, hwaddr addr,
752 uint64_t data, unsigned size)
753 {
754 SpaprMachineState *spapr = opaque;
755 uint32_t irq = data;
756
757 trace_spapr_pci_msi_write(addr, data, irq);
758
759 qemu_irq_pulse(spapr_qirq(spapr, irq));
760 }
761
762 static const MemoryRegionOps spapr_msi_ops = {
763 /*
764 * .read result is undefined by PCI spec.
765 * define .read method to avoid assert failure in memory_region_init_io
766 */
767 .read = spapr_msi_read,
768 .write = spapr_msi_write,
769 .endianness = DEVICE_LITTLE_ENDIAN
770 };
771
772 /*
773 * PHB PCI device
774 */
spapr_pci_dma_iommu(PCIBus * bus,void * opaque,int devfn)775 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
776 {
777 SpaprPhbState *phb = opaque;
778
779 return &phb->iommu_as;
780 }
781
782 static const PCIIOMMUOps spapr_iommu_ops = {
783 .get_address_space = spapr_pci_dma_iommu,
784 };
785
spapr_phb_vfio_get_loc_code(SpaprPhbState * sphb,PCIDevice * pdev)786 static char *spapr_phb_vfio_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev)
787 {
788 g_autofree char *path = NULL;
789 g_autofree char *host = NULL;
790 g_autofree char *devspec = NULL;
791 char *buf = NULL;
792
793 /* Get the PCI VFIO host id */
794 host = object_property_get_str(OBJECT(pdev), "host", NULL);
795 if (!host) {
796 return NULL;
797 }
798
799 /* Construct the path of the file that will give us the DT location */
800 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host);
801 if (!g_file_get_contents(path, &devspec, NULL, NULL)) {
802 return NULL;
803 }
804
805 /* Construct and read from host device tree the loc-code */
806 g_free(path);
807 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", devspec);
808 if (!g_file_get_contents(path, &buf, NULL, NULL)) {
809 return NULL;
810 }
811 return buf;
812 }
813
spapr_phb_get_loc_code(SpaprPhbState * sphb,PCIDevice * pdev)814 static char *spapr_phb_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev)
815 {
816 char *buf;
817 const char *devtype = "qemu";
818 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))));
819
820 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) {
821 buf = spapr_phb_vfio_get_loc_code(sphb, pdev);
822 if (buf) {
823 return buf;
824 }
825 devtype = "vfio";
826 }
827 /*
828 * For emulated devices and VFIO-failure case, make up
829 * the loc-code.
830 */
831 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x",
832 devtype, pdev->name, sphb->index, busnr,
833 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
834 return buf;
835 }
836
837 /* Macros to operate with address in OF binding to PCI */
838 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p))
839 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */
840 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */
841 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */
842 #define b_ss(x) b_x((x), 24, 2) /* the space code */
843 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */
844 #define b_ddddd(x) b_x((x), 11, 5) /* device number */
845 #define b_fff(x) b_x((x), 8, 3) /* function number */
846 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */
847
848 /* for 'reg' OF properties */
849 #define RESOURCE_CELLS_SIZE 2
850 #define RESOURCE_CELLS_ADDRESS 3
851
852 typedef struct ResourceFields {
853 uint32_t phys_hi;
854 uint32_t phys_mid;
855 uint32_t phys_lo;
856 uint32_t size_hi;
857 uint32_t size_lo;
858 } QEMU_PACKED ResourceFields;
859
860 typedef struct ResourceProps {
861 ResourceFields reg[8];
862 uint32_t reg_len;
863 } ResourceProps;
864
865 /* fill in the 'reg' OF properties for
866 * a PCI device. 'reg' describes resource requirements for a
867 * device's IO/MEM regions.
868 *
869 * the property is an array of ('phys-addr', 'size') pairs describing
870 * the addressable regions of the PCI device, where 'phys-addr' is a
871 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to
872 * (phys.hi, phys.mid, phys.lo), and 'size' is a
873 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo).
874 *
875 * phys.hi = 0xYYXXXXZZ, where:
876 * 0xYY = npt000ss
877 * ||| |
878 * ||| +-- space code
879 * ||| |
880 * ||| + 00 if configuration space
881 * ||| + 01 if IO region,
882 * ||| + 10 if 32-bit MEM region
883 * ||| + 11 if 64-bit MEM region
884 * |||
885 * ||+------ for non-relocatable IO: 1 if aliased
886 * || for relocatable IO: 1 if below 64KB
887 * || for MEM: 1 if below 1MB
888 * |+------- 1 if region is prefetchable
889 * +-------- 1 if region is non-relocatable
890 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function
891 * bits respectively
892 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding
893 * to the region
894 *
895 * phys.mid and phys.lo correspond respectively to the hi/lo portions
896 * of the actual address of the region.
897 *
898 * note also that addresses defined in this property are, at least
899 * for PAPR guests, relative to the PHBs IO/MEM windows, and
900 * correspond directly to the addresses in the BARs.
901 *
902 * in accordance with PCI Bus Binding to Open Firmware,
903 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7,
904 * Appendix C.
905 */
populate_resource_props(PCIDevice * d,ResourceProps * rp)906 static void populate_resource_props(PCIDevice *d, ResourceProps *rp)
907 {
908 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d))));
909 uint32_t dev_id = (b_bbbbbbbb(bus_num) |
910 b_ddddd(PCI_SLOT(d->devfn)) |
911 b_fff(PCI_FUNC(d->devfn)));
912 ResourceFields *reg;
913 int i, reg_idx = 0;
914
915 /* config space region */
916 reg = &rp->reg[reg_idx++];
917 reg->phys_hi = cpu_to_be32(dev_id);
918 reg->phys_mid = 0;
919 reg->phys_lo = 0;
920 reg->size_hi = 0;
921 reg->size_lo = 0;
922
923 for (i = 0; i < PCI_NUM_REGIONS; i++) {
924 if (!d->io_regions[i].size) {
925 continue;
926 }
927
928 reg = &rp->reg[reg_idx++];
929
930 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i)));
931 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) {
932 reg->phys_hi |= cpu_to_be32(b_ss(1));
933 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
934 reg->phys_hi |= cpu_to_be32(b_ss(3));
935 } else {
936 reg->phys_hi |= cpu_to_be32(b_ss(2));
937 }
938 reg->phys_mid = 0;
939 reg->phys_lo = 0;
940 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32);
941 reg->size_lo = cpu_to_be32(d->io_regions[i].size);
942 }
943
944 rp->reg_len = reg_idx * sizeof(ResourceFields);
945 }
946
947 typedef struct PCIClass PCIClass;
948 typedef struct PCISubClass PCISubClass;
949 typedef struct PCIIFace PCIIFace;
950
951 struct PCIIFace {
952 int iface;
953 const char *name;
954 };
955
956 struct PCISubClass {
957 int subclass;
958 const char *name;
959 const PCIIFace *iface;
960 };
961
962 struct PCIClass {
963 const char *name;
964 const PCISubClass *subc;
965 };
966
967 static const PCISubClass undef_subclass[] = {
968 { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL },
969 { 0xFF, NULL, NULL },
970 };
971
972 static const PCISubClass mass_subclass[] = {
973 { PCI_CLASS_STORAGE_SCSI, "scsi", NULL },
974 { PCI_CLASS_STORAGE_IDE, "ide", NULL },
975 { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL },
976 { PCI_CLASS_STORAGE_IPI, "ipi", NULL },
977 { PCI_CLASS_STORAGE_RAID, "raid", NULL },
978 { PCI_CLASS_STORAGE_ATA, "ata", NULL },
979 { PCI_CLASS_STORAGE_SATA, "sata", NULL },
980 { PCI_CLASS_STORAGE_SAS, "sas", NULL },
981 { 0xFF, NULL, NULL },
982 };
983
984 static const PCISubClass net_subclass[] = {
985 { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL },
986 { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL },
987 { PCI_CLASS_NETWORK_FDDI, "fddi", NULL },
988 { PCI_CLASS_NETWORK_ATM, "atm", NULL },
989 { PCI_CLASS_NETWORK_ISDN, "isdn", NULL },
990 { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL },
991 { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL },
992 { 0xFF, NULL, NULL },
993 };
994
995 static const PCISubClass displ_subclass[] = {
996 { PCI_CLASS_DISPLAY_VGA, "vga", NULL },
997 { PCI_CLASS_DISPLAY_XGA, "xga", NULL },
998 { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL },
999 { 0xFF, NULL, NULL },
1000 };
1001
1002 static const PCISubClass media_subclass[] = {
1003 { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL },
1004 { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL },
1005 { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL },
1006 { 0xFF, NULL, NULL },
1007 };
1008
1009 static const PCISubClass mem_subclass[] = {
1010 { PCI_CLASS_MEMORY_RAM, "memory", NULL },
1011 { PCI_CLASS_MEMORY_FLASH, "flash", NULL },
1012 { 0xFF, NULL, NULL },
1013 };
1014
1015 static const PCISubClass bridg_subclass[] = {
1016 { PCI_CLASS_BRIDGE_HOST, "host", NULL },
1017 { PCI_CLASS_BRIDGE_ISA, "isa", NULL },
1018 { PCI_CLASS_BRIDGE_EISA, "eisa", NULL },
1019 { PCI_CLASS_BRIDGE_MC, "mca", NULL },
1020 { PCI_CLASS_BRIDGE_PCI, "pci", NULL },
1021 { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL },
1022 { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL },
1023 { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL },
1024 { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL },
1025 { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL },
1026 { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL },
1027 { 0xFF, NULL, NULL },
1028 };
1029
1030 static const PCISubClass comm_subclass[] = {
1031 { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL },
1032 { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL },
1033 { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL },
1034 { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL },
1035 { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL },
1036 { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL },
1037 { 0xFF, NULL, NULL, },
1038 };
1039
1040 static const PCIIFace pic_iface[] = {
1041 { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" },
1042 { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" },
1043 { 0xFF, NULL },
1044 };
1045
1046 static const PCISubClass sys_subclass[] = {
1047 { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface },
1048 { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL },
1049 { PCI_CLASS_SYSTEM_TIMER, "timer", NULL },
1050 { PCI_CLASS_SYSTEM_RTC, "rtc", NULL },
1051 { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL },
1052 { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL },
1053 { 0xFF, NULL, NULL },
1054 };
1055
1056 static const PCISubClass inp_subclass[] = {
1057 { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL },
1058 { PCI_CLASS_INPUT_PEN, "pen", NULL },
1059 { PCI_CLASS_INPUT_MOUSE, "mouse", NULL },
1060 { PCI_CLASS_INPUT_SCANNER, "scanner", NULL },
1061 { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL },
1062 { 0xFF, NULL, NULL },
1063 };
1064
1065 static const PCISubClass dock_subclass[] = {
1066 { PCI_CLASS_DOCKING_GENERIC, "dock", NULL },
1067 { 0xFF, NULL, NULL },
1068 };
1069
1070 static const PCISubClass cpu_subclass[] = {
1071 { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL },
1072 { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL },
1073 { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL },
1074 { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL },
1075 { 0xFF, NULL, NULL },
1076 };
1077
1078 static const PCIIFace usb_iface[] = {
1079 { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" },
1080 { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", },
1081 { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" },
1082 { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" },
1083 { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" },
1084 { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" },
1085 { 0xFF, NULL },
1086 };
1087
1088 static const PCISubClass ser_subclass[] = {
1089 { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL },
1090 { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL },
1091 { PCI_CLASS_SERIAL_SSA, "ssa", NULL },
1092 { PCI_CLASS_SERIAL_USB, "usb", usb_iface },
1093 { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL },
1094 { PCI_CLASS_SERIAL_SMBUS, "smb", NULL },
1095 { PCI_CLASS_SERIAL_IB, "infiniband", NULL },
1096 { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL },
1097 { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL },
1098 { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL },
1099 { 0xFF, NULL, NULL },
1100 };
1101
1102 static const PCISubClass wrl_subclass[] = {
1103 { PCI_CLASS_WIRELESS_IRDA, "irda", NULL },
1104 { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL },
1105 { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL },
1106 { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL },
1107 { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL },
1108 { 0xFF, NULL, NULL },
1109 };
1110
1111 static const PCISubClass sat_subclass[] = {
1112 { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL },
1113 { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL },
1114 { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL },
1115 { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL },
1116 { 0xFF, NULL, NULL },
1117 };
1118
1119 static const PCISubClass crypt_subclass[] = {
1120 { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL },
1121 { PCI_CLASS_CRYPT_ENTERTAINMENT,
1122 "entertainment-encryption", NULL },
1123 { 0xFF, NULL, NULL },
1124 };
1125
1126 static const PCISubClass spc_subclass[] = {
1127 { PCI_CLASS_SP_DPIO, "dpio", NULL },
1128 { PCI_CLASS_SP_PERF, "counter", NULL },
1129 { PCI_CLASS_SP_SYNCH, "measurement", NULL },
1130 { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL },
1131 { 0xFF, NULL, NULL },
1132 };
1133
1134 static const PCIClass pci_classes[] = {
1135 { "legacy-device", undef_subclass },
1136 { "mass-storage", mass_subclass },
1137 { "network", net_subclass },
1138 { "display", displ_subclass, },
1139 { "multimedia-device", media_subclass },
1140 { "memory-controller", mem_subclass },
1141 { "unknown-bridge", bridg_subclass },
1142 { "communication-controller", comm_subclass},
1143 { "system-peripheral", sys_subclass },
1144 { "input-controller", inp_subclass },
1145 { "docking-station", dock_subclass },
1146 { "cpu", cpu_subclass },
1147 { "serial-bus", ser_subclass },
1148 { "wireless-controller", wrl_subclass },
1149 { "intelligent-io", NULL },
1150 { "satellite-device", sat_subclass },
1151 { "encryption", crypt_subclass },
1152 { "data-processing-controller", spc_subclass },
1153 };
1154
dt_name_from_class(uint8_t class,uint8_t subclass,uint8_t iface)1155 static const char *dt_name_from_class(uint8_t class, uint8_t subclass,
1156 uint8_t iface)
1157 {
1158 const PCIClass *pclass;
1159 const PCISubClass *psubclass;
1160 const PCIIFace *piface;
1161 const char *name;
1162
1163 if (class >= ARRAY_SIZE(pci_classes)) {
1164 return "pci";
1165 }
1166
1167 pclass = pci_classes + class;
1168 name = pclass->name;
1169
1170 if (pclass->subc == NULL) {
1171 return name;
1172 }
1173
1174 psubclass = pclass->subc;
1175 while ((psubclass->subclass & 0xff) != 0xff) {
1176 if ((psubclass->subclass & 0xff) == subclass) {
1177 name = psubclass->name;
1178 break;
1179 }
1180 psubclass++;
1181 }
1182
1183 piface = psubclass->iface;
1184 if (piface == NULL) {
1185 return name;
1186 }
1187 while ((piface->iface & 0xff) != 0xff) {
1188 if ((piface->iface & 0xff) == iface) {
1189 name = piface->name;
1190 break;
1191 }
1192 piface++;
1193 }
1194
1195 return name;
1196 }
1197
1198 /*
1199 * DRC helper functions
1200 */
1201
drc_id_from_devfn(SpaprPhbState * phb,uint8_t chassis,int32_t devfn)1202 static uint32_t drc_id_from_devfn(SpaprPhbState *phb,
1203 uint8_t chassis, int32_t devfn)
1204 {
1205 return (phb->index << 16) | (chassis << 8) | devfn;
1206 }
1207
drc_from_devfn(SpaprPhbState * phb,uint8_t chassis,int32_t devfn)1208 static SpaprDrc *drc_from_devfn(SpaprPhbState *phb,
1209 uint8_t chassis, int32_t devfn)
1210 {
1211 return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI,
1212 drc_id_from_devfn(phb, chassis, devfn));
1213 }
1214
chassis_from_bus(PCIBus * bus)1215 static uint8_t chassis_from_bus(PCIBus *bus)
1216 {
1217 if (pci_bus_is_root(bus)) {
1218 return 0;
1219 } else {
1220 PCIDevice *bridge = pci_bridge_get_device(bus);
1221
1222 return object_property_get_uint(OBJECT(bridge), "chassis_nr",
1223 &error_abort);
1224 }
1225 }
1226
drc_from_dev(SpaprPhbState * phb,PCIDevice * dev)1227 static SpaprDrc *drc_from_dev(SpaprPhbState *phb, PCIDevice *dev)
1228 {
1229 uint8_t chassis = chassis_from_bus(pci_get_bus(dev));
1230
1231 return drc_from_devfn(phb, chassis, dev->devfn);
1232 }
1233
add_drcs(SpaprPhbState * phb,PCIBus * bus)1234 static void add_drcs(SpaprPhbState *phb, PCIBus *bus)
1235 {
1236 Object *owner;
1237 int i;
1238 uint8_t chassis;
1239
1240 chassis = chassis_from_bus(bus);
1241
1242 if (pci_bus_is_root(bus)) {
1243 owner = OBJECT(phb);
1244 } else {
1245 owner = OBJECT(pci_bridge_get_device(bus));
1246 }
1247
1248 for (i = 0; i < PCI_SLOT_MAX * PCI_FUNC_MAX; i++) {
1249 spapr_dr_connector_new(owner, TYPE_SPAPR_DRC_PCI,
1250 drc_id_from_devfn(phb, chassis, i));
1251 }
1252 }
1253
remove_drcs(SpaprPhbState * phb,PCIBus * bus)1254 static void remove_drcs(SpaprPhbState *phb, PCIBus *bus)
1255 {
1256 int i;
1257 uint8_t chassis;
1258
1259 chassis = chassis_from_bus(bus);
1260
1261 for (i = PCI_SLOT_MAX * PCI_FUNC_MAX - 1; i >= 0; i--) {
1262 SpaprDrc *drc = drc_from_devfn(phb, chassis, i);
1263
1264 if (drc) {
1265 object_unparent(OBJECT(drc));
1266 }
1267 }
1268 }
1269
1270 typedef struct PciWalkFdt {
1271 void *fdt;
1272 int offset;
1273 SpaprPhbState *sphb;
1274 int err;
1275 } PciWalkFdt;
1276
1277 static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev,
1278 void *fdt, int parent_offset);
1279
spapr_dt_pci_device_cb(PCIBus * bus,PCIDevice * pdev,void * opaque)1280 static void spapr_dt_pci_device_cb(PCIBus *bus, PCIDevice *pdev,
1281 void *opaque)
1282 {
1283 PciWalkFdt *p = opaque;
1284 int err;
1285
1286 if (p->err) {
1287 /* Something's already broken, don't keep going */
1288 return;
1289 }
1290
1291 err = spapr_dt_pci_device(p->sphb, pdev, p->fdt, p->offset);
1292 if (err < 0) {
1293 p->err = err;
1294 }
1295 }
1296
1297 /* Augment PCI device node with bridge specific information */
spapr_dt_pci_bus(SpaprPhbState * sphb,PCIBus * bus,void * fdt,int offset)1298 static int spapr_dt_pci_bus(SpaprPhbState *sphb, PCIBus *bus,
1299 void *fdt, int offset)
1300 {
1301 Object *owner;
1302 PciWalkFdt cbinfo = {
1303 .fdt = fdt,
1304 .offset = offset,
1305 .sphb = sphb,
1306 .err = 0,
1307 };
1308 int ret;
1309
1310 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells",
1311 RESOURCE_CELLS_ADDRESS));
1312 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells",
1313 RESOURCE_CELLS_SIZE));
1314
1315 assert(bus);
1316 pci_for_each_device_under_bus_reverse(bus, spapr_dt_pci_device_cb, &cbinfo);
1317 if (cbinfo.err) {
1318 return cbinfo.err;
1319 }
1320
1321 if (pci_bus_is_root(bus)) {
1322 owner = OBJECT(sphb);
1323 } else {
1324 owner = OBJECT(pci_bridge_get_device(bus));
1325 }
1326
1327 ret = spapr_dt_drc(fdt, offset, owner,
1328 SPAPR_DR_CONNECTOR_TYPE_PCI);
1329 if (ret) {
1330 return ret;
1331 }
1332
1333 return offset;
1334 }
1335
spapr_pci_fw_dev_name(PCIDevice * dev)1336 char *spapr_pci_fw_dev_name(PCIDevice *dev)
1337 {
1338 const gchar *basename;
1339 int slot = PCI_SLOT(dev->devfn);
1340 int func = PCI_FUNC(dev->devfn);
1341 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
1342
1343 basename = dt_name_from_class((ccode >> 16) & 0xff, (ccode >> 8) & 0xff,
1344 ccode & 0xff);
1345
1346 if (func != 0) {
1347 return g_strdup_printf("%s@%x,%x", basename, slot, func);
1348 } else {
1349 return g_strdup_printf("%s@%x", basename, slot);
1350 }
1351 }
1352
1353 /* create OF node for pci device and required OF DT properties */
spapr_dt_pci_device(SpaprPhbState * sphb,PCIDevice * dev,void * fdt,int parent_offset)1354 static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev,
1355 void *fdt, int parent_offset)
1356 {
1357 int offset;
1358 g_autofree gchar *nodename = spapr_pci_fw_dev_name(dev);
1359 ResourceProps rp;
1360 SpaprDrc *drc = drc_from_dev(sphb, dev);
1361 uint32_t vendor_id = pci_default_read_config(dev, PCI_VENDOR_ID, 2);
1362 uint32_t device_id = pci_default_read_config(dev, PCI_DEVICE_ID, 2);
1363 uint32_t revision_id = pci_default_read_config(dev, PCI_REVISION_ID, 1);
1364 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3);
1365 uint32_t irq_pin = pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1);
1366 uint32_t subsystem_id = pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2);
1367 uint32_t subsystem_vendor_id =
1368 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2);
1369 uint32_t cache_line_size =
1370 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1);
1371 uint32_t pci_status = pci_default_read_config(dev, PCI_STATUS, 2);
1372 gchar *loc_code;
1373
1374 _FDT(offset = fdt_add_subnode(fdt, parent_offset, nodename));
1375
1376 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */
1377 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", vendor_id));
1378 _FDT(fdt_setprop_cell(fdt, offset, "device-id", device_id));
1379 _FDT(fdt_setprop_cell(fdt, offset, "revision-id", revision_id));
1380
1381 _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode));
1382 if (irq_pin) {
1383 _FDT(fdt_setprop_cell(fdt, offset, "interrupts", irq_pin));
1384 }
1385
1386 if (subsystem_id) {
1387 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", subsystem_id));
1388 }
1389
1390 if (subsystem_vendor_id) {
1391 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id",
1392 subsystem_vendor_id));
1393 }
1394
1395 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", cache_line_size));
1396
1397
1398 /* the following fdt cells are masked off the pci status register */
1399 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed",
1400 PCI_STATUS_DEVSEL_MASK & pci_status));
1401
1402 if (pci_status & PCI_STATUS_FAST_BACK) {
1403 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0));
1404 }
1405 if (pci_status & PCI_STATUS_66MHZ) {
1406 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0));
1407 }
1408 if (pci_status & PCI_STATUS_UDF) {
1409 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0));
1410 }
1411
1412 loc_code = spapr_phb_get_loc_code(sphb, dev);
1413 _FDT(fdt_setprop_string(fdt, offset, "ibm,loc-code", loc_code));
1414 g_free(loc_code);
1415
1416 if (drc) {
1417 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index",
1418 spapr_drc_index(drc)));
1419 }
1420
1421 if (msi_present(dev)) {
1422 uint32_t max_msi = msi_nr_vectors_allocated(dev);
1423 if (max_msi) {
1424 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi));
1425 }
1426 }
1427 if (msix_present(dev)) {
1428 uint32_t max_msix = dev->msix_entries_nr;
1429 if (max_msix) {
1430 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix));
1431 }
1432 }
1433
1434 populate_resource_props(dev, &rp);
1435 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len));
1436
1437 if (sphb->pcie_ecs && pci_is_express(dev)) {
1438 _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1));
1439 }
1440
1441 if (!IS_PCI_BRIDGE(dev)) {
1442 /* Properties only for non-bridges */
1443 uint32_t min_grant = pci_default_read_config(dev, PCI_MIN_GNT, 1);
1444 uint32_t max_latency = pci_default_read_config(dev, PCI_MAX_LAT, 1);
1445 _FDT(fdt_setprop_cell(fdt, offset, "min-grant", min_grant));
1446 _FDT(fdt_setprop_cell(fdt, offset, "max-latency", max_latency));
1447 return offset;
1448 } else {
1449 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
1450
1451 return spapr_dt_pci_bus(sphb, sec_bus, fdt, offset);
1452 }
1453 }
1454
1455 /* Callback to be called during DRC release. */
spapr_phb_remove_pci_device_cb(DeviceState * dev)1456 void spapr_phb_remove_pci_device_cb(DeviceState *dev)
1457 {
1458 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
1459
1460 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
1461 object_unparent(OBJECT(dev));
1462 }
1463
spapr_pci_dt_populate(SpaprDrc * drc,SpaprMachineState * spapr,void * fdt,int * fdt_start_offset,Error ** errp)1464 int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
1465 void *fdt, int *fdt_start_offset, Error **errp)
1466 {
1467 HotplugHandler *plug_handler = qdev_get_hotplug_handler(drc->dev);
1468 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(plug_handler);
1469 PCIDevice *pdev = PCI_DEVICE(drc->dev);
1470
1471 *fdt_start_offset = spapr_dt_pci_device(sphb, pdev, fdt, 0);
1472 return 0;
1473 }
1474
spapr_pci_bridge_plug(SpaprPhbState * phb,PCIBridge * bridge)1475 static void spapr_pci_bridge_plug(SpaprPhbState *phb,
1476 PCIBridge *bridge)
1477 {
1478 PCIBus *bus = pci_bridge_get_sec_bus(bridge);
1479
1480 add_drcs(phb, bus);
1481 }
1482
1483 /* Returns non-zero if the value of "chassis_nr" is already in use */
check_chassis_nr(Object * obj,void * opaque)1484 static int check_chassis_nr(Object *obj, void *opaque)
1485 {
1486 int new_chassis_nr =
1487 object_property_get_uint(opaque, "chassis_nr", &error_abort);
1488 int chassis_nr =
1489 object_property_get_uint(obj, "chassis_nr", NULL);
1490
1491 if (!object_dynamic_cast(obj, TYPE_PCI_BRIDGE)) {
1492 return 0;
1493 }
1494
1495 /* Skip unsupported bridge types */
1496 if (!chassis_nr) {
1497 return 0;
1498 }
1499
1500 /* Skip self */
1501 if (obj == opaque) {
1502 return 0;
1503 }
1504
1505 return chassis_nr == new_chassis_nr;
1506 }
1507
bridge_has_valid_chassis_nr(Object * bridge,Error ** errp)1508 static bool bridge_has_valid_chassis_nr(Object *bridge, Error **errp)
1509 {
1510 int chassis_nr =
1511 object_property_get_uint(bridge, "chassis_nr", NULL);
1512
1513 /*
1514 * slotid_cap_init() already ensures that "chassis_nr" isn't null for
1515 * standard PCI bridges, so this really tells if "chassis_nr" is present
1516 * or not.
1517 */
1518 if (!chassis_nr) {
1519 error_setg(errp, "PCI Bridge lacks a \"chassis_nr\" property");
1520 error_append_hint(errp, "Try -device pci-bridge instead.\n");
1521 return false;
1522 }
1523
1524 /* We want unique values for "chassis_nr" */
1525 if (object_child_foreach_recursive(object_get_root(), check_chassis_nr,
1526 bridge)) {
1527 error_setg(errp, "Bridge chassis %d already in use", chassis_nr);
1528 return false;
1529 }
1530
1531 return true;
1532 }
1533
spapr_pci_pre_plug(HotplugHandler * plug_handler,DeviceState * plugged_dev,Error ** errp)1534 static void spapr_pci_pre_plug(HotplugHandler *plug_handler,
1535 DeviceState *plugged_dev, Error **errp)
1536 {
1537 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1538 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1539 SpaprDrc *drc = drc_from_dev(phb, pdev);
1540 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)));
1541 uint32_t slotnr = PCI_SLOT(pdev->devfn);
1542
1543 if (IS_PCI_BRIDGE(plugged_dev)) {
1544 if (!bridge_has_valid_chassis_nr(OBJECT(plugged_dev), errp)) {
1545 return;
1546 }
1547 }
1548
1549 /* Following the QEMU convention used for PCIe multifunction
1550 * hotplug, we do not allow functions to be hotplugged to a
1551 * slot that already has function 0 present
1552 */
1553 if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] &&
1554 PCI_FUNC(pdev->devfn) != 0) {
1555 error_setg(errp, "PCI: slot %d function 0 already occupied by %s,"
1556 " additional functions can no longer be exposed to guest.",
1557 slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name);
1558 }
1559
1560 if (drc && drc->dev) {
1561 error_setg(errp, "PCI: slot %d already occupied by %s", slotnr,
1562 pci_get_function_0(PCI_DEVICE(drc->dev))->name);
1563 return;
1564 }
1565 }
1566
spapr_pci_plug(HotplugHandler * plug_handler,DeviceState * plugged_dev,Error ** errp)1567 static void spapr_pci_plug(HotplugHandler *plug_handler,
1568 DeviceState *plugged_dev, Error **errp)
1569 {
1570 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1571 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1572 SpaprDrc *drc = drc_from_dev(phb, pdev);
1573 uint32_t slotnr = PCI_SLOT(pdev->devfn);
1574
1575 g_assert(drc);
1576
1577 if (IS_PCI_BRIDGE(plugged_dev)) {
1578 spapr_pci_bridge_plug(phb, PCI_BRIDGE(plugged_dev));
1579 }
1580
1581 /* spapr_pci_pre_plug() already checked the DRC is attachable */
1582 spapr_drc_attach(drc, DEVICE(pdev));
1583
1584 /* If this is function 0, signal hotplug for all the device functions.
1585 * Otherwise defer sending the hotplug event.
1586 */
1587 if (!spapr_drc_hotplugged(plugged_dev)) {
1588 spapr_drc_reset(drc);
1589 } else if (PCI_FUNC(pdev->devfn) == 0) {
1590 int i;
1591 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev));
1592
1593 for (i = 0; i < 8; i++) {
1594 SpaprDrc *func_drc;
1595 SpaprDrcClass *func_drck;
1596 SpaprDREntitySense state;
1597
1598 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i));
1599 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1600 state = func_drck->dr_entity_sense(func_drc);
1601
1602 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1603 spapr_hotplug_req_add_by_index(func_drc);
1604 }
1605 }
1606 }
1607 }
1608
spapr_pci_bridge_unplug(SpaprPhbState * phb,PCIBridge * bridge)1609 static void spapr_pci_bridge_unplug(SpaprPhbState *phb,
1610 PCIBridge *bridge)
1611 {
1612 PCIBus *bus = pci_bridge_get_sec_bus(bridge);
1613
1614 remove_drcs(phb, bus);
1615 }
1616
spapr_pci_unplug(HotplugHandler * plug_handler,DeviceState * plugged_dev,Error ** errp)1617 static void spapr_pci_unplug(HotplugHandler *plug_handler,
1618 DeviceState *plugged_dev, Error **errp)
1619 {
1620 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1621
1622 /* some version guests do not wait for completion of a device
1623 * cleanup (generally done asynchronously by the kernel) before
1624 * signaling to QEMU that the device is safe, but instead sleep
1625 * for some 'safe' period of time. unfortunately on a busy host
1626 * this sleep isn't guaranteed to be long enough, resulting in
1627 * bad things like IRQ lines being left asserted during final
1628 * device removal. to deal with this we call reset just prior
1629 * to finalizing the device, which will put the device back into
1630 * an 'idle' state, as the device cleanup code expects.
1631 */
1632 pci_device_reset(PCI_DEVICE(plugged_dev));
1633
1634 if (IS_PCI_BRIDGE(plugged_dev)) {
1635 spapr_pci_bridge_unplug(phb, PCI_BRIDGE(plugged_dev));
1636 return;
1637 }
1638
1639 qdev_unrealize(plugged_dev);
1640 }
1641
spapr_pci_unplug_request(HotplugHandler * plug_handler,DeviceState * plugged_dev,Error ** errp)1642 static void spapr_pci_unplug_request(HotplugHandler *plug_handler,
1643 DeviceState *plugged_dev, Error **errp)
1644 {
1645 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler));
1646 PCIDevice *pdev = PCI_DEVICE(plugged_dev);
1647 SpaprDrc *drc = drc_from_dev(phb, pdev);
1648
1649 g_assert(drc);
1650 g_assert(drc->dev == plugged_dev);
1651
1652 if (!spapr_drc_unplug_requested(drc)) {
1653 uint32_t slotnr = PCI_SLOT(pdev->devfn);
1654 SpaprDrc *func_drc;
1655 SpaprDrcClass *func_drck;
1656 SpaprDREntitySense state;
1657 int i;
1658 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev));
1659
1660 if (IS_PCI_BRIDGE(plugged_dev)) {
1661 error_setg(errp, "PCI: Hot unplug of PCI bridges not supported");
1662 return;
1663 }
1664 if (object_property_get_uint(OBJECT(pdev), "nvlink2-tgt", NULL)) {
1665 error_setg(errp, "PCI: Cannot unplug NVLink2 devices");
1666 return;
1667 }
1668
1669 /* ensure any other present functions are pending unplug */
1670 if (PCI_FUNC(pdev->devfn) == 0) {
1671 for (i = 1; i < 8; i++) {
1672 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i));
1673 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1674 state = func_drck->dr_entity_sense(func_drc);
1675 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT
1676 && !spapr_drc_unplug_requested(func_drc)) {
1677 /*
1678 * Attempting to remove function 0 of a multifunction
1679 * device will will cascade into removing all child
1680 * functions, even if their unplug weren't requested
1681 * beforehand.
1682 */
1683 spapr_drc_unplug_request(func_drc);
1684 }
1685 }
1686 }
1687
1688 spapr_drc_unplug_request(drc);
1689
1690 /* if this isn't func 0, defer unplug event. otherwise signal removal
1691 * for all present functions
1692 */
1693 if (PCI_FUNC(pdev->devfn) == 0) {
1694 for (i = 7; i >= 0; i--) {
1695 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i));
1696 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc);
1697 state = func_drck->dr_entity_sense(func_drc);
1698 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) {
1699 spapr_hotplug_req_remove_by_index(func_drc);
1700 }
1701 }
1702 }
1703 } else {
1704 error_setg(errp,
1705 "PCI device unplug already in progress for device %s",
1706 drc->dev->id);
1707 }
1708 }
1709
spapr_phb_finalizefn(Object * obj)1710 static void spapr_phb_finalizefn(Object *obj)
1711 {
1712 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(obj);
1713
1714 g_free(sphb->dtbusname);
1715 sphb->dtbusname = NULL;
1716 }
1717
spapr_phb_unrealize(DeviceState * dev)1718 static void spapr_phb_unrealize(DeviceState *dev)
1719 {
1720 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1721 SysBusDevice *s = SYS_BUS_DEVICE(dev);
1722 PCIHostState *phb = PCI_HOST_BRIDGE(s);
1723 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(phb);
1724 SpaprTceTable *tcet;
1725 int i;
1726 const unsigned windows_supported = spapr_phb_windows_supported(sphb);
1727
1728 if (sphb->msi) {
1729 g_hash_table_unref(sphb->msi);
1730 sphb->msi = NULL;
1731 }
1732
1733 /*
1734 * Remove IO/MMIO subregions and aliases, rest should get cleaned
1735 * via PHB's unrealize->object_finalize
1736 */
1737 for (i = windows_supported - 1; i >= 0; i--) {
1738 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]);
1739 if (tcet) {
1740 memory_region_del_subregion(&sphb->iommu_root,
1741 spapr_tce_get_iommu(tcet));
1742 }
1743 }
1744
1745 remove_drcs(sphb, phb->bus);
1746
1747 for (i = PCI_NUM_PINS - 1; i >= 0; i--) {
1748 if (sphb->lsi_table[i].irq) {
1749 spapr_irq_free(spapr, sphb->lsi_table[i].irq, 1);
1750 sphb->lsi_table[i].irq = 0;
1751 }
1752 }
1753
1754 QLIST_REMOVE(sphb, list);
1755
1756 memory_region_del_subregion(&sphb->iommu_root, &sphb->msiwindow);
1757
1758 /*
1759 * An attached PCI device may have memory listeners, eg. VFIO PCI. We have
1760 * unmapped all sections. Remove the listeners now, before destroying the
1761 * address space.
1762 */
1763 address_space_remove_listeners(&sphb->iommu_as);
1764 address_space_destroy(&sphb->iommu_as);
1765
1766 qbus_set_hotplug_handler(BUS(phb->bus), NULL);
1767 pci_unregister_root_bus(phb->bus);
1768
1769 memory_region_del_subregion(get_system_memory(), &sphb->iowindow);
1770 if (sphb->mem64_win_pciaddr != (hwaddr)-1) {
1771 memory_region_del_subregion(get_system_memory(), &sphb->mem64window);
1772 }
1773 memory_region_del_subregion(get_system_memory(), &sphb->mem32window);
1774 }
1775
spapr_phb_destroy_msi(gpointer opaque)1776 static void spapr_phb_destroy_msi(gpointer opaque)
1777 {
1778 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1779 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
1780 SpaprPciMsi *msi = opaque;
1781
1782 if (!smc->legacy_irq_allocation) {
1783 spapr_irq_msi_free(spapr, msi->first_irq, msi->num);
1784 }
1785 spapr_irq_free(spapr, msi->first_irq, msi->num);
1786 g_free(msi);
1787 }
1788
spapr_phb_realize(DeviceState * dev,Error ** errp)1789 static void spapr_phb_realize(DeviceState *dev, Error **errp)
1790 {
1791 ERRP_GUARD();
1792 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
1793 * tries to add a sPAPR PHB to a non-pseries machine.
1794 */
1795 SpaprMachineState *spapr =
1796 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(),
1797 TYPE_SPAPR_MACHINE);
1798 SpaprMachineClass *smc = spapr ? SPAPR_MACHINE_GET_CLASS(spapr) : NULL;
1799 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1800 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(sbd);
1801 PCIHostState *phb = PCI_HOST_BRIDGE(sbd);
1802 MachineState *ms = MACHINE(spapr);
1803 char *namebuf;
1804 int i;
1805 PCIBus *bus;
1806 uint64_t msi_window_size = 4096;
1807 SpaprTceTable *tcet;
1808 const unsigned windows_supported = spapr_phb_windows_supported(sphb);
1809
1810 if (!spapr) {
1811 error_setg(errp, TYPE_SPAPR_PCI_HOST_BRIDGE " needs a pseries machine");
1812 return;
1813 }
1814
1815 assert(sphb->index != (uint32_t)-1); /* checked in spapr_phb_pre_plug() */
1816
1817 if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) {
1818 error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx
1819 " (max 2 GiB)", sphb->mem_win_size);
1820 return;
1821 }
1822
1823 /* 64-bit window defaults to identity mapping */
1824 sphb->mem64_win_pciaddr = sphb->mem64_win_addr;
1825
1826 if (spapr_pci_find_phb(spapr, sphb->buid)) {
1827 SpaprPhbState *s;
1828
1829 error_setg(errp, "PCI host bridges must have unique indexes");
1830 error_append_hint(errp, "The following indexes are already in use:");
1831 QLIST_FOREACH(s, &spapr->phbs, list) {
1832 error_append_hint(errp, " %d", s->index);
1833 }
1834 error_append_hint(errp, "\nTry another value for the index property\n");
1835 return;
1836 }
1837
1838 if (sphb->numa_node != -1 &&
1839 (sphb->numa_node >= MAX_NODES ||
1840 !ms->numa_state->nodes[sphb->numa_node].present)) {
1841 error_setg(errp, "Invalid NUMA node ID for PCI host bridge");
1842 return;
1843 }
1844
1845 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid);
1846
1847 /* Initialize memory regions */
1848 namebuf = g_strdup_printf("%s.mmio", sphb->dtbusname);
1849 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX);
1850 g_free(namebuf);
1851
1852 namebuf = g_strdup_printf("%s.mmio32-alias", sphb->dtbusname);
1853 memory_region_init_alias(&sphb->mem32window, OBJECT(sphb),
1854 namebuf, &sphb->memspace,
1855 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size);
1856 g_free(namebuf);
1857 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr,
1858 &sphb->mem32window);
1859
1860 if (sphb->mem64_win_size != 0) {
1861 namebuf = g_strdup_printf("%s.mmio64-alias", sphb->dtbusname);
1862 memory_region_init_alias(&sphb->mem64window, OBJECT(sphb),
1863 namebuf, &sphb->memspace,
1864 sphb->mem64_win_pciaddr, sphb->mem64_win_size);
1865 g_free(namebuf);
1866
1867 memory_region_add_subregion(get_system_memory(),
1868 sphb->mem64_win_addr,
1869 &sphb->mem64window);
1870 }
1871
1872 /* Initialize IO regions */
1873 namebuf = g_strdup_printf("%s.io", sphb->dtbusname);
1874 memory_region_init(&sphb->iospace, OBJECT(sphb),
1875 namebuf, SPAPR_PCI_IO_WIN_SIZE);
1876 g_free(namebuf);
1877
1878 namebuf = g_strdup_printf("%s.io-alias", sphb->dtbusname);
1879 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf,
1880 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE);
1881 g_free(namebuf);
1882 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr,
1883 &sphb->iowindow);
1884
1885 bus = pci_register_root_bus(dev, NULL,
1886 pci_spapr_set_irq, pci_swizzle_map_irq_fn, sphb,
1887 &sphb->memspace, &sphb->iospace,
1888 PCI_DEVFN(0, 0), PCI_NUM_PINS,
1889 TYPE_PCI_BUS);
1890
1891 /*
1892 * Despite resembling a vanilla PCI bus in most ways, the PAPR
1893 * para-virtualized PCI bus *does* permit PCI-E extended config
1894 * space access
1895 */
1896 if (sphb->pcie_ecs) {
1897 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
1898 }
1899 phb->bus = bus;
1900 qbus_set_hotplug_handler(BUS(phb->bus), OBJECT(sphb));
1901
1902 /*
1903 * Initialize PHB address space.
1904 * By default there will be at least one subregion for default
1905 * 32bit DMA window.
1906 * Later the guest might want to create another DMA window
1907 * which will become another memory subregion.
1908 */
1909 namebuf = g_strdup_printf("%s.iommu-root", sphb->dtbusname);
1910 memory_region_init(&sphb->iommu_root, OBJECT(sphb),
1911 namebuf, UINT64_MAX);
1912 g_free(namebuf);
1913 address_space_init(&sphb->iommu_as, &sphb->iommu_root,
1914 sphb->dtbusname);
1915
1916 /*
1917 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors,
1918 * we need to allocate some memory to catch those writes coming
1919 * from msi_notify()/msix_notify().
1920 * As MSIMessage:addr is going to be the same and MSIMessage:data
1921 * is going to be a VIRQ number, 4 bytes of the MSI MR will only
1922 * be used.
1923 *
1924 * For KVM we want to ensure that this memory is a full page so that
1925 * our memory slot is of page size granularity.
1926 */
1927 if (kvm_enabled()) {
1928 msi_window_size = qemu_real_host_page_size();
1929 }
1930
1931 memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr,
1932 "msi", msi_window_size);
1933 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW,
1934 &sphb->msiwindow);
1935
1936 pci_setup_iommu(bus, &spapr_iommu_ops, sphb);
1937
1938 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq);
1939
1940 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list);
1941
1942 /* Initialize the LSI table */
1943 for (i = 0; i < PCI_NUM_PINS; i++) {
1944 int irq = SPAPR_IRQ_PCI_LSI + sphb->index * PCI_NUM_PINS + i;
1945
1946 if (smc->legacy_irq_allocation) {
1947 irq = spapr_irq_findone(spapr, errp);
1948 if (irq < 0) {
1949 error_prepend(errp, "can't allocate LSIs: ");
1950 /*
1951 * Older machines will never support PHB hotplug, ie, this is an
1952 * init only path and QEMU will terminate. No need to rollback.
1953 */
1954 return;
1955 }
1956 }
1957
1958 if (spapr_irq_claim(spapr, irq, true, errp) < 0) {
1959 error_prepend(errp, "can't allocate LSIs: ");
1960 goto unrealize;
1961 }
1962
1963 sphb->lsi_table[i].irq = irq;
1964 }
1965
1966 /* allocate connectors for child PCI devices */
1967 add_drcs(sphb, phb->bus);
1968
1969 /* DMA setup */
1970 for (i = 0; i < windows_supported; ++i) {
1971 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]);
1972 if (!tcet) {
1973 error_setg(errp, "Creating window#%d failed for %s",
1974 i, sphb->dtbusname);
1975 goto unrealize;
1976 }
1977 memory_region_add_subregion(&sphb->iommu_root, 0,
1978 spapr_tce_get_iommu(tcet));
1979 }
1980
1981 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free,
1982 spapr_phb_destroy_msi);
1983 return;
1984
1985 unrealize:
1986 spapr_phb_unrealize(dev);
1987 }
1988
spapr_phb_children_reset(Object * child,void * opaque)1989 static int spapr_phb_children_reset(Object *child, void *opaque)
1990 {
1991 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE);
1992
1993 if (dev) {
1994 device_cold_reset(dev);
1995 }
1996
1997 return 0;
1998 }
1999
spapr_phb_dma_reset(SpaprPhbState * sphb)2000 void spapr_phb_dma_reset(SpaprPhbState *sphb)
2001 {
2002 int i;
2003 SpaprTceTable *tcet;
2004
2005 for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) {
2006 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]);
2007
2008 if (tcet && tcet->nb_table) {
2009 spapr_tce_table_disable(tcet);
2010 }
2011 }
2012
2013 /* Register default 32bit DMA window */
2014 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]);
2015 spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr,
2016 sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT);
2017 tcet->def_win = true;
2018 }
2019
spapr_phb_reset(DeviceState * qdev)2020 static void spapr_phb_reset(DeviceState *qdev)
2021 {
2022 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev);
2023
2024 spapr_phb_dma_reset(sphb);
2025
2026 /* Reset the IOMMU state */
2027 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL);
2028
2029 if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) {
2030 spapr_phb_vfio_reset(qdev);
2031 }
2032
2033 g_hash_table_remove_all(sphb->msi);
2034 }
2035
2036 static Property spapr_phb_properties[] = {
2037 DEFINE_PROP_UINT32("index", SpaprPhbState, index, -1),
2038 DEFINE_PROP_UINT64("mem_win_size", SpaprPhbState, mem_win_size,
2039 SPAPR_PCI_MEM32_WIN_SIZE),
2040 DEFINE_PROP_UINT64("mem64_win_size", SpaprPhbState, mem64_win_size,
2041 SPAPR_PCI_MEM64_WIN_SIZE),
2042 DEFINE_PROP_UINT64("io_win_size", SpaprPhbState, io_win_size,
2043 SPAPR_PCI_IO_WIN_SIZE),
2044 /* Default DMA window is 0..1GB */
2045 DEFINE_PROP_UINT64("dma_win_addr", SpaprPhbState, dma_win_addr, 0),
2046 DEFINE_PROP_UINT64("dma_win_size", SpaprPhbState, dma_win_size, 0x40000000),
2047 DEFINE_PROP_UINT64("dma64_win_addr", SpaprPhbState, dma64_win_addr,
2048 0x800000000000000ULL),
2049 DEFINE_PROP_BOOL("ddw", SpaprPhbState, ddw_enabled, true),
2050 DEFINE_PROP_UINT64("pgsz", SpaprPhbState, page_size_mask,
2051 (1ULL << 12) | (1ULL << 16)
2052 | (1ULL << 21) | (1ULL << 24)),
2053 DEFINE_PROP_UINT32("numa_node", SpaprPhbState, numa_node, -1),
2054 DEFINE_PROP_BOOL("pcie-extended-configuration-space", SpaprPhbState,
2055 pcie_ecs, true),
2056 DEFINE_PROP_BOOL("pre-5.1-associativity", SpaprPhbState,
2057 pre_5_1_assoc, false),
2058 DEFINE_PROP_END_OF_LIST(),
2059 };
2060
2061 static const VMStateDescription vmstate_spapr_pci_lsi = {
2062 .name = "spapr_pci/lsi",
2063 .version_id = 1,
2064 .minimum_version_id = 1,
2065 .fields = (const VMStateField[]) {
2066 VMSTATE_UINT32_EQUAL(irq, SpaprPciLsi, NULL),
2067
2068 VMSTATE_END_OF_LIST()
2069 },
2070 };
2071
2072 static const VMStateDescription vmstate_spapr_pci_msi = {
2073 .name = "spapr_pci/msi",
2074 .version_id = 1,
2075 .minimum_version_id = 1,
2076 .fields = (const VMStateField []) {
2077 VMSTATE_UINT32(key, SpaprPciMsiMig),
2078 VMSTATE_UINT32(value.first_irq, SpaprPciMsiMig),
2079 VMSTATE_UINT32(value.num, SpaprPciMsiMig),
2080 VMSTATE_END_OF_LIST()
2081 },
2082 };
2083
spapr_pci_pre_save(void * opaque)2084 static int spapr_pci_pre_save(void *opaque)
2085 {
2086 SpaprPhbState *sphb = opaque;
2087 GHashTableIter iter;
2088 gpointer key, value;
2089 int i;
2090
2091 g_free(sphb->msi_devs);
2092 sphb->msi_devs = NULL;
2093 sphb->msi_devs_num = g_hash_table_size(sphb->msi);
2094 if (!sphb->msi_devs_num) {
2095 return 0;
2096 }
2097 sphb->msi_devs = g_new(SpaprPciMsiMig, sphb->msi_devs_num);
2098
2099 g_hash_table_iter_init(&iter, sphb->msi);
2100 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) {
2101 sphb->msi_devs[i].key = *(uint32_t *) key;
2102 sphb->msi_devs[i].value = *(SpaprPciMsi *) value;
2103 }
2104
2105 return 0;
2106 }
2107
spapr_pci_post_save(void * opaque)2108 static int spapr_pci_post_save(void *opaque)
2109 {
2110 SpaprPhbState *sphb = opaque;
2111
2112 g_free(sphb->msi_devs);
2113 sphb->msi_devs = NULL;
2114 sphb->msi_devs_num = 0;
2115 return 0;
2116 }
2117
spapr_pci_post_load(void * opaque,int version_id)2118 static int spapr_pci_post_load(void *opaque, int version_id)
2119 {
2120 SpaprPhbState *sphb = opaque;
2121 gpointer key, value;
2122 int i;
2123
2124 for (i = 0; i < sphb->msi_devs_num; ++i) {
2125 key = g_memdup2(&sphb->msi_devs[i].key, sizeof(sphb->msi_devs[i].key));
2126 value = g_memdup2(&sphb->msi_devs[i].value,
2127 sizeof(sphb->msi_devs[i].value));
2128 g_hash_table_insert(sphb->msi, key, value);
2129 }
2130 g_free(sphb->msi_devs);
2131 sphb->msi_devs = NULL;
2132 sphb->msi_devs_num = 0;
2133
2134 return 0;
2135 }
2136
2137 static const VMStateDescription vmstate_spapr_pci = {
2138 .name = "spapr_pci",
2139 .version_id = 2,
2140 .minimum_version_id = 2,
2141 .pre_save = spapr_pci_pre_save,
2142 .post_save = spapr_pci_post_save,
2143 .post_load = spapr_pci_post_load,
2144 .fields = (const VMStateField[]) {
2145 VMSTATE_UINT64_EQUAL(buid, SpaprPhbState, NULL),
2146 VMSTATE_STRUCT_ARRAY(lsi_table, SpaprPhbState, PCI_NUM_PINS, 0,
2147 vmstate_spapr_pci_lsi, SpaprPciLsi),
2148 VMSTATE_INT32(msi_devs_num, SpaprPhbState),
2149 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, SpaprPhbState, msi_devs_num, 0,
2150 vmstate_spapr_pci_msi, SpaprPciMsiMig),
2151 VMSTATE_END_OF_LIST()
2152 },
2153 };
2154
spapr_phb_root_bus_path(PCIHostState * host_bridge,PCIBus * rootbus)2155 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge,
2156 PCIBus *rootbus)
2157 {
2158 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge);
2159
2160 return sphb->dtbusname;
2161 }
2162
spapr_phb_class_init(ObjectClass * klass,void * data)2163 static void spapr_phb_class_init(ObjectClass *klass, void *data)
2164 {
2165 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
2166 DeviceClass *dc = DEVICE_CLASS(klass);
2167 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass);
2168
2169 hc->root_bus_path = spapr_phb_root_bus_path;
2170 dc->realize = spapr_phb_realize;
2171 dc->unrealize = spapr_phb_unrealize;
2172 device_class_set_props(dc, spapr_phb_properties);
2173 device_class_set_legacy_reset(dc, spapr_phb_reset);
2174 dc->vmsd = &vmstate_spapr_pci;
2175 /* Supported by TYPE_SPAPR_MACHINE */
2176 dc->user_creatable = true;
2177 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
2178 hp->pre_plug = spapr_pci_pre_plug;
2179 hp->plug = spapr_pci_plug;
2180 hp->unplug = spapr_pci_unplug;
2181 hp->unplug_request = spapr_pci_unplug_request;
2182 }
2183
2184 static const TypeInfo spapr_phb_info = {
2185 .name = TYPE_SPAPR_PCI_HOST_BRIDGE,
2186 .parent = TYPE_PCI_HOST_BRIDGE,
2187 .instance_size = sizeof(SpaprPhbState),
2188 .instance_finalize = spapr_phb_finalizefn,
2189 .class_init = spapr_phb_class_init,
2190 .interfaces = (InterfaceInfo[]) {
2191 { TYPE_HOTPLUG_HANDLER },
2192 { }
2193 }
2194 };
2195
spapr_phb_pci_enumerate_bridge(PCIBus * bus,PCIDevice * pdev,void * opaque)2196 static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev,
2197 void *opaque)
2198 {
2199 unsigned int *bus_no = opaque;
2200 PCIBus *sec_bus = NULL;
2201
2202 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) !=
2203 PCI_HEADER_TYPE_BRIDGE)) {
2204 return;
2205 }
2206
2207 (*bus_no)++;
2208 pci_default_write_config(pdev, PCI_PRIMARY_BUS, pci_dev_bus_num(pdev), 1);
2209 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1);
2210 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2211
2212 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
2213 if (!sec_bus) {
2214 return;
2215 }
2216
2217 pci_for_each_device_under_bus(sec_bus, spapr_phb_pci_enumerate_bridge,
2218 bus_no);
2219 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1);
2220 }
2221
spapr_phb_pci_enumerate(SpaprPhbState * phb)2222 static void spapr_phb_pci_enumerate(SpaprPhbState *phb)
2223 {
2224 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus;
2225 unsigned int bus_no = 0;
2226
2227 pci_for_each_device_under_bus(bus, spapr_phb_pci_enumerate_bridge,
2228 &bus_no);
2229
2230 }
2231
spapr_dt_phb(SpaprMachineState * spapr,SpaprPhbState * phb,uint32_t intc_phandle,void * fdt,int * node_offset)2232 int spapr_dt_phb(SpaprMachineState *spapr, SpaprPhbState *phb,
2233 uint32_t intc_phandle, void *fdt, int *node_offset)
2234 {
2235 int bus_off, i, j, ret;
2236 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) };
2237 struct {
2238 uint32_t hi;
2239 uint64_t child;
2240 uint64_t parent;
2241 uint64_t size;
2242 } QEMU_PACKED ranges[] = {
2243 {
2244 cpu_to_be32(b_ss(1)), cpu_to_be64(0),
2245 cpu_to_be64(phb->io_win_addr),
2246 cpu_to_be64(memory_region_size(&phb->iospace)),
2247 },
2248 {
2249 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET),
2250 cpu_to_be64(phb->mem_win_addr),
2251 cpu_to_be64(phb->mem_win_size),
2252 },
2253 {
2254 cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr),
2255 cpu_to_be64(phb->mem64_win_addr),
2256 cpu_to_be64(phb->mem64_win_size),
2257 },
2258 };
2259 const unsigned sizeof_ranges =
2260 (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]);
2261 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 };
2262 uint32_t interrupt_map_mask[] = {
2263 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)};
2264 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7];
2265 uint32_t ddw_applicable[] = {
2266 cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW),
2267 cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW),
2268 cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW)
2269 };
2270 uint32_t ddw_extensions[] = {
2271 cpu_to_be32(2),
2272 cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW),
2273 cpu_to_be32(1), /* 1: ibm,query-pe-dma-window 6 outputs, PAPR 2.8 */
2274 };
2275 SpaprTceTable *tcet;
2276 SpaprDrc *drc;
2277
2278 /* Start populating the FDT */
2279 _FDT(bus_off = fdt_add_subnode(fdt, 0, phb->dtbusname));
2280 if (node_offset) {
2281 *node_offset = bus_off;
2282 }
2283
2284 /* Write PHB properties */
2285 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci"));
2286 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB"));
2287 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1));
2288 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0));
2289 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range)));
2290 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges));
2291 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
2292 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
2293 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi",
2294 spapr_irq_nr_msis(spapr)));
2295
2296 /* Dynamic DMA window */
2297 if (phb->ddw_enabled) {
2298 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable,
2299 sizeof(ddw_applicable)));
2300 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions",
2301 &ddw_extensions, sizeof(ddw_extensions)));
2302 }
2303
2304 /* Advertise NUMA via ibm,associativity */
2305 if (phb->numa_node != -1) {
2306 spapr_numa_write_associativity_dt(spapr, fdt, bus_off, phb->numa_node);
2307 }
2308
2309 /* Build the interrupt-map, this must matches what is done
2310 * in pci_swizzle_map_irq_fn
2311 */
2312 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask",
2313 &interrupt_map_mask, sizeof(interrupt_map_mask)));
2314 for (i = 0; i < PCI_SLOT_MAX; i++) {
2315 for (j = 0; j < PCI_NUM_PINS; j++) {
2316 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j];
2317 int lsi_num = pci_swizzle(i, j);
2318
2319 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0));
2320 irqmap[1] = 0;
2321 irqmap[2] = 0;
2322 irqmap[3] = cpu_to_be32(j+1);
2323 irqmap[4] = cpu_to_be32(intc_phandle);
2324 spapr_dt_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, true);
2325 }
2326 }
2327 /* Write interrupt map */
2328 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map,
2329 sizeof(interrupt_map)));
2330
2331 tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]);
2332 if (!tcet) {
2333 return -1;
2334 }
2335 spapr_dma_dt(fdt, bus_off, "ibm,dma-window",
2336 tcet->liobn, tcet->bus_offset,
2337 tcet->nb_table << tcet->page_shift);
2338
2339 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, phb->index);
2340 if (drc) {
2341 uint32_t drc_index = cpu_to_be32(spapr_drc_index(drc));
2342
2343 _FDT(fdt_setprop(fdt, bus_off, "ibm,my-drc-index", &drc_index,
2344 sizeof(drc_index)));
2345 }
2346
2347 /* Walk the bridges and program the bus numbers*/
2348 spapr_phb_pci_enumerate(phb);
2349 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1));
2350
2351 /* Walk the bridge and subordinate buses */
2352 ret = spapr_dt_pci_bus(phb, PCI_HOST_BRIDGE(phb)->bus, fdt, bus_off);
2353 if (ret < 0) {
2354 return ret;
2355 }
2356
2357 return 0;
2358 }
2359
spapr_pci_rtas_init(void)2360 void spapr_pci_rtas_init(void)
2361 {
2362 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config",
2363 rtas_read_pci_config);
2364 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config",
2365 rtas_write_pci_config);
2366 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config",
2367 rtas_ibm_read_pci_config);
2368 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config",
2369 rtas_ibm_write_pci_config);
2370 if (msi_nonbroken) {
2371 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER,
2372 "ibm,query-interrupt-source-number",
2373 rtas_ibm_query_interrupt_source_number);
2374 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi",
2375 rtas_ibm_change_msi);
2376 }
2377
2378 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION,
2379 "ibm,set-eeh-option",
2380 rtas_ibm_set_eeh_option);
2381 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2,
2382 "ibm,get-config-addr-info2",
2383 rtas_ibm_get_config_addr_info2);
2384 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2,
2385 "ibm,read-slot-reset-state2",
2386 rtas_ibm_read_slot_reset_state2);
2387 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET,
2388 "ibm,set-slot-reset",
2389 rtas_ibm_set_slot_reset);
2390 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE,
2391 "ibm,configure-pe",
2392 rtas_ibm_configure_pe);
2393 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL,
2394 "ibm,slot-error-detail",
2395 rtas_ibm_slot_error_detail);
2396 }
2397
spapr_pci_register_types(void)2398 static void spapr_pci_register_types(void)
2399 {
2400 type_register_static(&spapr_phb_info);
2401 }
2402
type_init(spapr_pci_register_types)2403 type_init(spapr_pci_register_types)
2404
2405 static int spapr_switch_one_vga(DeviceState *dev, void *opaque)
2406 {
2407 bool be = *(bool *)opaque;
2408
2409 if (object_dynamic_cast(OBJECT(dev), "VGA")
2410 || object_dynamic_cast(OBJECT(dev), "secondary-vga")
2411 || object_dynamic_cast(OBJECT(dev), "bochs-display")
2412 || object_dynamic_cast(OBJECT(dev), "virtio-vga")) {
2413 object_property_set_bool(OBJECT(dev), "big-endian-framebuffer", be,
2414 &error_abort);
2415 }
2416 return 0;
2417 }
2418
spapr_pci_switch_vga(SpaprMachineState * spapr,bool big_endian)2419 void spapr_pci_switch_vga(SpaprMachineState *spapr, bool big_endian)
2420 {
2421 SpaprPhbState *sphb;
2422
2423 /*
2424 * For backward compatibility with existing guests, we switch
2425 * the endianness of the VGA controller when changing the guest
2426 * interrupt mode
2427 */
2428 QLIST_FOREACH(sphb, &spapr->phbs, list) {
2429 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus;
2430 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL,
2431 &big_endian);
2432 }
2433 }
2434