xref: /dragonfly/sys/bus/u4b/wlan/if_urtwnreg.h (revision 326e57e8)
1 /*-
2  * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
3  *
4  * Permission to use, copy, modify, and distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  *
16  * $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $
17  * $FreeBSD$
18  */
19 
20 #define URTWN_CONFIG_INDEX	0
21 #define URTWN_IFACE_INDEX	0
22 
23 #define	URTWN_NOISE_FLOOR	-95
24 
25 #define R92C_MAX_CHAINS	2
26 
27 /* Maximum number of output pipes is 3. */
28 #define R92C_MAX_EPOUT	3
29 
30 #define R92C_MAX_TX_PWR	0x3f
31 
32 #define R92C_PUBQ_NPAGES	231
33 #define R92C_TXPKTBUF_COUNT	256
34 #define R92C_TX_PAGE_COUNT	248
35 #define R92C_TX_PAGE_BOUNDARY	(R92C_TX_PAGE_COUNT + 1)
36 #define R88E_TXPKTBUF_COUNT	177
37 #define R88E_TX_PAGE_COUNT	169
38 #define R88E_TX_PAGE_BOUNDARY	(R88E_TX_PAGE_COUNT + 1)
39 
40 #define R92C_H2C_NBOX	4
41 
42 /* USB Requests. */
43 #define R92C_REQ_REGS	0x05
44 
45 /*
46  * MAC registers.
47  */
48 /* System Configuration. */
49 #define R92C_SYS_ISO_CTRL		0x000
50 #define R92C_SYS_FUNC_EN		0x002
51 #define R92C_APS_FSMCO			0x004
52 #define R92C_SYS_CLKR			0x008
53 #define R92C_AFE_MISC			0x010
54 #define R92C_SPS0_CTRL			0x011
55 #define R92C_SPS_OCP_CFG		0x018
56 #define R92C_RSV_CTRL			0x01c
57 #define R92C_RF_CTRL			0x01f
58 #define R92C_LDOA15_CTRL		0x020
59 #define R92C_LDOV12D_CTRL		0x021
60 #define R92C_LDOHCI12_CTRL		0x022
61 #define R92C_LPLDO_CTRL			0x023
62 #define R92C_AFE_XTAL_CTRL		0x024
63 #define R92C_AFE_PLL_CTRL		0x028
64 #define R92C_EFUSE_CTRL			0x030
65 #define R92C_EFUSE_TEST			0x034
66 #define R92C_PWR_DATA			0x038
67 #define R92C_CAL_TIMER			0x03c
68 #define R92C_ACLK_MON			0x03e
69 #define R92C_GPIO_MUXCFG		0x040
70 #define R92C_GPIO_IO_SEL		0x042
71 #define R92C_MAC_PINMUX_CFG		0x043
72 #define R92C_GPIO_PIN_CTRL		0x044
73 #define R92C_GPIO_IN			0x044
74 #define R92C_GPIO_OUT			0x045
75 #define R92C_GPIO_IOSEL			0x046
76 #define R92C_GPIO_MOD			0x047
77 #define R92C_GPIO_INTM			0x048
78 #define R92C_LEDCFG0			0x04c
79 #define R92C_LEDCFG1			0x04d
80 #define R92C_LEDCFG2			0x04e
81 #define R92C_LEDCFG3			0x04f
82 #define R92C_FSIMR			0x050
83 #define R92C_FSISR			0x054
84 #define R92C_HSIMR			0x058
85 #define R92C_HSISR			0x05c
86 #define R88E_BB_PAD_CTRL		0x064
87 #define R92C_MCUFWDL			0x080
88 #define R92C_HMEBOX_EXT(idx)		(0x088 + (idx) * 2)
89 #define R88E_HIMR			0x0b0
90 #define R88E_HISR			0x0b4
91 #define R88E_HIMRE			0x0b8
92 #define R88E_HISRE			0x0bc
93 #define R92C_EFUSE_ACCESS               0x0cf
94 #define R92C_BIST_SCAN			0x0d0
95 #define R92C_BIST_RPT			0x0d4
96 #define R92C_BIST_ROM_RPT		0x0d8
97 #define R92C_USB_SIE_INTF		0x0e0
98 #define R92C_PCIE_MIO_INTF		0x0e4
99 #define R92C_PCIE_MIO_INTD		0x0e8
100 #define R92C_HPON_FSM			0x0ec
101 #define R92C_SYS_CFG			0x0f0
102 /* MAC General Configuration. */
103 #define R92C_CR				0x100
104 #define R92C_MSR			0x102
105 #define R92C_PBP			0x104
106 #define R92C_TRXDMA_CTRL		0x10c
107 #define R92C_TRXFF_BNDY			0x114
108 #define R92C_TRXFF_STATUS		0x118
109 #define R92C_RXFF_PTR			0x11c
110 #define R92C_HIMR			0x120
111 #define R92C_HISR			0x124
112 #define R92C_HIMRE			0x128
113 #define R92C_HISRE			0x12c
114 #define R92C_CPWM			0x12f
115 #define R92C_FWIMR			0x130
116 #define R92C_FWISR			0x134
117 #define R92C_PKTBUF_DBG_CTRL		0x140
118 #define R92C_PKTBUF_DBG_DATA_L		0x144
119 #define R92C_PKTBUF_DBG_DATA_H		0x148
120 #define R92C_TC0_CTRL(i)		(0x150 + (i) * 4)
121 #define R92C_TCUNIT_BASE		0x164
122 #define R92C_MBIST_START		0x174
123 #define R92C_MBIST_DONE			0x178
124 #define R92C_MBIST_FAIL			0x17c
125 #define R88E_32K_CTRL			0x194
126 #define R92C_C2HEVT_MSG_NORMAL		0x1a0
127 #define R92C_C2HEVT_MSG_TEST		0x1b8
128 #define R92C_C2HEVT_CLEAR		0x1bf
129 #define R92C_MCUTST_1			0x1c0
130 #define R92C_FMETHR			0x1c8
131 #define R92C_HMETFR			0x1cc
132 #define R92C_HMEBOX(idx)		(0x1d0 + (idx) * 4)
133 #define R92C_LLT_INIT			0x1e0
134 #define R92C_BB_ACCESS_CTRL		0x1e8
135 #define R92C_BB_ACCESS_DATA		0x1ec
136 #define R88E_HMEBOX_EXT(idx)            (0x1f0 + (idx) * 4)
137 /* Tx DMA Configuration. */
138 #define R92C_RQPN			0x200
139 #define R92C_FIFOPAGE			0x204
140 #define R92C_TDECTRL			0x208
141 #define R92C_TXDMA_OFFSET_CHK		0x20c
142 #define R92C_TXDMA_STATUS		0x210
143 #define R92C_RQPN_NPQ			0x214
144 /* Rx DMA Configuration. */
145 #define R92C_RXDMA_AGG_PG_TH		0x280
146 #define R92C_RXPKT_NUM			0x284
147 #define R92C_RXDMA_STATUS		0x288
148 /* Protocol Configuration. */
149 #define R92C_FWHW_TXQ_CTRL		0x420
150 #define R92C_HWSEQ_CTRL			0x423
151 #define R92C_TXPKTBUF_BCNQ_BDNY		0x424
152 #define R92C_TXPKTBUF_MGQ_BDNY		0x425
153 #define R92C_SPEC_SIFS			0x428
154 #define R92C_RL				0x42a
155 #define R92C_DARFRC			0x430
156 #define R92C_RARFRC			0x438
157 #define R92C_RRSR			0x440
158 #define R92C_ARFR(i)			(0x444 + (i) * 4)
159 #define R92C_AGGLEN_LMT			0x458
160 #define R92C_AMPDU_MIN_SPACE		0x45c
161 #define R92C_TXPKTBUF_WMAC_LBK_BF_HD	0x45d
162 #define R92C_FAST_EDCA_CTRL		0x460
163 #define R92C_RD_RESP_PKT_TH		0x463
164 #define R92C_INIRTS_RATE_SEL		0x480
165 #define R92C_INIDATA_RATE_SEL(macid)	(0x484 + (macid))
166 #define R92C_MAX_AGGR_NUM		0x4ca
167 #define R88E_TX_RPT_CTRL		0x4ec
168 #define R88E_TX_RPT_MACID_MAX		0x4ed
169 #define R88E_TX_RPT_TIME		0x4f0
170 /* EDCA Configuration. */
171 #define R92C_EDCA_VO_PARAM		0x500
172 #define R92C_EDCA_VI_PARAM		0x504
173 #define R92C_EDCA_BE_PARAM		0x508
174 #define R92C_EDCA_BK_PARAM		0x50c
175 #define R92C_BCNTCFG			0x510
176 #define R92C_PIFS			0x512
177 #define R92C_RDG_PIFS			0x513
178 #define R92C_SIFS_CCK			0x514
179 #define R92C_SIFS_OFDM			0x516
180 #define R92C_AGGR_BREAK_TIME		0x51a
181 #define R92C_SLOT			0x51b
182 #define R92C_TX_PTCL_CTRL		0x520
183 #define R92C_TXPAUSE			0x522
184 #define R92C_DIS_TXREQ_CLR		0x523
185 #define R92C_RD_CTRL			0x524
186 #define R92C_TBTT_PROHIBIT		0x540
187 #define R92C_RD_NAV_NXT			0x544
188 #define R92C_NAV_PROT_LEN		0x546
189 #define R92C_BCN_CTRL			0x550
190 #define R92C_MBID_NUM			0x552
191 #define R92C_DUAL_TSF_RST		0x553
192 #define R92C_BCN_INTERVAL		0x554
193 #define R92C_DRVERLYINT			0x558
194 #define R92C_BCNDMATIM			0x559
195 #define R92C_ATIMWND			0x55a
196 #define R92C_USTIME_TSF			0x55c
197 #define R92C_BCN_MAX_ERR		0x55d
198 #define R92C_RXTSF_OFFSET_CCK		0x55e
199 #define R92C_RXTSF_OFFSET_OFDM		0x55f
200 #define R92C_TSFTR			0x560
201 #define R92C_INIT_TSFTR			0x564
202 #define R92C_PSTIMER			0x580
203 #define R92C_TIMER0			0x584
204 #define R92C_TIMER1			0x588
205 #define R92C_ACMHWCTRL			0x5c0
206 #define R92C_ACMRSTCTRL			0x5c1
207 #define R92C_ACMAVG			0x5c2
208 #define R92C_VO_ADMTIME			0x5c4
209 #define R92C_VI_ADMTIME			0x5c6
210 #define R92C_BE_ADMTIME			0x5c8
211 #define R92C_EDCA_RANDOM_GEN		0x5cc
212 #define R92C_SCH_TXCMD			0x5d0
213 #define R88E_SCH_TXCMD			0x5f8
214 /* WMAC Configuration. */
215 #define R92C_APSD_CTRL			0x600
216 #define R92C_BWOPMODE			0x603
217 #define R92C_RCR			0x608
218 #define R92C_RX_DRVINFO_SZ		0x60f
219 #define R92C_MACID			0x610
220 #define R92C_BSSID			0x618
221 #define R92C_MAR			0x620
222 #define R92C_MAC_SPEC_SIFS		0x63a
223 #define R92C_R2T_SIFS			0x63c
224 #define R92C_T2T_SIFS			0x63e
225 #define R92C_ACKTO			0x640
226 #define R92C_CAMCMD			0x670
227 #define R92C_CAMWRITE			0x674
228 #define R92C_CAMREAD			0x678
229 #define R92C_CAMDBG			0x67c
230 #define R92C_SECCFG			0x680
231 #define R92C_RXFLTMAP0			0x6a0
232 #define R92C_RXFLTMAP1			0x6a2
233 #define R92C_RXFLTMAP2			0x6a4
234 
235 /* Bits for R92C_SYS_ISO_CTRL. */
236 #define R92C_SYS_ISO_CTRL_MD2PP		0x0001
237 #define R92C_SYS_ISO_CTRL_UA2USB	0x0002
238 #define R92C_SYS_ISO_CTRL_UD2CORE	0x0004
239 #define R92C_SYS_ISO_CTRL_PA2PCIE	0x0008
240 #define R92C_SYS_ISO_CTRL_PD2CORE	0x0010
241 #define R92C_SYS_ISO_CTRL_IP2MAC	0x0020
242 #define R92C_SYS_ISO_CTRL_DIOP		0x0040
243 #define R92C_SYS_ISO_CTRL_DIOE		0x0080
244 #define R92C_SYS_ISO_CTRL_EB2CORE	0x0100
245 #define R92C_SYS_ISO_CTRL_DIOR		0x0200
246 #define R92C_SYS_ISO_CTRL_PWC_EV25V	0x4000
247 #define R92C_SYS_ISO_CTRL_PWC_EV12V	0x8000
248 
249 /* Bits for R92C_SYS_FUNC_EN. */
250 #define R92C_SYS_FUNC_EN_BBRSTB		0x0001
251 #define R92C_SYS_FUNC_EN_BB_GLB_RST	0x0002
252 #define R92C_SYS_FUNC_EN_USBA		0x0004
253 #define R92C_SYS_FUNC_EN_UPLL		0x0008
254 #define R92C_SYS_FUNC_EN_USBD		0x0010
255 #define R92C_SYS_FUNC_EN_DIO_PCIE	0x0020
256 #define R92C_SYS_FUNC_EN_PCIEA		0x0040
257 #define R92C_SYS_FUNC_EN_PPLL		0x0080
258 #define R92C_SYS_FUNC_EN_PCIED		0x0100
259 #define R92C_SYS_FUNC_EN_DIOE		0x0200
260 #define R92C_SYS_FUNC_EN_CPUEN		0x0400
261 #define R92C_SYS_FUNC_EN_DCORE		0x0800
262 #define R92C_SYS_FUNC_EN_ELDR		0x1000
263 #define R92C_SYS_FUNC_EN_DIO_RF		0x2000
264 #define R92C_SYS_FUNC_EN_HWPDN		0x4000
265 #define R92C_SYS_FUNC_EN_MREGEN		0x8000
266 
267 /* Bits for R92C_APS_FSMCO. */
268 #define R92C_APS_FSMCO_PFM_LDALL	0x00000001
269 #define R92C_APS_FSMCO_PFM_ALDN		0x00000002
270 #define R92C_APS_FSMCO_PFM_LDKP		0x00000004
271 #define R92C_APS_FSMCO_PFM_WOWL		0x00000008
272 #define R92C_APS_FSMCO_PDN_EN		0x00000010
273 #define R92C_APS_FSMCO_PDN_PL		0x00000020
274 #define R92C_APS_FSMCO_APFM_ONMAC	0x00000100
275 #define R92C_APS_FSMCO_APFM_OFF		0x00000200
276 #define R92C_APS_FSMCO_APFM_RSM		0x00000400
277 #define R92C_APS_FSMCO_AFSM_HSUS	0x00000800
278 #define R92C_APS_FSMCO_AFSM_PCIE	0x00001000
279 #define R92C_APS_FSMCO_APDM_MAC		0x00002000
280 #define R92C_APS_FSMCO_APDM_HOST	0x00004000
281 #define R92C_APS_FSMCO_APDM_HPDN	0x00008000
282 #define R92C_APS_FSMCO_RDY_MACON	0x00010000
283 #define R92C_APS_FSMCO_SUS_HOST		0x00020000
284 #define R92C_APS_FSMCO_ROP_ALD		0x00100000
285 #define R92C_APS_FSMCO_ROP_PWR		0x00200000
286 #define R92C_APS_FSMCO_ROP_SPS		0x00400000
287 #define R92C_APS_FSMCO_SOP_MRST		0x02000000
288 #define R92C_APS_FSMCO_SOP_FUSE		0x04000000
289 #define R92C_APS_FSMCO_SOP_ABG		0x08000000
290 #define R92C_APS_FSMCO_SOP_AMB		0x10000000
291 #define R92C_APS_FSMCO_SOP_RCK		0x20000000
292 #define R92C_APS_FSMCO_SOP_A8M		0x40000000
293 #define R92C_APS_FSMCO_XOP_BTCK		0x80000000
294 
295 /* Bits for R92C_SYS_CLKR. */
296 #define R92C_SYS_CLKR_ANAD16V_EN	0x00000001
297 #define R92C_SYS_CLKR_ANA8M		0x00000002
298 #define R92C_SYS_CLKR_MACSLP		0x00000010
299 #define R92C_SYS_CLKR_LOADER_EN		0x00000020
300 #define R92C_SYS_CLKR_80M_SSC_DIS	0x00000080
301 #define R92C_SYS_CLKR_80M_SSC_EN_HO	0x00000100
302 #define R92C_SYS_CLKR_PHY_SSC_RSTB	0x00000200
303 #define R92C_SYS_CLKR_SEC_EN		0x00000400
304 #define R92C_SYS_CLKR_MAC_EN		0x00000800
305 #define R92C_SYS_CLKR_SYS_EN		0x00001000
306 #define R92C_SYS_CLKR_RING_EN		0x00002000
307 
308 /* Bits for R92C_RF_CTRL. */
309 #define R92C_RF_CTRL_EN		0x01
310 #define R92C_RF_CTRL_RSTB	0x02
311 #define R92C_RF_CTRL_SDMRSTB	0x04
312 
313 /* Bits for R92C_LDOA15_CTRL. */
314 #define R92C_LDOA15_CTRL_EN		0x01
315 #define R92C_LDOA15_CTRL_STBY		0x02
316 #define R92C_LDOA15_CTRL_OBUF		0x04
317 #define R92C_LDOA15_CTRL_REG_VOS	0x08
318 
319 /* Bits for R92C_LDOV12D_CTRL. */
320 #define R92C_LDOV12D_CTRL_LDV12_EN	0x01
321 
322 /* Bits for R92C_LPLDO_CTRL. */
323 #define R92C_LPLDO_CTRL_SLEEP		0x10
324 
325 /* Bits for R92C_AFE_XTAL_CTRL. */
326 #define R92C_AFE_XTAL_CTRL_ADDR_M	0x007ff800
327 #define R92C_AFE_XTAL_CTRL_ADDR_S	11
328 
329 /* Bits for R92C_AFE_PLL_CTRL. */
330 #define R92C_AFE_PLL_CTRL_EN		0x0001
331 #define R92C_AFE_PLL_CTRL_320_EN	0x0002
332 #define R92C_AFE_PLL_CTRL_FREF_SEL	0x0004
333 #define R92C_AFE_PLL_CTRL_EDGE_SEL	0x0008
334 #define R92C_AFE_PLL_CTRL_WDOGB		0x0010
335 #define R92C_AFE_PLL_CTRL_LPFEN		0x0020
336 
337 /* Bits for R92C_EFUSE_CTRL. */
338 #define R92C_EFUSE_CTRL_DATA_M	0x000000ff
339 #define R92C_EFUSE_CTRL_DATA_S	0
340 #define R92C_EFUSE_CTRL_ADDR_M	0x0003ff00
341 #define R92C_EFUSE_CTRL_ADDR_S	8
342 #define R92C_EFUSE_CTRL_VALID	0x80000000
343 
344 /* Bits for R92C_GPIO_MUXCFG. */
345 #define R92C_GPIO_MUXCFG_ENBT	0x0020
346 
347 /* Bits for R92C_LEDCFG0. */
348 #define R92C_LEDCFG0_DIS	0x08
349 
350 /* Bits for R92C_MCUFWDL. */
351 #define R92C_MCUFWDL_EN			0x00000001
352 #define R92C_MCUFWDL_RDY		0x00000002
353 #define R92C_MCUFWDL_CHKSUM_RPT		0x00000004
354 #define R92C_MCUFWDL_MACINI_RDY		0x00000008
355 #define R92C_MCUFWDL_BBINI_RDY		0x00000010
356 #define R92C_MCUFWDL_RFINI_RDY		0x00000020
357 #define R92C_MCUFWDL_WINTINI_RDY	0x00000040
358 #define R92C_MCUFWDL_RAM_DL_SEL		0x00000080
359 #define R92C_MCUFWDL_PAGE_M		0x00070000
360 #define R92C_MCUFWDL_PAGE_S		16
361 #define R92C_MCUFWDL_CPRST		0x00800000
362 
363 /* Bits for R88E_HIMR. */
364 #define R88E_HIMR_CPWM			0x00000100
365 #define R88E_HIMR_CPWM2			0x00000200
366 #define R88E_HIMR_TBDER			0x04000000
367 #define R88E_HIMR_PSTIMEOUT		0x20000000
368 
369 /* Bits for R88E_HIMRE.*/
370 #define R88E_HIMRE_RXFOVW		0x00000100
371 #define R88E_HIMRE_TXFOVW		0x00000200
372 #define R88E_HIMRE_RXERR		0x00000400
373 #define R88E_HIMRE_TXERR		0x00000800
374 
375 /* Bits for R92C_EFUSE_ACCESS. */
376 #define R92C_EFUSE_ACCESS_OFF		0x00
377 #define R92C_EFUSE_ACCESS_ON		0x69
378 
379 /* Bits for R92C_HPON_FSM. */
380 #define R92C_HPON_FSM_CHIP_BONDING_ID_S		22
381 #define R92C_HPON_FSM_CHIP_BONDING_ID_M		0x00c00000
382 #define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R	1
383 
384 /* Bits for R92C_SYS_CFG. */
385 #define R92C_SYS_CFG_XCLK_VLD		0x00000001
386 #define R92C_SYS_CFG_ACLK_VLD		0x00000002
387 #define R92C_SYS_CFG_UCLK_VLD		0x00000004
388 #define R92C_SYS_CFG_PCLK_VLD		0x00000008
389 #define R92C_SYS_CFG_PCIRSTB		0x00000010
390 #define R92C_SYS_CFG_V15_VLD		0x00000020
391 #define R92C_SYS_CFG_TRP_B15V_EN	0x00000080
392 #define R92C_SYS_CFG_SIC_IDLE		0x00000100
393 #define R92C_SYS_CFG_BD_MAC2		0x00000200
394 #define R92C_SYS_CFG_BD_MAC1		0x00000400
395 #define R92C_SYS_CFG_IC_MACPHY_MODE	0x00000800
396 #define R92C_SYS_CFG_CHIP_VER_RTL_M	0x0000f000
397 #define R92C_SYS_CFG_CHIP_VER_RTL_S	12
398 #define R92C_SYS_CFG_BT_FUNC		0x00010000
399 #define R92C_SYS_CFG_VENDOR_UMC		0x00080000
400 #define R92C_SYS_CFG_PAD_HWPD_IDN	0x00400000
401 #define R92C_SYS_CFG_TRP_VAUX_EN	0x00800000
402 #define R92C_SYS_CFG_TRP_BT_EN		0x01000000
403 #define R92C_SYS_CFG_BD_PKG_SEL		0x02000000
404 #define R92C_SYS_CFG_BD_HCI_SEL		0x04000000
405 #define R92C_SYS_CFG_TYPE_92C		0x08000000
406 
407 /* Bits for R92C_CR. */
408 #define R92C_CR_HCI_TXDMA_EN	0x0001
409 #define R92C_CR_HCI_RXDMA_EN	0x0002
410 #define R92C_CR_TXDMA_EN	0x0004
411 #define R92C_CR_RXDMA_EN	0x0008
412 #define R92C_CR_PROTOCOL_EN	0x0010
413 #define R92C_CR_SCHEDULE_EN	0x0020
414 #define R92C_CR_MACTXEN		0x0040
415 #define R92C_CR_MACRXEN		0x0080
416 #define R92C_CR_ENSEC		0x0200
417 #define R92C_CR_CALTMR_EN	0x0400
418 
419 /* Bits for R92C_MSR. */
420 #define R92C_MSR_NOLINK		0x00
421 #define R92C_MSR_ADHOC		0x01
422 #define R92C_MSR_INFRA		0x02
423 #define R92C_MSR_AP		0x03
424 #define R92C_MSR_MASK		(R92C_MSR_AP)
425 
426 /* Bits for R92C_PBP. */
427 #define R92C_PBP_PSRX_M		0x0f
428 #define R92C_PBP_PSRX_S		0
429 #define R92C_PBP_PSTX_M		0xf0
430 #define R92C_PBP_PSTX_S		4
431 #define R92C_PBP_64		0
432 #define R92C_PBP_128		1
433 #define R92C_PBP_256		2
434 #define R92C_PBP_512		3
435 #define R92C_PBP_1024		4
436 
437 /* Bits for R92C_TRXDMA_CTRL. */
438 #define R92C_TRXDMA_CTRL_RXDMA_AGG_EN		0x0004
439 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M	0x0030
440 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S	4
441 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M	0x00c0
442 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S	6
443 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M	0x0300
444 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S	8
445 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M	0x0c00
446 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S	10
447 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M	0x3000
448 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S	12
449 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M	0xc000
450 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S	14
451 #define R92C_TRXDMA_CTRL_QUEUE_LOW		1
452 #define R92C_TRXDMA_CTRL_QUEUE_NORMAL		2
453 #define R92C_TRXDMA_CTRL_QUEUE_HIGH		3
454 #define R92C_TRXDMA_CTRL_QMAP_M			0xfff0
455 /* Shortcuts. */
456 #define R92C_TRXDMA_CTRL_QMAP_3EP		0xf5b0
457 #define R92C_TRXDMA_CTRL_QMAP_HQ_LQ		0xf5f0
458 #define R92C_TRXDMA_CTRL_QMAP_HQ_NQ		0xfaf0
459 #define R92C_TRXDMA_CTRL_QMAP_LQ		0x5550
460 #define R92C_TRXDMA_CTRL_QMAP_NQ		0xaaa0
461 #define R92C_TRXDMA_CTRL_QMAP_HQ		0xfff0
462 
463 /* Bits for R92C_LLT_INIT. */
464 #define R92C_LLT_INIT_DATA_M		0x000000ff
465 #define R92C_LLT_INIT_DATA_S		0
466 #define R92C_LLT_INIT_ADDR_M		0x0000ff00
467 #define R92C_LLT_INIT_ADDR_S		8
468 #define R92C_LLT_INIT_OP_M		0xc0000000
469 #define R92C_LLT_INIT_OP_S		30
470 #define R92C_LLT_INIT_OP_NO_ACTIVE	0
471 #define R92C_LLT_INIT_OP_WRITE		1
472 
473 /* Bits for R92C_RQPN. */
474 #define R92C_RQPN_HPQ_M		0x000000ff
475 #define R92C_RQPN_HPQ_S		0
476 #define R92C_RQPN_LPQ_M		0x0000ff00
477 #define R92C_RQPN_LPQ_S		8
478 #define R92C_RQPN_PUBQ_M	0x00ff0000
479 #define R92C_RQPN_PUBQ_S	16
480 #define R92C_RQPN_LD		0x80000000
481 
482 /* Bits for R92C_TDECTRL. */
483 #define R92C_TDECTRL_BLK_DESC_NUM_M	0x000000f0
484 #define R92C_TDECTRL_BLK_DESC_NUM_S	4
485 #define R92C_TDECTRL_BCN_VALID		0x00010000
486 
487 /* Bits for R92C_FWHW_TXQ_CTRL. */
488 #define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW	0x80
489 
490 /* Bits for R92C_SPEC_SIFS. */
491 #define R92C_SPEC_SIFS_CCK_M	0x00ff
492 #define R92C_SPEC_SIFS_CCK_S	0
493 #define R92C_SPEC_SIFS_OFDM_M	0xff00
494 #define R92C_SPEC_SIFS_OFDM_S	8
495 
496 /* Bits for R92C_RL. */
497 #define R92C_RL_LRL_M		0x003f
498 #define R92C_RL_LRL_S		0
499 #define R92C_RL_SRL_M		0x3f00
500 #define R92C_RL_SRL_S		8
501 
502 /* Bits for R92C_RRSR. */
503 #define R92C_RRSR_RATE_BITMAP_M		0x000fffff
504 #define R92C_RRSR_RATE_BITMAP_S		0
505 #define R92C_RRSR_RATE_CCK_ONLY_1M	0xffff1
506 #define R92C_RRSR_RSC_LOWSUBCHNL	0x00200000
507 #define R92C_RRSR_RSC_UPSUBCHNL		0x00400000
508 #define R92C_RRSR_SHORT			0x00800000
509 
510 /* Bits for R88E_TX_RPT_CTRL. */
511 #define R88E_TX_RPT1_ENA		0x01
512 #define R88E_TX_RPT2_ENA		0x02
513 
514 /* Bits for R92C_EDCA_XX_PARAM. */
515 #define R92C_EDCA_PARAM_AIFS_M		0x000000ff
516 #define R92C_EDCA_PARAM_AIFS_S		0
517 #define R92C_EDCA_PARAM_ECWMIN_M	0x00000f00
518 #define R92C_EDCA_PARAM_ECWMIN_S	8
519 #define R92C_EDCA_PARAM_ECWMAX_M	0x0000f000
520 #define R92C_EDCA_PARAM_ECWMAX_S	12
521 #define R92C_EDCA_PARAM_TXOP_M		0xffff0000
522 #define R92C_EDCA_PARAM_TXOP_S		16
523 
524 /* Bits for R92C_HWSEQ_CTRL / R92C_TXPAUSE. */
525 #define R92C_TX_QUEUE_VO		0x01
526 #define R92C_TX_QUEUE_VI		0x02
527 #define R92C_TX_QUEUE_BE		0x04
528 #define R92C_TX_QUEUE_BK		0x08
529 #define R92C_TX_QUEUE_MGT		0x10
530 #define R92C_TX_QUEUE_HIGH		0x20
531 #define R92C_TX_QUEUE_BCN		0x40
532 
533 /* Shortcuts. */
534 #define R92C_TX_QUEUE_AC			\
535 	(R92C_TX_QUEUE_VO | R92C_TX_QUEUE_VI |	\
536 	 R92C_TX_QUEUE_BE | R92C_TX_QUEUE_BK)
537 
538 #define R92C_TX_QUEUE_ALL			\
539 	(R92C_TX_QUEUE_AC | R92C_TX_QUEUE_MGT |	\
540 	 R92C_TX_QUEUE_HIGH | R92C_TX_QUEUE_BCN | 0x80)	/* XXX */
541 
542 /* Bits for R92C_BCN_CTRL. */
543 #define R92C_BCN_CTRL_EN_MBSSID		0x02
544 #define R92C_BCN_CTRL_TXBCN_RPT		0x04
545 #define R92C_BCN_CTRL_EN_BCN		0x08
546 #define R92C_BCN_CTRL_DIS_TSF_UDT0	0x10
547 
548 /* Bits for R92C_MBID_NUM. */
549 #define R92C_MBID_TXBCN_RPT0		0x08
550 #define R92C_MBID_TXBCN_RPT1		0x10
551 
552 /* Bits for R92C_DUAL_TSF_RST. */
553 #define R92C_DUAL_TSF_RST0		0x01
554 #define R92C_DUAL_TSF_RST1		0x02
555 
556 /* Bits for R92C_ACMHWCTRL. */
557 #define R92C_ACMHWCTRL_EN		0x01
558 #define R92C_ACMHWCTRL_BE		0x02
559 #define R92C_ACMHWCTRL_VI		0x04
560 #define R92C_ACMHWCTRL_VO		0x08
561 #define R92C_ACMHWCTRL_ACM_MASK		0x0f
562 
563 /* Bits for R92C_APSD_CTRL. */
564 #define R92C_APSD_CTRL_OFF		0x40
565 #define R92C_APSD_CTRL_OFF_STATUS	0x80
566 
567 /* Bits for R92C_BWOPMODE. */
568 #define R92C_BWOPMODE_11J	0x01
569 #define R92C_BWOPMODE_5G	0x02
570 #define R92C_BWOPMODE_20MHZ	0x04
571 
572 /* Bits for R92C_RCR. */
573 #define R92C_RCR_AAP		0x00000001
574 #define R92C_RCR_APM		0x00000002
575 #define R92C_RCR_AM		0x00000004
576 #define R92C_RCR_AB		0x00000008
577 #define R92C_RCR_ADD3		0x00000010
578 #define R92C_RCR_APWRMGT	0x00000020
579 #define R92C_RCR_CBSSID_DATA	0x00000040
580 #define R92C_RCR_CBSSID_BCN	0x00000080
581 #define R92C_RCR_ACRC32		0x00000100
582 #define R92C_RCR_AICV		0x00000200
583 #define R92C_RCR_ADF		0x00000800
584 #define R92C_RCR_ACF		0x00001000
585 #define R92C_RCR_AMF		0x00002000
586 #define R92C_RCR_HTC_LOC_CTRL	0x00004000
587 #define R92C_RCR_MFBEN		0x00400000
588 #define R92C_RCR_LSIGEN		0x00800000
589 #define R92C_RCR_ENMBID		0x01000000
590 #define R92C_RCR_APP_BA_SSN	0x08000000
591 #define R92C_RCR_APP_PHYSTS	0x10000000
592 #define R92C_RCR_APP_ICV	0x20000000
593 #define R92C_RCR_APP_MIC	0x40000000
594 #define R92C_RCR_APPFCS		0x80000000
595 
596 /* Bits for R92C_CAMCMD. */
597 #define R92C_CAMCMD_ADDR_M	0x0000ffff
598 #define R92C_CAMCMD_ADDR_S	0
599 #define R92C_CAMCMD_WRITE	0x00010000
600 #define R92C_CAMCMD_CLR		0x40000000
601 #define R92C_CAMCMD_POLLING	0x80000000
602 
603 /* Bits for R92C_SECCFG. */
604 #define R92C_SECCFG_TXUCKEY_DEF	0x0001
605 #define R92C_SECCFG_RXUCKEY_DEF	0x0002
606 #define R92C_SECCFG_TXENC_ENA	0x0004
607 #define R92C_SECCFG_RXDEC_ENA	0x0008
608 #define R92C_SECCFG_CMP_A2	0x0010
609 #define R92C_SECCFG_TXBCKEY_DEF	0x0040
610 #define R92C_SECCFG_RXBCKEY_DEF	0x0080
611 #define R88E_SECCFG_CHK_KEYID	0x0100
612 
613 /* Bits for R92C_RXFLTMAP*. */
614 #define R92C_RXFLTMAP_SUBTYPE(subtype)	\
615 	(1 << ((subtype) >> IEEE80211_FC0_SUBTYPE_SHIFT))
616 
617 
618 /*
619  * Baseband registers.
620  */
621 #define R92C_FPGA0_RFMOD		0x800
622 #define R92C_FPGA0_TXINFO		0x804
623 #define R92C_HSSI_PARAM1(chain)		(0x820 + (chain) * 8)
624 #define R92C_HSSI_PARAM2(chain)		(0x824 + (chain) * 8)
625 #define R92C_TXAGC_RATE18_06(i)		(((i) == 0) ? 0xe00 : 0x830)
626 #define R92C_TXAGC_RATE54_24(i)		(((i) == 0) ? 0xe04 : 0x834)
627 #define R92C_TXAGC_A_CCK1_MCS32		0xe08
628 #define R92C_TXAGC_B_CCK1_55_MCS32	0x838
629 #define R92C_TXAGC_B_CCK11_A_CCK2_11	0x86c
630 #define R92C_TXAGC_MCS03_MCS00(i)	(((i) == 0) ? 0xe10 : 0x83c)
631 #define R92C_TXAGC_MCS07_MCS04(i)	(((i) == 0) ? 0xe14 : 0x848)
632 #define R92C_TXAGC_MCS11_MCS08(i)	(((i) == 0) ? 0xe18 : 0x84c)
633 #define R92C_TXAGC_MCS15_MCS12(i)	(((i) == 0) ? 0xe1c : 0x868)
634 #define R92C_LSSI_PARAM(chain)		(0x840 + (chain) * 4)
635 #define R92C_FPGA0_RFIFACEOE(chain)	(0x860 + (chain) * 4)
636 #define R92C_FPGA0_RFIFACESW(idx)	(0x870 + (idx) * 4)
637 #define R92C_FPGA0_RFPARAM(idx)		(0x878 + (idx) * 4)
638 #define R92C_FPGA0_ANAPARAM2		0x884
639 #define R92C_LSSI_READBACK(chain)	(0x8a0 + (chain) * 4)
640 #define R92C_HSPI_READBACK(chain)	(0x8b8 + (chain) * 4)
641 #define R92C_FPGA1_RFMOD		0x900
642 #define R92C_FPGA1_TXINFO		0x90c
643 #define R92C_CCK0_SYSTEM		0xa00
644 #define R92C_CCK0_AFESETTING		0xa04
645 #define R92C_OFDM0_TRXPATHENA		0xc04
646 #define R92C_OFDM0_TRMUXPAR		0xc08
647 #define R92C_OFDM0_AGCCORE1(chain)	(0xc50 + (chain) * 8)
648 #define R92C_OFDM0_AGCPARAM1		0xc70
649 #define R92C_OFDM0_AGCRSSITABLE		0xc78
650 #define R92C_OFDM1_LSTF			0xd00
651 
652 /* Bits for R92C_FPGA[01]_RFMOD. */
653 #define R92C_RFMOD_40MHZ	0x00000001
654 #define R92C_RFMOD_JAPAN	0x00000002
655 #define R92C_RFMOD_CCK_TXSC	0x00000030
656 #define R92C_RFMOD_CCK_EN	0x01000000
657 #define R92C_RFMOD_OFDM_EN	0x02000000
658 
659 /* Bits for R92C_HSSI_PARAM1(i). */
660 #define R92C_HSSI_PARAM1_PI	0x00000100
661 
662 /* Bits for R92C_HSSI_PARAM2(i). */
663 #define R92C_HSSI_PARAM2_CCK_HIPWR	0x00000200
664 #define R92C_HSSI_PARAM2_ADDR_LENGTH	0x00000400
665 #define R92C_HSSI_PARAM2_DATA_LENGTH	0x00000800
666 #define R92C_HSSI_PARAM2_READ_ADDR_M	0x7f800000
667 #define R92C_HSSI_PARAM2_READ_ADDR_S	23
668 #define R92C_HSSI_PARAM2_READ_EDGE	0x80000000
669 
670 /* Bits for R92C_TXAGC_A_CCK1_MCS32. */
671 #define R92C_TXAGC_A_CCK1_M	0x0000ff00
672 #define R92C_TXAGC_A_CCK1_S	8
673 
674 /* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */
675 #define R92C_TXAGC_B_CCK11_M	0x000000ff
676 #define R92C_TXAGC_B_CCK11_S	0
677 #define R92C_TXAGC_A_CCK2_M	0x0000ff00
678 #define R92C_TXAGC_A_CCK2_S	8
679 #define R92C_TXAGC_A_CCK55_M	0x00ff0000
680 #define R92C_TXAGC_A_CCK55_S	16
681 #define R92C_TXAGC_A_CCK11_M	0xff000000
682 #define R92C_TXAGC_A_CCK11_S	24
683 
684 /* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */
685 #define R92C_TXAGC_B_CCK1_M	0x0000ff00
686 #define R92C_TXAGC_B_CCK1_S	8
687 #define R92C_TXAGC_B_CCK2_M	0x00ff0000
688 #define R92C_TXAGC_B_CCK2_S	16
689 #define R92C_TXAGC_B_CCK55_M	0xff000000
690 #define R92C_TXAGC_B_CCK55_S	24
691 
692 /* Bits for R92C_TXAGC_RATE18_06(x). */
693 #define R92C_TXAGC_RATE06_M	0x000000ff
694 #define R92C_TXAGC_RATE06_S	0
695 #define R92C_TXAGC_RATE09_M	0x0000ff00
696 #define R92C_TXAGC_RATE09_S	8
697 #define R92C_TXAGC_RATE12_M	0x00ff0000
698 #define R92C_TXAGC_RATE12_S	16
699 #define R92C_TXAGC_RATE18_M	0xff000000
700 #define R92C_TXAGC_RATE18_S	24
701 
702 /* Bits for R92C_TXAGC_RATE54_24(x). */
703 #define R92C_TXAGC_RATE24_M	0x000000ff
704 #define R92C_TXAGC_RATE24_S	0
705 #define R92C_TXAGC_RATE36_M	0x0000ff00
706 #define R92C_TXAGC_RATE36_S	8
707 #define R92C_TXAGC_RATE48_M	0x00ff0000
708 #define R92C_TXAGC_RATE48_S	16
709 #define R92C_TXAGC_RATE54_M	0xff000000
710 #define R92C_TXAGC_RATE54_S	24
711 
712 /* Bits for R92C_TXAGC_MCS03_MCS00(x). */
713 #define R92C_TXAGC_MCS00_M	0x000000ff
714 #define R92C_TXAGC_MCS00_S	0
715 #define R92C_TXAGC_MCS01_M	0x0000ff00
716 #define R92C_TXAGC_MCS01_S	8
717 #define R92C_TXAGC_MCS02_M	0x00ff0000
718 #define R92C_TXAGC_MCS02_S	16
719 #define R92C_TXAGC_MCS03_M	0xff000000
720 #define R92C_TXAGC_MCS03_S	24
721 
722 /* Bits for R92C_TXAGC_MCS07_MCS04(x). */
723 #define R92C_TXAGC_MCS04_M	0x000000ff
724 #define R92C_TXAGC_MCS04_S	0
725 #define R92C_TXAGC_MCS05_M	0x0000ff00
726 #define R92C_TXAGC_MCS05_S	8
727 #define R92C_TXAGC_MCS06_M	0x00ff0000
728 #define R92C_TXAGC_MCS06_S	16
729 #define R92C_TXAGC_MCS07_M	0xff000000
730 #define R92C_TXAGC_MCS07_S	24
731 
732 /* Bits for R92C_TXAGC_MCS11_MCS08(x). */
733 #define R92C_TXAGC_MCS08_M	0x000000ff
734 #define R92C_TXAGC_MCS08_S	0
735 #define R92C_TXAGC_MCS09_M	0x0000ff00
736 #define R92C_TXAGC_MCS09_S	8
737 #define R92C_TXAGC_MCS10_M	0x00ff0000
738 #define R92C_TXAGC_MCS10_S	16
739 #define R92C_TXAGC_MCS11_M	0xff000000
740 #define R92C_TXAGC_MCS11_S	24
741 
742 /* Bits for R92C_TXAGC_MCS15_MCS12(x). */
743 #define R92C_TXAGC_MCS12_M	0x000000ff
744 #define R92C_TXAGC_MCS12_S	0
745 #define R92C_TXAGC_MCS13_M	0x0000ff00
746 #define R92C_TXAGC_MCS13_S	8
747 #define R92C_TXAGC_MCS14_M	0x00ff0000
748 #define R92C_TXAGC_MCS14_S	16
749 #define R92C_TXAGC_MCS15_M	0xff000000
750 #define R92C_TXAGC_MCS15_S	24
751 
752 /* Bits for R92C_LSSI_PARAM(i). */
753 #define R92C_LSSI_PARAM_DATA_M	0x000fffff
754 #define R92C_LSSI_PARAM_DATA_S	0
755 #define R92C_LSSI_PARAM_ADDR_M	0x03f00000
756 #define R92C_LSSI_PARAM_ADDR_S	20
757 #define R88E_LSSI_PARAM_ADDR_M	0x0ff00000
758 #define R88E_LSSI_PARAM_ADDR_S	20
759 
760 /* Bits for R92C_FPGA0_ANAPARAM2. */
761 #define R92C_FPGA0_ANAPARAM2_CBW20	0x00000400
762 
763 /* Bits for R92C_LSSI_READBACK(i). */
764 #define R92C_LSSI_READBACK_DATA_M	0x000fffff
765 #define R92C_LSSI_READBACK_DATA_S	0
766 
767 /* Bits for R92C_OFDM0_AGCCORE1(i). */
768 #define R92C_OFDM0_AGCCORE1_GAIN_M	0x0000007f
769 #define R92C_OFDM0_AGCCORE1_GAIN_S	0
770 
771 
772 /*
773  * USB registers.
774  */
775 #define R92C_USB_SUSPEND		0xfe10
776 #define R92C_USB_INFO			0xfe17
777 #define R92C_USB_SPECIAL_OPTION		0xfe55
778 #define R92C_USB_HCPWM			0xfe57
779 #define R92C_USB_HRPWM			0xfe58
780 #define R92C_USB_DMA_AGG_TO		0xfe5b
781 #define R92C_USB_AGG_TO			0xfe5c
782 #define R92C_USB_AGG_TH			0xfe5d
783 #define R92C_USB_VID			0xfe60
784 #define R92C_USB_PID			0xfe62
785 #define R92C_USB_OPTIONAL		0xfe64
786 #define R92C_USB_EP			0xfe65
787 #define R92C_USB_PHY			0xfe68
788 #define R92C_USB_MAC_ADDR		0xfe70
789 #define R92C_USB_STRING			0xfe80
790 
791 /* Bits for R92C_USB_SPECIAL_OPTION. */
792 #define R92C_USB_SPECIAL_OPTION_AGG_EN		0x08
793 #define R92C_USB_SPECIAL_OPTION_INT_BULK_SEL	0x10
794 
795 /* Bits for R92C_USB_EP. */
796 #define R92C_USB_EP_HQ_M	0x000f
797 #define R92C_USB_EP_HQ_S	0
798 #define R92C_USB_EP_NQ_M	0x00f0
799 #define R92C_USB_EP_NQ_S	4
800 #define R92C_USB_EP_LQ_M	0x0f00
801 #define R92C_USB_EP_LQ_S	8
802 
803 
804 /*
805  * Firmware base address.
806  */
807 #define R92C_FW_START_ADDR	0x1000
808 #define R92C_FW_PAGE_SIZE	4096
809 
810 
811 /*
812  * RF (6052) registers.
813  */
814 #define R92C_RF_AC		0x00
815 #define R92C_RF_IQADJ_G(i)	(0x01 + (i))
816 #define R92C_RF_POW_TRSW	0x05
817 #define R92C_RF_GAIN_RX		0x06
818 #define R92C_RF_GAIN_TX		0x07
819 #define R92C_RF_TXM_IDAC	0x08
820 #define R92C_RF_BS_IQGEN	0x0f
821 #define R92C_RF_MODE1		0x10
822 #define R92C_RF_MODE2		0x11
823 #define R92C_RF_RX_AGC_HP	0x12
824 #define R92C_RF_TX_AGC		0x13
825 #define R92C_RF_BIAS		0x14
826 #define R92C_RF_IPA		0x15
827 #define R92C_RF_POW_ABILITY	0x17
828 #define R92C_RF_CHNLBW		0x18
829 #define R92C_RF_RX_G1		0x1a
830 #define R92C_RF_RX_G2		0x1b
831 #define R92C_RF_RX_BB2		0x1c
832 #define R92C_RF_RX_BB1		0x1d
833 #define R92C_RF_RCK1		0x1e
834 #define R92C_RF_RCK2		0x1f
835 #define R92C_RF_TX_G(i)		(0x20 + (i))
836 #define R92C_RF_TX_BB1		0x23
837 #define R92C_RF_T_METER		0x24
838 #define R92C_RF_SYN_G(i)	(0x25 + (i))
839 #define R92C_RF_RCK_OS		0x30
840 #define R92C_RF_TXPA_G(i)	(0x31 + (i))
841 #define R88E_RF_T_METER		0x42
842 
843 /* Bits for R92C_RF_AC. */
844 #define R92C_RF_AC_MODE_M	0x70000
845 #define R92C_RF_AC_MODE_S	16
846 #define R92C_RF_AC_MODE_STANDBY	1
847 
848 /* Bits for R92C_RF_CHNLBW. */
849 #define R92C_RF_CHNLBW_CHNL_M	0x003ff
850 #define R92C_RF_CHNLBW_CHNL_S	0
851 #define R92C_RF_CHNLBW_BW20	0x00400
852 #define R88E_RF_CHNLBW_BW20	0x00c00
853 #define R92C_RF_CHNLBW_LCSTART	0x08000
854 
855 /* Bits for R92C_RF_T_METER. */
856 #define R92C_RF_T_METER_START	0x60
857 #define R92C_RF_T_METER_VAL_M	0x1f
858 #define R92C_RF_T_METER_VAL_S	0
859 
860 /* Bits for R88E_RF_T_METER. */
861 #define R88E_RF_T_METER_VAL_M	0x0fc00
862 #define R88E_RF_T_METER_VAL_S	10
863 #define R88E_RF_T_METER_START	0x30000
864 
865 
866 /*
867  * CAM entries.
868  */
869 #define R92C_CAM_ENTRY_COUNT	32
870 
871 #define R92C_CAM_CTL0(entry)	((entry) * 8 + 0)
872 #define R92C_CAM_CTL1(entry)	((entry) * 8 + 1)
873 #define R92C_CAM_KEY(entry, i)	((entry) * 8 + 2 + (i))
874 
875 /* Bits for R92C_CAM_CTL0(i). */
876 #define R92C_CAM_KEYID_M	0x00000003
877 #define R92C_CAM_KEYID_S	0
878 #define R92C_CAM_ALGO_M		0x0000001c
879 #define R92C_CAM_ALGO_S		2
880 #define R92C_CAM_ALGO_NONE	0
881 #define R92C_CAM_ALGO_WEP40	1
882 #define R92C_CAM_ALGO_TKIP	2
883 #define R92C_CAM_ALGO_AES	4
884 #define R92C_CAM_ALGO_WEP104	5
885 #define R92C_CAM_VALID		0x00008000
886 #define R92C_CAM_MACLO_M	0xffff0000
887 #define R92C_CAM_MACLO_S	16
888 
889 /* Rate adaptation modes. */
890 #define R92C_RAID_11GN	1
891 #define R92C_RAID_11N	3
892 #define R92C_RAID_11BG	4
893 #define R92C_RAID_11G	5	/* "pure" 11g */
894 #define R92C_RAID_11B	6
895 
896 
897 /*
898  * Macros to access subfields in registers.
899  */
900 /* Mask and Shift (getter). */
901 #define MS(val, field)							\
902 	(((val) & field##_M) >> field##_S)
903 
904 /* Shift and Mask (setter). */
905 #define SM(field, val)							\
906 	(((val) << field##_S) & field##_M)
907 
908 /* Rewrite. */
909 #define RW(var, field, val)						\
910 	(((var) & ~field##_M) | SM(field, val))
911 
912 /*
913  * Firmware image header.
914  */
915 struct r92c_fw_hdr {
916 	/* QWORD0 */
917 	uint16_t	signature;
918 	uint8_t		category;
919 	uint8_t		function;
920 	uint16_t	version;
921 	uint16_t	subversion;
922 	/* QWORD1 */
923 	uint8_t		month;
924 	uint8_t		date;
925 	uint8_t		hour;
926 	uint8_t		minute;
927 	uint16_t	ramcodesize;
928 	uint16_t	reserved2;
929 	/* QWORD2 */
930 	uint32_t	svnidx;
931 	uint32_t	reserved3;
932 	/* QWORD3 */
933 	uint32_t	reserved4;
934 	uint32_t	reserved5;
935 } __packed;
936 
937 /*
938  * Host to firmware commands.
939  */
940 struct r92c_fw_cmd {
941 	uint8_t	id;
942 #define R92C_CMD_AP_OFFLOAD		0
943 #define R92C_CMD_SET_PWRMODE		1
944 #define R92C_CMD_JOINBSS_RPT		2
945 #define R92C_CMD_RSVD_PAGE		3
946 #define R92C_CMD_RSSI			4
947 #define R92C_CMD_RSSI_SETTING		5
948 #define R92C_CMD_MACID_CONFIG		6
949 #define R92C_CMD_MACID_PS_MODE		7
950 #define R92C_CMD_P2P_PS_OFFLOAD		8
951 #define R92C_CMD_SELECTIVE_SUSPEND	9
952 #define R92C_CMD_FLAG_EXT		0x80
953 
954 	uint8_t	msg[5];
955 } __packed;
956 
957 /* Structure for R92C_CMD_RSSI_SETTING. */
958 struct r92c_fw_cmd_rssi {
959 	uint8_t	macid;
960 	uint8_t	reserved;
961 	uint8_t	pwdb;
962 } __packed;
963 
964 /* Structure for R92C_CMD_MACID_CONFIG. */
965 struct r92c_fw_cmd_macid_cfg {
966 	uint32_t	mask;
967 	uint8_t		macid;
968 #define URTWN_MACID_BSS		0
969 #define URTWN_MACID_BC		4	/* Broadcast. */
970 #define R92C_MACID_MAX		31
971 #define R88E_MACID_MAX		63
972 #define URTWN_MACID_MAX(sc)	(((sc)->chip & URTWN_CHIP_88E) ? \
973 				    R88E_MACID_MAX : R92C_MACID_MAX)
974 #define URTWN_MACID_UNDEFINED	(uint8_t)-1
975 #define URTWN_MACID_VALID	0x80
976 } __packed;
977 
978 /*
979  * RTL8192CU ROM image.
980  */
981 struct r92c_rom {
982 	uint16_t	id;		/* 0x8192 */
983 	uint8_t		reserved1[5];
984 	uint8_t		dbg_sel;
985 	uint16_t	reserved2;
986 	uint16_t	vid;
987 	uint16_t	pid;
988 	uint8_t		usb_opt;
989 	uint8_t		ep_setting;
990 	uint16_t	reserved3;
991 	uint8_t		usb_phy;
992 	uint8_t		reserved4[3];
993 	uint8_t		macaddr[IEEE80211_ADDR_LEN];
994 	uint8_t		string[61];	/* "Realtek" */
995 	uint8_t		subcustomer_id;
996 	uint8_t		cck_tx_pwr[R92C_MAX_CHAINS][3];
997 	uint8_t		ht40_1s_tx_pwr[R92C_MAX_CHAINS][3];
998 	uint8_t		ht40_2s_tx_pwr_diff[3];
999 	uint8_t		ht20_tx_pwr_diff[3];
1000 	uint8_t		ofdm_tx_pwr_diff[3];
1001 	uint8_t		ht40_max_pwr[3];
1002 	uint8_t		ht20_max_pwr[3];
1003 	uint8_t		xtal_calib;
1004 	uint8_t		tssi[R92C_MAX_CHAINS];
1005 	uint8_t		thermal_meter;
1006 	uint8_t		rf_opt1;
1007 #define R92C_ROM_RF1_REGULATORY_M	0x07
1008 #define R92C_ROM_RF1_REGULATORY_S	0
1009 #define R92C_ROM_RF1_BOARD_TYPE_M	0xe0
1010 #define R92C_ROM_RF1_BOARD_TYPE_S	5
1011 #define R92C_BOARD_TYPE_DONGLE		0
1012 #define R92C_BOARD_TYPE_HIGHPA		1
1013 #define R92C_BOARD_TYPE_MINICARD	2
1014 #define R92C_BOARD_TYPE_SOLO		3
1015 #define R92C_BOARD_TYPE_COMBO		4
1016 
1017 	uint8_t		rf_opt2;
1018 	uint8_t		rf_opt3;
1019 	uint8_t		rf_opt4;
1020 	uint8_t		channel_plan;
1021 	uint8_t		version;
1022 	uint8_t		customer_id;
1023 } __packed;
1024 
1025 /*
1026  * RTL8188EU ROM image.
1027  */
1028 struct r88e_rom {
1029 	uint8_t		reserved1[16];
1030 	uint8_t		cck_tx_pwr[6];
1031 	uint8_t		ht40_tx_pwr[5];
1032 	uint8_t		tx_pwr_diff;
1033 	uint8_t		reserved2[156];
1034 	uint8_t		channel_plan;
1035 	uint8_t		crystalcap;
1036 	uint8_t		reserved3[7];
1037 	uint8_t		rf_board_opt;
1038 	uint8_t		rf_feature_opt;
1039 	uint8_t		rf_bt_opt;
1040 	uint8_t		version;
1041 	uint8_t		customer_id;
1042 	uint8_t		reserved4[3];
1043 	uint8_t		rf_ant_opt;
1044 	uint8_t		reserved5[6];
1045 	uint16_t	vid;
1046 	uint16_t	pid;
1047 	uint8_t		usb_opt;
1048 	uint8_t		reserved6[2];
1049 	uint8_t		macaddr[IEEE80211_ADDR_LEN];
1050 	uint8_t		reserved7[2];
1051 	uint8_t		string[33];	/* "realtek 802.11n NIC" */
1052 	uint8_t		reserved8[256];
1053 } __packed;
1054 
1055 #define	URTWN_EFUSE_MAX_LEN		512
1056 
1057 /* Rx MAC descriptor. */
1058 struct r92c_rx_stat {
1059 	uint32_t	rxdw0;
1060 #define R92C_RXDW0_PKTLEN_M	0x00003fff
1061 #define R92C_RXDW0_PKTLEN_S	0
1062 #define R92C_RXDW0_CRCERR	0x00004000
1063 #define R92C_RXDW0_ICVERR	0x00008000
1064 #define R92C_RXDW0_INFOSZ_M	0x000f0000
1065 #define R92C_RXDW0_INFOSZ_S	16
1066 #define R92C_RXDW0_CIPHER_M	0x00700000
1067 #define R92C_RXDW0_CIPHER_S	20
1068 #define R92C_RXDW0_QOS		0x00800000
1069 #define R92C_RXDW0_SHIFT_M	0x03000000
1070 #define R92C_RXDW0_SHIFT_S	24
1071 #define R92C_RXDW0_PHYST	0x04000000
1072 #define R92C_RXDW0_DECRYPTED	0x08000000
1073 
1074 	uint32_t	rxdw1;
1075 	uint32_t	rxdw2;
1076 #define R92C_RXDW2_PKTCNT_M	0x00ff0000
1077 #define R92C_RXDW2_PKTCNT_S	16
1078 
1079 	uint32_t	rxdw3;
1080 #define R92C_RXDW3_RATE_M	0x0000003f
1081 #define R92C_RXDW3_RATE_S	0
1082 #define R92C_RXDW3_HT		0x00000040
1083 #define R92C_RXDW3_HTC		0x00000400
1084 #define R88E_RXDW3_RPT_M	0x0000c000
1085 #define R88E_RXDW3_RPT_S	14
1086 #define R88E_RXDW3_RPT_RX	0
1087 #define R88E_RXDW3_RPT_TX1	1
1088 #define R88E_RXDW3_RPT_TX2	2
1089 
1090 	uint32_t	rxdw4;
1091 	uint32_t	rxdw5;
1092 } __packed __attribute__((aligned(4)));
1093 
1094 /* Rx PHY descriptor. */
1095 struct r92c_rx_phystat {
1096 	uint32_t	phydw0;
1097 	uint32_t	phydw1;
1098 	uint32_t	phydw2;
1099 	uint32_t	phydw3;
1100 	uint32_t	phydw4;
1101 	uint32_t	phydw5;
1102 	uint32_t	phydw6;
1103 	uint32_t	phydw7;
1104 } __packed __attribute__((aligned(4)));
1105 
1106 /* Rx PHY CCK descriptor. */
1107 struct r92c_rx_cck {
1108 	uint8_t		adc_pwdb[4];
1109 	uint8_t		sq_rpt;
1110 	uint8_t		agc_rpt;
1111 } __packed;
1112 
1113 struct r88e_rx_cck {
1114 	uint8_t		path_agc[2];
1115 	uint8_t		chan;
1116 	uint8_t		reserved1;
1117 	uint8_t		sig_qual;
1118 	uint8_t		agc_rpt;
1119 	uint8_t		rpt_b;
1120 	uint8_t		reserved2;
1121 	uint8_t		noise_power;
1122 	uint8_t		path_cfotail[2];
1123 	uint8_t		pcts_mask[2];
1124 	uint8_t		stream_rxevm[2];
1125 	uint8_t		path_rxsnr[2];
1126 	uint8_t		noise_power_db_lsb;
1127 	uint8_t		reserved3[3];
1128 	uint8_t		stream_csi[2];
1129 	uint8_t		stream_target_csi[2];
1130 	uint8_t		sig_evm;
1131 } __packed;
1132 
1133 /* Tx MAC descriptor. */
1134 struct r92c_tx_desc {
1135 	uint32_t	txdw0;
1136 #define R92C_TXDW0_PKTLEN_M	0x0000ffff
1137 #define R92C_TXDW0_PKTLEN_S	0
1138 #define R92C_TXDW0_OFFSET_M	0x00ff0000
1139 #define R92C_TXDW0_OFFSET_S	16
1140 #define R92C_TXDW0_BMCAST	0x01000000
1141 #define R92C_TXDW0_LSG		0x04000000
1142 #define R92C_TXDW0_FSG		0x08000000
1143 #define R92C_TXDW0_OWN		0x80000000
1144 
1145 	uint32_t	txdw1;
1146 #define R92C_TXDW1_MACID_M	0x0000001f
1147 #define R92C_TXDW1_MACID_S	0
1148 #define R88E_TXDW1_MACID_M	0x0000003f
1149 #define R88E_TXDW1_MACID_S	0
1150 #define R92C_TXDW1_AGGEN	0x00000020
1151 #define R92C_TXDW1_AGGBK	0x00000040
1152 #define R92C_TXDW1_QSEL_M	0x00001f00
1153 #define R92C_TXDW1_QSEL_S	8
1154 
1155 #define R92C_TXDW1_QSEL_BE	0x00	/* or 0x03 */
1156 #define R92C_TXDW1_QSEL_BK	0x01	/* or 0x02 */
1157 #define R92C_TXDW1_QSEL_VI	0x04	/* or 0x05 */
1158 #define R92C_TXDW1_QSEL_VO	0x06	/* or 0x07 */
1159 #define URTWN_MAX_TID		8
1160 
1161 #define R92C_TXDW1_QSEL_BEACON	0x10
1162 #define R92C_TXDW1_QSEL_MGNT	0x12
1163 
1164 #define R92C_TXDW1_RAID_M	0x000f0000
1165 #define R92C_TXDW1_RAID_S	16
1166 #define R92C_TXDW1_CIPHER_M	0x00c00000
1167 #define R92C_TXDW1_CIPHER_S	22
1168 #define R92C_TXDW1_CIPHER_NONE	0
1169 #define R92C_TXDW1_CIPHER_RC4	1
1170 #define R92C_TXDW1_CIPHER_AES	3
1171 #define R92C_TXDW1_PKTOFF_M	0x7c000000
1172 #define R92C_TXDW1_PKTOFF_S	26
1173 
1174 	uint32_t	txdw2;
1175 #define R88E_TXDW2_AGGBK	0x00010000
1176 #define R88E_TXDW2_CCX_RPT	0x00080000
1177 
1178 	uint16_t	txdw3;
1179 	uint16_t	txdseq;
1180 #define R88E_TXDSEQ_HWSEQ_EN	0x8000
1181 
1182 	uint32_t	txdw4;
1183 #define R92C_TXDW4_RTSRATE_M	0x0000003f
1184 #define R92C_TXDW4_RTSRATE_S	0
1185 #define R92C_TXDW4_HWSEQ_QOS	0x00000040
1186 #define R92C_TXDW4_HWSEQ_EN	0x00000080
1187 #define R92C_TXDW4_DRVRATE	0x00000100
1188 #define R92C_TXDW4_CTS2SELF	0x00000800
1189 #define R92C_TXDW4_RTSEN	0x00001000
1190 #define R92C_TXDW4_HWRTSEN	0x00002000
1191 #define R92C_TXDW4_SCO_M	0x003f0000
1192 #define R92C_TXDW4_SCO_S	20
1193 #define R92C_TXDW4_SCO_SCA	1
1194 #define R92C_TXDW4_SCO_SCB	2
1195 #define R92C_TXDW4_40MHZ	0x02000000
1196 
1197 	uint32_t	txdw5;
1198 #define R92C_TXDW5_DATARATE_M	0x0000003f
1199 #define R92C_TXDW5_DATARATE_S	0
1200 #define R92C_TXDW5_SGI		0x00000040
1201 #define R92C_TXDW5_AGGNUM_M	0xff000000
1202 #define R92C_TXDW5_AGGNUM_S	24
1203 
1204 	uint32_t	txdw6;
1205 	uint16_t	txdsum;
1206 	uint16_t	pad;
1207 } __packed __attribute__((aligned(4)));
1208 
1209 struct r88e_tx_rpt_ccx {
1210 	uint8_t		rptb0;
1211 	uint8_t		rptb1;
1212 #define R88E_RPTB1_MACID_M	0x3f
1213 #define R88E_RPTB1_MACID_S	0
1214 #define R88E_RPTB1_PKT_OK	0x40
1215 #define R88E_RPTB1_BMC		0x80
1216 
1217 	uint8_t		rptb2;
1218 #define R88E_RPTB2_RETRY_CNT_M	0x3f
1219 #define R88E_RPTB2_RETRY_CNT_S	0
1220 #define R88E_RPTB2_LIFE_EXPIRE	0x40
1221 #define R88E_RPTB2_RETRY_OVER	0x80
1222 
1223 	uint8_t		rptb3;
1224 	uint8_t		rptb4;
1225 	uint8_t		rptb5;
1226 	uint8_t		rptb6;
1227 #define R88E_RPTB6_QSEL_M	0xf0
1228 #define R88E_RPTB6_QSEL_S	4
1229 
1230 	uint8_t		rptb7;
1231 } __packed;
1232 
1233 
1234 static const uint8_t ridx2rate[] =
1235 	{ 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 };
1236 
1237 /* HW rate indices. */
1238 #define URTWN_RIDX_CCK1		0
1239 #define URTWN_RIDX_CCK11	3
1240 #define URTWN_RIDX_OFDM6	4
1241 #define URTWN_RIDX_OFDM24	8
1242 #define URTWN_RIDX_OFDM54	11
1243 
1244 #define URTWN_RIDX_COUNT	28
1245 #define URTWN_RIDX_UNKNOWN	(uint8_t)-1
1246 
1247 
1248 /*
1249  * MAC initialization values.
1250  */
1251 static const struct {
1252 	uint16_t	reg;
1253 	uint8_t		val;
1254 } rtl8188eu_mac[] = {
1255 	{ 0x026, 0x41 }, { 0x027, 0x35 }, { 0x040, 0x00 }, { 0x428, 0x0a },
1256 	{ 0x429, 0x10 }, { 0x430, 0x00 }, { 0x431, 0x01 }, { 0x432, 0x02 },
1257 	{ 0x433, 0x04 }, { 0x434, 0x05 }, { 0x435, 0x06 }, { 0x436, 0x07 },
1258 	{ 0x437, 0x08 }, { 0x438, 0x00 }, { 0x439, 0x00 }, { 0x43a, 0x01 },
1259 	{ 0x43b, 0x02 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, { 0x43e, 0x06 },
1260 	{ 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, { 0x442, 0x00 },
1261 	{ 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, { 0x447, 0x00 },
1262 	{ 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, { 0x45b, 0xb9 },
1263 	{ 0x460, 0x66 }, { 0x461, 0x66 }, { 0x480, 0x08 }, { 0x4c8, 0xff },
1264 	{ 0x4c9, 0x08 }, { 0x4cc, 0xff }, { 0x4cd, 0xff }, { 0x4ce, 0x01 },
1265 	{ 0x4d3, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, { 0x502, 0x2f },
1266 	{ 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, { 0x506, 0x5e },
1267 	{ 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, { 0x50a, 0x5e },
1268 	{ 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, { 0x50e, 0x00 },
1269 	{ 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, { 0x516, 0x0a },
1270 	{ 0x525, 0x4f }, { 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 },
1271 	{ 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a },
1272 	{ 0x620, 0xff }, { 0x621, 0xff }, { 0x622, 0xff }, { 0x623, 0xff },
1273 	{ 0x624, 0xff }, { 0x625, 0xff }, { 0x626, 0xff }, { 0x627, 0xff },
1274 	{ 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0a }, { 0x63e, 0x0e },
1275 	{ 0x63f, 0x0e }, { 0x640, 0x40 }, { 0x66e, 0x05 }, { 0x700, 0x21 },
1276 	{ 0x701, 0x43 }, { 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 },
1277 	{ 0x709, 0x43 }, { 0x70a, 0x65 }, { 0x70b, 0x87 }
1278 }, rtl8192cu_mac[] = {
1279 	{ 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 },
1280 	{ 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 },
1281 	{ 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 },
1282 	{ 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 },
1283 	{ 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 },
1284 	{ 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f },
1285 	{ 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 },
1286 	{ 0x45b, 0xb9 }, { 0x460, 0x66 }, { 0x461, 0x66 }, { 0x462, 0x08 },
1287 	{ 0x463, 0x03 }, { 0x4c8, 0xff }, { 0x4c9, 0x08 }, { 0x4cc, 0xff },
1288 	{ 0x4cd, 0xff }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 },
1289 	{ 0x502, 0x2f }, { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 },
1290 	{ 0x506, 0x5e }, { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 },
1291 	{ 0x50a, 0x5e }, { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 },
1292 	{ 0x50e, 0x00 }, { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a },
1293 	{ 0x515, 0x10 }, { 0x516, 0x0a }, { 0x517, 0x10 }, { 0x51a, 0x16 },
1294 	{ 0x524, 0x0f }, { 0x525, 0x4f }, { 0x546, 0x40 }, { 0x547, 0x00 },
1295 	{ 0x550, 0x10 }, { 0x551, 0x10 }, { 0x559, 0x02 }, { 0x55a, 0x02 },
1296 	{ 0x55d, 0xff }, { 0x605, 0x30 }, { 0x608, 0x0e }, { 0x609, 0x2a },
1297 	{ 0x652, 0x20 }, { 0x63c, 0x0a }, { 0x63d, 0x0e }, { 0x63e, 0x0a },
1298 	{ 0x63f, 0x0e }, { 0x66e, 0x05 }, { 0x700, 0x21 }, { 0x701, 0x43 },
1299 	{ 0x702, 0x65 }, { 0x703, 0x87 }, { 0x708, 0x21 }, { 0x709, 0x43 },
1300 	{ 0x70a, 0x65 }, { 0x70b, 0x87 }
1301 };
1302 
1303 /*
1304  * Baseband initialization values.
1305  */
1306 struct urtwn_bb_prog {
1307 	int		count;
1308 	const uint16_t	*regs;
1309 	const uint32_t	*vals;
1310 	int		agccount;
1311 	const uint32_t	*agcvals;
1312 };
1313 
1314 /*
1315  * RTL8192CU and RTL8192CE-VAU.
1316  */
1317 static const uint16_t rtl8192ce_bb_regs[] = {
1318 	0x024, 0x028, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818,
1319 	0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c,
1320 	0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860,
1321 	0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884,
1322 	0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 0x908,
1323 	0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c,
1324 	0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 0xc08,
1325 	0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 0xc2c,
1326 	0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50,
1327 	0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74,
1328 	0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98,
1329 	0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc,
1330 	0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 0xce0,
1331 	0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14,
1332 	0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48,
1333 	0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 0xd6c,
1334 	0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 0xe18,
1335 	0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48,
1336 	0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70,
1337 	0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4,
1338 	0xed8, 0xedc, 0xee0, 0xeec, 0xf14, 0xf4c, 0xf00
1339 };
1340 
1341 static const uint32_t rtl8192ce_bb_vals[] = {
1342 	0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00,
1343 	0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000,
1344 	0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727,
1345 	0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000,
1346 	0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a,
1347 	0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27,
1348 	0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070,
1349 	0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe,
1350 	0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000,
1351 	0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f,
1352 	0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000,
1353 	0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007,
1354 	0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000,
1355 	0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000,
1356 	0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994,
1357 	0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f,
1358 	0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000,
1359 	0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db,
1360 	0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100,
1361 	0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f,
1362 	0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000,
1363 	0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000,
1364 	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427,
1365 	0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c,
1366 	0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333,
1367 	0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000,
1368 	0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000,
1369 	0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064,
1370 	0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e,
1371 	0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a,
1372 	0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000,
1373 	0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00,
1374 	0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f,
1375 	0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4,
1376 	0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4,
1377 	0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4,
1378 	0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003,
1379 	0x00000000, 0x00000300
1380 };
1381 
1382 static const uint32_t rtl8192ce_agc_vals[] = {
1383 	0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001,
1384 	0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001,
1385 	0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001,
1386 	0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001,
1387 	0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001,
1388 	0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001,
1389 	0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001,
1390 	0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001,
1391 	0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001,
1392 	0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001,
1393 	0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001,
1394 	0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001,
1395 	0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001,
1396 	0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001,
1397 	0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001,
1398 	0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001,
1399 	0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001,
1400 	0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001,
1401 	0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001,
1402 	0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001,
1403 	0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001,
1404 	0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001,
1405 	0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001,
1406 	0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001,
1407 	0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001,
1408 	0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e,
1409 	0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e,
1410 	0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e,
1411 	0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e,
1412 	0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e,
1413 	0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e,
1414 	0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e
1415 };
1416 
1417 static const struct urtwn_bb_prog rtl8192ce_bb_prog = {
1418 	nitems(rtl8192ce_bb_regs),
1419 	rtl8192ce_bb_regs,
1420 	rtl8192ce_bb_vals,
1421 	nitems(rtl8192ce_agc_vals),
1422 	rtl8192ce_agc_vals
1423 };
1424 
1425 /*
1426  * RTL8188CU.
1427  */
1428 static const uint32_t rtl8192cu_bb_vals[] = {
1429 	0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00,
1430 	0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000,
1431 	0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727,
1432 	0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000,
1433 	0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a,
1434 	0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27,
1435 	0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070,
1436 	0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe,
1437 	0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000,
1438 	0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f,
1439 	0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000,
1440 	0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007,
1441 	0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000,
1442 	0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000,
1443 	0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994,
1444 	0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f,
1445 	0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000,
1446 	0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x0186115b,
1447 	0x0000001f, 0x00b99612, 0x40000100, 0x20f60000, 0x40000100,
1448 	0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f,
1449 	0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000,
1450 	0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000,
1451 	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427,
1452 	0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c,
1453 	0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333,
1454 	0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000,
1455 	0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000,
1456 	0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064,
1457 	0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e,
1458 	0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a,
1459 	0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000,
1460 	0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00,
1461 	0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f,
1462 	0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4,
1463 	0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4,
1464 	0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4,
1465 	0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003,
1466 	0x00000000, 0x00000300
1467 };
1468 
1469 static const struct urtwn_bb_prog rtl8192cu_bb_prog = {
1470 	nitems(rtl8192ce_bb_regs),
1471 	rtl8192ce_bb_regs,
1472 	rtl8192cu_bb_vals,
1473 	nitems(rtl8192ce_agc_vals),
1474 	rtl8192ce_agc_vals
1475 };
1476 
1477 /*
1478  * RTL8188CE-VAU.
1479  */
1480 static const uint32_t rtl8188ce_bb_vals[] = {
1481 	0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00,
1482 	0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000,
1483 	0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000,
1484 	0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000,
1485 	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a,
1486 	0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200,
1487 	0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070,
1488 	0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe,
1489 	0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000,
1490 	0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f,
1491 	0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000,
1492 	0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007,
1493 	0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000,
1494 	0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000,
1495 	0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994,
1496 	0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f,
1497 	0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000,
1498 	0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db,
1499 	0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100,
1500 	0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f,
1501 	0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000,
1502 	0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000,
1503 	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427,
1504 	0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c,
1505 	0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333,
1506 	0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000,
1507 	0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000,
1508 	0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064,
1509 	0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e,
1510 	0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a,
1511 	0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000,
1512 	0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00,
1513 	0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f,
1514 	0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0,
1515 	0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0,
1516 	0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0,
1517 	0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003,
1518 	0x00000000, 0x00000300
1519 };
1520 
1521 static const uint32_t rtl8188ce_agc_vals[] = {
1522 	0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001,
1523 	0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001,
1524 	0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001,
1525 	0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001,
1526 	0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001,
1527 	0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001,
1528 	0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001,
1529 	0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001,
1530 	0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001,
1531 	0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001,
1532 	0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001,
1533 	0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001,
1534 	0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001,
1535 	0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001,
1536 	0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001,
1537 	0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001,
1538 	0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001,
1539 	0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001,
1540 	0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001,
1541 	0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001,
1542 	0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001,
1543 	0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001,
1544 	0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001,
1545 	0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001,
1546 	0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001,
1547 	0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e,
1548 	0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e,
1549 	0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e,
1550 	0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e,
1551 	0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e,
1552 	0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e,
1553 	0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e
1554 };
1555 
1556 static const struct urtwn_bb_prog rtl8188ce_bb_prog = {
1557 	nitems(rtl8192ce_bb_regs),
1558 	rtl8192ce_bb_regs,
1559 	rtl8188ce_bb_vals,
1560 	nitems(rtl8188ce_agc_vals),
1561 	rtl8188ce_agc_vals
1562 };
1563 
1564 static const uint32_t rtl8188cu_bb_vals[] = {
1565 	0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00,
1566 	0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000,
1567 	0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000,
1568 	0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000,
1569 	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a,
1570 	0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200,
1571 	0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070,
1572 	0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe,
1573 	0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000,
1574 	0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f,
1575 	0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000,
1576 	0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007,
1577 	0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000,
1578 	0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000,
1579 	0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994,
1580 	0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f,
1581 	0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000,
1582 	0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db,
1583 	0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100,
1584 	0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f,
1585 	0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000,
1586 	0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000,
1587 	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427,
1588 	0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c,
1589 	0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333,
1590 	0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000,
1591 	0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000,
1592 	0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064,
1593 	0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e,
1594 	0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a,
1595 	0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000,
1596 	0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00,
1597 	0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f,
1598 	0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0,
1599 	0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0,
1600 	0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0,
1601 	0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003,
1602 	0x00000000, 0x00000300
1603 };
1604 
1605 static const struct urtwn_bb_prog rtl8188cu_bb_prog = {
1606 	nitems(rtl8192ce_bb_regs),
1607 	rtl8192ce_bb_regs,
1608 	rtl8188cu_bb_vals,
1609 	nitems(rtl8188ce_agc_vals),
1610 	rtl8188ce_agc_vals
1611 };
1612 
1613 /*
1614  * RTL8188EU.
1615  */
1616 static const uint16_t rtl8188eu_bb_regs[] = {
1617 	0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 0x81c,
1618 	0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c,
1619 	0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c,
1620 	0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c,
1621 	0x880, 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c,
1622 	0x900, 0x904, 0x908, 0x90c, 0x910, 0x914, 0xa00, 0xa04,
1623 	0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 0xa20, 0xa24,
1624 	0xa28, 0xa2c, 0xa70, 0xa74, 0xa78, 0xa7c, 0xa80, 0xb2c,
1625 	0xc00, 0xc04, 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c,
1626 	0xc20, 0xc24, 0xc28, 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c,
1627 	0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 0xc54, 0xc58, 0xc5c,
1628 	0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 0xc78, 0xc7c,
1629 	0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 0xc9c,
1630 	0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc,
1631 	0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc,
1632 	0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c,
1633 	0xd10, 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c,
1634 	0xd40, 0xd44, 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c,
1635 	0xd60, 0xd64, 0xd68, 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00,
1636 	0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 0xe1c, 0xe28, 0xe30,
1637 	0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 0xe4c, 0xe50,
1638 	0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 0xe74,
1639 	0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4,
1640 	0xed8, 0xedc, 0xee0, 0xee8, 0xeec, 0xf14, 0xf4c, 0xf00
1641 };
1642 
1643 static const uint32_t rtl8188eu_bb_vals[] = {
1644 	0x80040000, 0x00000003, 0x0000fc00, 0x0000000a, 0x10001331,
1645 	0x020c3d10, 0x02200385, 0x00000000, 0x01000100, 0x00390204,
1646 	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1647 	0x00000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000,
1648 	0x00000000, 0x00000000, 0x569a11a9, 0x01000014, 0x66f60110,
1649 	0x061f0649, 0x00000000, 0x27272700, 0x07000760, 0x25004000,
1650 	0x00000808, 0x00000000, 0xb0000c1c, 0x00000001, 0x00000000,
1651 	0xccc000c0, 0x00000800, 0xfffffffe, 0x40302010, 0x00706050,
1652 	0x00000000, 0x00000023, 0x00000000, 0x81121111, 0x00000002,
1653 	0x00000201, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e7f120f,
1654 	0x9500bb78, 0x1114d028, 0x00881117, 0x89140f00, 0x1a1b0000,
1655 	0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007,
1656 	0x00000900, 0x225b0606, 0x218075b1, 0x80000000, 0x48071d40,
1657 	0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 0x40000100,
1658 	0x08800000, 0x40000100, 0x00000000, 0x00000000, 0x00000000,
1659 	0x00000000, 0x69e9ac47, 0x469652af, 0x49795994, 0x0a97971c,
1660 	0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 0x69553420,
1661 	0x43bc0094, 0x00013169, 0x00250492, 0x00000000, 0x7112848b,
1662 	0x47c00bff, 0x00000036, 0x2c7f000d, 0x020610db, 0x0000001f,
1663 	0x00b91612, 0x390000e4, 0x20f60000, 0x40000100, 0x20200000,
1664 	0x00091521, 0x00000000, 0x00121820, 0x00007f7f, 0x00000000,
1665 	0x000300a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1666 	0x00000000, 0x28000000, 0x00000000, 0x00000000, 0x00000000,
1667 	0x00000000, 0x00000000, 0x00000000, 0x64b22427, 0x00766932,
1668 	0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 0x00000740,
1669 	0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 0x3333bc43,
1670 	0x7a8f5b6f, 0xcc979975, 0x00000000, 0x80608000, 0x00000000,
1671 	0x00127353, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1672 	0x6437140a, 0x00000000, 0x00000282, 0x30032064, 0x4653de68,
1673 	0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 0x322c2220,
1674 	0x000e3c24, 0x2d2d2d2d, 0x2d2d2d2d, 0x0390272d, 0x2d2d2d2d,
1675 	0x2d2d2d2d, 0x2d2d2d2d, 0x2d2d2d2d, 0x00000000, 0x1000dc1f,
1676 	0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 0x01004800,
1677 	0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 0x02140102,
1678 	0x28160d05, 0x00000008, 0x001b25a4, 0x00c00014, 0x00c00014,
1679 	0x01000014, 0x01000014, 0x01000014, 0x01000014, 0x00c00014,
1680 	0x01000014, 0x00c00014, 0x00c00014, 0x00c00014, 0x00c00014,
1681 	0x00000014, 0x00000014, 0x21555448, 0x01c00014, 0x00000003,
1682 	0x00000000, 0x00000300
1683 };
1684 
1685 static const uint32_t rtl8188eu_agc_vals[] = {
1686 	0xfb000001, 0xfb010001, 0xfb020001, 0xfb030001, 0xfb040001,
1687 	0xfb050001, 0xfa060001, 0xf9070001, 0xf8080001, 0xf7090001,
1688 	0xf60a0001, 0xf50b0001, 0xf40c0001, 0xf30d0001, 0xf20e0001,
1689 	0xf10f0001, 0xf0100001, 0xef110001, 0xee120001, 0xed130001,
1690 	0xec140001, 0xeb150001, 0xea160001, 0xe9170001, 0xe8180001,
1691 	0xe7190001, 0xe61a0001, 0xe51b0001, 0xe41c0001, 0xe31d0001,
1692 	0xe21e0001, 0xe11f0001, 0x8a200001, 0x89210001, 0x88220001,
1693 	0x87230001, 0x86240001, 0x85250001, 0x84260001, 0x83270001,
1694 	0x82280001, 0x6b290001, 0x6a2a0001, 0x692b0001, 0x682c0001,
1695 	0x672d0001, 0x662e0001, 0x652f0001, 0x64300001, 0x63310001,
1696 	0x62320001, 0x61330001, 0x46340001, 0x45350001, 0x44360001,
1697 	0x43370001, 0x42380001, 0x41390001, 0x403a0001, 0x403b0001,
1698 	0x403c0001, 0x403d0001, 0x403e0001, 0x403f0001, 0xfb400001,
1699 	0xfb410001, 0xfb420001, 0xfb430001, 0xfb440001, 0xfb450001,
1700 	0xfb460001, 0xfb470001, 0xfb480001, 0xfa490001, 0xf94a0001,
1701 	0xf84B0001, 0xf74c0001, 0xf64d0001, 0xf54e0001, 0xf44f0001,
1702 	0xf3500001, 0xf2510001, 0xf1520001, 0xf0530001, 0xef540001,
1703 	0xee550001, 0xed560001, 0xec570001, 0xeb580001, 0xea590001,
1704 	0xe95a0001, 0xe85b0001, 0xe75c0001, 0xe65d0001, 0xe55e0001,
1705 	0xe45f0001, 0xe3600001, 0xe2610001, 0xc3620001, 0xc2630001,
1706 	0xc1640001, 0x8b650001, 0x8a660001, 0x89670001, 0x88680001,
1707 	0x87690001, 0x866a0001, 0x856b0001, 0x846c0001, 0x676d0001,
1708 	0x666e0001, 0x656f0001, 0x64700001, 0x63710001, 0x62720001,
1709 	0x61730001, 0x60740001, 0x46750001, 0x45760001, 0x44770001,
1710 	0x43780001, 0x42790001, 0x417a0001, 0x407b0001, 0x407c0001,
1711 	0x407d0001, 0x407e0001, 0x407f0001
1712 };
1713 
1714 static const struct urtwn_bb_prog rtl8188eu_bb_prog = {
1715 	nitems(rtl8188eu_bb_regs),
1716 	rtl8188eu_bb_regs,
1717 	rtl8188eu_bb_vals,
1718 	nitems(rtl8188eu_agc_vals),
1719 	rtl8188eu_agc_vals
1720 };
1721 
1722 /*
1723  * RTL8188RU.
1724  */
1725 static const uint16_t rtl8188ru_bb_regs[] = {
1726 	0x024, 0x028, 0x040, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814,
1727 	0x818, 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838,
1728 	0x83c, 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c,
1729 	0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880,
1730 	0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904,
1731 	0x908, 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18,
1732 	0xa1c, 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04,
1733 	0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28,
1734 	0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c,
1735 	0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70,
1736 	0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94,
1737 	0xc98, 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8,
1738 	0xcbc, 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc,
1739 	0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10,
1740 	0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44,
1741 	0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68,
1742 	0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14,
1743 	0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44,
1744 	0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c,
1745 	0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0,
1746 	0xed4, 0xed8, 0xedc, 0xee0, 0xeec, 0xee8, 0xf14, 0xf4c, 0xf00
1747 };
1748 
1749 static const uint32_t rtl8188ru_bb_vals[] = {
1750 	0x0011800d, 0x00ffdb83, 0x000c0004, 0x80040000, 0x00000001,
1751 	0x0000fc00, 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385,
1752 	0x00000000, 0x01000100, 0x00390204, 0x00000000, 0x00000000,
1753 	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010000,
1754 	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1755 	0x569a569a, 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000,
1756 	0x32323200, 0x03000300, 0x22004000, 0x00000808, 0x00ffc3f1,
1757 	0xc0083070, 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800,
1758 	0xfffffffe, 0x40302010, 0x00706050, 0x00000000, 0x00000023,
1759 	0x00000000, 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300,
1760 	0x2e68120f, 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00,
1761 	0x15160000, 0x070b0f12, 0x00000104, 0x00d30000, 0x101fbf00,
1762 	0x00000007, 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c,
1763 	0x08800000, 0x40000100, 0x08800000, 0x40000100, 0x00000000,
1764 	0x00000000, 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf,
1765 	0x49795994, 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107,
1766 	0x007f037f, 0x6954342e, 0x43bc0094, 0x6954342f, 0x433c0094,
1767 	0x00000000, 0x5116848b, 0x47c00bff, 0x00000036, 0x2c56000d,
1768 	0x018610db, 0x0000001f, 0x00b91612, 0x24000090, 0x20f60000,
1769 	0x24000090, 0x20200000, 0x00121820, 0x00000000, 0x00121820,
1770 	0x00007f7f, 0x00000000, 0x00000080, 0x00000000, 0x00000000,
1771 	0x00000000, 0x00000000, 0x00000000, 0x28000000, 0x00000000,
1772 	0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
1773 	0x64b22427, 0x00766932, 0x00222222, 0x00000000, 0x37644302,
1774 	0x2f97d40c, 0x00080740, 0x00020401, 0x0000907f, 0x20010201,
1775 	0xa0633333, 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000,
1776 	0x80608000, 0x00000000, 0x00027293, 0x00000000, 0x00000000,
1777 	0x00000000, 0x00000000, 0x6437140a, 0x00000000, 0x00000000,
1778 	0x30032064, 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16,
1779 	0x1812362e, 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a,
1780 	0x03902a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a,
1781 	0x00000000, 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2,
1782 	0x01007c00, 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f,
1783 	0x10008c1f, 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4,
1784 	0x631b25a0, 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0,
1785 	0x081b25a0, 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0,
1786 	0x631b25a0, 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0,
1787 	0x31555448, 0x00000003, 0x00000000, 0x00000300
1788 };
1789 
1790 static const uint32_t rtl8188ru_agc_vals[] = {
1791 	0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001,
1792 	0x7b050001, 0x7b060001, 0x7b070001, 0x7b080001, 0x7a090001,
1793 	0x790a0001, 0x780b0001, 0x770c0001, 0x760d0001, 0x750e0001,
1794 	0x740f0001, 0x73100001, 0x72110001, 0x71120001, 0x70130001,
1795 	0x6f140001, 0x6e150001, 0x6d160001, 0x6c170001, 0x6b180001,
1796 	0x6a190001, 0x691a0001, 0x681b0001, 0x671c0001, 0x661d0001,
1797 	0x651e0001, 0x641f0001, 0x63200001, 0x62210001, 0x61220001,
1798 	0x60230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001,
1799 	0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001,
1800 	0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001,
1801 	0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001,
1802 	0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001,
1803 	0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001,
1804 	0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001,
1805 	0x7b460001, 0x7b470001, 0x7b480001, 0x7a490001, 0x794a0001,
1806 	0x784b0001, 0x774c0001, 0x764d0001, 0x754e0001, 0x744f0001,
1807 	0x73500001, 0x72510001, 0x71520001, 0x70530001, 0x6f540001,
1808 	0x6e550001, 0x6d560001, 0x6c570001, 0x6b580001, 0x6a590001,
1809 	0x695a0001, 0x685b0001, 0x675c0001, 0x665d0001, 0x655e0001,
1810 	0x645f0001, 0x63600001, 0x62610001, 0x61620001, 0x60630001,
1811 	0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001,
1812 	0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001,
1813 	0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001,
1814 	0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001,
1815 	0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001,
1816 	0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e,
1817 	0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e,
1818 	0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e,
1819 	0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e,
1820 	0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e,
1821 	0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e,
1822 	0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e
1823 };
1824 
1825 static const struct urtwn_bb_prog rtl8188ru_bb_prog = {
1826 	nitems(rtl8188ru_bb_regs),
1827 	rtl8188ru_bb_regs,
1828 	rtl8188ru_bb_vals,
1829 	nitems(rtl8188ru_agc_vals),
1830 	rtl8188ru_agc_vals
1831 };
1832 
1833 /*
1834  * RF initialization values.
1835  */
1836 struct urtwn_rf_prog {
1837 	int		count;
1838 	const uint8_t	*regs;
1839 	const uint32_t	*vals;
1840 };
1841 
1842 /*
1843  * RTL8192CU and RTL8192CE-VAU.
1844  */
1845 static const uint8_t rtl8192ce_rf1_regs[] = {
1846 	0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e,
1847 	0x0f, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22,
1848 	0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2a, 0x2b,
1849 	0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b,
1850 	0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b,
1851 	0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a,
1852 	0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c,
1853 	0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b,
1854 	0x2c, 0x2a, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10,
1855 	0x11, 0x10, 0x11, 0x10, 0x11, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13,
1856 	0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14,
1857 	0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x00,
1858 	0x18, 0xfe, 0xfe, 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00
1859 };
1860 
1861 static const uint32_t rtl8192ce_rf1_vals[] = {
1862 	0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1,
1863 	0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255,
1864 	0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000,
1865 	0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0,
1866 	0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808,
1867 	0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003,
1868 	0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d,
1869 	0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333,
1870 	0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a,
1871 	0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a,
1872 	0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d,
1873 	0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333,
1874 	0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f,
1875 	0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500,
1876 	0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000,
1877 	0x71000, 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f,
1878 	0x18493, 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c,
1879 	0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424,
1880 	0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401,
1881 	0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000,
1882 	0x30159
1883 };
1884 
1885 static const uint8_t rtl8192ce_rf2_regs[] = {
1886 	0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e,
1887 	0x0f, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
1888 	0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 0x14, 0x14, 0x15, 0x15,
1889 	0x15, 0x15, 0x16, 0x16, 0x16, 0x16
1890 };
1891 
1892 static const uint32_t rtl8192ce_rf2_vals[] = {
1893 	0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1,
1894 	0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x32000, 0x71000,
1895 	0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 0x18493,
1896 	0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 0x1944c,
1897 	0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 0xcf424,
1898 	0xe0330, 0xa0330, 0x60330, 0x20330
1899 };
1900 
1901 static const struct urtwn_rf_prog rtl8192ce_rf_prog[] = {
1902 	{
1903 		nitems(rtl8192ce_rf1_regs),
1904 		rtl8192ce_rf1_regs,
1905 		rtl8192ce_rf1_vals
1906 	},
1907 	{
1908 		nitems(rtl8192ce_rf2_regs),
1909 		rtl8192ce_rf2_regs,
1910 		rtl8192ce_rf2_vals
1911 	}
1912 };
1913 
1914 /*
1915  * RTL8188CE-VAU.
1916  */
1917 static const uint32_t rtl8188ce_rf_vals[] = {
1918 	0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1,
1919 	0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255,
1920 	0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000,
1921 	0x00000, 0x01558, 0x00060, 0x00483, 0x4f200, 0xec7d9, 0x577c0,
1922 	0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808,
1923 	0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003,
1924 	0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d,
1925 	0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333,
1926 	0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a,
1927 	0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a,
1928 	0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d,
1929 	0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333,
1930 	0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f,
1931 	0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500,
1932 	0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000,
1933 	0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f,
1934 	0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020,
1935 	0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424,
1936 	0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401,
1937 	0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000,
1938 	0x30159
1939 };
1940 
1941 static const struct urtwn_rf_prog rtl8188ce_rf_prog[] = {
1942 	{
1943 		nitems(rtl8192ce_rf1_regs),
1944 		rtl8192ce_rf1_regs,
1945 		rtl8188ce_rf_vals
1946 	}
1947 };
1948 
1949 
1950 /*
1951  * RTL8188CU.
1952  */
1953 static const uint32_t rtl8188cu_rf_vals[] = {
1954 	0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1,
1955 	0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255,
1956 	0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000,
1957 	0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0,
1958 	0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808,
1959 	0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003,
1960 	0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d,
1961 	0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333,
1962 	0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a,
1963 	0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a,
1964 	0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d,
1965 	0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333,
1966 	0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f,
1967 	0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500,
1968 	0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000,
1969 	0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f,
1970 	0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020,
1971 	0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405,
1972 	0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401,
1973 	0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000,
1974 	0x30159
1975 };
1976 
1977 static const struct urtwn_rf_prog rtl8188cu_rf_prog[] = {
1978 	{
1979 		nitems(rtl8192ce_rf1_regs),
1980 		rtl8192ce_rf1_regs,
1981 		rtl8188cu_rf_vals
1982 	}
1983 };
1984 
1985 /*
1986  * RTL8188EU.
1987  */
1988 static const uint8_t rtl8188eu_rf_regs[] = {
1989 	0x00, 0x08, 0x18, 0x19, 0x1e, 0x1f, 0x2f, 0x3f, 0x42, 0x57,
1990 	0x58, 0x67, 0x83, 0xb0, 0xb1, 0xb2, 0xb4, 0xb6, 0xb7, 0xb8,
1991 	0xb9, 0xba, 0xbb, 0xbf, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
1992 	0xc8, 0xc9, 0xca, 0xdf, 0xef, 0x51, 0x52, 0x53, 0x56,
1993 	0x35, 0x35, 0x35, 0x36, 0x36, 0x36, 0x36, 0xb6, 0x18, 0x5a,
1994 	0x19, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34,
1995 	0x34, 0x34, 0x00, 0x84, 0x86, 0x87, 0x8e, 0x8f, 0xef, 0x3b,
1996 	0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b,
1997 	0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0xef, 0x00, 0x18, 0xfe, 0xfe,
1998 	0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00
1999 };
2000 
2001 static const uint32_t rtl8188eu_rf_vals[] = {
2002 	0x30000, 0x84000, 0x00407, 0x00012, 0x80009, 0x00880, 0x1a060,
2003 	0x00000, 0x060c0, 0xd0000, 0xbe180, 0x01552, 0x00000, 0xff8fc,
2004 	0x54400, 0xccc19, 0x43003, 0x4953e, 0x1c718, 0x060ff, 0x80001,
2005 	0x40000, 0x00400, 0xc0000, 0x02400, 0x00009, 0x40c91, 0x99999,
2006 	0x000a3, 0x88820, 0x76c06, 0x00000, 0x80000, 0x00180, 0x001a0,
2007 	0x6b27d, 0x7e49d, 0x00073, 0x51ff3, 0x00086, 0x00186,
2008 	0x00286, 0x01c25, 0x09c25, 0x11c25, 0x19c25, 0x48538, 0x00c07,
2009 	0x4bd00, 0x739d0, 0x0adf3, 0x09df0, 0x08ded, 0x07dea, 0x06de7,
2010 	0x054ee, 0x044eb, 0x034e8, 0x0246b, 0x01468, 0x0006d, 0x30159,
2011 	0x68200, 0x000ce, 0x48a00, 0x65540, 0x88000, 0x020a0, 0xf02b0,
2012 	0xef7b0, 0xd4fb0, 0xcf060, 0xb0090, 0xa0080, 0x90080, 0x8f780,
2013 	0x722b0, 0x6f7b0, 0x54fb0, 0x4f060, 0x30090, 0x20080, 0x10080,
2014 	0x0f780, 0x000a0, 0x10159, 0x0f407, 0x00000, 0x00000, 0x80003,
2015 	0x00000, 0x00000, 0x00001, 0x80000, 0x33e60
2016 };
2017 
2018 static const struct urtwn_rf_prog rtl8188eu_rf_prog[] = {
2019 	{
2020 		nitems(rtl8188eu_rf_regs),
2021 		rtl8188eu_rf_regs,
2022 		rtl8188eu_rf_vals
2023 	}
2024 };
2025 
2026 /*
2027  * RTL8188RU.
2028  */
2029 static const uint32_t rtl8188ru_rf_vals[] = {
2030 	0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb0,
2031 	0x54867, 0x8992e, 0x0e529, 0x39ce7, 0x00451, 0x00000, 0x00255,
2032 	0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000,
2033 	0x0083c, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x977c0,
2034 	0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808,
2035 	0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003,
2036 	0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d,
2037 	0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333,
2038 	0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a,
2039 	0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a,
2040 	0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d,
2041 	0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333,
2042 	0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f,
2043 	0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500,
2044 	0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0xd8000,
2045 	0x90000, 0x51000, 0x12000, 0x28fb4, 0x24fa8, 0x207a4, 0x1c798,
2046 	0x183a4, 0x14398, 0x101a4, 0x0c198, 0x080a4, 0x04098, 0x00014,
2047 	0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405,
2048 	0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401,
2049 	0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000,
2050 	0x30159
2051 };
2052 
2053 static const struct urtwn_rf_prog rtl8188ru_rf_prog[] = {
2054 	{
2055 		nitems(rtl8192ce_rf1_regs),
2056 		rtl8192ce_rf1_regs,
2057 		rtl8188ru_rf_vals
2058 	}
2059 };
2060 
2061 struct urtwn_txpwr {
2062 	uint8_t	pwr[3][28];
2063 };
2064 
2065 struct urtwn_r88e_txpwr {
2066 	uint8_t	pwr[6][28];
2067 };
2068 
2069 /*
2070  * Per RF chain/group/rate Tx gain values.
2071  */
2072 static const struct urtwn_txpwr rtl8192cu_txagc[] = {
2073 	{ {	/* Chain 0. */
2074 	{	/* Group 0. */
2075 	0x00, 0x00, 0x00, 0x00,				/* CCK1~11. */
2076 	0x0c, 0x0c, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02,	/* OFDM6~54. */
2077 	0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02,	/* MCS0~7. */
2078 	0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02	/* MCS8~15. */
2079 	},
2080 	{	/* Group 1. */
2081 	0x00, 0x00, 0x00, 0x00,				/* CCK1~11. */
2082 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* OFDM6~54. */
2083 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* MCS0~7. */
2084 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00	/* MCS8~15. */
2085 	},
2086 	{	/* Group 2. */
2087 	0x00, 0x00, 0x00, 0x00,				/* CCK1~11. */
2088 	0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00,	/* OFDM6~54. */
2089 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* MCS0~7. */
2090 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00	/* MCS8~15. */
2091 	}
2092 	} },
2093 	{ {	/* Chain 1. */
2094 	{	/* Group 0. */
2095 	0x00, 0x00, 0x00, 0x00,				/* CCK1~11. */
2096 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* OFDM6~54. */
2097 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* MCS0~7. */
2098 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00	/* MCS8~15. */
2099 	},
2100 	{	/* Group 1. */
2101 	0x00, 0x00, 0x00, 0x00,				/* CCK1~11. */
2102 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* OFDM6~54. */
2103 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* MCS0~7. */
2104 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00	/* MCS8~15. */
2105 	},
2106 	{	/* Group 2. */
2107 	0x00, 0x00, 0x00, 0x00,				/* CCK1~11. */
2108 	0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00,	/* OFDM6~54. */
2109 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* MCS0~7. */
2110 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00	/* MCS8~15. */
2111 	}
2112 	} }
2113 };
2114 
2115 static const struct urtwn_txpwr rtl8188ru_txagc[] = {
2116 	{ {	/* Chain 0. */
2117 	{	/* Group 0. */
2118 	0x00, 0x00, 0x00, 0x00,				/* CCK1~11. */
2119 	0x08, 0x08, 0x08, 0x06, 0x06, 0x04, 0x04, 0x00,	/* OFDM6~54. */
2120 	0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00,	/* MCS0~7. */
2121 	0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00	/* MCS8~15. */
2122 	},
2123 	{	/* Group 1. */
2124 	0x00, 0x00, 0x00, 0x00,				/* CCK1~11. */
2125 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* OFDM6~54. */
2126 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* MCS0~7. */
2127 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00	/* MCS8~15. */
2128 	},
2129 	{	/* Group 2. */
2130 	0x00, 0x00, 0x00, 0x00,				/* CCK1~11. */
2131 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* OFDM6~54. */
2132 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* MCS0~7. */
2133 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00	/* MCS8~15. */
2134 	}
2135 	} }
2136 };
2137 
2138 static const struct urtwn_r88e_txpwr rtl8188eu_txagc[] = {
2139 	{ {	/* Chain 0. */
2140 	{	/* Group 0. */
2141 	0x00, 0x00, 0x00, 0x00,				/* CCK1~11. */
2142 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* OFDM6~54. */
2143 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* MCS0~7. */
2144 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00	/* MCS8~15. */
2145 	},
2146 	{	/* Group 1. */
2147 	0x00, 0x00, 0x00, 0x00,				/* CCK1~11. */
2148 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* OFDM6~54. */
2149 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* MCS0~7. */
2150 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00	/* MCS8~15. */
2151 	},
2152 	{	/* Group 2. */
2153 	0x00, 0x00, 0x00, 0x00,				/* CCK1~11. */
2154 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* OFDM6~54. */
2155 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* MCS0~7. */
2156 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00	/* MCS8~15. */
2157 	},
2158 	{	/* Group 3. */
2159 	0x00, 0x00, 0x00, 0x00,				/* CCK1~11. */
2160 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* OFDM6~54. */
2161 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* MCS0~7. */
2162 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00	/* MCS8~15. */
2163 	},
2164 	{	/* Group 4. */
2165 	0x00, 0x00, 0x00, 0x00,				/* CCK1~11. */
2166 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* OFDM6~54. */
2167 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* MCS0~7. */
2168 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00	/* MCS8~15. */
2169 	},
2170 	{	/* Group 5. */
2171 	0x00, 0x00, 0x00, 0x00,				/* CCK1~11. */
2172 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* OFDM6~54. */
2173 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	/* MCS0~7. */
2174 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00	/* MCS8~15. */
2175 	}
2176 	} }
2177 };
2178