1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include "coex.h"
6 #include "fw.h"
7 #include "mac.h"
8 #include "phy.h"
9 #include "reg.h"
10 #include "rtw8852a.h"
11 #include "rtw8852a_rfk.h"
12 #include "rtw8852a_table.h"
13 #include "txrx.h"
14
15 #define RTW8852A_FW_FORMAT_MAX 0
16 #define RTW8852A_FW_BASENAME "rtw89/rtw8852a_fw"
17 #define RTW8852A_MODULE_FIRMWARE \
18 RTW8852A_FW_BASENAME ".bin"
19
20 static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = {
21 {128, 1896, grp_0}, /* ACH 0 */
22 {128, 1896, grp_0}, /* ACH 1 */
23 {128, 1896, grp_0}, /* ACH 2 */
24 {128, 1896, grp_0}, /* ACH 3 */
25 {128, 1896, grp_1}, /* ACH 4 */
26 {128, 1896, grp_1}, /* ACH 5 */
27 {128, 1896, grp_1}, /* ACH 6 */
28 {128, 1896, grp_1}, /* ACH 7 */
29 {32, 1896, grp_0}, /* B0MGQ */
30 {128, 1896, grp_0}, /* B0HIQ */
31 {32, 1896, grp_1}, /* B1MGQ */
32 {128, 1896, grp_1}, /* B1HIQ */
33 {40, 0, 0} /* FWCMDQ */
34 };
35
36 static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = {
37 1896, /* Group 0 */
38 1896, /* Group 1 */
39 3792, /* Public Max */
40 0 /* WP threshold */
41 };
42
43 static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = {
44 [RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie,
45 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
46 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
47 RTW89_HCIFC_POH},
48 [RTW89_QTA_INVALID] = {NULL},
49 };
50
51 static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = {
52 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size0,
53 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
54 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
55 &rtw89_mac_size.ple_qt5},
56 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size0,
57 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0,
58 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4,
59 &rtw89_mac_size.ple_qt_52a_wow},
60 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4,
61 &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4,
62 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
63 &rtw89_mac_size.ple_qt13},
64 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
65 NULL},
66 };
67
68 static const struct rtw89_reg2_def rtw8852a_pmac_ht20_mcs7_tbl[] = {
69 {0x44AC, 0x00000000},
70 {0x44B0, 0x00000000},
71 {0x44B4, 0x00000000},
72 {0x44B8, 0x00000000},
73 {0x44BC, 0x00000000},
74 {0x44C0, 0x00000000},
75 {0x44C4, 0x00000000},
76 {0x44C8, 0x00000000},
77 {0x44CC, 0x00000000},
78 {0x44D0, 0x00000000},
79 {0x44D4, 0x00000000},
80 {0x44D8, 0x00000000},
81 {0x44DC, 0x00000000},
82 {0x44E0, 0x00000000},
83 {0x44E4, 0x00000000},
84 {0x44E8, 0x00000000},
85 {0x44EC, 0x00000000},
86 {0x44F0, 0x00000000},
87 {0x44F4, 0x00000000},
88 {0x44F8, 0x00000000},
89 {0x44FC, 0x00000000},
90 {0x4500, 0x00000000},
91 {0x4504, 0x00000000},
92 {0x4508, 0x00000000},
93 {0x450C, 0x00000000},
94 {0x4510, 0x00000000},
95 {0x4514, 0x00000000},
96 {0x4518, 0x00000000},
97 {0x451C, 0x00000000},
98 {0x4520, 0x00000000},
99 {0x4524, 0x00000000},
100 {0x4528, 0x00000000},
101 {0x452C, 0x00000000},
102 {0x4530, 0x4E1F3E81},
103 {0x4534, 0x00000000},
104 {0x4538, 0x0000005A},
105 {0x453C, 0x00000000},
106 {0x4540, 0x00000000},
107 {0x4544, 0x00000000},
108 {0x4548, 0x00000000},
109 {0x454C, 0x00000000},
110 {0x4550, 0x00000000},
111 {0x4554, 0x00000000},
112 {0x4558, 0x00000000},
113 {0x455C, 0x00000000},
114 {0x4560, 0x4060001A},
115 {0x4564, 0x40000000},
116 {0x4568, 0x00000000},
117 {0x456C, 0x00000000},
118 {0x4570, 0x04000007},
119 {0x4574, 0x0000DC87},
120 {0x4578, 0x00000BAB},
121 {0x457C, 0x03E00000},
122 {0x4580, 0x00000048},
123 {0x4584, 0x00000000},
124 {0x4588, 0x000003E8},
125 {0x458C, 0x30000000},
126 {0x4590, 0x00000000},
127 {0x4594, 0x10000000},
128 {0x4598, 0x00000001},
129 {0x459C, 0x00030000},
130 {0x45A0, 0x01000000},
131 {0x45A4, 0x03000200},
132 {0x45A8, 0xC00001C0},
133 {0x45AC, 0x78018000},
134 {0x45B0, 0x80000000},
135 {0x45B4, 0x01C80600},
136 {0x45B8, 0x00000002},
137 {0x4594, 0x10000000}
138 };
139
140 static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = {
141 {0x4624, GENMASK(20, 14), 0x40},
142 {0x46f8, GENMASK(20, 14), 0x40},
143 {0x4674, GENMASK(20, 19), 0x2},
144 {0x4748, GENMASK(20, 19), 0x2},
145 {0x4650, GENMASK(14, 10), 0x18},
146 {0x4724, GENMASK(14, 10), 0x18},
147 {0x4688, GENMASK(1, 0), 0x3},
148 {0x475c, GENMASK(1, 0), 0x3},
149 };
150
151 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs);
152
153 static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = {
154 {0x4624, GENMASK(20, 14), 0x1a},
155 {0x46f8, GENMASK(20, 14), 0x1a},
156 {0x4674, GENMASK(20, 19), 0x1},
157 {0x4748, GENMASK(20, 19), 0x1},
158 {0x4650, GENMASK(14, 10), 0x12},
159 {0x4724, GENMASK(14, 10), 0x12},
160 {0x4688, GENMASK(1, 0), 0x0},
161 {0x475c, GENMASK(1, 0), 0x0},
162 };
163
164 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs);
165
166 static const struct rtw89_pwr_cfg rtw8852a_pwron[] = {
167 {0x00C6,
168 PWR_CV_MSK_B,
169 PWR_INTF_MSK_PCIE,
170 PWR_BASE_MAC,
171 PWR_CMD_WRITE, BIT(6), BIT(6)},
172 {0x1086,
173 PWR_CV_MSK_ALL,
174 PWR_INTF_MSK_SDIO,
175 PWR_BASE_MAC,
176 PWR_CMD_WRITE, BIT(0), 0},
177 {0x1086,
178 PWR_CV_MSK_ALL,
179 PWR_INTF_MSK_SDIO,
180 PWR_BASE_MAC,
181 PWR_CMD_POLL, BIT(1), BIT(1)},
182 {0x0005,
183 PWR_CV_MSK_ALL,
184 PWR_INTF_MSK_ALL,
185 PWR_BASE_MAC,
186 PWR_CMD_WRITE, BIT(4) | BIT(3), 0},
187 {0x0005,
188 PWR_CV_MSK_ALL,
189 PWR_INTF_MSK_ALL,
190 PWR_BASE_MAC,
191 PWR_CMD_WRITE, BIT(7), 0},
192 {0x0005,
193 PWR_CV_MSK_ALL,
194 PWR_INTF_MSK_ALL,
195 PWR_BASE_MAC,
196 PWR_CMD_WRITE, BIT(2), 0},
197 {0x0006,
198 PWR_CV_MSK_ALL,
199 PWR_INTF_MSK_ALL,
200 PWR_BASE_MAC,
201 PWR_CMD_POLL, BIT(1), BIT(1)},
202 {0x0006,
203 PWR_CV_MSK_ALL,
204 PWR_INTF_MSK_ALL,
205 PWR_BASE_MAC,
206 PWR_CMD_WRITE, BIT(0), BIT(0)},
207 {0x0005,
208 PWR_CV_MSK_ALL,
209 PWR_INTF_MSK_ALL,
210 PWR_BASE_MAC,
211 PWR_CMD_WRITE, BIT(0), BIT(0)},
212 {0x0005,
213 PWR_CV_MSK_ALL,
214 PWR_INTF_MSK_ALL,
215 PWR_BASE_MAC,
216 PWR_CMD_POLL, BIT(0), 0},
217 {0x106D,
218 PWR_CV_MSK_B | PWR_CV_MSK_C,
219 PWR_INTF_MSK_USB,
220 PWR_BASE_MAC,
221 PWR_CMD_WRITE, BIT(6), 0},
222 {0x0088,
223 PWR_CV_MSK_ALL,
224 PWR_INTF_MSK_ALL,
225 PWR_BASE_MAC,
226 PWR_CMD_WRITE, BIT(0), BIT(0)},
227 {0x0088,
228 PWR_CV_MSK_ALL,
229 PWR_INTF_MSK_ALL,
230 PWR_BASE_MAC,
231 PWR_CMD_WRITE, BIT(0), 0},
232 {0x0088,
233 PWR_CV_MSK_ALL,
234 PWR_INTF_MSK_ALL,
235 PWR_BASE_MAC,
236 PWR_CMD_WRITE, BIT(0), BIT(0)},
237 {0x0088,
238 PWR_CV_MSK_ALL,
239 PWR_INTF_MSK_ALL,
240 PWR_BASE_MAC,
241 PWR_CMD_WRITE, BIT(0), 0},
242 {0x0088,
243 PWR_CV_MSK_ALL,
244 PWR_INTF_MSK_ALL,
245 PWR_BASE_MAC,
246 PWR_CMD_WRITE, BIT(0), BIT(0)},
247 {0x0083,
248 PWR_CV_MSK_ALL,
249 PWR_INTF_MSK_ALL,
250 PWR_BASE_MAC,
251 PWR_CMD_WRITE, BIT(6), 0},
252 {0x0080,
253 PWR_CV_MSK_ALL,
254 PWR_INTF_MSK_ALL,
255 PWR_BASE_MAC,
256 PWR_CMD_WRITE, BIT(5), BIT(5)},
257 {0x0024,
258 PWR_CV_MSK_ALL,
259 PWR_INTF_MSK_ALL,
260 PWR_BASE_MAC,
261 PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0},
262 {0x02A0,
263 PWR_CV_MSK_ALL,
264 PWR_INTF_MSK_ALL,
265 PWR_BASE_MAC,
266 PWR_CMD_WRITE, BIT(1), BIT(1)},
267 {0x02A2,
268 PWR_CV_MSK_ALL,
269 PWR_INTF_MSK_ALL,
270 PWR_BASE_MAC,
271 PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0},
272 {0x0071,
273 PWR_CV_MSK_ALL,
274 PWR_INTF_MSK_PCIE,
275 PWR_BASE_MAC,
276 PWR_CMD_WRITE, BIT(4), 0},
277 {0x0010,
278 PWR_CV_MSK_A,
279 PWR_INTF_MSK_PCIE,
280 PWR_BASE_MAC,
281 PWR_CMD_WRITE, BIT(2), BIT(2)},
282 {0x02A0,
283 PWR_CV_MSK_A,
284 PWR_INTF_MSK_ALL,
285 PWR_BASE_MAC,
286 PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
287 {0xFFFF,
288 PWR_CV_MSK_ALL,
289 PWR_INTF_MSK_ALL,
290 0,
291 PWR_CMD_END, 0, 0},
292 };
293
294 static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = {
295 {0x02F0,
296 PWR_CV_MSK_ALL,
297 PWR_INTF_MSK_ALL,
298 PWR_BASE_MAC,
299 PWR_CMD_WRITE, 0xFF, 0},
300 {0x02F1,
301 PWR_CV_MSK_ALL,
302 PWR_INTF_MSK_ALL,
303 PWR_BASE_MAC,
304 PWR_CMD_WRITE, 0xFF, 0},
305 {0x0006,
306 PWR_CV_MSK_ALL,
307 PWR_INTF_MSK_ALL,
308 PWR_BASE_MAC,
309 PWR_CMD_WRITE, BIT(0), BIT(0)},
310 {0x0002,
311 PWR_CV_MSK_ALL,
312 PWR_INTF_MSK_ALL,
313 PWR_BASE_MAC,
314 PWR_CMD_WRITE, BIT(1) | BIT(0), 0},
315 {0x0082,
316 PWR_CV_MSK_ALL,
317 PWR_INTF_MSK_ALL,
318 PWR_BASE_MAC,
319 PWR_CMD_WRITE, BIT(1) | BIT(0), 0},
320 {0x106D,
321 PWR_CV_MSK_B | PWR_CV_MSK_C,
322 PWR_INTF_MSK_USB,
323 PWR_BASE_MAC,
324 PWR_CMD_WRITE, BIT(6), BIT(6)},
325 {0x0005,
326 PWR_CV_MSK_ALL,
327 PWR_INTF_MSK_ALL,
328 PWR_BASE_MAC,
329 PWR_CMD_WRITE, BIT(1), BIT(1)},
330 {0x0005,
331 PWR_CV_MSK_ALL,
332 PWR_INTF_MSK_ALL,
333 PWR_BASE_MAC,
334 PWR_CMD_POLL, BIT(1), 0},
335 {0x0091,
336 PWR_CV_MSK_ALL,
337 PWR_INTF_MSK_PCIE,
338 PWR_BASE_MAC,
339 PWR_CMD_WRITE, BIT(0), 0},
340 {0x0005,
341 PWR_CV_MSK_ALL,
342 PWR_INTF_MSK_PCIE,
343 PWR_BASE_MAC,
344 PWR_CMD_WRITE, BIT(2), BIT(2)},
345 {0x0007,
346 PWR_CV_MSK_ALL,
347 PWR_INTF_MSK_USB,
348 PWR_BASE_MAC,
349 PWR_CMD_WRITE, BIT(4), 0},
350 {0x0007,
351 PWR_CV_MSK_ALL,
352 PWR_INTF_MSK_SDIO,
353 PWR_BASE_MAC,
354 PWR_CMD_WRITE, BIT(6) | BIT(4), 0},
355 {0x0005,
356 PWR_CV_MSK_ALL,
357 PWR_INTF_MSK_SDIO,
358 PWR_BASE_MAC,
359 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)},
360 {0x0005,
361 PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F |
362 PWR_CV_MSK_G,
363 PWR_INTF_MSK_USB,
364 PWR_BASE_MAC,
365 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)},
366 {0x1086,
367 PWR_CV_MSK_ALL,
368 PWR_INTF_MSK_SDIO,
369 PWR_BASE_MAC,
370 PWR_CMD_WRITE, BIT(0), BIT(0)},
371 {0x1086,
372 PWR_CV_MSK_ALL,
373 PWR_INTF_MSK_SDIO,
374 PWR_BASE_MAC,
375 PWR_CMD_POLL, BIT(1), 0},
376 {0xFFFF,
377 PWR_CV_MSK_ALL,
378 PWR_INTF_MSK_ALL,
379 0,
380 PWR_CMD_END, 0, 0},
381 };
382
383 static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = {
384 rtw8852a_pwron, NULL
385 };
386
387 static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = {
388 rtw8852a_pwroff, NULL
389 };
390
391 static const u32 rtw8852a_h2c_regs[RTW89_H2CREG_MAX] = {
392 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2,
393 R_AX_H2CREG_DATA3
394 };
395
396 static const u32 rtw8852a_c2h_regs[RTW89_C2HREG_MAX] = {
397 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2,
398 R_AX_C2HREG_DATA3
399 };
400
401 static const struct rtw89_page_regs rtw8852a_page_regs = {
402 .hci_fc_ctrl = R_AX_HCI_FC_CTRL,
403 .ch_page_ctrl = R_AX_CH_PAGE_CTRL,
404 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL,
405 .ach_page_info = R_AX_ACH0_PAGE_INFO,
406 .pub_page_info3 = R_AX_PUB_PAGE_INFO3,
407 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1,
408 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2,
409 .pub_page_info1 = R_AX_PUB_PAGE_INFO1,
410 .pub_page_info2 = R_AX_PUB_PAGE_INFO2,
411 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1,
412 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2,
413 .wp_page_info1 = R_AX_WP_PAGE_INFO1,
414 };
415
416 static const struct rtw89_reg_def rtw8852a_dcfo_comp = {
417 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK
418 };
419
420 static const struct rtw89_imr_info rtw8852a_imr_info = {
421 .wdrls_imr_set = B_AX_WDRLS_IMR_SET,
422 .wsec_imr_reg = R_AX_SEC_DEBUG,
423 .wsec_imr_set = B_AX_IMR_ERROR,
424 .mpdu_tx_imr_set = 0,
425 .mpdu_rx_imr_set = 0,
426 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET,
427 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR,
428 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR,
429 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET,
430 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1,
431 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR,
432 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET,
433 .wde_imr_clr = B_AX_WDE_IMR_CLR,
434 .wde_imr_set = B_AX_WDE_IMR_SET,
435 .ple_imr_clr = B_AX_PLE_IMR_CLR,
436 .ple_imr_set = B_AX_PLE_IMR_SET,
437 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR,
438 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET,
439 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR,
440 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET,
441 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR,
442 .other_disp_imr_set = 0,
443 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR,
444 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
445 .bbrpt_err_imr_set = 0,
446 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR,
447 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR,
448 .ptcl_imr_set = B_AX_PTCL_IMR_SET,
449 .cdma_imr_0_reg = R_AX_DLE_CTRL,
450 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR,
451 .cdma_imr_0_set = B_AX_DLE_IMR_SET,
452 .cdma_imr_1_reg = 0,
453 .cdma_imr_1_clr = 0,
454 .cdma_imr_1_set = 0,
455 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR,
456 .phy_intf_imr_clr = 0,
457 .phy_intf_imr_set = 0,
458 .rmac_imr_reg = R_AX_RMAC_ERR_ISR,
459 .rmac_imr_clr = B_AX_RMAC_IMR_CLR,
460 .rmac_imr_set = B_AX_RMAC_IMR_SET,
461 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR,
462 .tmac_imr_clr = B_AX_TMAC_IMR_CLR,
463 .tmac_imr_set = B_AX_TMAC_IMR_SET,
464 };
465
466 static const struct rtw89_xtal_info rtw8852a_xtal_info = {
467 .xcap_reg = R_AX_XTAL_ON_CTRL0,
468 .sc_xo_mask = B_AX_XTAL_SC_XO_MASK,
469 .sc_xi_mask = B_AX_XTAL_SC_XI_MASK,
470 };
471
472 static const struct rtw89_rrsr_cfgs rtw8852a_rrsr_cfgs = {
473 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
474 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
475 };
476
477 static const struct rtw89_dig_regs rtw8852a_dig_regs = {
478 .seg0_pd_reg = R_SEG0R_PD,
479 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
480 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK,
481 .p0_lna_init = {R_PATH0_LNA_INIT, B_PATH0_LNA_INIT_IDX_MSK},
482 .p1_lna_init = {R_PATH1_LNA_INIT, B_PATH1_LNA_INIT_IDX_MSK},
483 .p0_tia_init = {R_PATH0_TIA_INIT, B_PATH0_TIA_INIT_IDX_MSK},
484 .p1_tia_init = {R_PATH1_TIA_INIT, B_PATH1_TIA_INIT_IDX_MSK},
485 .p0_rxb_init = {R_PATH0_RXB_INIT, B_PATH0_RXB_INIT_IDX_MSK},
486 .p1_rxb_init = {R_PATH1_RXB_INIT, B_PATH1_RXB_INIT_IDX_MSK},
487 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC,
488 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
489 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC,
490 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
491 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC,
492 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
493 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC,
494 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
495 };
496
rtw8852ae_efuse_parsing(struct rtw89_efuse * efuse,struct rtw8852a_efuse * map)497 static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse,
498 struct rtw8852a_efuse *map)
499 {
500 ether_addr_copy(efuse->addr, map->e.mac_addr);
501 efuse->rfe_type = map->rfe_type;
502 efuse->xtal_cap = map->xtal_k;
503 }
504
rtw8852a_efuse_parsing_tssi(struct rtw89_dev * rtwdev,struct rtw8852a_efuse * map)505 static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
506 struct rtw8852a_efuse *map)
507 {
508 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
509 struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
510 u8 i, j;
511
512 tssi->thermal[RF_PATH_A] = map->path_a_therm;
513 tssi->thermal[RF_PATH_B] = map->path_b_therm;
514
515 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
516 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
517 sizeof(ofst[i]->cck_tssi));
518
519 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
520 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
521 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
522 i, j, tssi->tssi_cck[i][j]);
523
524 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
525 sizeof(ofst[i]->bw40_tssi));
526 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
527 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
528
529 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
530 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
531 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
532 i, j, tssi->tssi_mcs[i][j]);
533 }
534 }
535
rtw8852a_read_efuse(struct rtw89_dev * rtwdev,u8 * log_map)536 static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map)
537 {
538 struct rtw89_efuse *efuse = &rtwdev->efuse;
539 struct rtw8852a_efuse *map;
540
541 map = (struct rtw8852a_efuse *)log_map;
542
543 efuse->country_code[0] = map->country_code[0];
544 efuse->country_code[1] = map->country_code[1];
545 rtw8852a_efuse_parsing_tssi(rtwdev, map);
546
547 switch (rtwdev->hci.type) {
548 case RTW89_HCI_TYPE_PCIE:
549 rtw8852ae_efuse_parsing(efuse, map);
550 break;
551 default:
552 return -ENOTSUPP;
553 }
554
555 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
556
557 return 0;
558 }
559
rtw8852a_phycap_parsing_tssi(struct rtw89_dev * rtwdev,u8 * phycap_map)560 static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
561 {
562 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
563 static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB};
564 u32 addr = rtwdev->chip->phycap_addr;
565 bool pg = false;
566 u32 ofst;
567 u8 i, j;
568
569 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
570 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
571 /* addrs are in decreasing order */
572 ofst = tssi_trim_addr[i] - addr - j;
573 tssi->tssi_trim[i][j] = phycap_map[ofst];
574
575 if (phycap_map[ofst] != 0xff)
576 pg = true;
577 }
578 }
579
580 if (!pg) {
581 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
582 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
583 "[TSSI][TRIM] no PG, set all trim info to 0\n");
584 }
585
586 for (i = 0; i < RF_PATH_NUM_8852A; i++)
587 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
588 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
589 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
590 i, j, tssi->tssi_trim[i][j],
591 tssi_trim_addr[i] - j);
592 }
593
rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)594 static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
595 u8 *phycap_map)
596 {
597 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
598 static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC};
599 u32 addr = rtwdev->chip->phycap_addr;
600 u8 i;
601
602 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
603 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
604
605 rtw89_debug(rtwdev, RTW89_DBG_RFK,
606 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
607 i, info->thermal_trim[i]);
608
609 if (info->thermal_trim[i] != 0xff)
610 info->pg_thermal_trim = true;
611 }
612 }
613
rtw8852a_thermal_trim(struct rtw89_dev * rtwdev)614 static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev)
615 {
616 #define __thm_setting(raw) \
617 ({ \
618 u8 __v = (raw); \
619 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
620 })
621 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
622 u8 i, val;
623
624 if (!info->pg_thermal_trim) {
625 rtw89_debug(rtwdev, RTW89_DBG_RFK,
626 "[THERMAL][TRIM] no PG, do nothing\n");
627
628 return;
629 }
630
631 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
632 val = __thm_setting(info->thermal_trim[i]);
633 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
634
635 rtw89_debug(rtwdev, RTW89_DBG_RFK,
636 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
637 i, val);
638 }
639 #undef __thm_setting
640 }
641
rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)642 static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
643 u8 *phycap_map)
644 {
645 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
646 static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB};
647 u32 addr = rtwdev->chip->phycap_addr;
648 u8 i;
649
650 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
651 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
652
653 rtw89_debug(rtwdev, RTW89_DBG_RFK,
654 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
655 i, info->pa_bias_trim[i]);
656
657 if (info->pa_bias_trim[i] != 0xff)
658 info->pg_pa_bias_trim = true;
659 }
660 }
661
rtw8852a_pa_bias_trim(struct rtw89_dev * rtwdev)662 static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev)
663 {
664 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
665 u8 pabias_2g, pabias_5g;
666 u8 i;
667
668 if (!info->pg_pa_bias_trim) {
669 rtw89_debug(rtwdev, RTW89_DBG_RFK,
670 "[PA_BIAS][TRIM] no PG, do nothing\n");
671
672 return;
673 }
674
675 for (i = 0; i < RF_PATH_NUM_8852A; i++) {
676 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
677 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
678
679 rtw89_debug(rtwdev, RTW89_DBG_RFK,
680 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
681 i, pabias_2g, pabias_5g);
682
683 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
684 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
685 }
686 }
687
rtw8852a_read_phycap(struct rtw89_dev * rtwdev,u8 * phycap_map)688 static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
689 {
690 rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map);
691 rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map);
692 rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
693
694 return 0;
695 }
696
rtw8852a_power_trim(struct rtw89_dev * rtwdev)697 static void rtw8852a_power_trim(struct rtw89_dev *rtwdev)
698 {
699 rtw8852a_thermal_trim(rtwdev);
700 rtw8852a_pa_bias_trim(rtwdev);
701 }
702
rtw8852a_set_channel_mac(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 mac_idx)703 static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev,
704 const struct rtw89_chan *chan,
705 u8 mac_idx)
706 {
707 u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx);
708 u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE,
709 mac_idx);
710 u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx);
711 u8 txsc20 = 0, txsc40 = 0;
712
713 switch (chan->band_width) {
714 case RTW89_CHANNEL_WIDTH_80:
715 txsc40 = rtw89_phy_get_txsc(rtwdev, chan,
716 RTW89_CHANNEL_WIDTH_40);
717 fallthrough;
718 case RTW89_CHANNEL_WIDTH_40:
719 txsc20 = rtw89_phy_get_txsc(rtwdev, chan,
720 RTW89_CHANNEL_WIDTH_20);
721 break;
722 default:
723 break;
724 }
725
726 switch (chan->band_width) {
727 case RTW89_CHANNEL_WIDTH_80:
728 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
729 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
730 break;
731 case RTW89_CHANNEL_WIDTH_40:
732 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
733 rtw89_write32(rtwdev, sub_carr, txsc20);
734 break;
735 case RTW89_CHANNEL_WIDTH_20:
736 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
737 rtw89_write32(rtwdev, sub_carr, 0);
738 break;
739 default:
740 break;
741 }
742
743 if (chan->channel > 14)
744 rtw89_write8_set(rtwdev, chk_rate,
745 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
746 else
747 rtw89_write8_clr(rtwdev, chk_rate,
748 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
749 }
750
751 static const u32 rtw8852a_sco_barker_threshold[14] = {
752 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
753 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4
754 };
755
756 static const u32 rtw8852a_sco_cck_threshold[14] = {
757 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724,
758 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed
759 };
760
rtw8852a_ctrl_sco_cck(struct rtw89_dev * rtwdev,u8 central_ch,u8 primary_ch,enum rtw89_bandwidth bw)761 static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch,
762 u8 primary_ch, enum rtw89_bandwidth bw)
763 {
764 u8 ch_element;
765
766 if (bw == RTW89_CHANNEL_WIDTH_20) {
767 ch_element = central_ch - 1;
768 } else if (bw == RTW89_CHANNEL_WIDTH_40) {
769 if (primary_ch == 1)
770 ch_element = central_ch - 1 + 2;
771 else
772 ch_element = central_ch - 1 - 2;
773 } else {
774 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw);
775 return -EINVAL;
776 }
777 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
778 rtw8852a_sco_barker_threshold[ch_element]);
779 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
780 rtw8852a_sco_cck_threshold[ch_element]);
781
782 return 0;
783 }
784
rtw8852a_ch_setting(struct rtw89_dev * rtwdev,u8 central_ch,u8 path)785 static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch,
786 u8 path)
787 {
788 u32 val;
789
790 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
791 if (val == INV_RF_DATA) {
792 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path);
793 return;
794 }
795 val &= ~0x303ff;
796 val |= central_ch;
797 if (central_ch > 14)
798 val |= (BIT(16) | BIT(8));
799 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val);
800 }
801
rtw8852a_sco_mapping(u8 central_ch)802 static u8 rtw8852a_sco_mapping(u8 central_ch)
803 {
804 if (central_ch == 1)
805 return 109;
806 else if (central_ch >= 2 && central_ch <= 6)
807 return 108;
808 else if (central_ch >= 7 && central_ch <= 10)
809 return 107;
810 else if (central_ch >= 11 && central_ch <= 14)
811 return 106;
812 else if (central_ch == 36 || central_ch == 38)
813 return 51;
814 else if (central_ch >= 40 && central_ch <= 58)
815 return 50;
816 else if (central_ch >= 60 && central_ch <= 64)
817 return 49;
818 else if (central_ch == 100 || central_ch == 102)
819 return 48;
820 else if (central_ch >= 104 && central_ch <= 126)
821 return 47;
822 else if (central_ch >= 128 && central_ch <= 151)
823 return 46;
824 else if (central_ch >= 153 && central_ch <= 177)
825 return 45;
826 else
827 return 0;
828 }
829
rtw8852a_ctrl_ch(struct rtw89_dev * rtwdev,u8 central_ch,enum rtw89_phy_idx phy_idx)830 static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch,
831 enum rtw89_phy_idx phy_idx)
832 {
833 u8 sco_comp;
834 bool is_2g = central_ch <= 14;
835
836 if (phy_idx == RTW89_PHY_0) {
837 /* Path A */
838 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A);
839 if (is_2g)
840 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1,
841 B_PATH0_TIA_ERR_G1_SEL, 1,
842 phy_idx);
843 else
844 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1,
845 B_PATH0_TIA_ERR_G1_SEL, 0,
846 phy_idx);
847
848 /* Path B */
849 if (!rtwdev->dbcc_en) {
850 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B);
851 if (is_2g)
852 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
853 B_P1_MODE_SEL,
854 1, phy_idx);
855 else
856 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
857 B_P1_MODE_SEL,
858 0, phy_idx);
859 } else {
860 if (is_2g)
861 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND,
862 B_2P4G_BAND_SEL);
863 else
864 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND,
865 B_2P4G_BAND_SEL);
866 }
867 /* SCO compensate FC setting */
868 sco_comp = rtw8852a_sco_mapping(central_ch);
869 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV,
870 sco_comp, phy_idx);
871 } else {
872 /* Path B */
873 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B);
874 if (is_2g)
875 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
876 B_P1_MODE_SEL,
877 1, phy_idx);
878 else
879 rtw89_phy_write32_idx(rtwdev, R_P1_MODE,
880 B_P1_MODE_SEL,
881 0, phy_idx);
882 /* SCO compensate FC setting */
883 sco_comp = rtw8852a_sco_mapping(central_ch);
884 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV,
885 sco_comp, phy_idx);
886 }
887
888 /* Band edge */
889 if (is_2g)
890 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1,
891 phy_idx);
892 else
893 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0,
894 phy_idx);
895
896 /* CCK parameters */
897 if (central_ch == 14) {
898 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
899 0x3b13ff);
900 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23,
901 0x1c42de);
902 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45,
903 0xfdb0ad);
904 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67,
905 0xf60f6e);
906 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89,
907 0xfd8f92);
908 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
909 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
910 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF,
911 0xfff00a);
912 } else {
913 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01,
914 0x3d23ff);
915 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23,
916 0x29b354);
917 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
918 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67,
919 0xfdb053);
920 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89,
921 0xf86f9a);
922 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB,
923 0xfaef92);
924 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD,
925 0xfe5fcc);
926 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF,
927 0xffdff5);
928 }
929 }
930
rtw8852a_bw_setting(struct rtw89_dev * rtwdev,u8 bw,u8 path)931 static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
932 {
933 u32 val = 0;
934 u32 adc_sel[2] = {0x12d0, 0x32d0};
935 u32 wbadc_sel[2] = {0x12ec, 0x32ec};
936
937 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK);
938 if (val == INV_RF_DATA) {
939 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path);
940 return;
941 }
942 val &= ~(BIT(11) | BIT(10));
943 switch (bw) {
944 case RTW89_CHANNEL_WIDTH_5:
945 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
946 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
947 val |= (BIT(11) | BIT(10));
948 break;
949 case RTW89_CHANNEL_WIDTH_10:
950 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
951 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
952 val |= (BIT(11) | BIT(10));
953 break;
954 case RTW89_CHANNEL_WIDTH_20:
955 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
956 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
957 val |= (BIT(11) | BIT(10));
958 break;
959 case RTW89_CHANNEL_WIDTH_40:
960 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
961 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
962 val |= BIT(11);
963 break;
964 case RTW89_CHANNEL_WIDTH_80:
965 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
966 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
967 val |= BIT(10);
968 break;
969 default:
970 rtw89_warn(rtwdev, "Fail to set ADC\n");
971 }
972
973 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val);
974 }
975
976 static void
rtw8852a_ctrl_bw(struct rtw89_dev * rtwdev,u8 pri_ch,u8 bw,enum rtw89_phy_idx phy_idx)977 rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
978 enum rtw89_phy_idx phy_idx)
979 {
980 /* Switch bandwidth */
981 switch (bw) {
982 case RTW89_CHANNEL_WIDTH_5:
983 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
984 phy_idx);
985 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1,
986 phy_idx);
987 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
988 0x0, phy_idx);
989 break;
990 case RTW89_CHANNEL_WIDTH_10:
991 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
992 phy_idx);
993 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2,
994 phy_idx);
995 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
996 0x0, phy_idx);
997 break;
998 case RTW89_CHANNEL_WIDTH_20:
999 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
1000 phy_idx);
1001 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1002 phy_idx);
1003 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1004 0x0, phy_idx);
1005 break;
1006 case RTW89_CHANNEL_WIDTH_40:
1007 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1,
1008 phy_idx);
1009 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1010 phy_idx);
1011 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1012 pri_ch,
1013 phy_idx);
1014 if (pri_ch == RTW89_SC_20_UPPER)
1015 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
1016 else
1017 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
1018 break;
1019 case RTW89_CHANNEL_WIDTH_80:
1020 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2,
1021 phy_idx);
1022 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1023 phy_idx);
1024 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1025 pri_ch,
1026 phy_idx);
1027 break;
1028 default:
1029 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
1030 pri_ch);
1031 }
1032
1033 if (phy_idx == RTW89_PHY_0) {
1034 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A);
1035 if (!rtwdev->dbcc_en)
1036 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B);
1037 } else {
1038 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B);
1039 }
1040 }
1041
rtw8852a_spur_elimination(struct rtw89_dev * rtwdev,u8 central_ch)1042 static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch)
1043 {
1044 if (central_ch == 153) {
1045 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1046 0x210);
1047 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1048 0x210);
1049 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x7c0);
1050 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1051 B_P0_NBIIDX_NOTCH_EN, 0x1);
1052 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1053 B_P1_NBIIDX_NOTCH_EN, 0x1);
1054 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1055 0x1);
1056 } else if (central_ch == 151) {
1057 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1058 0x210);
1059 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1060 0x210);
1061 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x40);
1062 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1063 B_P0_NBIIDX_NOTCH_EN, 0x1);
1064 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1065 B_P1_NBIIDX_NOTCH_EN, 0x1);
1066 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1067 0x1);
1068 } else if (central_ch == 155) {
1069 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL,
1070 0x2d0);
1071 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL,
1072 0x2d0);
1073 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x740);
1074 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1075 B_P0_NBIIDX_NOTCH_EN, 0x1);
1076 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1077 B_P1_NBIIDX_NOTCH_EN, 0x1);
1078 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1079 0x1);
1080 } else {
1081 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX,
1082 B_P0_NBIIDX_NOTCH_EN, 0x0);
1083 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX,
1084 B_P1_NBIIDX_NOTCH_EN, 0x0);
1085 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN,
1086 0x0);
1087 }
1088 }
1089
rtw8852a_bb_reset_all(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1090 static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev,
1091 enum rtw89_phy_idx phy_idx)
1092 {
1093 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1094 phy_idx);
1095 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0,
1096 phy_idx);
1097 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1098 phy_idx);
1099 }
1100
rtw8852a_bb_reset_en(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,bool en)1101 static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev,
1102 enum rtw89_phy_idx phy_idx, bool en)
1103 {
1104 if (en)
1105 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL,
1106 1,
1107 phy_idx);
1108 else
1109 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL,
1110 0,
1111 phy_idx);
1112 }
1113
rtw8852a_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1114 static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev,
1115 enum rtw89_phy_idx phy_idx)
1116 {
1117 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1118 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1119 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1120 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1121 rtw8852a_bb_reset_all(rtwdev, phy_idx);
1122 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1123 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1124 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1125 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1126 }
1127
rtw8852a_bb_macid_ctrl_init(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1128 static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1129 enum rtw89_phy_idx phy_idx)
1130 {
1131 u32 addr;
1132
1133 for (addr = R_AX_PWR_MACID_LMT_TABLE0;
1134 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
1135 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1136 }
1137
rtw8852a_bb_sethw(struct rtw89_dev * rtwdev)1138 static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev)
1139 {
1140 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
1141 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP);
1142
1143 if (rtwdev->hal.cv <= CHIP_CCV) {
1144 rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG);
1145 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000);
1146 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x43F);
1147 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF);
1148 rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST);
1149 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1150 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1151 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, B_STS_PARSING_TIME);
1152 }
1153 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f);
1154 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c);
1155 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
1156 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1);
1157 rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK);
1158 rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK);
1159
1160 rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1161 }
1162
rtw8852a_bbrst_for_rfk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1163 static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev,
1164 enum rtw89_phy_idx phy_idx)
1165 {
1166 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1167 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1168 rtw8852a_bb_reset_all(rtwdev, phy_idx);
1169 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1170 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1171 udelay(1);
1172 }
1173
rtw8852a_set_channel_bb(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1174 static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev,
1175 const struct rtw89_chan *chan,
1176 enum rtw89_phy_idx phy_idx)
1177 {
1178 bool cck_en = chan->channel <= 14;
1179 u8 pri_ch_idx = chan->pri_ch_idx;
1180
1181 if (cck_en)
1182 rtw8852a_ctrl_sco_cck(rtwdev, chan->channel,
1183 chan->primary_channel,
1184 chan->band_width);
1185
1186 rtw8852a_ctrl_ch(rtwdev, chan->channel, phy_idx);
1187 rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1188 if (cck_en) {
1189 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
1190 } else {
1191 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
1192 rtw8852a_bbrst_for_rfk(rtwdev, phy_idx);
1193 }
1194 rtw8852a_spur_elimination(rtwdev, chan->channel);
1195 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0,
1196 chan->primary_channel);
1197 rtw8852a_bb_reset_all(rtwdev, phy_idx);
1198 }
1199
rtw8852a_set_channel(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)1200 static void rtw8852a_set_channel(struct rtw89_dev *rtwdev,
1201 const struct rtw89_chan *chan,
1202 enum rtw89_mac_idx mac_idx,
1203 enum rtw89_phy_idx phy_idx)
1204 {
1205 rtw8852a_set_channel_mac(rtwdev, chan, mac_idx);
1206 rtw8852a_set_channel_bb(rtwdev, chan, phy_idx);
1207 }
1208
rtw8852a_dfs_en(struct rtw89_dev * rtwdev,bool en)1209 static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en)
1210 {
1211 if (en)
1212 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1);
1213 else
1214 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0);
1215 }
1216
rtw8852a_tssi_cont_en(struct rtw89_dev * rtwdev,bool en,enum rtw89_rf_path path)1217 static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
1218 enum rtw89_rf_path path)
1219 {
1220 static const u32 tssi_trk[2] = {0x5818, 0x7818};
1221 static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc};
1222
1223 if (en) {
1224 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0);
1225 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0);
1226 } else {
1227 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1);
1228 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1);
1229 }
1230 }
1231
rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev * rtwdev,bool en,u8 phy_idx)1232 static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
1233 u8 phy_idx)
1234 {
1235 if (!rtwdev->dbcc_en) {
1236 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A);
1237 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B);
1238 } else {
1239 if (phy_idx == RTW89_PHY_0)
1240 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A);
1241 else
1242 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B);
1243 }
1244 }
1245
rtw8852a_adc_en(struct rtw89_dev * rtwdev,bool en)1246 static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en)
1247 {
1248 if (en)
1249 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1250 0x0);
1251 else
1252 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1253 0xf);
1254 }
1255
rtw8852a_set_channel_help(struct rtw89_dev * rtwdev,bool enter,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)1256 static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1257 struct rtw89_channel_help_params *p,
1258 const struct rtw89_chan *chan,
1259 enum rtw89_mac_idx mac_idx,
1260 enum rtw89_phy_idx phy_idx)
1261 {
1262 if (enter) {
1263 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en,
1264 RTW89_SCH_TX_SEL_ALL);
1265 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false);
1266 rtw8852a_dfs_en(rtwdev, false);
1267 rtw8852a_tssi_cont_en_phyidx(rtwdev, false, phy_idx);
1268 rtw8852a_adc_en(rtwdev, false);
1269 fsleep(40);
1270 rtw8852a_bb_reset_en(rtwdev, phy_idx, false);
1271 } else {
1272 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true);
1273 rtw8852a_adc_en(rtwdev, true);
1274 rtw8852a_dfs_en(rtwdev, true);
1275 rtw8852a_tssi_cont_en_phyidx(rtwdev, true, phy_idx);
1276 rtw8852a_bb_reset_en(rtwdev, phy_idx, true);
1277 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en);
1278 }
1279 }
1280
rtw8852a_fem_setup(struct rtw89_dev * rtwdev)1281 static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev)
1282 {
1283 struct rtw89_efuse *efuse = &rtwdev->efuse;
1284
1285 switch (efuse->rfe_type) {
1286 case 11:
1287 case 12:
1288 case 17:
1289 case 18:
1290 case 51:
1291 case 53:
1292 rtwdev->fem.epa_2g = true;
1293 rtwdev->fem.elna_2g = true;
1294 fallthrough;
1295 case 9:
1296 case 10:
1297 case 15:
1298 case 16:
1299 rtwdev->fem.epa_5g = true;
1300 rtwdev->fem.elna_5g = true;
1301 break;
1302 default:
1303 break;
1304 }
1305 }
1306
rtw8852a_rfk_init(struct rtw89_dev * rtwdev)1307 static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev)
1308 {
1309 rtwdev->is_tssi_mode[RF_PATH_A] = false;
1310 rtwdev->is_tssi_mode[RF_PATH_B] = false;
1311
1312 rtw8852a_rck(rtwdev);
1313 rtw8852a_dack(rtwdev);
1314 rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true);
1315 }
1316
rtw8852a_rfk_channel(struct rtw89_dev * rtwdev)1317 static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev)
1318 {
1319 enum rtw89_phy_idx phy_idx = RTW89_PHY_0;
1320
1321 rtw8852a_rx_dck(rtwdev, phy_idx, true);
1322 rtw8852a_iqk(rtwdev, phy_idx);
1323 rtw8852a_tssi(rtwdev, phy_idx);
1324 rtw8852a_dpk(rtwdev, phy_idx);
1325 }
1326
rtw8852a_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1327 static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev,
1328 enum rtw89_phy_idx phy_idx)
1329 {
1330 rtw8852a_tssi_scan(rtwdev, phy_idx);
1331 }
1332
rtw8852a_rfk_scan(struct rtw89_dev * rtwdev,bool start)1333 static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev, bool start)
1334 {
1335 rtw8852a_wifi_scan_notify(rtwdev, start, RTW89_PHY_0);
1336 }
1337
rtw8852a_rfk_track(struct rtw89_dev * rtwdev)1338 static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev)
1339 {
1340 rtw8852a_dpk_track(rtwdev);
1341 rtw8852a_tssi_track(rtwdev);
1342 }
1343
rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,s16 ref)1344 static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1345 enum rtw89_phy_idx phy_idx, s16 ref)
1346 {
1347 s8 ofst_int = 0;
1348 u8 base_cw_0db = 0x27;
1349 u16 tssi_16dbm_cw = 0x12c;
1350 s16 pwr_s10_3 = 0;
1351 s16 rf_pwr_cw = 0;
1352 u16 bb_pwr_cw = 0;
1353 u32 pwr_cw = 0;
1354 u32 tssi_ofst_cw = 0;
1355
1356 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3);
1357 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3);
1358 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3);
1359 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
1360 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
1361
1362 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
1363 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1364 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
1365 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
1366
1367 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0));
1368 }
1369
1370 static
rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,s8 pw_ofst,enum rtw89_mac_idx mac_idx)1371 void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1372 s8 pw_ofst, enum rtw89_mac_idx mac_idx)
1373 {
1374 s8 val_1t = 0;
1375 s8 val_2t = 0;
1376 u32 reg;
1377
1378 if (pw_ofst < -16 || pw_ofst > 15) {
1379 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n",
1380 pw_ofst);
1381 return;
1382 }
1383 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_CTRL, mac_idx);
1384 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
1385 val_1t = pw_ofst;
1386 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx);
1387 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t);
1388 val_2t = max(val_1t - 3, -16);
1389 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx);
1390 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t);
1391 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n",
1392 val_1t, val_2t);
1393 }
1394
rtw8852a_set_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1395 static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev,
1396 enum rtw89_phy_idx phy_idx)
1397 {
1398 static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800};
1399 const u32 mask = 0x7FFFFFF;
1400 const u8 ofst_ofdm = 0x4;
1401 const u8 ofst_cck = 0x8;
1402 s16 ref_ofdm = 0;
1403 s16 ref_cck = 0;
1404 u32 val;
1405 u8 i;
1406
1407 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1408
1409 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1410 GENMASK(27, 10), 0x0);
1411
1412 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1413 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1414
1415 for (i = 0; i < RF_PATH_NUM_8852A; i++)
1416 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
1417 phy_idx);
1418
1419 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1420 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1421
1422 for (i = 0; i < RF_PATH_NUM_8852A; i++)
1423 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
1424 phy_idx);
1425 }
1426
rtw8852a_set_txpwr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1427 static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev,
1428 const struct rtw89_chan *chan,
1429 enum rtw89_phy_idx phy_idx)
1430 {
1431 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
1432 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
1433 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
1434 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
1435 }
1436
rtw8852a_set_txpwr_ctrl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1437 static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
1438 enum rtw89_phy_idx phy_idx)
1439 {
1440 rtw8852a_set_txpwr_ref(rtwdev, phy_idx);
1441 }
1442
1443 static int
rtw8852a_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1444 rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1445 {
1446 int ret;
1447
1448 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
1449 if (ret)
1450 return ret;
1451
1452 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004);
1453 if (ret)
1454 return ret;
1455
1456 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
1457 if (ret)
1458 return ret;
1459
1460 return 0;
1461 }
1462
rtw8852a_bb_set_plcp_tx(struct rtw89_dev * rtwdev)1463 void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev)
1464 {
1465 u8 i = 0;
1466 u32 addr, val;
1467
1468 for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) {
1469 addr = rtw8852a_pmac_ht20_mcs7_tbl[i].addr;
1470 val = rtw8852a_pmac_ht20_mcs7_tbl[i].data;
1471 rtw89_phy_write32(rtwdev, addr, val);
1472 }
1473 }
1474
rtw8852a_stop_pmac_tx(struct rtw89_dev * rtwdev,struct rtw8852a_bb_pmac_info * tx_info,enum rtw89_phy_idx idx)1475 static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev,
1476 struct rtw8852a_bb_pmac_info *tx_info,
1477 enum rtw89_phy_idx idx)
1478 {
1479 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx");
1480 if (tx_info->mode == CONT_TX)
1481 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0,
1482 idx);
1483 else if (tx_info->mode == PKTS_TX)
1484 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0,
1485 idx);
1486 }
1487
rtw8852a_start_pmac_tx(struct rtw89_dev * rtwdev,struct rtw8852a_bb_pmac_info * tx_info,enum rtw89_phy_idx idx)1488 static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev,
1489 struct rtw8852a_bb_pmac_info *tx_info,
1490 enum rtw89_phy_idx idx)
1491 {
1492 enum rtw8852a_pmac_mode mode = tx_info->mode;
1493 u32 pkt_cnt = tx_info->tx_cnt;
1494 u16 period = tx_info->period;
1495
1496 if (mode == CONT_TX && !tx_info->is_cck) {
1497 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1,
1498 idx);
1499 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start");
1500 } else if (mode == PKTS_TX) {
1501 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1,
1502 idx);
1503 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD,
1504 B_PMAC_TX_PRD_MSK, period, idx);
1505 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK,
1506 pkt_cnt, idx);
1507 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start");
1508 }
1509 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx);
1510 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx);
1511 }
1512
rtw8852a_bb_set_pmac_tx(struct rtw89_dev * rtwdev,struct rtw8852a_bb_pmac_info * tx_info,enum rtw89_phy_idx idx)1513 void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
1514 struct rtw8852a_bb_pmac_info *tx_info,
1515 enum rtw89_phy_idx idx)
1516 {
1517 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1518
1519 if (!tx_info->en_pmac_tx) {
1520 rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx);
1521 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx);
1522 if (chan->band_type == RTW89_BAND_2G)
1523 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS);
1524 return;
1525 }
1526 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable");
1527 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx);
1528 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx);
1529 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f,
1530 idx);
1531 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx);
1532 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx);
1533 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS);
1534 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx);
1535 rtw8852a_start_pmac_tx(rtwdev, tx_info, idx);
1536 }
1537
rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev * rtwdev,u8 enable,u16 tx_cnt,u16 period,u16 tx_time,enum rtw89_phy_idx idx)1538 void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
1539 u16 tx_cnt, u16 period, u16 tx_time,
1540 enum rtw89_phy_idx idx)
1541 {
1542 struct rtw8852a_bb_pmac_info tx_info = {0};
1543
1544 tx_info.en_pmac_tx = enable;
1545 tx_info.is_cck = 0;
1546 tx_info.mode = PKTS_TX;
1547 tx_info.tx_cnt = tx_cnt;
1548 tx_info.period = period;
1549 tx_info.tx_time = tx_time;
1550 rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx);
1551 }
1552
rtw8852a_bb_set_power(struct rtw89_dev * rtwdev,s16 pwr_dbm,enum rtw89_phy_idx idx)1553 void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
1554 enum rtw89_phy_idx idx)
1555 {
1556 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm);
1557 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx);
1558 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx);
1559 }
1560
rtw8852a_bb_cfg_tx_path(struct rtw89_dev * rtwdev,u8 tx_path)1561 void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path)
1562 {
1563 u32 rst_mask0 = 0;
1564 u32 rst_mask1 = 0;
1565
1566 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0);
1567 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1);
1568 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path);
1569 if (!rtwdev->dbcc_en) {
1570 if (tx_path == RF_PATH_A) {
1571 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1572 B_TXPATH_SEL_MSK, 1);
1573 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1574 B_TXNSS_MAP_MSK, 0);
1575 } else if (tx_path == RF_PATH_B) {
1576 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1577 B_TXPATH_SEL_MSK, 2);
1578 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1579 B_TXNSS_MAP_MSK, 0);
1580 } else if (tx_path == RF_PATH_AB) {
1581 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL,
1582 B_TXPATH_SEL_MSK, 3);
1583 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP,
1584 B_TXNSS_MAP_MSK, 4);
1585 } else {
1586 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path");
1587 }
1588 } else {
1589 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK,
1590 1);
1591 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2,
1592 RTW89_PHY_1);
1593 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK,
1594 0);
1595 rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4,
1596 RTW89_PHY_1);
1597 }
1598 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
1599 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI;
1600 if (tx_path == RF_PATH_A) {
1601 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
1602 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
1603 } else {
1604 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1);
1605 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3);
1606 }
1607 }
1608
rtw8852a_bb_tx_mode_switch(struct rtw89_dev * rtwdev,enum rtw89_phy_idx idx,u8 mode)1609 void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
1610 enum rtw89_phy_idx idx, u8 mode)
1611 {
1612 if (mode != 0)
1613 return;
1614 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch");
1615 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx);
1616 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx);
1617 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx);
1618 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx);
1619 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx);
1620 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx);
1621 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx);
1622 }
1623
rtw8852a_bb_ctrl_btc_preagc(struct rtw89_dev * rtwdev,bool bt_en)1624 static void rtw8852a_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en)
1625 {
1626 rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8852a_btc_preagc_en_defs_tbl :
1627 &rtw8852a_btc_preagc_dis_defs_tbl);
1628 }
1629
rtw8852a_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)1630 static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
1631 {
1632 if (rtwdev->is_tssi_mode[rf_path]) {
1633 u32 addr = 0x1c10 + (rf_path << 13);
1634
1635 return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000);
1636 }
1637
1638 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1639 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
1640 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1641
1642 fsleep(200);
1643
1644 return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
1645 }
1646
rtw8852a_btc_set_rfe(struct rtw89_dev * rtwdev)1647 static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev)
1648 {
1649 struct rtw89_btc *btc = &rtwdev->btc;
1650 struct rtw89_btc_module *module = &btc->mdinfo;
1651
1652 module->rfe_type = rtwdev->efuse.rfe_type;
1653 module->cv = rtwdev->hal.cv;
1654 module->bt_solo = 0;
1655 module->switch_type = BTC_SWITCH_INTERNAL;
1656
1657 if (module->rfe_type > 0)
1658 module->ant.num = (module->rfe_type % 2 ? 2 : 3);
1659 else
1660 module->ant.num = 2;
1661
1662 module->ant.diversity = 0;
1663 module->ant.isolation = 10;
1664
1665 if (module->ant.num == 3) {
1666 module->ant.type = BTC_ANT_DEDICATED;
1667 module->bt_pos = BTC_BT_ALONE;
1668 } else {
1669 module->ant.type = BTC_ANT_SHARED;
1670 module->bt_pos = BTC_BT_BTG;
1671 }
1672 }
1673
1674 static
rtw8852a_set_trx_mask(struct rtw89_dev * rtwdev,u8 path,u8 group,u32 val)1675 void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
1676 {
1677 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000);
1678 rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group);
1679 rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val);
1680 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0);
1681 }
1682
rtw8852a_ctrl_btg(struct rtw89_dev * rtwdev,bool btg)1683 static void rtw8852a_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
1684 {
1685 if (btg) {
1686 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1);
1687 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3);
1688 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
1689 } else {
1690 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0);
1691 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0);
1692 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf);
1693 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4);
1694 }
1695 }
1696
rtw8852a_btc_init_cfg(struct rtw89_dev * rtwdev)1697 static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev)
1698 {
1699 struct rtw89_btc *btc = &rtwdev->btc;
1700 struct rtw89_btc_module *module = &btc->mdinfo;
1701 const struct rtw89_chip_info *chip = rtwdev->chip;
1702 const struct rtw89_mac_ax_coex coex_params = {
1703 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
1704 .direction = RTW89_MAC_AX_COEX_INNER,
1705 };
1706
1707 /* PTA init */
1708 rtw89_mac_coex_init(rtwdev, &coex_params);
1709
1710 /* set WL Tx response = Hi-Pri */
1711 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
1712 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
1713
1714 /* set rf gnt debug off */
1715 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0);
1716 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0);
1717
1718 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */
1719 if (module->ant.type == BTC_ANT_SHARED) {
1720 rtw8852a_set_trx_mask(rtwdev,
1721 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff);
1722 rtw8852a_set_trx_mask(rtwdev,
1723 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff);
1724 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */
1725 rtw8852a_set_trx_mask(rtwdev,
1726 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
1727 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */
1728 rtw8852a_set_trx_mask(rtwdev,
1729 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df);
1730 rtw8852a_set_trx_mask(rtwdev,
1731 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df);
1732 }
1733
1734 /* set PTA break table */
1735 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
1736
1737 /* enable BT counter 0xda40[16,2] = 2b'11 */
1738 rtw89_write32_set(rtwdev,
1739 R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
1740 btc->cx.wl.status.map.init_ok = true;
1741 }
1742
1743 static
rtw8852a_btc_set_wl_pri(struct rtw89_dev * rtwdev,u8 map,bool state)1744 void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
1745 {
1746 u32 bitmap = 0;
1747 u32 reg = 0;
1748
1749 switch (map) {
1750 case BTC_PRI_MASK_TX_RESP:
1751 reg = R_BTC_BT_COEX_MSK_TABLE;
1752 bitmap = B_BTC_PRI_MASK_TX_RESP_V1;
1753 break;
1754 case BTC_PRI_MASK_BEACON:
1755 reg = R_AX_WL_PRI_MSK;
1756 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ;
1757 break;
1758 default:
1759 return;
1760 }
1761
1762 if (state)
1763 rtw89_write32_set(rtwdev, reg, bitmap);
1764 else
1765 rtw89_write32_clr(rtwdev, reg, bitmap);
1766 }
1767
__btc_ctrl_val_all_time(u32 ctrl)1768 static inline u32 __btc_ctrl_val_all_time(u32 ctrl)
1769 {
1770 return FIELD_GET(GENMASK(15, 0), ctrl);
1771 }
1772
__btc_ctrl_rst_all_time(u32 cur)1773 static inline u32 __btc_ctrl_rst_all_time(u32 cur)
1774 {
1775 return cur & ~B_AX_FORCE_PWR_BY_RATE_EN;
1776 }
1777
__btc_ctrl_gen_all_time(u32 cur,u32 val)1778 static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val)
1779 {
1780 u32 hv = cur & ~B_AX_FORCE_PWR_BY_RATE_VALUE_MASK;
1781 u32 lv = val & B_AX_FORCE_PWR_BY_RATE_VALUE_MASK;
1782
1783 return hv | lv | B_AX_FORCE_PWR_BY_RATE_EN;
1784 }
1785
__btc_ctrl_val_gnt_bt(u32 ctrl)1786 static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl)
1787 {
1788 return FIELD_GET(GENMASK(31, 16), ctrl);
1789 }
1790
__btc_ctrl_rst_gnt_bt(u32 cur)1791 static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur)
1792 {
1793 return cur & ~B_AX_TXAGC_BT_EN;
1794 }
1795
__btc_ctrl_gen_gnt_bt(u32 cur,u32 val)1796 static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val)
1797 {
1798 u32 ov = cur & ~B_AX_TXAGC_BT_MASK;
1799 u32 iv = FIELD_PREP(B_AX_TXAGC_BT_MASK, val);
1800
1801 return ov | iv | B_AX_TXAGC_BT_EN;
1802 }
1803
1804 static void
rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev * rtwdev,u32 txpwr_val)1805 rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
1806 {
1807 const u32 __btc_cr_all_time = R_AX_PWR_RATE_CTRL;
1808 const u32 __btc_cr_gnt_bt = R_AX_PWR_COEXT_CTRL;
1809
1810 #define __do_clr(_chk) ((_chk) == GENMASK(15, 0))
1811 #define __handle(_case) \
1812 do { \
1813 const u32 _reg = __btc_cr_ ## _case; \
1814 u32 _val = __btc_ctrl_val_ ## _case(txpwr_val); \
1815 u32 _cur, _wrt; \
1816 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \
1817 "btc ctrl %s: 0x%x\n", #_case, _val); \
1818 if (rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur))\
1819 break; \
1820 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \
1821 "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur); \
1822 _wrt = __do_clr(_val) ? \
1823 __btc_ctrl_rst_ ## _case(_cur) : \
1824 __btc_ctrl_gen_ ## _case(_cur, _val); \
1825 rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\
1826 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \
1827 "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt); \
1828 } while (0)
1829
1830 __handle(all_time);
1831 __handle(gnt_bt);
1832
1833 #undef __handle
1834 #undef __do_clr
1835 }
1836
1837 static
rtw8852a_btc_get_bt_rssi(struct rtw89_dev * rtwdev,s8 val)1838 s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
1839 {
1840 /* +6 for compensate offset */
1841 return clamp_t(s8, val + 6, -100, 0) + 100;
1842 }
1843
1844 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_ul[] = {
1845 {255, 0, 0, 7}, /* 0 -> original */
1846 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
1847 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
1848 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
1849 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
1850 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
1851 {6, 1, 0, 7},
1852 {13, 1, 0, 7},
1853 {13, 1, 0, 7}
1854 };
1855
1856 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_dl[] = {
1857 {255, 0, 0, 7}, /* 0 -> original */
1858 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
1859 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
1860 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
1861 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
1862 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
1863 {255, 1, 0, 7},
1864 {255, 1, 0, 7},
1865 {255, 1, 0, 7}
1866 };
1867
1868 static const
1869 u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30};
1870 static const
1871 u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28};
1872
1873 static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = {
1874 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
1875 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28),
1876 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c),
1877 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
1878 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
1879 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10),
1880 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20),
1881 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
1882 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4),
1883 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424),
1884 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
1885 RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178),
1886 };
1887
1888 static
rtw8852a_btc_update_bt_cnt(struct rtw89_dev * rtwdev)1889 void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
1890 {
1891 struct rtw89_btc *btc = &rtwdev->btc;
1892 const struct rtw89_btc_ver *ver = btc->ver;
1893 struct rtw89_btc_cx *cx = &btc->cx;
1894 u32 val;
1895
1896 if (ver->fcxbtcrpt != 1)
1897 return;
1898
1899 val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH);
1900 cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val);
1901 cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val);
1902
1903 val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW);
1904 cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val);
1905 cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val);
1906
1907 /* clock-gate off before reset counter*/
1908 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
1909 rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST);
1910 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST);
1911 rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G);
1912 }
1913
1914 static
rtw8852a_btc_wl_s1_standby(struct rtw89_dev * rtwdev,bool state)1915 void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
1916 {
1917 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
1918 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
1919 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1);
1920
1921 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
1922 if (state)
1923 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
1924 RFREG_MASK, 0xa2d7c);
1925 else
1926 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
1927 RFREG_MASK, 0xa2020);
1928
1929 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
1930 }
1931
rtw8852a_set_wl_lna2(struct rtw89_dev * rtwdev,u8 level)1932 static void rtw8852a_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level)
1933 {
1934 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB
1935 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB
1936 * To improve BT ACI in co-rx
1937 */
1938
1939 switch (level) {
1940 case 0: /* default */
1941 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
1942 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
1943 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17);
1944 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
1945 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
1946 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
1947 break;
1948 case 1: /* Fix LNA2=5 */
1949 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
1950 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
1951 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5);
1952 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
1953 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
1954 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
1955 break;
1956 }
1957 }
1958
rtw8852a_btc_set_wl_rx_gain(struct rtw89_dev * rtwdev,u32 level)1959 static void rtw8852a_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
1960 {
1961 struct rtw89_btc *btc = &rtwdev->btc;
1962
1963 switch (level) {
1964 case 0: /* original */
1965 default:
1966 rtw8852a_bb_ctrl_btc_preagc(rtwdev, false);
1967 btc->dm.wl_lna2 = 0;
1968 break;
1969 case 1: /* for FDD free-run */
1970 rtw8852a_bb_ctrl_btc_preagc(rtwdev, true);
1971 btc->dm.wl_lna2 = 0;
1972 break;
1973 case 2: /* for BTG Co-Rx*/
1974 rtw8852a_bb_ctrl_btc_preagc(rtwdev, false);
1975 btc->dm.wl_lna2 = 1;
1976 break;
1977 }
1978
1979 rtw8852a_set_wl_lna2(rtwdev, btc->dm.wl_lna2);
1980 }
1981
rtw8852a_fill_freq_with_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)1982 static void rtw8852a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
1983 struct rtw89_rx_phy_ppdu *phy_ppdu,
1984 struct ieee80211_rx_status *status)
1985 {
1986 u16 chan = phy_ppdu->chan_idx;
1987 u8 band;
1988
1989 if (chan == 0)
1990 return;
1991
1992 band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
1993 status->freq = ieee80211_channel_to_frequency(chan, band);
1994 status->band = band;
1995 }
1996
rtw8852a_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)1997 static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev,
1998 struct rtw89_rx_phy_ppdu *phy_ppdu,
1999 struct ieee80211_rx_status *status)
2000 {
2001 u8 path;
2002 u8 *rx_power = phy_ppdu->rssi;
2003
2004 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B]));
2005 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2006 status->chains |= BIT(path);
2007 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
2008 }
2009 if (phy_ppdu->valid)
2010 rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2011 }
2012
2013 #ifdef CONFIG_PM
2014 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852a = {
2015 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
2016 .n_patterns = RTW89_MAX_PATTERN_NUM,
2017 .pattern_max_len = RTW89_MAX_PATTERN_SIZE,
2018 .pattern_min_len = 1,
2019 };
2020 #endif
2021
2022 static const struct rtw89_chip_ops rtw8852a_chip_ops = {
2023 .enable_bb_rf = rtw89_mac_enable_bb_rf,
2024 .disable_bb_rf = rtw89_mac_disable_bb_rf,
2025 .bb_reset = rtw8852a_bb_reset,
2026 .bb_sethw = rtw8852a_bb_sethw,
2027 .read_rf = rtw89_phy_read_rf,
2028 .write_rf = rtw89_phy_write_rf,
2029 .set_channel = rtw8852a_set_channel,
2030 .set_channel_help = rtw8852a_set_channel_help,
2031 .read_efuse = rtw8852a_read_efuse,
2032 .read_phycap = rtw8852a_read_phycap,
2033 .fem_setup = rtw8852a_fem_setup,
2034 .rfe_gpio = NULL,
2035 .rfk_init = rtw8852a_rfk_init,
2036 .rfk_channel = rtw8852a_rfk_channel,
2037 .rfk_band_changed = rtw8852a_rfk_band_changed,
2038 .rfk_scan = rtw8852a_rfk_scan,
2039 .rfk_track = rtw8852a_rfk_track,
2040 .power_trim = rtw8852a_power_trim,
2041 .set_txpwr = rtw8852a_set_txpwr,
2042 .set_txpwr_ctrl = rtw8852a_set_txpwr_ctrl,
2043 .init_txpwr_unit = rtw8852a_init_txpwr_unit,
2044 .get_thermal = rtw8852a_get_thermal,
2045 .ctrl_btg = rtw8852a_ctrl_btg,
2046 .query_ppdu = rtw8852a_query_ppdu,
2047 .bb_ctrl_btc_preagc = rtw8852a_bb_ctrl_btc_preagc,
2048 .cfg_txrx_path = NULL,
2049 .set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset,
2050 .pwr_on_func = NULL,
2051 .pwr_off_func = NULL,
2052 .query_rxdesc = rtw89_core_query_rxdesc,
2053 .fill_txdesc = rtw89_core_fill_txdesc,
2054 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
2055 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
2056 .mac_cfg_gnt = rtw89_mac_cfg_gnt,
2057 .stop_sch_tx = rtw89_mac_stop_sch_tx,
2058 .resume_sch_tx = rtw89_mac_resume_sch_tx,
2059 .h2c_dctl_sec_cam = NULL,
2060
2061 .btc_set_rfe = rtw8852a_btc_set_rfe,
2062 .btc_init_cfg = rtw8852a_btc_init_cfg,
2063 .btc_set_wl_pri = rtw8852a_btc_set_wl_pri,
2064 .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl,
2065 .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi,
2066 .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt,
2067 .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby,
2068 .btc_set_wl_rx_gain = rtw8852a_btc_set_wl_rx_gain,
2069 .btc_set_policy = rtw89_btc_set_policy,
2070 };
2071
2072 const struct rtw89_chip_info rtw8852a_chip_info = {
2073 .chip_id = RTL8852A,
2074 .chip_gen = RTW89_CHIP_AX,
2075 .ops = &rtw8852a_chip_ops,
2076 .fw_basename = RTW8852A_FW_BASENAME,
2077 .fw_format_max = RTW8852A_FW_FORMAT_MAX,
2078 .try_ce_fw = false,
2079 .needed_fw_elms = 0,
2080 .fifo_size = 458752,
2081 .small_fifo_size = false,
2082 .dle_scc_rsvd_size = 0,
2083 .max_amsdu_limit = 3500,
2084 .dis_2g_40m_ul_ofdma = true,
2085 .rsvd_ple_ofst = 0x6f800,
2086 .hfc_param_ini = rtw8852a_hfc_param_ini_pcie,
2087 .dle_mem = rtw8852a_dle_mem_pcie,
2088 .wde_qempty_acq_num = 16,
2089 .wde_qempty_mgq_sel = 16,
2090 .rf_base_addr = {0xc000, 0xd000},
2091 .pwr_on_seq = pwr_on_seq_8852a,
2092 .pwr_off_seq = pwr_off_seq_8852a,
2093 .bb_table = &rtw89_8852a_phy_bb_table,
2094 .bb_gain_table = NULL,
2095 .rf_table = {&rtw89_8852a_phy_radioa_table,
2096 &rtw89_8852a_phy_radiob_table,},
2097 .nctl_table = &rtw89_8852a_phy_nctl_table,
2098 .nctl_post_table = NULL,
2099 .byr_table = &rtw89_8852a_byr_table,
2100 .dflt_parms = &rtw89_8852a_dflt_parms,
2101 .rfe_parms_conf = NULL,
2102 .txpwr_factor_rf = 2,
2103 .txpwr_factor_mac = 1,
2104 .dig_table = &rtw89_8852a_phy_dig_table,
2105 .dig_regs = &rtw8852a_dig_regs,
2106 .tssi_dbw_table = NULL,
2107 .support_chanctx_num = 1,
2108 .support_bands = BIT(NL80211_BAND_2GHZ) |
2109 BIT(NL80211_BAND_5GHZ),
2110 .support_bw160 = false,
2111 .support_unii4 = false,
2112 .support_ul_tb_ctrl = false,
2113 .hw_sec_hdr = false,
2114 .rf_path_num = 2,
2115 .tx_nss = 2,
2116 .rx_nss = 2,
2117 .acam_num = 128,
2118 .bcam_num = 10,
2119 .scam_num = 128,
2120 .bacam_num = 2,
2121 .bacam_dynamic_num = 4,
2122 .bacam_ver = RTW89_BACAM_V0,
2123 .sec_ctrl_efuse_size = 4,
2124 .physical_efuse_size = 1216,
2125 .logical_efuse_size = 1536,
2126 .limit_efuse_size = 1152,
2127 .dav_phy_efuse_size = 0,
2128 .dav_log_efuse_size = 0,
2129 .phycap_addr = 0x580,
2130 .phycap_size = 128,
2131 .para_ver = 0x0,
2132 .wlcx_desired = 0x06000000,
2133 .btcx_desired = 0x7,
2134 .scbd = 0x1,
2135 .mailbox = 0x1,
2136
2137 .afh_guard_ch = 6,
2138 .wl_rssi_thres = rtw89_btc_8852a_wl_rssi_thres,
2139 .bt_rssi_thres = rtw89_btc_8852a_bt_rssi_thres,
2140 .rssi_tol = 2,
2141 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852a_mon_reg),
2142 .mon_reg = rtw89_btc_8852a_mon_reg,
2143 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_ul),
2144 .rf_para_ulink = rtw89_btc_8852a_rf_ul,
2145 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_dl),
2146 .rf_para_dlink = rtw89_btc_8852a_rf_dl,
2147 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
2148 BIT(RTW89_PS_MODE_CLK_GATED) |
2149 BIT(RTW89_PS_MODE_PWR_GATED),
2150 .low_power_hci_modes = 0,
2151 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD,
2152 .hci_func_en_addr = R_AX_HCI_FUNC_EN,
2153 .h2c_desc_size = sizeof(struct rtw89_txwd_body),
2154 .txwd_body_size = sizeof(struct rtw89_txwd_body),
2155 .h2c_ctrl_reg = R_AX_H2CREG_CTRL,
2156 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
2157 .h2c_regs = rtw8852a_h2c_regs,
2158 .c2h_ctrl_reg = R_AX_C2HREG_CTRL,
2159 .c2h_regs = rtw8852a_c2h_regs,
2160 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
2161 .page_regs = &rtw8852a_page_regs,
2162 .cfo_src_fd = false,
2163 .cfo_hw_comp = false,
2164 .dcfo_comp = &rtw8852a_dcfo_comp,
2165 .dcfo_comp_sft = 10,
2166 .imr_info = &rtw8852a_imr_info,
2167 .rrsr_cfgs = &rtw8852a_rrsr_cfgs,
2168 .bss_clr_map_reg = R_BSS_CLR_MAP,
2169 .dma_ch_mask = 0,
2170 .edcca_lvl_reg = R_SEG0R_EDCCA_LVL,
2171 #ifdef CONFIG_PM
2172 .wowlan_stub = &rtw_wowlan_stub_8852a,
2173 #endif
2174 .xtal_info = &rtw8852a_xtal_info,
2175 };
2176 EXPORT_SYMBOL(rtw8852a_chip_info);
2177
2178 MODULE_FIRMWARE(RTW8852A_MODULE_FIRMWARE);
2179 MODULE_AUTHOR("Realtek Corporation");
2180 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852A driver");
2181 MODULE_LICENSE("Dual BSD/GPL");
2182