1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #if defined(__FreeBSD__)
6 #define LINUXKPI_PARAM_PREFIX rtw89_
7 #endif
8
9 #include <linux/ip.h>
10 #include <linux/udp.h>
11
12 #include "cam.h"
13 #include "chan.h"
14 #include "coex.h"
15 #include "core.h"
16 #include "efuse.h"
17 #include "fw.h"
18 #include "mac.h"
19 #include "phy.h"
20 #include "ps.h"
21 #include "reg.h"
22 #include "sar.h"
23 #include "ser.h"
24 #include "txrx.h"
25 #include "util.h"
26
27 static bool rtw89_disable_ps_mode;
28 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644);
29 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode");
30
31 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \
32 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, }
33 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \
34 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ)
35 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \
36 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ)
37 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \
38 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ)
39 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \
40 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ)
41
42 static struct ieee80211_channel rtw89_channels_2ghz[] = {
43 RTW89_DEF_CHAN_2G(2412, 1),
44 RTW89_DEF_CHAN_2G(2417, 2),
45 RTW89_DEF_CHAN_2G(2422, 3),
46 RTW89_DEF_CHAN_2G(2427, 4),
47 RTW89_DEF_CHAN_2G(2432, 5),
48 RTW89_DEF_CHAN_2G(2437, 6),
49 RTW89_DEF_CHAN_2G(2442, 7),
50 RTW89_DEF_CHAN_2G(2447, 8),
51 RTW89_DEF_CHAN_2G(2452, 9),
52 RTW89_DEF_CHAN_2G(2457, 10),
53 RTW89_DEF_CHAN_2G(2462, 11),
54 RTW89_DEF_CHAN_2G(2467, 12),
55 RTW89_DEF_CHAN_2G(2472, 13),
56 RTW89_DEF_CHAN_2G(2484, 14),
57 };
58
59 static struct ieee80211_channel rtw89_channels_5ghz[] = {
60 RTW89_DEF_CHAN_5G(5180, 36),
61 RTW89_DEF_CHAN_5G(5200, 40),
62 RTW89_DEF_CHAN_5G(5220, 44),
63 RTW89_DEF_CHAN_5G(5240, 48),
64 RTW89_DEF_CHAN_5G(5260, 52),
65 RTW89_DEF_CHAN_5G(5280, 56),
66 RTW89_DEF_CHAN_5G(5300, 60),
67 RTW89_DEF_CHAN_5G(5320, 64),
68 RTW89_DEF_CHAN_5G(5500, 100),
69 RTW89_DEF_CHAN_5G(5520, 104),
70 RTW89_DEF_CHAN_5G(5540, 108),
71 RTW89_DEF_CHAN_5G(5560, 112),
72 RTW89_DEF_CHAN_5G(5580, 116),
73 RTW89_DEF_CHAN_5G(5600, 120),
74 RTW89_DEF_CHAN_5G(5620, 124),
75 RTW89_DEF_CHAN_5G(5640, 128),
76 RTW89_DEF_CHAN_5G(5660, 132),
77 RTW89_DEF_CHAN_5G(5680, 136),
78 RTW89_DEF_CHAN_5G(5700, 140),
79 RTW89_DEF_CHAN_5G(5720, 144),
80 RTW89_DEF_CHAN_5G(5745, 149),
81 RTW89_DEF_CHAN_5G(5765, 153),
82 RTW89_DEF_CHAN_5G(5785, 157),
83 RTW89_DEF_CHAN_5G(5805, 161),
84 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165),
85 RTW89_DEF_CHAN_5G(5845, 169),
86 RTW89_DEF_CHAN_5G(5865, 173),
87 RTW89_DEF_CHAN_5G(5885, 177),
88 };
89
90 static struct ieee80211_channel rtw89_channels_6ghz[] = {
91 RTW89_DEF_CHAN_6G(5955, 1),
92 RTW89_DEF_CHAN_6G(5975, 5),
93 RTW89_DEF_CHAN_6G(5995, 9),
94 RTW89_DEF_CHAN_6G(6015, 13),
95 RTW89_DEF_CHAN_6G(6035, 17),
96 RTW89_DEF_CHAN_6G(6055, 21),
97 RTW89_DEF_CHAN_6G(6075, 25),
98 RTW89_DEF_CHAN_6G(6095, 29),
99 RTW89_DEF_CHAN_6G(6115, 33),
100 RTW89_DEF_CHAN_6G(6135, 37),
101 RTW89_DEF_CHAN_6G(6155, 41),
102 RTW89_DEF_CHAN_6G(6175, 45),
103 RTW89_DEF_CHAN_6G(6195, 49),
104 RTW89_DEF_CHAN_6G(6215, 53),
105 RTW89_DEF_CHAN_6G(6235, 57),
106 RTW89_DEF_CHAN_6G(6255, 61),
107 RTW89_DEF_CHAN_6G(6275, 65),
108 RTW89_DEF_CHAN_6G(6295, 69),
109 RTW89_DEF_CHAN_6G(6315, 73),
110 RTW89_DEF_CHAN_6G(6335, 77),
111 RTW89_DEF_CHAN_6G(6355, 81),
112 RTW89_DEF_CHAN_6G(6375, 85),
113 RTW89_DEF_CHAN_6G(6395, 89),
114 RTW89_DEF_CHAN_6G(6415, 93),
115 RTW89_DEF_CHAN_6G(6435, 97),
116 RTW89_DEF_CHAN_6G(6455, 101),
117 RTW89_DEF_CHAN_6G(6475, 105),
118 RTW89_DEF_CHAN_6G(6495, 109),
119 RTW89_DEF_CHAN_6G(6515, 113),
120 RTW89_DEF_CHAN_6G(6535, 117),
121 RTW89_DEF_CHAN_6G(6555, 121),
122 RTW89_DEF_CHAN_6G(6575, 125),
123 RTW89_DEF_CHAN_6G(6595, 129),
124 RTW89_DEF_CHAN_6G(6615, 133),
125 RTW89_DEF_CHAN_6G(6635, 137),
126 RTW89_DEF_CHAN_6G(6655, 141),
127 RTW89_DEF_CHAN_6G(6675, 145),
128 RTW89_DEF_CHAN_6G(6695, 149),
129 RTW89_DEF_CHAN_6G(6715, 153),
130 RTW89_DEF_CHAN_6G(6735, 157),
131 RTW89_DEF_CHAN_6G(6755, 161),
132 RTW89_DEF_CHAN_6G(6775, 165),
133 RTW89_DEF_CHAN_6G(6795, 169),
134 RTW89_DEF_CHAN_6G(6815, 173),
135 RTW89_DEF_CHAN_6G(6835, 177),
136 RTW89_DEF_CHAN_6G(6855, 181),
137 RTW89_DEF_CHAN_6G(6875, 185),
138 RTW89_DEF_CHAN_6G(6895, 189),
139 RTW89_DEF_CHAN_6G(6915, 193),
140 RTW89_DEF_CHAN_6G(6935, 197),
141 RTW89_DEF_CHAN_6G(6955, 201),
142 RTW89_DEF_CHAN_6G(6975, 205),
143 RTW89_DEF_CHAN_6G(6995, 209),
144 RTW89_DEF_CHAN_6G(7015, 213),
145 RTW89_DEF_CHAN_6G(7035, 217),
146 RTW89_DEF_CHAN_6G(7055, 221),
147 RTW89_DEF_CHAN_6G(7075, 225),
148 RTW89_DEF_CHAN_6G(7095, 229),
149 RTW89_DEF_CHAN_6G(7115, 233),
150 };
151
152 static struct ieee80211_rate rtw89_bitrates[] = {
153 { .bitrate = 10, .hw_value = 0x00, },
154 { .bitrate = 20, .hw_value = 0x01, },
155 { .bitrate = 55, .hw_value = 0x02, },
156 { .bitrate = 110, .hw_value = 0x03, },
157 { .bitrate = 60, .hw_value = 0x04, },
158 { .bitrate = 90, .hw_value = 0x05, },
159 { .bitrate = 120, .hw_value = 0x06, },
160 { .bitrate = 180, .hw_value = 0x07, },
161 { .bitrate = 240, .hw_value = 0x08, },
162 { .bitrate = 360, .hw_value = 0x09, },
163 { .bitrate = 480, .hw_value = 0x0a, },
164 { .bitrate = 540, .hw_value = 0x0b, },
165 };
166
167 static const struct ieee80211_iface_limit rtw89_iface_limits[] = {
168 {
169 .max = 1,
170 .types = BIT(NL80211_IFTYPE_STATION),
171 },
172 {
173 .max = 1,
174 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
175 BIT(NL80211_IFTYPE_P2P_GO) |
176 BIT(NL80211_IFTYPE_AP),
177 },
178 };
179
180 static const struct ieee80211_iface_combination rtw89_iface_combs[] = {
181 {
182 .limits = rtw89_iface_limits,
183 .n_limits = ARRAY_SIZE(rtw89_iface_limits),
184 .max_interfaces = 2,
185 .num_different_channels = 1,
186 }
187 };
188
rtw89_ra_report_to_bitrate(struct rtw89_dev * rtwdev,u8 rpt_rate,u16 * bitrate)189 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate)
190 {
191 struct ieee80211_rate rate;
192
193 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) {
194 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate);
195 return false;
196 }
197
198 rate = rtw89_bitrates[rpt_rate];
199 *bitrate = rate.bitrate;
200
201 return true;
202 }
203
204 static const struct ieee80211_supported_band rtw89_sband_2ghz = {
205 .band = NL80211_BAND_2GHZ,
206 .channels = rtw89_channels_2ghz,
207 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz),
208 .bitrates = rtw89_bitrates,
209 .n_bitrates = ARRAY_SIZE(rtw89_bitrates),
210 .ht_cap = {0},
211 .vht_cap = {0},
212 };
213
214 static const struct ieee80211_supported_band rtw89_sband_5ghz = {
215 .band = NL80211_BAND_5GHZ,
216 .channels = rtw89_channels_5ghz,
217 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz),
218
219 /* 5G has no CCK rates, 1M/2M/5.5M/11M */
220 .bitrates = rtw89_bitrates + 4,
221 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4,
222 .ht_cap = {0},
223 .vht_cap = {0},
224 };
225
226 static const struct ieee80211_supported_band rtw89_sband_6ghz = {
227 .band = NL80211_BAND_6GHZ,
228 .channels = rtw89_channels_6ghz,
229 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz),
230
231 /* 6G has no CCK rates, 1M/2M/5.5M/11M */
232 .bitrates = rtw89_bitrates + 4,
233 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4,
234 };
235
rtw89_traffic_stats_accu(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats,struct sk_buff * skb,bool tx)236 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev,
237 struct rtw89_traffic_stats *stats,
238 struct sk_buff *skb, bool tx)
239 {
240 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
241
242 if (!ieee80211_is_data(hdr->frame_control))
243 return;
244
245 if (is_broadcast_ether_addr(hdr->addr1) ||
246 is_multicast_ether_addr(hdr->addr1))
247 return;
248
249 if (tx) {
250 stats->tx_cnt++;
251 stats->tx_unicast += skb->len;
252 } else {
253 stats->rx_cnt++;
254 stats->rx_unicast += skb->len;
255 }
256 }
257
rtw89_get_default_chandef(struct cfg80211_chan_def * chandef)258 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef)
259 {
260 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0],
261 NL80211_CHAN_NO_HT);
262 }
263
rtw89_get_channel_params(const struct cfg80211_chan_def * chandef,struct rtw89_chan * chan)264 static void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
265 struct rtw89_chan *chan)
266 {
267 struct ieee80211_channel *channel = chandef->chan;
268 enum nl80211_chan_width width = chandef->width;
269 u32 primary_freq, center_freq;
270 u8 center_chan;
271 u8 bandwidth = RTW89_CHANNEL_WIDTH_20;
272 u32 offset;
273 u8 band;
274
275 center_chan = channel->hw_value;
276 primary_freq = channel->center_freq;
277 center_freq = chandef->center_freq1;
278
279 switch (width) {
280 case NL80211_CHAN_WIDTH_20_NOHT:
281 case NL80211_CHAN_WIDTH_20:
282 bandwidth = RTW89_CHANNEL_WIDTH_20;
283 break;
284 case NL80211_CHAN_WIDTH_40:
285 bandwidth = RTW89_CHANNEL_WIDTH_40;
286 if (primary_freq > center_freq) {
287 center_chan -= 2;
288 } else {
289 center_chan += 2;
290 }
291 break;
292 case NL80211_CHAN_WIDTH_80:
293 case NL80211_CHAN_WIDTH_160:
294 bandwidth = nl_to_rtw89_bandwidth(width);
295 if (primary_freq > center_freq) {
296 offset = (primary_freq - center_freq - 10) / 20;
297 center_chan -= 2 + offset * 4;
298 } else {
299 offset = (center_freq - primary_freq - 10) / 20;
300 center_chan += 2 + offset * 4;
301 }
302 break;
303 default:
304 center_chan = 0;
305 break;
306 }
307
308 switch (channel->band) {
309 default:
310 case NL80211_BAND_2GHZ:
311 band = RTW89_BAND_2G;
312 break;
313 case NL80211_BAND_5GHZ:
314 band = RTW89_BAND_5G;
315 break;
316 case NL80211_BAND_6GHZ:
317 band = RTW89_BAND_6G;
318 break;
319 }
320
321 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth);
322 }
323
rtw89_core_set_chip_txpwr(struct rtw89_dev * rtwdev)324 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev)
325 {
326 const struct rtw89_chip_info *chip = rtwdev->chip;
327 const struct rtw89_chan *chan;
328 enum rtw89_sub_entity_idx sub_entity_idx;
329 enum rtw89_phy_idx phy_idx;
330 enum rtw89_entity_mode mode;
331 bool entity_active;
332
333 entity_active = rtw89_get_entity_state(rtwdev);
334 if (!entity_active)
335 return;
336
337 mode = rtw89_get_entity_mode(rtwdev);
338 if (WARN(mode != RTW89_ENTITY_MODE_SCC, "Invalid ent mode: %d\n", mode))
339 return;
340
341 sub_entity_idx = RTW89_SUB_ENTITY_0;
342 phy_idx = RTW89_PHY_0;
343 chan = rtw89_chan_get(rtwdev, sub_entity_idx);
344 chip->ops->set_txpwr(rtwdev, chan, phy_idx);
345 }
346
rtw89_set_channel(struct rtw89_dev * rtwdev)347 void rtw89_set_channel(struct rtw89_dev *rtwdev)
348 {
349 const struct rtw89_chip_info *chip = rtwdev->chip;
350 const struct cfg80211_chan_def *chandef;
351 enum rtw89_sub_entity_idx sub_entity_idx;
352 enum rtw89_mac_idx mac_idx;
353 enum rtw89_phy_idx phy_idx;
354 struct rtw89_chan chan;
355 struct rtw89_channel_help_params bak;
356 enum rtw89_entity_mode mode;
357 bool band_changed;
358 bool entity_active;
359
360 entity_active = rtw89_get_entity_state(rtwdev);
361
362 mode = rtw89_entity_recalc(rtwdev);
363 if (WARN(mode != RTW89_ENTITY_MODE_SCC, "Invalid ent mode: %d\n", mode))
364 return;
365
366 sub_entity_idx = RTW89_SUB_ENTITY_0;
367 mac_idx = RTW89_MAC_0;
368 phy_idx = RTW89_PHY_0;
369 chandef = rtw89_chandef_get(rtwdev, sub_entity_idx);
370 rtw89_get_channel_params(chandef, &chan);
371 if (WARN(chan.channel == 0, "Invalid channel\n"))
372 return;
373
374 band_changed = rtw89_assign_entity_chan(rtwdev, sub_entity_idx, &chan);
375
376 rtw89_chip_set_channel_prepare(rtwdev, &bak, &chan, mac_idx, phy_idx);
377
378 chip->ops->set_channel(rtwdev, &chan, mac_idx, phy_idx);
379
380 chip->ops->set_txpwr(rtwdev, &chan, phy_idx);
381
382 rtw89_chip_set_channel_done(rtwdev, &bak, &chan, mac_idx, phy_idx);
383
384 if (!entity_active || band_changed) {
385 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan.band_type);
386 rtw89_chip_rfk_band_changed(rtwdev, phy_idx);
387 }
388
389 rtw89_set_entity_state(rtwdev, true);
390 }
391
rtw89_get_channel(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_chan * chan)392 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
393 struct rtw89_chan *chan)
394 {
395 const struct cfg80211_chan_def *chandef;
396
397 chandef = rtw89_chandef_get(rtwdev, rtwvif->sub_entity_idx);
398 rtw89_get_channel_params(chandef, chan);
399 }
400
401 static enum rtw89_core_tx_type
rtw89_core_get_tx_type(struct rtw89_dev * rtwdev,struct sk_buff * skb)402 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev,
403 struct sk_buff *skb)
404 {
405 struct ieee80211_hdr *hdr = (void *)skb->data;
406 __le16 fc = hdr->frame_control;
407
408 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc))
409 return RTW89_CORE_TX_TYPE_MGMT;
410
411 return RTW89_CORE_TX_TYPE_DATA;
412 }
413
414 static void
rtw89_core_tx_update_ampdu_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)415 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev,
416 struct rtw89_core_tx_request *tx_req,
417 enum btc_pkt_type pkt_type)
418 {
419 struct ieee80211_sta *sta = tx_req->sta;
420 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
421 struct sk_buff *skb = tx_req->skb;
422 struct rtw89_sta *rtwsta;
423 u8 ampdu_num;
424 u8 tid;
425
426 if (pkt_type == PACKET_EAPOL) {
427 desc_info->bk = true;
428 return;
429 }
430
431 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU))
432 return;
433
434 if (!sta) {
435 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n");
436 return;
437 }
438
439 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
440 rtwsta = (struct rtw89_sta *)sta->drv_priv;
441
442 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ?
443 rtwsta->ampdu_params[tid].agg_num :
444 4 << sta->deflink.ht_cap.ampdu_factor) - 1);
445
446 desc_info->agg_en = true;
447 desc_info->ampdu_density = sta->deflink.ht_cap.ampdu_density;
448 desc_info->ampdu_num = ampdu_num;
449 }
450
451 static void
rtw89_core_tx_update_sec_key(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)452 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev,
453 struct rtw89_core_tx_request *tx_req)
454 {
455 const struct rtw89_chip_info *chip = rtwdev->chip;
456 struct ieee80211_vif *vif = tx_req->vif;
457 struct ieee80211_sta *sta = tx_req->sta;
458 struct ieee80211_tx_info *info;
459 struct ieee80211_key_conf *key;
460 struct rtw89_vif *rtwvif;
461 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
462 struct rtw89_addr_cam_entry *addr_cam;
463 struct rtw89_sec_cam_entry *sec_cam;
464 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
465 struct sk_buff *skb = tx_req->skb;
466 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE;
467 u64 pn64;
468
469 if (!vif) {
470 rtw89_warn(rtwdev, "cannot set sec key without vif\n");
471 return;
472 }
473
474 rtwvif = (struct rtw89_vif *)vif->drv_priv;
475 addr_cam = rtw89_get_addr_cam_of(rtwvif, rtwsta);
476
477 info = IEEE80211_SKB_CB(skb);
478 key = info->control.hw_key;
479 sec_cam = addr_cam->sec_entries[key->hw_key_idx];
480 if (!sec_cam) {
481 rtw89_warn(rtwdev, "sec cam entry is empty\n");
482 return;
483 }
484
485 switch (key->cipher) {
486 case WLAN_CIPHER_SUITE_WEP40:
487 sec_type = RTW89_SEC_KEY_TYPE_WEP40;
488 break;
489 case WLAN_CIPHER_SUITE_WEP104:
490 sec_type = RTW89_SEC_KEY_TYPE_WEP104;
491 break;
492 case WLAN_CIPHER_SUITE_TKIP:
493 sec_type = RTW89_SEC_KEY_TYPE_TKIP;
494 break;
495 case WLAN_CIPHER_SUITE_CCMP:
496 sec_type = RTW89_SEC_KEY_TYPE_CCMP128;
497 break;
498 case WLAN_CIPHER_SUITE_CCMP_256:
499 sec_type = RTW89_SEC_KEY_TYPE_CCMP256;
500 break;
501 case WLAN_CIPHER_SUITE_GCMP:
502 sec_type = RTW89_SEC_KEY_TYPE_GCMP128;
503 break;
504 case WLAN_CIPHER_SUITE_GCMP_256:
505 sec_type = RTW89_SEC_KEY_TYPE_GCMP256;
506 break;
507 default:
508 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher);
509 return;
510 }
511
512 desc_info->sec_en = true;
513 desc_info->sec_keyid = key->keyidx;
514 desc_info->sec_type = sec_type;
515 desc_info->sec_cam_idx = sec_cam->sec_cam_idx;
516
517 if (!chip->hw_sec_hdr)
518 return;
519
520 pn64 = atomic64_inc_return(&key->tx_pn);
521 desc_info->sec_seq[0] = pn64;
522 desc_info->sec_seq[1] = pn64 >> 8;
523 desc_info->sec_seq[2] = pn64 >> 16;
524 desc_info->sec_seq[3] = pn64 >> 24;
525 desc_info->sec_seq[4] = pn64 >> 32;
526 desc_info->sec_seq[5] = pn64 >> 40;
527 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */
528 }
529
rtw89_core_get_mgmt_rate(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)530 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev,
531 struct rtw89_core_tx_request *tx_req)
532 {
533 struct sk_buff *skb = tx_req->skb;
534 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
535 struct ieee80211_vif *vif = tx_info->control.vif;
536 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
537 u16 lowest_rate;
538
539 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE ||
540 (vif && vif->p2p))
541 lowest_rate = RTW89_HW_RATE_OFDM6;
542 else if (chan->band_type == RTW89_BAND_2G)
543 lowest_rate = RTW89_HW_RATE_CCK1;
544 else
545 lowest_rate = RTW89_HW_RATE_OFDM6;
546
547 if (!vif || !vif->bss_conf.basic_rates || !tx_req->sta)
548 return lowest_rate;
549
550 return __ffs(vif->bss_conf.basic_rates) + lowest_rate;
551 }
552
rtw89_core_tx_get_mac_id(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)553 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev,
554 struct rtw89_core_tx_request *tx_req)
555 {
556 struct ieee80211_vif *vif = tx_req->vif;
557 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
558 struct ieee80211_sta *sta = tx_req->sta;
559 struct rtw89_sta *rtwsta;
560
561 if (!sta)
562 return rtwvif->mac_id;
563
564 rtwsta = (struct rtw89_sta *)sta->drv_priv;
565 return rtwsta->mac_id;
566 }
567
568 static void
rtw89_core_tx_update_mgmt_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)569 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev,
570 struct rtw89_core_tx_request *tx_req)
571 {
572 struct ieee80211_vif *vif = tx_req->vif;
573 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
574 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
575 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
576 u8 qsel, ch_dma;
577
578 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT;
579 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
580
581 desc_info->qsel = qsel;
582 desc_info->ch_dma = ch_dma;
583 desc_info->port = desc_info->hiq ? rtwvif->port : 0;
584 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req);
585 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL;
586 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE;
587
588 /* fixed data rate for mgmt frames */
589 desc_info->en_wd_info = true;
590 desc_info->use_rate = true;
591 desc_info->dis_data_fb = true;
592 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req);
593
594 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
595 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n",
596 desc_info->data_rate, chan->channel, chan->band_type,
597 chan->band_width);
598 }
599
600 static void
rtw89_core_tx_update_h2c_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)601 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev,
602 struct rtw89_core_tx_request *tx_req)
603 {
604 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
605
606 desc_info->is_bmc = false;
607 desc_info->wd_page = false;
608 desc_info->ch_dma = RTW89_DMA_H2C;
609 }
610
rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev * rtwdev,__le32 * htc)611 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc)
612 {
613 static const u8 rtw89_bandwidth_to_om[] = {
614 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20,
615 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40,
616 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80,
617 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80,
618 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80,
619 };
620 const struct rtw89_chip_info *chip = rtwdev->chip;
621 struct rtw89_hal *hal = &rtwdev->hal;
622 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
623 u8 om_bandwidth;
624
625 if (!chip->dis_2g_40m_ul_ofdma ||
626 chan->band_type != RTW89_BAND_2G ||
627 chan->band_width != RTW89_CHANNEL_WIDTH_40)
628 return;
629
630 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ?
631 rtw89_bandwidth_to_om[chan->band_width] : 0;
632 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) |
633 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) |
634 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) |
635 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) |
636 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) |
637 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) |
638 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) |
639 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) |
640 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS);
641 }
642
643 static bool
__rtw89_core_tx_check_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)644 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev,
645 struct rtw89_core_tx_request *tx_req,
646 enum btc_pkt_type pkt_type)
647 {
648 struct ieee80211_sta *sta = tx_req->sta;
649 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
650 struct sk_buff *skb = tx_req->skb;
651 struct ieee80211_hdr *hdr = (void *)skb->data;
652 __le16 fc = hdr->frame_control;
653
654 /* AP IOT issue with EAPoL, ARP and DHCP */
655 if (pkt_type < PACKET_MAX)
656 return false;
657
658 if (!sta || !sta->deflink.he_cap.has_he)
659 return false;
660
661 if (!ieee80211_is_data_qos(fc))
662 return false;
663
664 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN)
665 return false;
666
667 if (rtwsta && rtwsta->ra_report.might_fallback_legacy)
668 return false;
669
670 return true;
671 }
672
673 static void
__rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)674 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev,
675 struct rtw89_core_tx_request *tx_req)
676 {
677 struct ieee80211_sta *sta = tx_req->sta;
678 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
679 struct sk_buff *skb = tx_req->skb;
680 struct ieee80211_hdr *hdr = (void *)skb->data;
681 __le16 fc = hdr->frame_control;
682 void *data;
683 __le32 *htc;
684 u8 *qc;
685 int hdr_len;
686
687 hdr_len = ieee80211_has_a4(fc) ? 32 : 26;
688 data = skb_push(skb, IEEE80211_HT_CTL_LEN);
689 #if defined(__linux__)
690 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len);
691 #elif defined(__FreeBSD__)
692 memmove(data, (u8 *)data + IEEE80211_HT_CTL_LEN, hdr_len);
693 #endif
694
695 hdr = data;
696 #if defined(__linux__)
697 htc = data + hdr_len;
698 #elif defined(__FreeBSD__)
699 htc = (__le32 *)((u8 *)data + hdr_len);
700 #endif
701 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER);
702 *htc = rtwsta->htc_template ? rtwsta->htc_template :
703 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) |
704 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID);
705
706 #if defined(__linux__)
707 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN;
708 #elif defined(__FreeBSD__)
709 qc = (u8 *)data + hdr_len - IEEE80211_QOS_CTL_LEN;
710 #endif
711 qc[0] |= IEEE80211_QOS_CTL_EOSP;
712 }
713
714 static void
rtw89_core_tx_update_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)715 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev,
716 struct rtw89_core_tx_request *tx_req,
717 enum btc_pkt_type pkt_type)
718 {
719 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
720 struct ieee80211_vif *vif = tx_req->vif;
721 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
722
723 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type))
724 goto desc_bk;
725
726 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req);
727
728 desc_info->pkt_size += IEEE80211_HT_CTL_LEN;
729 desc_info->a_ctrl_bsr = true;
730
731 desc_bk:
732 if (!rtwvif || rtwvif->last_a_ctrl == desc_info->a_ctrl_bsr)
733 return;
734
735 rtwvif->last_a_ctrl = desc_info->a_ctrl_bsr;
736 desc_info->bk = true;
737 }
738
rtw89_core_get_data_rate(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)739 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev,
740 struct rtw89_core_tx_request *tx_req)
741 {
742 struct ieee80211_vif *vif = tx_req->vif;
743 struct ieee80211_sta *sta = tx_req->sta;
744 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
745 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern;
746 enum rtw89_sub_entity_idx idx = rtwvif->sub_entity_idx;
747 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx);
748 u16 lowest_rate;
749
750 if (rate_pattern->enable)
751 return rate_pattern->rate;
752
753 if (vif->p2p)
754 lowest_rate = RTW89_HW_RATE_OFDM6;
755 else if (chan->band_type == RTW89_BAND_2G)
756 lowest_rate = RTW89_HW_RATE_CCK1;
757 else
758 lowest_rate = RTW89_HW_RATE_OFDM6;
759
760 if (!sta || !sta->deflink.supp_rates[chan->band_type])
761 return lowest_rate;
762
763 return __ffs(sta->deflink.supp_rates[chan->band_type]) + lowest_rate;
764 }
765
766 static void
rtw89_core_tx_update_data_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)767 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev,
768 struct rtw89_core_tx_request *tx_req)
769 {
770 struct ieee80211_vif *vif = tx_req->vif;
771 struct ieee80211_sta *sta = tx_req->sta;
772 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
773 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
774 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
775 struct sk_buff *skb = tx_req->skb;
776 u8 tid, tid_indicate;
777 u8 qsel, ch_dma;
778
779 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
780 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid);
781 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid);
782 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
783
784 desc_info->ch_dma = ch_dma;
785 desc_info->tid_indicate = tid_indicate;
786 desc_info->qsel = qsel;
787 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req);
788 desc_info->port = desc_info->hiq ? rtwvif->port : 0;
789 desc_info->er_cap = rtwsta ? rtwsta->er_cap : false;
790
791 /* enable wd_info for AMPDU */
792 desc_info->en_wd_info = true;
793
794 if (IEEE80211_SKB_CB(skb)->control.hw_key)
795 rtw89_core_tx_update_sec_key(rtwdev, tx_req);
796
797 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req);
798 }
799
800 static enum btc_pkt_type
rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)801 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev,
802 struct rtw89_core_tx_request *tx_req)
803 {
804 struct sk_buff *skb = tx_req->skb;
805 struct udphdr *udphdr;
806
807 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) {
808 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work);
809 return PACKET_EAPOL;
810 }
811
812 if (skb->protocol == htons(ETH_P_ARP)) {
813 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work);
814 return PACKET_ARP;
815 }
816
817 if (skb->protocol == htons(ETH_P_IP) &&
818 ip_hdr(skb)->protocol == IPPROTO_UDP) {
819 udphdr = udp_hdr(skb);
820 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) ||
821 (udphdr->source == htons(68) && udphdr->dest == htons(67))) &&
822 skb->len > 282) {
823 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work);
824 return PACKET_DHCP;
825 }
826 }
827
828 if (skb->protocol == htons(ETH_P_IP) &&
829 ip_hdr(skb)->protocol == IPPROTO_ICMP) {
830 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work);
831 return PACKET_ICMP;
832 }
833
834 return PACKET_MAX;
835 }
836
rtw89_core_tx_update_llc_hdr(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,struct sk_buff * skb)837 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev,
838 struct rtw89_tx_desc_info *desc_info,
839 struct sk_buff *skb)
840 {
841 struct ieee80211_hdr *hdr = (void *)skb->data;
842 __le16 fc = hdr->frame_control;
843
844 desc_info->hdr_llc_len = ieee80211_hdrlen(fc);
845 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */
846 }
847
848 static void
rtw89_core_tx_wake(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)849 rtw89_core_tx_wake(struct rtw89_dev *rtwdev,
850 struct rtw89_core_tx_request *tx_req)
851 {
852 const struct rtw89_chip_info *chip = rtwdev->chip;
853
854 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw))
855 return;
856
857 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags))
858 return;
859
860 if (chip->chip_id != RTL8852C &&
861 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT)
862 return;
863
864 rtw89_mac_notify_wake(rtwdev);
865 }
866
867 static void
rtw89_core_tx_update_desc_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)868 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev,
869 struct rtw89_core_tx_request *tx_req)
870 {
871 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
872 struct sk_buff *skb = tx_req->skb;
873 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
874 struct ieee80211_hdr *hdr = (void *)skb->data;
875 enum rtw89_core_tx_type tx_type;
876 enum btc_pkt_type pkt_type;
877 bool is_bmc;
878 u16 seq;
879
880 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
881 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) {
882 tx_type = rtw89_core_get_tx_type(rtwdev, skb);
883 tx_req->tx_type = tx_type;
884 }
885 is_bmc = (is_broadcast_ether_addr(hdr->addr1) ||
886 is_multicast_ether_addr(hdr->addr1));
887
888 desc_info->seq = seq;
889 desc_info->pkt_size = skb->len;
890 desc_info->is_bmc = is_bmc;
891 desc_info->wd_page = true;
892 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM;
893
894 switch (tx_req->tx_type) {
895 case RTW89_CORE_TX_TYPE_MGMT:
896 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req);
897 break;
898 case RTW89_CORE_TX_TYPE_DATA:
899 rtw89_core_tx_update_data_info(rtwdev, tx_req);
900 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req);
901 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type);
902 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type);
903 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb);
904 break;
905 case RTW89_CORE_TX_TYPE_FWCMD:
906 rtw89_core_tx_update_h2c_info(rtwdev, tx_req);
907 break;
908 }
909 }
910
rtw89_core_tx_kick_off(struct rtw89_dev * rtwdev,u8 qsel)911 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel)
912 {
913 u8 ch_dma;
914
915 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
916
917 rtw89_hci_tx_kick_off(rtwdev, ch_dma);
918 }
919
rtw89_core_tx_kick_off_and_wait(struct rtw89_dev * rtwdev,struct sk_buff * skb,int qsel,unsigned int timeout)920 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
921 int qsel, unsigned int timeout)
922 {
923 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb);
924 struct rtw89_tx_wait_info *wait;
925 unsigned long time_left;
926 int ret = 0;
927
928 wait = kzalloc(sizeof(*wait), GFP_KERNEL);
929 if (!wait) {
930 rtw89_core_tx_kick_off(rtwdev, qsel);
931 return 0;
932 }
933
934 init_completion(&wait->completion);
935 rcu_assign_pointer(skb_data->wait, wait);
936
937 rtw89_core_tx_kick_off(rtwdev, qsel);
938 time_left = wait_for_completion_timeout(&wait->completion,
939 msecs_to_jiffies(timeout));
940 if (time_left == 0)
941 ret = -ETIMEDOUT;
942 else if (!wait->tx_done)
943 ret = -EAGAIN;
944
945 rcu_assign_pointer(skb_data->wait, NULL);
946 kfree_rcu(wait, rcu_head);
947
948 return ret;
949 }
950
rtw89_h2c_tx(struct rtw89_dev * rtwdev,struct sk_buff * skb,bool fwdl)951 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
952 struct sk_buff *skb, bool fwdl)
953 {
954 struct rtw89_core_tx_request tx_req = {0};
955 u32 cnt;
956 int ret;
957
958 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) {
959 rtw89_debug(rtwdev, RTW89_DBG_FW,
960 "ignore h2c due to power is off with firmware state=%d\n",
961 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags));
962 dev_kfree_skb(skb);
963 return 0;
964 }
965
966 tx_req.skb = skb;
967 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD;
968 if (fwdl)
969 tx_req.desc_info.fw_dl = true;
970
971 rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
972
973 if (!fwdl)
974 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len);
975
976 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12);
977 if (cnt == 0) {
978 rtw89_err(rtwdev, "no tx fwcmd resource\n");
979 return -ENOSPC;
980 }
981
982 ret = rtw89_hci_tx_write(rtwdev, &tx_req);
983 if (ret) {
984 rtw89_err(rtwdev, "failed to transmit skb to HCI\n");
985 return ret;
986 }
987 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12);
988
989 return 0;
990 }
991
rtw89_core_tx_write(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct sk_buff * skb,int * qsel)992 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
993 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel)
994 {
995 struct rtw89_core_tx_request tx_req = {0};
996 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
997 int ret;
998
999 tx_req.skb = skb;
1000 tx_req.sta = sta;
1001 tx_req.vif = vif;
1002
1003 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true);
1004 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true);
1005 rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
1006 rtw89_core_tx_wake(rtwdev, &tx_req);
1007
1008 ret = rtw89_hci_tx_write(rtwdev, &tx_req);
1009 if (ret) {
1010 rtw89_err(rtwdev, "failed to transmit skb to HCI\n");
1011 return ret;
1012 }
1013
1014 if (qsel)
1015 *qsel = tx_req.desc_info.qsel;
1016
1017 return 0;
1018 }
1019
rtw89_build_txwd_body0(struct rtw89_tx_desc_info * desc_info)1020 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info)
1021 {
1022 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) |
1023 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) |
1024 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) |
1025 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1026 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) |
1027 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) |
1028 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) |
1029 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode);
1030
1031 return cpu_to_le32(dword);
1032 }
1033
rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info * desc_info)1034 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info)
1035 {
1036 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) |
1037 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) |
1038 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) |
1039 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1040 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) |
1041 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl);
1042
1043 return cpu_to_le32(dword);
1044 }
1045
rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info * desc_info)1046 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info)
1047 {
1048 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) |
1049 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) |
1050 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type);
1051
1052 return cpu_to_le32(dword);
1053 }
1054
rtw89_build_txwd_body2(struct rtw89_tx_desc_info * desc_info)1055 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info)
1056 {
1057 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) |
1058 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) |
1059 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) |
1060 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id);
1061
1062 return cpu_to_le32(dword);
1063 }
1064
rtw89_build_txwd_body3(struct rtw89_tx_desc_info * desc_info)1065 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info)
1066 {
1067 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) |
1068 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) |
1069 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk);
1070
1071 return cpu_to_le32(dword);
1072 }
1073
rtw89_build_txwd_body4(struct rtw89_tx_desc_info * desc_info)1074 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info)
1075 {
1076 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) |
1077 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]);
1078
1079 return cpu_to_le32(dword);
1080 }
1081
rtw89_build_txwd_body5(struct rtw89_tx_desc_info * desc_info)1082 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info)
1083 {
1084 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) |
1085 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) |
1086 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) |
1087 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]);
1088
1089 return cpu_to_le32(dword);
1090 }
1091
rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info * desc_info)1092 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info)
1093 {
1094 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) |
1095 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate);
1096
1097 return cpu_to_le32(dword);
1098 }
1099
rtw89_build_txwd_info0(struct rtw89_tx_desc_info * desc_info)1100 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info)
1101 {
1102 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) |
1103 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) |
1104 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1105 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port);
1106
1107 return cpu_to_le32(dword);
1108 }
1109
rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info * desc_info)1110 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info)
1111 {
1112 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1113 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) |
1114 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) |
1115 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0);
1116
1117 return cpu_to_le32(dword);
1118 }
1119
rtw89_build_txwd_info1(struct rtw89_tx_desc_info * desc_info)1120 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info)
1121 {
1122 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) |
1123 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) |
1124 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE,
1125 desc_info->data_retry_lowest_rate);
1126
1127 return cpu_to_le32(dword);
1128 }
1129
rtw89_build_txwd_info2(struct rtw89_tx_desc_info * desc_info)1130 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info)
1131 {
1132 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1133 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) |
1134 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) |
1135 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1136
1137 return cpu_to_le32(dword);
1138 }
1139
rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info * desc_info)1140 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info)
1141 {
1142 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1143 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) |
1144 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1145
1146 return cpu_to_le32(dword);
1147 }
1148
rtw89_build_txwd_info4(struct rtw89_tx_desc_info * desc_info)1149 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info)
1150 {
1151 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, 1) |
1152 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1);
1153
1154 return cpu_to_le32(dword);
1155 }
1156
rtw89_core_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1157 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
1158 struct rtw89_tx_desc_info *desc_info,
1159 void *txdesc)
1160 {
1161 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc;
1162 struct rtw89_txwd_info *txwd_info;
1163
1164 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info);
1165 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info);
1166 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info);
1167
1168 if (!desc_info->en_wd_info)
1169 return;
1170
1171 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1);
1172 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info);
1173 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1174 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info);
1175 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1176
1177 }
1178 EXPORT_SYMBOL(rtw89_core_fill_txdesc);
1179
rtw89_core_fill_txdesc_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1180 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
1181 struct rtw89_tx_desc_info *desc_info,
1182 void *txdesc)
1183 {
1184 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc;
1185 struct rtw89_txwd_info *txwd_info;
1186
1187 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info);
1188 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info);
1189 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info);
1190 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info);
1191 if (desc_info->sec_en) {
1192 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info);
1193 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info);
1194 }
1195 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info);
1196
1197 if (!desc_info->en_wd_info)
1198 return;
1199
1200 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1);
1201 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info);
1202 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1203 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info);
1204 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1205 }
1206 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1);
1207
rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info * desc_info)1208 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info)
1209 {
1210 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) |
1211 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ?
1212 RTW89_CORE_RX_TYPE_FWDL :
1213 RTW89_CORE_RX_TYPE_H2C);
1214
1215 return cpu_to_le32(dword);
1216 }
1217
rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1218 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
1219 struct rtw89_tx_desc_info *desc_info,
1220 void *txdesc)
1221 {
1222 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc;
1223
1224 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info);
1225 }
1226 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1);
1227
rtw89_core_rx_process_mac_ppdu(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct rtw89_rx_phy_ppdu * phy_ppdu)1228 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev,
1229 struct sk_buff *skb,
1230 struct rtw89_rx_phy_ppdu *phy_ppdu)
1231 {
1232 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data;
1233 bool rx_cnt_valid = false;
1234 u8 plcp_size = 0;
1235 u8 usr_num = 0;
1236 u8 *phy_sts;
1237
1238 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD);
1239 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3;
1240 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM);
1241 if (usr_num > RTW89_PPDU_MAX_USR) {
1242 rtw89_warn(rtwdev, "Invalid user number in mac info\n");
1243 return -EINVAL;
1244 }
1245
1246 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE;
1247 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE;
1248 /* 8-byte alignment */
1249 if (usr_num & BIT(0))
1250 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE;
1251 if (rx_cnt_valid)
1252 phy_sts += RTW89_PPDU_MAC_RX_CNT_SIZE;
1253 phy_sts += plcp_size;
1254
1255 phy_ppdu->buf = phy_sts;
1256 phy_ppdu->len = skb->data + skb->len - phy_sts;
1257
1258 return 0;
1259 }
1260
rtw89_core_rx_process_phy_ppdu_iter(void * data,struct ieee80211_sta * sta)1261 static void rtw89_core_rx_process_phy_ppdu_iter(void *data,
1262 struct ieee80211_sta *sta)
1263 {
1264 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
1265 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data;
1266 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
1267 struct rtw89_hal *hal = &rtwdev->hal;
1268 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
1269 u8 ant_pos = U8_MAX;
1270 u8 evm_pos = 0;
1271 int i;
1272
1273 if (rtwsta->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self)
1274 return;
1275
1276 if (hal->ant_diversity && hal->antenna_rx) {
1277 ant_pos = __ffs(hal->antenna_rx);
1278 evm_pos = ant_pos;
1279 }
1280
1281 ewma_rssi_add(&rtwsta->avg_rssi, phy_ppdu->rssi_avg);
1282
1283 if (ant_pos < ant_num) {
1284 ewma_rssi_add(&rtwsta->rssi[ant_pos], phy_ppdu->rssi[0]);
1285 } else {
1286 for (i = 0; i < rtwdev->chip->rf_path_num; i++)
1287 ewma_rssi_add(&rtwsta->rssi[i], phy_ppdu->rssi[i]);
1288 }
1289
1290 if (phy_ppdu->ofdm.has) {
1291 ewma_snr_add(&rtwsta->avg_snr, phy_ppdu->ofdm.avg_snr);
1292 ewma_evm_add(&rtwsta->evm_min[evm_pos], phy_ppdu->ofdm.evm_min);
1293 ewma_evm_add(&rtwsta->evm_max[evm_pos], phy_ppdu->ofdm.evm_max);
1294 }
1295 }
1296
1297 #define VAR_LEN 0xff
1298 #define VAR_LEN_UNIT 8
rtw89_core_get_phy_status_ie_len(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr)1299 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev,
1300 const struct rtw89_phy_sts_iehdr *iehdr)
1301 {
1302 static const u8 physts_ie_len_tab[32] = {
1303 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN,
1304 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN,
1305 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32
1306 };
1307 u16 ie_len;
1308 u8 ie;
1309
1310 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE);
1311 if (physts_ie_len_tab[ie] != VAR_LEN)
1312 ie_len = physts_ie_len_tab[ie];
1313 else
1314 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT;
1315
1316 return ie_len;
1317 }
1318
rtw89_core_parse_phy_status_ie01(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1319 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev,
1320 const struct rtw89_phy_sts_iehdr *iehdr,
1321 struct rtw89_rx_phy_ppdu *phy_ppdu)
1322 {
1323 const struct rtw89_phy_sts_ie0 *ie = (const struct rtw89_phy_sts_ie0 *)iehdr;
1324 s16 cfo;
1325 u32 t;
1326
1327 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX);
1328 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6)
1329 return;
1330
1331 if (!phy_ppdu->to_self)
1332 return;
1333
1334 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR);
1335 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX);
1336 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN);
1337 phy_ppdu->ofdm.has = true;
1338
1339 /* sign conversion for S(12,2) */
1340 if (rtwdev->chip->cfo_src_fd) {
1341 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO);
1342 cfo = sign_extend32(t, 11);
1343 } else {
1344 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO);
1345 cfo = sign_extend32(t, 11);
1346 }
1347
1348 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu);
1349 }
1350
rtw89_core_process_phy_status_ie(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)1351 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev,
1352 const struct rtw89_phy_sts_iehdr *iehdr,
1353 struct rtw89_rx_phy_ppdu *phy_ppdu)
1354 {
1355 u8 ie;
1356
1357 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE);
1358
1359 switch (ie) {
1360 case RTW89_PHYSTS_IE01_CMN_OFDM:
1361 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu);
1362 break;
1363 default:
1364 break;
1365 }
1366
1367 return 0;
1368 }
1369
rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu * phy_ppdu)1370 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu)
1371 {
1372 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf;
1373 u8 *rssi = phy_ppdu->rssi;
1374
1375 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP);
1376 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG);
1377 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A);
1378 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B);
1379 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C);
1380 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D);
1381 }
1382
rtw89_core_rx_process_phy_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1383 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev,
1384 struct rtw89_rx_phy_ppdu *phy_ppdu)
1385 {
1386 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf;
1387 u32 len_from_header;
1388
1389 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3;
1390
1391 if (len_from_header != phy_ppdu->len) {
1392 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n");
1393 return -EINVAL;
1394 }
1395 rtw89_core_update_phy_ppdu(phy_ppdu);
1396
1397 return 0;
1398 }
1399
rtw89_core_rx_parse_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1400 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev,
1401 struct rtw89_rx_phy_ppdu *phy_ppdu)
1402 {
1403 u16 ie_len;
1404 #if defined(__linux__)
1405 void *pos, *end;
1406 #elif defined(__FreeBSD__)
1407 u8 *pos, *end;
1408 #endif
1409
1410 /* mark invalid reports and bypass them */
1411 if (phy_ppdu->ie < RTW89_CCK_PKT)
1412 return -EINVAL;
1413
1414 #if defined(__linux__)
1415 pos = phy_ppdu->buf + PHY_STS_HDR_LEN;
1416 end = phy_ppdu->buf + phy_ppdu->len;
1417 #elif defined(__FreeBSD__)
1418 pos = (u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN;
1419 end = (u8 *)phy_ppdu->buf + phy_ppdu->len;
1420 #endif
1421 while (pos < end) {
1422 #if defined(__linux__)
1423 const struct rtw89_phy_sts_iehdr *iehdr = pos;
1424 #elif defined(__FreeBSD__)
1425 const struct rtw89_phy_sts_iehdr *iehdr = (void *)pos;
1426 #endif
1427
1428 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr);
1429 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu);
1430 pos += ie_len;
1431 if (pos > end || ie_len == 0) {
1432 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
1433 "phy status parse failed\n");
1434 return -EINVAL;
1435 }
1436 }
1437
1438 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu);
1439
1440 return 0;
1441 }
1442
rtw89_core_rx_process_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1443 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev,
1444 struct rtw89_rx_phy_ppdu *phy_ppdu)
1445 {
1446 int ret;
1447
1448 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu);
1449 if (ret)
1450 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n");
1451 else
1452 phy_ppdu->valid = true;
1453
1454 ieee80211_iterate_stations_atomic(rtwdev->hw,
1455 rtw89_core_rx_process_phy_ppdu_iter,
1456 phy_ppdu);
1457 }
1458
rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev * rtwdev,const struct rtw89_rx_desc_info * desc_info,bool rx_status)1459 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev,
1460 const struct rtw89_rx_desc_info *desc_info,
1461 bool rx_status)
1462 {
1463 switch (desc_info->gi_ltf) {
1464 case RTW89_GILTF_SGI_4XHE08:
1465 case RTW89_GILTF_2XHE08:
1466 case RTW89_GILTF_1XHE08:
1467 return NL80211_RATE_INFO_HE_GI_0_8;
1468 case RTW89_GILTF_2XHE16:
1469 case RTW89_GILTF_1XHE16:
1470 return NL80211_RATE_INFO_HE_GI_1_6;
1471 case RTW89_GILTF_LGI_4XHE32:
1472 return NL80211_RATE_INFO_HE_GI_3_2;
1473 default:
1474 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info->gi_ltf);
1475 return rx_status ? NL80211_RATE_INFO_HE_GI_3_2 : U8_MAX;
1476 }
1477 }
1478
rtw89_core_rx_ppdu_match(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * status)1479 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev,
1480 struct rtw89_rx_desc_info *desc_info,
1481 struct ieee80211_rx_status *status)
1482 {
1483 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
1484 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf;
1485 u16 data_rate;
1486 bool ret;
1487
1488 data_rate = desc_info->data_rate;
1489 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
1490 if (data_rate_mode == DATA_RATE_MODE_NON_HT) {
1491 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate);
1492 /* rate_idx is still hardware value here */
1493 } else if (data_rate_mode == DATA_RATE_MODE_HT) {
1494 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate);
1495 } else if (data_rate_mode == DATA_RATE_MODE_VHT) {
1496 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
1497 } else if (data_rate_mode == DATA_RATE_MODE_HE) {
1498 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
1499 } else {
1500 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
1501 }
1502
1503 bw = rtw89_hw_to_rate_info_bw(desc_info->bw);
1504 gi_ltf = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, false);
1505 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt &&
1506 status->rate_idx == rate_idx &&
1507 status->he_gi == gi_ltf &&
1508 status->bw == bw;
1509
1510 return ret;
1511 }
1512
1513 struct rtw89_vif_rx_stats_iter_data {
1514 struct rtw89_dev *rtwdev;
1515 struct rtw89_rx_phy_ppdu *phy_ppdu;
1516 struct rtw89_rx_desc_info *desc_info;
1517 struct sk_buff *skb;
1518 const u8 *bssid;
1519 };
1520
rtw89_stats_trigger_frame(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct sk_buff * skb)1521 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev,
1522 struct ieee80211_vif *vif,
1523 struct sk_buff *skb)
1524 {
1525 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
1526 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data;
1527 u8 *pos, *end, type;
1528 u16 aid;
1529
1530 if (!ether_addr_equal(vif->bss_conf.bssid, tf->ta) ||
1531 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION ||
1532 rtwvif->net_type == RTW89_NET_TYPE_NO_LINK)
1533 return;
1534
1535 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK);
1536 if (type != IEEE80211_TRIGGER_TYPE_BASIC)
1537 return;
1538
1539 end = (u8 *)tf + skb->len;
1540 pos = tf->variable;
1541
1542 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) {
1543 aid = RTW89_GET_TF_USER_INFO_AID12(pos);
1544 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
1545 "[TF] aid: %d, ul_mcs: %d, rua: %d\n",
1546 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos),
1547 RTW89_GET_TF_USER_INFO_RUA(pos));
1548
1549 if (aid == RTW89_TF_PAD)
1550 break;
1551
1552 if (aid == vif->cfg.aid) {
1553 rtwvif->stats.rx_tf_acc++;
1554 rtwdev->stats.rx_tf_acc++;
1555 break;
1556 }
1557
1558 pos += RTW89_TF_BASIC_USER_INFO_SZ;
1559 }
1560 }
1561
rtw89_cancel_6ghz_probe_work(struct work_struct * work)1562 static void rtw89_cancel_6ghz_probe_work(struct work_struct *work)
1563 {
1564 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
1565 cancel_6ghz_probe_work);
1566 struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
1567 struct rtw89_pktofld_info *info;
1568
1569 mutex_lock(&rtwdev->mutex);
1570
1571 if (!rtwdev->scanning)
1572 goto out;
1573
1574 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) {
1575 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload))
1576 continue;
1577
1578 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
1579
1580 /* Don't delete/free info from pkt_list at this moment. Let it
1581 * be deleted/freed in rtw89_release_pkt_list() after scanning,
1582 * since if during scanning, pkt_list is accessed in bottom half.
1583 */
1584 }
1585
1586 out:
1587 mutex_unlock(&rtwdev->mutex);
1588 }
1589
rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev * rtwdev,struct sk_buff * skb)1590 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev,
1591 struct sk_buff *skb)
1592 {
1593 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
1594 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1595 struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
1596 struct rtw89_pktofld_info *info;
1597 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie;
1598 bool queue_work = false;
1599
1600 if (rx_status->band != NL80211_BAND_6GHZ)
1601 return;
1602
1603 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len);
1604
1605 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) {
1606 if (ether_addr_equal(info->bssid, mgmt->bssid)) {
1607 info->cancel = true;
1608 queue_work = true;
1609 continue;
1610 }
1611
1612 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0)
1613 continue;
1614
1615 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) {
1616 info->cancel = true;
1617 queue_work = true;
1618 }
1619 }
1620
1621 if (queue_work)
1622 ieee80211_queue_work(rtwdev->hw, &rtwdev->cancel_6ghz_probe_work);
1623 }
1624
rtw89_vif_rx_stats_iter(void * data,u8 * mac,struct ieee80211_vif * vif)1625 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac,
1626 struct ieee80211_vif *vif)
1627 {
1628 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
1629 struct rtw89_vif_rx_stats_iter_data *iter_data = data;
1630 struct rtw89_dev *rtwdev = iter_data->rtwdev;
1631 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat;
1632 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info;
1633 struct sk_buff *skb = iter_data->skb;
1634 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1635 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu;
1636 const u8 *bssid = iter_data->bssid;
1637
1638 if (rtwdev->scanning &&
1639 (ieee80211_is_beacon(hdr->frame_control) ||
1640 ieee80211_is_probe_resp(hdr->frame_control)))
1641 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb);
1642
1643 if (!vif->bss_conf.bssid)
1644 return;
1645
1646 if (ieee80211_is_trigger(hdr->frame_control)) {
1647 rtw89_stats_trigger_frame(rtwdev, vif, skb);
1648 return;
1649 }
1650
1651 if (!ether_addr_equal(vif->bss_conf.bssid, bssid))
1652 return;
1653
1654 if (ieee80211_is_beacon(hdr->frame_control)) {
1655 if (vif->type == NL80211_IFTYPE_STATION)
1656 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu);
1657 pkt_stat->beacon_nr++;
1658 }
1659
1660 if (!ether_addr_equal(vif->addr, hdr->addr1))
1661 return;
1662
1663 if (desc_info->data_rate < RTW89_HW_RATE_NR)
1664 pkt_stat->rx_rate_cnt[desc_info->data_rate]++;
1665
1666 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false);
1667 }
1668
rtw89_core_rx_stats(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)1669 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev,
1670 struct rtw89_rx_phy_ppdu *phy_ppdu,
1671 struct rtw89_rx_desc_info *desc_info,
1672 struct sk_buff *skb)
1673 {
1674 struct rtw89_vif_rx_stats_iter_data iter_data;
1675
1676 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false);
1677
1678 iter_data.rtwdev = rtwdev;
1679 iter_data.phy_ppdu = phy_ppdu;
1680 iter_data.desc_info = desc_info;
1681 iter_data.skb = skb;
1682 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data);
1683 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data);
1684 }
1685
rtw89_correct_cck_chan(struct rtw89_dev * rtwdev,struct ieee80211_rx_status * status)1686 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev,
1687 struct ieee80211_rx_status *status)
1688 {
1689 const struct rtw89_chan_rcd *rcd =
1690 rtw89_chan_rcd_get(rtwdev, RTW89_SUB_ENTITY_0);
1691 u16 chan = rcd->prev_primary_channel;
1692 u8 band = rcd->prev_band_type == RTW89_BAND_2G ?
1693 NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
1694
1695 if (status->band != NL80211_BAND_2GHZ &&
1696 status->encoding == RX_ENC_LEGACY &&
1697 status->rate_idx < RTW89_HW_RATE_OFDM6) {
1698 status->freq = ieee80211_channel_to_frequency(chan, band);
1699 status->band = band;
1700 }
1701 }
1702
rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status * rx_status)1703 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status)
1704 {
1705 if (rx_status->band == NL80211_BAND_2GHZ ||
1706 rx_status->encoding != RX_ENC_LEGACY)
1707 return;
1708
1709 /* Some control frames' freq(ACKs in this case) are reported wrong due
1710 * to FW notify timing, set to lowest rate to prevent overflow.
1711 */
1712 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) {
1713 rx_status->rate_idx = 0;
1714 return;
1715 }
1716
1717 /* No 4 CCK rates for non-2G */
1718 rx_status->rate_idx -= 4;
1719 }
1720
rtw89_core_update_radiotap(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status)1721 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev,
1722 struct sk_buff *skb,
1723 struct ieee80211_rx_status *rx_status)
1724 {
1725 static const struct ieee80211_radiotap_he known_he = {
1726 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
1727 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
1728 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
1729 };
1730 struct ieee80211_radiotap_he *he;
1731
1732 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR))
1733 return;
1734
1735 if (rx_status->encoding == RX_ENC_HE) {
1736 rx_status->flag |= RX_FLAG_RADIOTAP_HE;
1737 he = skb_push(skb, sizeof(*he));
1738 *he = known_he;
1739 }
1740 }
1741
rtw89_core_rx_to_mac80211(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb_ppdu,struct ieee80211_rx_status * rx_status)1742 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev,
1743 struct rtw89_rx_phy_ppdu *phy_ppdu,
1744 struct rtw89_rx_desc_info *desc_info,
1745 struct sk_buff *skb_ppdu,
1746 struct ieee80211_rx_status *rx_status)
1747 {
1748 struct napi_struct *napi = &rtwdev->napi;
1749
1750 /* In low power mode, napi isn't scheduled. Receive it to netif. */
1751 if (unlikely(!test_bit(NAPI_STATE_SCHED, &napi->state)))
1752 napi = NULL;
1753
1754 rtw89_core_hw_to_sband_rate(rx_status);
1755 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu);
1756 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status);
1757 /* In low power mode, it does RX in thread context. */
1758 local_bh_disable();
1759 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi);
1760 local_bh_enable();
1761 rtwdev->napi_budget_countdown--;
1762 }
1763
rtw89_core_rx_pending_skb(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)1764 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev,
1765 struct rtw89_rx_phy_ppdu *phy_ppdu,
1766 struct rtw89_rx_desc_info *desc_info,
1767 struct sk_buff *skb)
1768 {
1769 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
1770 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band];
1771 struct sk_buff *skb_ppdu = NULL, *tmp;
1772 struct ieee80211_rx_status *rx_status;
1773
1774 if (curr > RTW89_MAX_PPDU_CNT)
1775 return;
1776
1777 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) {
1778 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]);
1779 rx_status = IEEE80211_SKB_RXCB(skb_ppdu);
1780 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status))
1781 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status);
1782 rtw89_correct_cck_chan(rtwdev, rx_status);
1783 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status);
1784 }
1785 }
1786
rtw89_core_rx_process_ppdu_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)1787 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev,
1788 struct rtw89_rx_desc_info *desc_info,
1789 struct sk_buff *skb)
1790 {
1791 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false,
1792 .len = skb->len,
1793 .to_self = desc_info->addr1_match,
1794 .rate = desc_info->data_rate,
1795 .mac_id = desc_info->mac_id};
1796 int ret;
1797
1798 if (desc_info->mac_info_valid)
1799 rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu);
1800 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu);
1801 if (ret)
1802 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "process ppdu failed\n");
1803
1804 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu);
1805 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb);
1806 dev_kfree_skb_any(skb);
1807 }
1808
rtw89_core_rx_process_report(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)1809 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev,
1810 struct rtw89_rx_desc_info *desc_info,
1811 struct sk_buff *skb)
1812 {
1813 switch (desc_info->pkt_type) {
1814 case RTW89_CORE_RX_TYPE_C2H:
1815 rtw89_fw_c2h_irqsafe(rtwdev, skb);
1816 break;
1817 case RTW89_CORE_RX_TYPE_PPDU_STAT:
1818 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb);
1819 break;
1820 default:
1821 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n",
1822 desc_info->pkt_type);
1823 dev_kfree_skb_any(skb);
1824 break;
1825 }
1826 }
1827
rtw89_core_query_rxdesc(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)1828 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
1829 struct rtw89_rx_desc_info *desc_info,
1830 u8 *data, u32 data_offset)
1831 {
1832 const struct rtw89_chip_info *chip = rtwdev->chip;
1833 struct rtw89_rxdesc_short *rxd_s;
1834 struct rtw89_rxdesc_long *rxd_l;
1835 u8 shift_len, drv_info_len;
1836
1837 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset);
1838 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK);
1839 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK);
1840 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD);
1841 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK);
1842 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD);
1843 if (chip->chip_id == RTL8852C)
1844 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK);
1845 else
1846 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK);
1847 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK);
1848 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK);
1849 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK);
1850 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN);
1851 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK);
1852 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK);
1853 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK);
1854 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR);
1855 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR);
1856 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC);
1857 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC);
1858 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH);
1859
1860 shift_len = desc_info->shift << 1; /* 2-byte unit */
1861 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
1862 desc_info->offset = data_offset + shift_len + drv_info_len;
1863 if (desc_info->long_rxdesc)
1864 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long);
1865 else
1866 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short);
1867 desc_info->ready = true;
1868
1869 if (!desc_info->long_rxdesc)
1870 return;
1871
1872 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset);
1873 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK);
1874 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD);
1875 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK);
1876 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK);
1877 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK);
1878 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK);
1879 }
1880 EXPORT_SYMBOL(rtw89_core_query_rxdesc);
1881
1882 struct rtw89_core_iter_rx_status {
1883 struct rtw89_dev *rtwdev;
1884 struct ieee80211_rx_status *rx_status;
1885 struct rtw89_rx_desc_info *desc_info;
1886 u8 mac_id;
1887 };
1888
1889 static
rtw89_core_stats_sta_rx_status_iter(void * data,struct ieee80211_sta * sta)1890 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta)
1891 {
1892 struct rtw89_core_iter_rx_status *iter_data =
1893 (struct rtw89_core_iter_rx_status *)data;
1894 struct ieee80211_rx_status *rx_status = iter_data->rx_status;
1895 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
1896 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info;
1897 u8 mac_id = iter_data->mac_id;
1898
1899 if (mac_id != rtwsta->mac_id)
1900 return;
1901
1902 rtwsta->rx_status = *rx_status;
1903 rtwsta->rx_hw_rate = desc_info->data_rate;
1904 }
1905
rtw89_core_stats_sta_rx_status(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)1906 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev,
1907 struct rtw89_rx_desc_info *desc_info,
1908 struct ieee80211_rx_status *rx_status)
1909 {
1910 struct rtw89_core_iter_rx_status iter_data;
1911
1912 if (!desc_info->addr1_match || !desc_info->long_rxdesc)
1913 return;
1914
1915 if (desc_info->frame_type != RTW89_RX_TYPE_DATA)
1916 return;
1917
1918 iter_data.rtwdev = rtwdev;
1919 iter_data.rx_status = rx_status;
1920 iter_data.desc_info = desc_info;
1921 iter_data.mac_id = desc_info->mac_id;
1922 ieee80211_iterate_stations_atomic(rtwdev->hw,
1923 rtw89_core_stats_sta_rx_status_iter,
1924 &iter_data);
1925 }
1926
rtw89_core_update_rx_status(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)1927 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev,
1928 struct rtw89_rx_desc_info *desc_info,
1929 struct ieee80211_rx_status *rx_status)
1930 {
1931 const struct cfg80211_chan_def *chandef =
1932 rtw89_chandef_get(rtwdev, RTW89_SUB_ENTITY_0);
1933 const struct rtw89_chan *cur = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1934 u16 data_rate;
1935 u8 data_rate_mode;
1936
1937 /* currently using single PHY */
1938 rx_status->freq = chandef->chan->center_freq;
1939 rx_status->band = chandef->chan->band;
1940
1941 if (rtwdev->scanning &&
1942 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) {
1943 u8 chan = cur->primary_channel;
1944 u8 band = cur->band_type;
1945 enum nl80211_band nl_band;
1946
1947 nl_band = rtw89_hw_to_nl80211_band(band);
1948 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band);
1949 rx_status->band = nl_band;
1950 }
1951
1952 if (desc_info->icv_err || desc_info->crc32_err)
1953 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
1954
1955 if (desc_info->hw_dec &&
1956 !(desc_info->sw_dec || desc_info->icv_err))
1957 rx_status->flag |= RX_FLAG_DECRYPTED;
1958
1959 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw);
1960
1961 data_rate = desc_info->data_rate;
1962 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
1963 if (data_rate_mode == DATA_RATE_MODE_NON_HT) {
1964 rx_status->encoding = RX_ENC_LEGACY;
1965 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate);
1966 /* convert rate_idx after we get the correct band */
1967 } else if (data_rate_mode == DATA_RATE_MODE_HT) {
1968 rx_status->encoding = RX_ENC_HT;
1969 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate);
1970 if (desc_info->gi_ltf)
1971 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
1972 } else if (data_rate_mode == DATA_RATE_MODE_VHT) {
1973 rx_status->encoding = RX_ENC_VHT;
1974 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
1975 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
1976 if (desc_info->gi_ltf)
1977 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
1978 } else if (data_rate_mode == DATA_RATE_MODE_HE) {
1979 rx_status->encoding = RX_ENC_HE;
1980 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
1981 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
1982 } else {
1983 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
1984 }
1985
1986 /* he_gi is used to match ppdu, so we always fill it. */
1987 rx_status->he_gi = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, true);
1988 rx_status->flag |= RX_FLAG_MACTIME_START;
1989 rx_status->mactime = desc_info->free_run_cnt;
1990
1991 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status);
1992 }
1993
rtw89_update_ps_mode(struct rtw89_dev * rtwdev)1994 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev)
1995 {
1996 const struct rtw89_chip_info *chip = rtwdev->chip;
1997
1998 if (rtw89_disable_ps_mode || !chip->ps_mode_supported ||
1999 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw))
2000 return RTW89_PS_MODE_NONE;
2001
2002 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) &&
2003 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw))
2004 return RTW89_PS_MODE_PWR_GATED;
2005
2006 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED))
2007 return RTW89_PS_MODE_CLK_GATED;
2008
2009 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF))
2010 return RTW89_PS_MODE_RFOFF;
2011
2012 return RTW89_PS_MODE_NONE;
2013 }
2014
rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info)2015 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev,
2016 struct rtw89_rx_desc_info *desc_info)
2017 {
2018 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts;
2019 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
2020 struct ieee80211_rx_status *rx_status;
2021 struct sk_buff *skb_ppdu, *tmp;
2022
2023 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) {
2024 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]);
2025 rx_status = IEEE80211_SKB_RXCB(skb_ppdu);
2026 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status);
2027 }
2028 }
2029
rtw89_core_rx(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)2030 void rtw89_core_rx(struct rtw89_dev *rtwdev,
2031 struct rtw89_rx_desc_info *desc_info,
2032 struct sk_buff *skb)
2033 {
2034 struct ieee80211_rx_status *rx_status;
2035 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts;
2036 u8 ppdu_cnt = desc_info->ppdu_cnt;
2037 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
2038
2039 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) {
2040 rtw89_core_rx_process_report(rtwdev, desc_info, skb);
2041 return;
2042 }
2043
2044 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) {
2045 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info);
2046 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt;
2047 }
2048
2049 rx_status = IEEE80211_SKB_RXCB(skb);
2050 memset(rx_status, 0, sizeof(*rx_status));
2051 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status);
2052 if (desc_info->long_rxdesc &&
2053 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP)
2054 skb_queue_tail(&ppdu_sts->rx_queue[band], skb);
2055 else
2056 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status);
2057 }
2058 EXPORT_SYMBOL(rtw89_core_rx);
2059
rtw89_core_napi_start(struct rtw89_dev * rtwdev)2060 void rtw89_core_napi_start(struct rtw89_dev *rtwdev)
2061 {
2062 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
2063 return;
2064
2065 napi_enable(&rtwdev->napi);
2066 }
2067 EXPORT_SYMBOL(rtw89_core_napi_start);
2068
rtw89_core_napi_stop(struct rtw89_dev * rtwdev)2069 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev)
2070 {
2071 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
2072 return;
2073
2074 napi_synchronize(&rtwdev->napi);
2075 napi_disable(&rtwdev->napi);
2076 }
2077 EXPORT_SYMBOL(rtw89_core_napi_stop);
2078
rtw89_core_napi_init(struct rtw89_dev * rtwdev)2079 void rtw89_core_napi_init(struct rtw89_dev *rtwdev)
2080 {
2081 init_dummy_netdev(&rtwdev->netdev);
2082 netif_napi_add(&rtwdev->netdev, &rtwdev->napi,
2083 rtwdev->hci.ops->napi_poll);
2084 }
2085 EXPORT_SYMBOL(rtw89_core_napi_init);
2086
rtw89_core_napi_deinit(struct rtw89_dev * rtwdev)2087 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev)
2088 {
2089 rtw89_core_napi_stop(rtwdev);
2090 netif_napi_del(&rtwdev->napi);
2091 }
2092 EXPORT_SYMBOL(rtw89_core_napi_deinit);
2093
rtw89_core_ba_work(struct work_struct * work)2094 static void rtw89_core_ba_work(struct work_struct *work)
2095 {
2096 struct rtw89_dev *rtwdev =
2097 container_of(work, struct rtw89_dev, ba_work);
2098 struct rtw89_txq *rtwtxq, *tmp;
2099 int ret;
2100
2101 spin_lock_bh(&rtwdev->ba_lock);
2102 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) {
2103 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2104 struct ieee80211_sta *sta = txq->sta;
2105 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL;
2106 u8 tid = txq->tid;
2107
2108 if (!sta) {
2109 rtw89_warn(rtwdev, "cannot start BA without sta\n");
2110 goto skip_ba_work;
2111 }
2112
2113 if (rtwsta->disassoc) {
2114 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2115 "cannot start BA with disassoc sta\n");
2116 goto skip_ba_work;
2117 }
2118
2119 ret = ieee80211_start_tx_ba_session(sta, tid, 0);
2120 if (ret) {
2121 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2122 "failed to setup BA session for %pM:%2d: %d\n",
2123 sta->addr, tid, ret);
2124 if (ret == -EINVAL)
2125 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags);
2126 }
2127 skip_ba_work:
2128 list_del_init(&rtwtxq->list);
2129 }
2130 spin_unlock_bh(&rtwdev->ba_lock);
2131 }
2132
rtw89_core_free_sta_pending_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)2133 static void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev,
2134 struct ieee80211_sta *sta)
2135 {
2136 struct rtw89_txq *rtwtxq, *tmp;
2137
2138 spin_lock_bh(&rtwdev->ba_lock);
2139 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) {
2140 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2141
2142 if (sta == txq->sta)
2143 list_del_init(&rtwtxq->list);
2144 }
2145 spin_unlock_bh(&rtwdev->ba_lock);
2146 }
2147
rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)2148 static void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev,
2149 struct ieee80211_sta *sta)
2150 {
2151 struct rtw89_txq *rtwtxq, *tmp;
2152
2153 spin_lock_bh(&rtwdev->ba_lock);
2154 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) {
2155 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2156
2157 if (sta == txq->sta) {
2158 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
2159 list_del_init(&rtwtxq->list);
2160 }
2161 }
2162 spin_unlock_bh(&rtwdev->ba_lock);
2163 }
2164
rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)2165 static void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev,
2166 struct ieee80211_sta *sta)
2167 {
2168 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
2169 struct sk_buff *skb, *tmp;
2170
2171 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) {
2172 skb_unlink(skb, &rtwsta->roc_queue);
2173 dev_kfree_skb_any(skb);
2174 }
2175 }
2176
rtw89_core_stop_tx_ba_session(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq)2177 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev,
2178 struct rtw89_txq *rtwtxq)
2179 {
2180 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2181 struct ieee80211_sta *sta = txq->sta;
2182 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
2183
2184 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc))
2185 return;
2186
2187 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) ||
2188 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
2189 return;
2190
2191 spin_lock_bh(&rtwdev->ba_lock);
2192 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
2193 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list);
2194 spin_unlock_bh(&rtwdev->ba_lock);
2195
2196 ieee80211_stop_tx_ba_session(sta, txq->tid);
2197 cancel_delayed_work(&rtwdev->forbid_ba_work);
2198 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work,
2199 RTW89_FORBID_BA_TIMER);
2200 }
2201
rtw89_core_txq_check_agg(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,struct sk_buff * skb)2202 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev,
2203 struct rtw89_txq *rtwtxq,
2204 struct sk_buff *skb)
2205 {
2206 struct ieee80211_hw *hw = rtwdev->hw;
2207 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2208 struct ieee80211_sta *sta = txq->sta;
2209 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL;
2210
2211 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
2212 return;
2213
2214 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
2215 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq);
2216 return;
2217 }
2218
2219 if (unlikely(!sta))
2220 return;
2221
2222 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags)))
2223 return;
2224
2225 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) {
2226 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU;
2227 return;
2228 }
2229
2230 spin_lock_bh(&rtwdev->ba_lock);
2231 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) {
2232 list_add_tail(&rtwtxq->list, &rtwdev->ba_list);
2233 ieee80211_queue_work(hw, &rtwdev->ba_work);
2234 }
2235 spin_unlock_bh(&rtwdev->ba_lock);
2236 }
2237
rtw89_core_txq_push(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,unsigned long frame_cnt,unsigned long byte_cnt)2238 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev,
2239 struct rtw89_txq *rtwtxq,
2240 unsigned long frame_cnt,
2241 unsigned long byte_cnt)
2242 {
2243 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
2244 struct ieee80211_vif *vif = txq->vif;
2245 struct ieee80211_sta *sta = txq->sta;
2246 struct sk_buff *skb;
2247 unsigned long i;
2248 int ret;
2249
2250 rcu_read_lock();
2251 for (i = 0; i < frame_cnt; i++) {
2252 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq);
2253 if (!skb) {
2254 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n");
2255 goto out;
2256 }
2257 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb);
2258 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL);
2259 if (ret) {
2260 rtw89_err(rtwdev, "failed to push txq: %d\n", ret);
2261 ieee80211_free_txskb(rtwdev->hw, skb);
2262 break;
2263 }
2264 }
2265 out:
2266 rcu_read_unlock();
2267 }
2268
rtw89_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 tid)2269 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid)
2270 {
2271 u8 qsel, ch_dma;
2272
2273 qsel = rtw89_core_get_qsel(rtwdev, tid);
2274 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel);
2275
2276 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma);
2277 }
2278
rtw89_core_txq_agg_wait(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq,unsigned long * frame_cnt,bool * sched_txq,bool * reinvoke)2279 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev,
2280 struct ieee80211_txq *txq,
2281 unsigned long *frame_cnt,
2282 bool *sched_txq, bool *reinvoke)
2283 {
2284 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv;
2285 struct ieee80211_sta *sta = txq->sta;
2286 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL;
2287
2288 if (!sta || rtwsta->max_agg_wait <= 0)
2289 return false;
2290
2291 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID)
2292 return false;
2293
2294 if (*frame_cnt > 1) {
2295 *frame_cnt -= 1;
2296 *sched_txq = true;
2297 *reinvoke = true;
2298 rtwtxq->wait_cnt = 1;
2299 return false;
2300 }
2301
2302 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta->max_agg_wait) {
2303 *reinvoke = true;
2304 rtwtxq->wait_cnt++;
2305 return true;
2306 }
2307
2308 rtwtxq->wait_cnt = 0;
2309 return false;
2310 }
2311
rtw89_core_txq_schedule(struct rtw89_dev * rtwdev,u8 ac,bool * reinvoke)2312 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke)
2313 {
2314 struct ieee80211_hw *hw = rtwdev->hw;
2315 struct ieee80211_txq *txq;
2316 struct rtw89_vif *rtwvif;
2317 struct rtw89_txq *rtwtxq;
2318 unsigned long frame_cnt;
2319 unsigned long byte_cnt;
2320 u32 tx_resource;
2321 bool sched_txq;
2322
2323 ieee80211_txq_schedule_start(hw, ac);
2324 while ((txq = ieee80211_next_txq(hw, ac))) {
2325 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
2326 rtwvif = (struct rtw89_vif *)txq->vif->drv_priv;
2327
2328 if (rtwvif->offchan) {
2329 ieee80211_return_txq(hw, txq, true);
2330 continue;
2331 }
2332 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid);
2333 sched_txq = false;
2334
2335 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt);
2336 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) {
2337 ieee80211_return_txq(hw, txq, true);
2338 continue;
2339 }
2340 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource);
2341 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt);
2342 ieee80211_return_txq(hw, txq, sched_txq);
2343 if (frame_cnt != 0)
2344 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid));
2345
2346 /* bound of tx_resource could get stuck due to burst traffic */
2347 if (frame_cnt == tx_resource)
2348 *reinvoke = true;
2349 }
2350 ieee80211_txq_schedule_end(hw, ac);
2351 }
2352
rtw89_ips_work(struct work_struct * work)2353 static void rtw89_ips_work(struct work_struct *work)
2354 {
2355 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
2356 ips_work);
2357 mutex_lock(&rtwdev->mutex);
2358 rtw89_enter_ips_by_hwflags(rtwdev);
2359 mutex_unlock(&rtwdev->mutex);
2360 }
2361
rtw89_core_txq_work(struct work_struct * w)2362 static void rtw89_core_txq_work(struct work_struct *w)
2363 {
2364 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work);
2365 bool reinvoke = false;
2366 u8 ac;
2367
2368 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2369 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke);
2370
2371 if (reinvoke) {
2372 /* reinvoke to process the last frame */
2373 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1);
2374 }
2375 }
2376
rtw89_core_txq_reinvoke_work(struct work_struct * w)2377 static void rtw89_core_txq_reinvoke_work(struct work_struct *w)
2378 {
2379 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev,
2380 txq_reinvoke_work.work);
2381
2382 queue_work(rtwdev->txq_wq, &rtwdev->txq_work);
2383 }
2384
rtw89_forbid_ba_work(struct work_struct * w)2385 static void rtw89_forbid_ba_work(struct work_struct *w)
2386 {
2387 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev,
2388 forbid_ba_work.work);
2389 struct rtw89_txq *rtwtxq, *tmp;
2390
2391 spin_lock_bh(&rtwdev->ba_lock);
2392 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) {
2393 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
2394 list_del_init(&rtwtxq->list);
2395 }
2396 spin_unlock_bh(&rtwdev->ba_lock);
2397 }
2398
rtw89_core_sta_pending_tx_iter(void * data,struct ieee80211_sta * sta)2399 static void rtw89_core_sta_pending_tx_iter(void *data,
2400 struct ieee80211_sta *sta)
2401 {
2402 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
2403 struct rtw89_vif *rtwvif_target = data, *rtwvif = rtwsta->rtwvif;
2404 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
2405 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
2406 struct sk_buff *skb, *tmp;
2407 int qsel, ret;
2408
2409 if (rtwvif->sub_entity_idx != rtwvif_target->sub_entity_idx)
2410 return;
2411
2412 if (skb_queue_len(&rtwsta->roc_queue) == 0)
2413 return;
2414
2415 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) {
2416 skb_unlink(skb, &rtwsta->roc_queue);
2417
2418 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel);
2419 if (ret) {
2420 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret);
2421 dev_kfree_skb_any(skb);
2422 } else {
2423 rtw89_core_tx_kick_off(rtwdev, qsel);
2424 }
2425 }
2426 }
2427
rtw89_core_handle_sta_pending_tx(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)2428 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev,
2429 struct rtw89_vif *rtwvif)
2430 {
2431 ieee80211_iterate_stations_atomic(rtwdev->hw,
2432 rtw89_core_sta_pending_tx_iter,
2433 rtwvif);
2434 }
2435
rtw89_core_send_nullfunc(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,bool qos,bool ps)2436 static int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev,
2437 struct rtw89_vif *rtwvif, bool qos, bool ps)
2438 {
2439 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
2440 struct ieee80211_sta *sta;
2441 struct ieee80211_hdr *hdr;
2442 struct sk_buff *skb;
2443 int ret, qsel;
2444
2445 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc)
2446 return 0;
2447
2448 rcu_read_lock();
2449 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid);
2450 if (!sta) {
2451 ret = -EINVAL;
2452 goto out;
2453 }
2454
2455 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, -1, qos);
2456 if (!skb) {
2457 ret = -ENOMEM;
2458 goto out;
2459 }
2460
2461 hdr = (struct ieee80211_hdr *)skb->data;
2462 if (ps)
2463 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2464
2465 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel);
2466 if (ret) {
2467 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret);
2468 dev_kfree_skb_any(skb);
2469 goto out;
2470 }
2471
2472 rcu_read_unlock();
2473
2474 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, qsel,
2475 RTW89_ROC_TX_TIMEOUT);
2476 out:
2477 rcu_read_unlock();
2478
2479 return ret;
2480 }
2481
rtw89_roc_start(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)2482 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
2483 {
2484 struct ieee80211_hw *hw = rtwdev->hw;
2485 struct rtw89_roc *roc = &rtwvif->roc;
2486 struct cfg80211_chan_def roc_chan;
2487 struct rtw89_vif *tmp;
2488 int ret;
2489
2490 lockdep_assert_held(&rtwdev->mutex);
2491
2492 ieee80211_queue_delayed_work(hw, &rtwvif->roc.roc_work,
2493 msecs_to_jiffies(rtwvif->roc.duration));
2494
2495 rtw89_leave_ips_by_hwflags(rtwdev);
2496 rtw89_leave_lps(rtwdev);
2497
2498 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, true);
2499 if (ret)
2500 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2501 "roc send null-1 failed: %d\n", ret);
2502
2503 rtw89_for_each_rtwvif(rtwdev, tmp)
2504 if (tmp->sub_entity_idx == rtwvif->sub_entity_idx)
2505 tmp->offchan = true;
2506
2507 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT);
2508 rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, &roc_chan);
2509 rtw89_set_channel(rtwdev);
2510 rtw89_write32_clr(rtwdev,
2511 rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, RTW89_MAC_0),
2512 B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH);
2513
2514 ieee80211_ready_on_channel(hw);
2515 }
2516
rtw89_roc_end(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)2517 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
2518 {
2519 struct ieee80211_hw *hw = rtwdev->hw;
2520 struct rtw89_roc *roc = &rtwvif->roc;
2521 struct rtw89_vif *tmp;
2522 int ret;
2523
2524 lockdep_assert_held(&rtwdev->mutex);
2525
2526 ieee80211_remain_on_channel_expired(hw);
2527
2528 rtw89_leave_ips_by_hwflags(rtwdev);
2529 rtw89_leave_lps(rtwdev);
2530
2531 rtw89_write32_mask(rtwdev,
2532 rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, RTW89_MAC_0),
2533 B_AX_RX_FLTR_CFG_MASK,
2534 rtwdev->hal.rx_fltr);
2535
2536 roc->state = RTW89_ROC_IDLE;
2537 rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, NULL);
2538 rtw89_set_channel(rtwdev);
2539 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, false);
2540 if (ret)
2541 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2542 "roc send null-0 failed: %d\n", ret);
2543
2544 rtw89_for_each_rtwvif(rtwdev, tmp)
2545 if (tmp->sub_entity_idx == rtwvif->sub_entity_idx)
2546 tmp->offchan = false;
2547
2548 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif);
2549 queue_work(rtwdev->txq_wq, &rtwdev->txq_work);
2550
2551 if (hw->conf.flags & IEEE80211_CONF_IDLE)
2552 ieee80211_queue_delayed_work(hw, &roc->roc_work,
2553 RTW89_ROC_IDLE_TIMEOUT);
2554 }
2555
rtw89_roc_work(struct work_struct * work)2556 void rtw89_roc_work(struct work_struct *work)
2557 {
2558 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif,
2559 roc.roc_work.work);
2560 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
2561 struct rtw89_roc *roc = &rtwvif->roc;
2562
2563 mutex_lock(&rtwdev->mutex);
2564
2565 switch (roc->state) {
2566 case RTW89_ROC_IDLE:
2567 rtw89_enter_ips_by_hwflags(rtwdev);
2568 break;
2569 case RTW89_ROC_MGMT:
2570 case RTW89_ROC_NORMAL:
2571 rtw89_roc_end(rtwdev, rtwvif);
2572 break;
2573 default:
2574 break;
2575 }
2576
2577 mutex_unlock(&rtwdev->mutex);
2578 }
2579
rtw89_get_traffic_level(struct rtw89_dev * rtwdev,u32 throughput,u64 cnt)2580 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev,
2581 u32 throughput, u64 cnt)
2582 {
2583 if (cnt < 100)
2584 return RTW89_TFC_IDLE;
2585 if (throughput > 50)
2586 return RTW89_TFC_HIGH;
2587 if (throughput > 10)
2588 return RTW89_TFC_MID;
2589 if (throughput > 2)
2590 return RTW89_TFC_LOW;
2591 return RTW89_TFC_ULTRA_LOW;
2592 }
2593
rtw89_traffic_stats_calc(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats)2594 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev,
2595 struct rtw89_traffic_stats *stats)
2596 {
2597 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv;
2598 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv;
2599
2600 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT);
2601 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT);
2602
2603 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw);
2604 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw);
2605
2606 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
2607 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
2608 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput,
2609 stats->tx_cnt);
2610 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput,
2611 stats->rx_cnt);
2612 stats->tx_avg_len = stats->tx_cnt ?
2613 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0;
2614 stats->rx_avg_len = stats->rx_cnt ?
2615 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0;
2616
2617 stats->tx_unicast = 0;
2618 stats->rx_unicast = 0;
2619 stats->tx_cnt = 0;
2620 stats->rx_cnt = 0;
2621 stats->rx_tf_periodic = stats->rx_tf_acc;
2622 stats->rx_tf_acc = 0;
2623
2624 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv)
2625 return true;
2626
2627 return false;
2628 }
2629
rtw89_traffic_stats_track(struct rtw89_dev * rtwdev)2630 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev)
2631 {
2632 struct rtw89_vif *rtwvif;
2633 bool tfc_changed;
2634
2635 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats);
2636 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
2637 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats);
2638 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif);
2639 }
2640
2641 return tfc_changed;
2642 }
2643
rtw89_vif_enter_lps(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)2644 static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
2645 {
2646 if ((rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION &&
2647 rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT) ||
2648 rtwvif->tdls_peer)
2649 return;
2650
2651 if (rtwvif->offchan)
2652 return;
2653
2654 if (rtwvif->stats.tx_tfc_lv == RTW89_TFC_IDLE &&
2655 rtwvif->stats.rx_tfc_lv == RTW89_TFC_IDLE)
2656 rtw89_enter_lps(rtwdev, rtwvif, true);
2657 }
2658
rtw89_enter_lps_track(struct rtw89_dev * rtwdev)2659 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev)
2660 {
2661 struct rtw89_vif *rtwvif;
2662
2663 rtw89_for_each_rtwvif(rtwdev, rtwvif)
2664 rtw89_vif_enter_lps(rtwdev, rtwvif);
2665 }
2666
rtw89_traffic_stats_init(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats)2667 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
2668 struct rtw89_traffic_stats *stats)
2669 {
2670 stats->tx_unicast = 0;
2671 stats->rx_unicast = 0;
2672 stats->tx_cnt = 0;
2673 stats->rx_cnt = 0;
2674 ewma_tp_init(&stats->tx_ewma_tp);
2675 ewma_tp_init(&stats->rx_ewma_tp);
2676 }
2677
rtw89_track_work(struct work_struct * work)2678 static void rtw89_track_work(struct work_struct *work)
2679 {
2680 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
2681 track_work.work);
2682 bool tfc_changed;
2683
2684 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags))
2685 return;
2686
2687 mutex_lock(&rtwdev->mutex);
2688
2689 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
2690 goto out;
2691
2692 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work,
2693 RTW89_TRACK_WORK_PERIOD);
2694
2695 tfc_changed = rtw89_traffic_stats_track(rtwdev);
2696 if (rtwdev->scanning)
2697 goto out;
2698
2699 rtw89_leave_lps(rtwdev);
2700
2701 if (tfc_changed) {
2702 rtw89_hci_recalc_int_mit(rtwdev);
2703 rtw89_btc_ntfy_wl_sta(rtwdev);
2704 }
2705 rtw89_mac_bf_monitor_track(rtwdev);
2706 rtw89_phy_stat_track(rtwdev);
2707 rtw89_phy_env_monitor_track(rtwdev);
2708 rtw89_phy_dig(rtwdev);
2709 rtw89_chip_rfk_track(rtwdev);
2710 rtw89_phy_ra_update(rtwdev);
2711 rtw89_phy_cfo_track(rtwdev);
2712 rtw89_phy_tx_path_div_track(rtwdev);
2713 rtw89_phy_antdiv_track(rtwdev);
2714 rtw89_phy_ul_tb_ctrl_track(rtwdev);
2715
2716 if (rtwdev->lps_enabled && !rtwdev->btc.lps)
2717 rtw89_enter_lps_track(rtwdev);
2718
2719 out:
2720 mutex_unlock(&rtwdev->mutex);
2721 }
2722
rtw89_core_acquire_bit_map(unsigned long * addr,unsigned long size)2723 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size)
2724 {
2725 unsigned long bit;
2726
2727 bit = find_first_zero_bit(addr, size);
2728 if (bit < size)
2729 set_bit(bit, addr);
2730
2731 return bit;
2732 }
2733
rtw89_core_release_bit_map(unsigned long * addr,u8 bit)2734 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit)
2735 {
2736 clear_bit(bit, addr);
2737 }
2738
rtw89_core_release_all_bits_map(unsigned long * addr,unsigned int nbits)2739 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits)
2740 {
2741 bitmap_zero(addr, nbits);
2742 }
2743
rtw89_core_acquire_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,u8 tid,u8 * cam_idx)2744 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
2745 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx)
2746 {
2747 const struct rtw89_chip_info *chip = rtwdev->chip;
2748 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
2749 struct rtw89_ba_cam_entry *entry = NULL, *tmp;
2750 u8 idx;
2751 int i;
2752
2753 lockdep_assert_held(&rtwdev->mutex);
2754
2755 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num);
2756 if (idx == chip->bacam_num) {
2757 /* allocate a static BA CAM to tid=0/5, so replace the existing
2758 * one if BA CAM is full. Hardware will process the original tid
2759 * automatically.
2760 */
2761 if (tid != 0 && tid != 5)
2762 return -ENOSPC;
2763
2764 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) {
2765 tmp = &cam_info->ba_cam_entry[i];
2766 if (tmp->tid == 0 || tmp->tid == 5)
2767 continue;
2768
2769 idx = i;
2770 entry = tmp;
2771 list_del(&entry->list);
2772 break;
2773 }
2774
2775 if (!entry)
2776 return -ENOSPC;
2777 } else {
2778 entry = &cam_info->ba_cam_entry[idx];
2779 }
2780
2781 entry->tid = tid;
2782 list_add_tail(&entry->list, &rtwsta->ba_cam_list);
2783
2784 *cam_idx = idx;
2785
2786 return 0;
2787 }
2788
rtw89_core_release_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,u8 tid,u8 * cam_idx)2789 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
2790 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx)
2791 {
2792 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
2793 struct rtw89_ba_cam_entry *entry = NULL, *tmp;
2794 u8 idx;
2795
2796 lockdep_assert_held(&rtwdev->mutex);
2797
2798 list_for_each_entry_safe(entry, tmp, &rtwsta->ba_cam_list, list) {
2799 if (entry->tid != tid)
2800 continue;
2801
2802 idx = entry - cam_info->ba_cam_entry;
2803 list_del(&entry->list);
2804
2805 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx);
2806 *cam_idx = idx;
2807 return 0;
2808 }
2809
2810 return -ENOENT;
2811 }
2812
2813 #define RTW89_TYPE_MAPPING(_type) \
2814 case NL80211_IFTYPE_ ## _type: \
2815 rtwvif->wifi_role = RTW89_WIFI_ROLE_ ## _type; \
2816 break
rtw89_vif_type_mapping(struct ieee80211_vif * vif,bool assoc)2817 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc)
2818 {
2819 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
2820
2821 switch (vif->type) {
2822 case NL80211_IFTYPE_STATION:
2823 if (vif->p2p)
2824 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT;
2825 else
2826 rtwvif->wifi_role = RTW89_WIFI_ROLE_STATION;
2827 break;
2828 case NL80211_IFTYPE_AP:
2829 if (vif->p2p)
2830 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_GO;
2831 else
2832 rtwvif->wifi_role = RTW89_WIFI_ROLE_AP;
2833 break;
2834 RTW89_TYPE_MAPPING(ADHOC);
2835 RTW89_TYPE_MAPPING(MONITOR);
2836 RTW89_TYPE_MAPPING(MESH_POINT);
2837 default:
2838 WARN_ON(1);
2839 break;
2840 }
2841
2842 switch (vif->type) {
2843 case NL80211_IFTYPE_AP:
2844 case NL80211_IFTYPE_MESH_POINT:
2845 rtwvif->net_type = RTW89_NET_TYPE_AP_MODE;
2846 rtwvif->self_role = RTW89_SELF_ROLE_AP;
2847 break;
2848 case NL80211_IFTYPE_ADHOC:
2849 rtwvif->net_type = RTW89_NET_TYPE_AD_HOC;
2850 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT;
2851 break;
2852 case NL80211_IFTYPE_STATION:
2853 if (assoc) {
2854 rtwvif->net_type = RTW89_NET_TYPE_INFRA;
2855 rtwvif->trigger = vif->bss_conf.he_support;
2856 } else {
2857 rtwvif->net_type = RTW89_NET_TYPE_NO_LINK;
2858 rtwvif->trigger = false;
2859 }
2860 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT;
2861 rtwvif->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL;
2862 break;
2863 case NL80211_IFTYPE_MONITOR:
2864 break;
2865 default:
2866 WARN_ON(1);
2867 break;
2868 }
2869 }
2870
rtw89_core_sta_add(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)2871 int rtw89_core_sta_add(struct rtw89_dev *rtwdev,
2872 struct ieee80211_vif *vif,
2873 struct ieee80211_sta *sta)
2874 {
2875 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
2876 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
2877 struct rtw89_hal *hal = &rtwdev->hal;
2878 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
2879 int i;
2880 int ret;
2881
2882 rtwsta->rtwdev = rtwdev;
2883 rtwsta->rtwvif = rtwvif;
2884 rtwsta->prev_rssi = 0;
2885 INIT_LIST_HEAD(&rtwsta->ba_cam_list);
2886 skb_queue_head_init(&rtwsta->roc_queue);
2887
2888 for (i = 0; i < ARRAY_SIZE(sta->txq); i++)
2889 rtw89_core_txq_init(rtwdev, sta->txq[i]);
2890
2891 ewma_rssi_init(&rtwsta->avg_rssi);
2892 ewma_snr_init(&rtwsta->avg_snr);
2893 for (i = 0; i < ant_num; i++) {
2894 ewma_rssi_init(&rtwsta->rssi[i]);
2895 ewma_evm_init(&rtwsta->evm_min[i]);
2896 ewma_evm_init(&rtwsta->evm_max[i]);
2897 }
2898
2899 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
2900 /* for station mode, assign the mac_id from itself */
2901 rtwsta->mac_id = rtwvif->mac_id;
2902 /* must do rtw89_reg_6ghz_power_recalc() before rfk channel */
2903 rtw89_reg_6ghz_power_recalc(rtwdev, rtwvif, true);
2904 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta,
2905 BTC_ROLE_MSTS_STA_CONN_START);
2906 rtw89_chip_rfk_channel(rtwdev);
2907 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
2908 rtwsta->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map,
2909 RTW89_MAX_MAC_ID_NUM);
2910 if (rtwsta->mac_id == RTW89_MAX_MAC_ID_NUM)
2911 return -ENOSPC;
2912
2913 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta->mac_id, false);
2914 if (ret) {
2915 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id);
2916 rtw89_warn(rtwdev, "failed to send h2c macid pause\n");
2917 return ret;
2918 }
2919
2920 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta,
2921 RTW89_ROLE_CREATE);
2922 if (ret) {
2923 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id);
2924 rtw89_warn(rtwdev, "failed to send h2c role info\n");
2925 return ret;
2926 }
2927 }
2928
2929 return 0;
2930 }
2931
rtw89_core_sta_disassoc(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)2932 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev,
2933 struct ieee80211_vif *vif,
2934 struct ieee80211_sta *sta)
2935 {
2936 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
2937 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
2938
2939 if (vif->type == NL80211_IFTYPE_STATION)
2940 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, false);
2941
2942 rtwdev->total_sta_assoc--;
2943 if (sta->tdls)
2944 rtwvif->tdls_peer--;
2945 rtwsta->disassoc = true;
2946
2947 return 0;
2948 }
2949
rtw89_core_sta_disconnect(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)2950 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev,
2951 struct ieee80211_vif *vif,
2952 struct ieee80211_sta *sta)
2953 {
2954 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
2955 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
2956 int ret;
2957
2958 rtw89_mac_bf_monitor_calc(rtwdev, sta, true);
2959 rtw89_mac_bf_disassoc(rtwdev, vif, sta);
2960 rtw89_core_free_sta_pending_ba(rtwdev, sta);
2961 rtw89_core_free_sta_pending_forbid_ba(rtwdev, sta);
2962 rtw89_core_free_sta_pending_roc_tx(rtwdev, sta);
2963
2964 if (vif->type == NL80211_IFTYPE_AP || sta->tdls)
2965 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta->addr_cam);
2966 if (sta->tdls)
2967 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta->bssid_cam);
2968
2969 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
2970 rtw89_vif_type_mapping(vif, false);
2971 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif, true);
2972 }
2973
2974 ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta);
2975 if (ret) {
2976 rtw89_warn(rtwdev, "failed to send h2c cmac table\n");
2977 return ret;
2978 }
2979
2980 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, true);
2981 if (ret) {
2982 rtw89_warn(rtwdev, "failed to send h2c join info\n");
2983 return ret;
2984 }
2985
2986 /* update cam aid mac_id net_type */
2987 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL);
2988 if (ret) {
2989 rtw89_warn(rtwdev, "failed to send h2c cam\n");
2990 return ret;
2991 }
2992
2993 return ret;
2994 }
2995
rtw89_core_sta_assoc(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)2996 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev,
2997 struct ieee80211_vif *vif,
2998 struct ieee80211_sta *sta)
2999 {
3000 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
3001 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
3002 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif, rtwsta);
3003 int ret;
3004
3005 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
3006 if (sta->tdls) {
3007 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif, bssid_cam, sta->addr);
3008 if (ret) {
3009 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n");
3010 return ret;
3011 }
3012 }
3013
3014 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta->addr_cam, bssid_cam);
3015 if (ret) {
3016 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n");
3017 return ret;
3018 }
3019 }
3020
3021 ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta);
3022 if (ret) {
3023 rtw89_warn(rtwdev, "failed to send h2c cmac table\n");
3024 return ret;
3025 }
3026
3027 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, false);
3028 if (ret) {
3029 rtw89_warn(rtwdev, "failed to send h2c join info\n");
3030 return ret;
3031 }
3032
3033 /* update cam aid mac_id net_type */
3034 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL);
3035 if (ret) {
3036 rtw89_warn(rtwdev, "failed to send h2c cam\n");
3037 return ret;
3038 }
3039
3040 rtwdev->total_sta_assoc++;
3041 if (sta->tdls)
3042 rtwvif->tdls_peer++;
3043 rtw89_phy_ra_assoc(rtwdev, sta);
3044 rtw89_mac_bf_assoc(rtwdev, vif, sta);
3045 rtw89_mac_bf_monitor_calc(rtwdev, sta, false);
3046
3047 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
3048 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
3049
3050 if (bss_conf->he_support &&
3051 !(bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE))
3052 rtwsta->er_cap = true;
3053
3054 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta,
3055 BTC_ROLE_MSTS_STA_CONN_END);
3056 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template);
3057 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif);
3058
3059 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif, rtwsta->mac_id);
3060 if (ret) {
3061 rtw89_warn(rtwdev, "failed to send h2c general packet\n");
3062 return ret;
3063 }
3064 }
3065
3066 return ret;
3067 }
3068
rtw89_core_sta_remove(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)3069 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev,
3070 struct ieee80211_vif *vif,
3071 struct ieee80211_sta *sta)
3072 {
3073 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
3074 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
3075 int ret;
3076
3077 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
3078 rtw89_reg_6ghz_power_recalc(rtwdev, rtwvif, false);
3079 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta,
3080 BTC_ROLE_MSTS_STA_DIS_CONN);
3081 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
3082 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id);
3083
3084 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta,
3085 RTW89_ROLE_REMOVE);
3086 if (ret) {
3087 rtw89_warn(rtwdev, "failed to send h2c role info\n");
3088 return ret;
3089 }
3090 }
3091
3092 return 0;
3093 }
3094
_rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_cfg * tid_conf)3095 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
3096 struct ieee80211_sta *sta,
3097 struct cfg80211_tid_cfg *tid_conf)
3098 {
3099 struct ieee80211_txq *txq;
3100 struct rtw89_txq *rtwtxq;
3101 u32 mask = tid_conf->mask;
3102 u8 tids = tid_conf->tids;
3103 int tids_nbit = BITS_PER_BYTE;
3104 int i;
3105
3106 for (i = 0; i < tids_nbit; i++, tids >>= 1) {
3107 if (!tids)
3108 break;
3109
3110 if (!(tids & BIT(0)))
3111 continue;
3112
3113 txq = sta->txq[i];
3114 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
3115
3116 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) {
3117 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) {
3118 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
3119 } else {
3120 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags))
3121 ieee80211_stop_tx_ba_session(sta, txq->tid);
3122 spin_lock_bh(&rtwdev->ba_lock);
3123 list_del_init(&rtwtxq->list);
3124 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
3125 spin_unlock_bh(&rtwdev->ba_lock);
3126 }
3127 }
3128
3129 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) {
3130 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE)
3131 sta->max_amsdu_subframes = 0;
3132 else
3133 sta->max_amsdu_subframes = 1;
3134 }
3135 }
3136 }
3137
rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_config * tid_config)3138 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
3139 struct ieee80211_sta *sta,
3140 struct cfg80211_tid_config *tid_config)
3141 {
3142 int i;
3143
3144 for (i = 0; i < tid_config->n_tid_conf; i++)
3145 _rtw89_core_set_tid_config(rtwdev, sta,
3146 &tid_config->tid_conf[i]);
3147 }
3148
rtw89_init_ht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_ht_cap * ht_cap)3149 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev,
3150 struct ieee80211_sta_ht_cap *ht_cap)
3151 {
3152 static const __le16 highest[RF_PATH_MAX] = {
3153 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600),
3154 };
3155 struct rtw89_hal *hal = &rtwdev->hal;
3156 u8 nss = hal->rx_nss;
3157 int i;
3158
3159 ht_cap->ht_supported = true;
3160 ht_cap->cap = 0;
3161 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
3162 IEEE80211_HT_CAP_MAX_AMSDU |
3163 IEEE80211_HT_CAP_TX_STBC |
3164 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
3165 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
3166 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
3167 IEEE80211_HT_CAP_DSSSCCK40 |
3168 IEEE80211_HT_CAP_SGI_40;
3169 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
3170 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
3171 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
3172 for (i = 0; i < nss; i++)
3173 ht_cap->mcs.rx_mask[i] = 0xFF;
3174 ht_cap->mcs.rx_mask[4] = 0x01;
3175 ht_cap->mcs.rx_highest = highest[nss - 1];
3176 }
3177
rtw89_init_vht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_vht_cap * vht_cap)3178 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev,
3179 struct ieee80211_sta_vht_cap *vht_cap)
3180 {
3181 static const __le16 highest_bw80[RF_PATH_MAX] = {
3182 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733),
3183 };
3184 static const __le16 highest_bw160[RF_PATH_MAX] = {
3185 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467),
3186 };
3187 const struct rtw89_chip_info *chip = rtwdev->chip;
3188 const __le16 *highest = chip->support_bw160 ? highest_bw160 : highest_bw80;
3189 struct rtw89_hal *hal = &rtwdev->hal;
3190 u16 tx_mcs_map = 0, rx_mcs_map = 0;
3191 u8 sts_cap = 3;
3192 int i;
3193
3194 for (i = 0; i < 8; i++) {
3195 if (i < hal->tx_nss)
3196 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
3197 else
3198 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
3199 if (i < hal->rx_nss)
3200 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
3201 else
3202 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
3203 }
3204
3205 vht_cap->vht_supported = true;
3206 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
3207 IEEE80211_VHT_CAP_SHORT_GI_80 |
3208 IEEE80211_VHT_CAP_RXSTBC_1 |
3209 IEEE80211_VHT_CAP_HTC_VHT |
3210 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
3211 0;
3212 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
3213 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
3214 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
3215 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
3216 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT;
3217 if (chip->support_bw160)
3218 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
3219 IEEE80211_VHT_CAP_SHORT_GI_160;
3220 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map);
3221 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map);
3222 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1];
3223 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1];
3224 }
3225
3226 #define RTW89_SBAND_IFTYPES_NR 2
3227
rtw89_init_he_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,struct ieee80211_supported_band * sband)3228 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev,
3229 enum nl80211_band band,
3230 struct ieee80211_supported_band *sband)
3231 {
3232 const struct rtw89_chip_info *chip = rtwdev->chip;
3233 struct rtw89_hal *hal = &rtwdev->hal;
3234 struct ieee80211_sband_iftype_data *iftype_data;
3235 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) ||
3236 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV);
3237 u16 mcs_map = 0;
3238 int i;
3239 int nss = hal->rx_nss;
3240 int idx = 0;
3241
3242 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL);
3243 if (!iftype_data)
3244 return;
3245
3246 for (i = 0; i < 8; i++) {
3247 if (i < nss)
3248 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2);
3249 else
3250 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2);
3251 }
3252
3253 for (i = 0; i < NUM_NL80211_IFTYPES; i++) {
3254 struct ieee80211_sta_he_cap *he_cap;
3255 u8 *mac_cap_info;
3256 u8 *phy_cap_info;
3257
3258 switch (i) {
3259 case NL80211_IFTYPE_STATION:
3260 case NL80211_IFTYPE_AP:
3261 break;
3262 default:
3263 continue;
3264 }
3265
3266 if (idx >= RTW89_SBAND_IFTYPES_NR) {
3267 rtw89_warn(rtwdev, "run out of iftype_data\n");
3268 break;
3269 }
3270
3271 iftype_data[idx].types_mask = BIT(i);
3272 he_cap = &iftype_data[idx].he_cap;
3273 mac_cap_info = he_cap->he_cap_elem.mac_cap_info;
3274 phy_cap_info = he_cap->he_cap_elem.phy_cap_info;
3275
3276 he_cap->has_he = true;
3277 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE;
3278 if (i == NL80211_IFTYPE_STATION)
3279 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US;
3280 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK |
3281 IEEE80211_HE_MAC_CAP2_BSR;
3282 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2;
3283 if (i == NL80211_IFTYPE_AP)
3284 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL;
3285 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS |
3286 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU;
3287 if (i == NL80211_IFTYPE_STATION)
3288 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX;
3289 if (band == NL80211_BAND_2GHZ) {
3290 phy_cap_info[0] =
3291 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
3292 } else {
3293 phy_cap_info[0] =
3294 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G;
3295 if (chip->support_bw160)
3296 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
3297 }
3298 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
3299 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD |
3300 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US;
3301 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
3302 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
3303 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ |
3304 IEEE80211_HE_PHY_CAP2_DOPPLER_TX;
3305 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM;
3306 if (i == NL80211_IFTYPE_STATION)
3307 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM |
3308 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2;
3309 if (i == NL80211_IFTYPE_AP)
3310 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU;
3311 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
3312 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4;
3313 if (chip->support_bw160)
3314 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4;
3315 phy_cap_info[5] = no_ng16 ? 0 :
3316 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK |
3317 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK;
3318 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
3319 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU |
3320 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
3321 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE;
3322 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
3323 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
3324 IEEE80211_HE_PHY_CAP7_MAX_NC_1;
3325 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
3326 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI |
3327 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996;
3328 if (chip->support_bw160)
3329 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
3330 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU;
3331 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM |
3332 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU |
3333 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
3334 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
3335 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US,
3336 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK);
3337 if (i == NL80211_IFTYPE_STATION)
3338 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU;
3339 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map);
3340 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map);
3341 if (chip->support_bw160) {
3342 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map);
3343 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map);
3344 }
3345
3346 if (band == NL80211_BAND_6GHZ) {
3347 __le16 capa;
3348
3349 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE,
3350 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
3351 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
3352 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
3353 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
3354 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
3355 iftype_data[idx].he_6ghz_capa.capa = capa;
3356 }
3357
3358 idx++;
3359 }
3360
3361 sband->iftype_data = iftype_data;
3362 sband->n_iftype_data = idx;
3363 }
3364
rtw89_core_set_supported_band(struct rtw89_dev * rtwdev)3365 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev)
3366 {
3367 struct ieee80211_hw *hw = rtwdev->hw;
3368 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL;
3369 struct ieee80211_supported_band *sband_6ghz = NULL;
3370 u32 size = sizeof(struct ieee80211_supported_band);
3371 u8 support_bands = rtwdev->chip->support_bands;
3372
3373 if (support_bands & BIT(NL80211_BAND_2GHZ)) {
3374 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL);
3375 if (!sband_2ghz)
3376 goto err;
3377 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap);
3378 rtw89_init_he_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz);
3379 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz;
3380 }
3381
3382 if (support_bands & BIT(NL80211_BAND_5GHZ)) {
3383 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL);
3384 if (!sband_5ghz)
3385 goto err;
3386 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap);
3387 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap);
3388 rtw89_init_he_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz);
3389 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz;
3390 }
3391
3392 if (support_bands & BIT(NL80211_BAND_6GHZ)) {
3393 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL);
3394 if (!sband_6ghz)
3395 goto err;
3396 rtw89_init_he_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz);
3397 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz;
3398 }
3399
3400 return 0;
3401
3402 err:
3403 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL;
3404 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL;
3405 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL;
3406 if (sband_2ghz)
3407 kfree(sband_2ghz->iftype_data);
3408 if (sband_5ghz)
3409 kfree(sband_5ghz->iftype_data);
3410 if (sband_6ghz)
3411 kfree(sband_6ghz->iftype_data);
3412 kfree(sband_2ghz);
3413 kfree(sband_5ghz);
3414 kfree(sband_6ghz);
3415 return -ENOMEM;
3416 }
3417
rtw89_core_clr_supported_band(struct rtw89_dev * rtwdev)3418 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev)
3419 {
3420 struct ieee80211_hw *hw = rtwdev->hw;
3421
3422 if (hw->wiphy->bands[NL80211_BAND_2GHZ])
3423 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data);
3424 if (hw->wiphy->bands[NL80211_BAND_5GHZ])
3425 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data);
3426 if (hw->wiphy->bands[NL80211_BAND_6GHZ])
3427 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data);
3428 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]);
3429 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]);
3430 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]);
3431 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL;
3432 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL;
3433 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL;
3434 }
3435
rtw89_core_ppdu_sts_init(struct rtw89_dev * rtwdev)3436 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev)
3437 {
3438 int i;
3439
3440 for (i = 0; i < RTW89_PHY_MAX; i++)
3441 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]);
3442 for (i = 0; i < RTW89_PHY_MAX; i++)
3443 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX;
3444 }
3445
rtw89_core_update_beacon_work(struct work_struct * work)3446 void rtw89_core_update_beacon_work(struct work_struct *work)
3447 {
3448 struct rtw89_dev *rtwdev;
3449 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif,
3450 update_beacon_work);
3451
3452 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE)
3453 return;
3454
3455 rtwdev = rtwvif->rtwdev;
3456 mutex_lock(&rtwdev->mutex);
3457 rtw89_fw_h2c_update_beacon(rtwdev, rtwvif);
3458 mutex_unlock(&rtwdev->mutex);
3459 }
3460
rtw89_wait_for_cond(struct rtw89_wait_info * wait,unsigned int cond)3461 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond)
3462 {
3463 struct completion *cmpl = &wait->completion;
3464 unsigned long timeout;
3465 unsigned int cur;
3466
3467 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond);
3468 if (cur != RTW89_WAIT_COND_IDLE)
3469 return -EBUSY;
3470
3471 timeout = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT);
3472 if (timeout == 0) {
3473 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
3474 return -ETIMEDOUT;
3475 }
3476
3477 if (wait->data.err)
3478 return -EFAULT;
3479
3480 return 0;
3481 }
3482
rtw89_complete_cond(struct rtw89_wait_info * wait,unsigned int cond,const struct rtw89_completion_data * data)3483 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
3484 const struct rtw89_completion_data *data)
3485 {
3486 unsigned int cur;
3487
3488 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE);
3489 if (cur != cond)
3490 return;
3491
3492 wait->data = *data;
3493 complete(&wait->completion);
3494 }
3495
rtw89_core_start(struct rtw89_dev * rtwdev)3496 int rtw89_core_start(struct rtw89_dev *rtwdev)
3497 {
3498 int ret;
3499
3500 rtwdev->mac.qta_mode = RTW89_QTA_SCC;
3501 ret = rtw89_mac_init(rtwdev);
3502 if (ret) {
3503 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret);
3504 return ret;
3505 }
3506
3507 rtw89_btc_ntfy_poweron(rtwdev);
3508
3509 /* efuse process */
3510
3511 /* pre-config BB/RF, BB reset/RFC reset */
3512 ret = rtw89_chip_disable_bb_rf(rtwdev);
3513 if (ret)
3514 return ret;
3515 ret = rtw89_chip_enable_bb_rf(rtwdev);
3516 if (ret)
3517 return ret;
3518
3519 rtw89_phy_init_bb_reg(rtwdev);
3520 rtw89_phy_init_rf_reg(rtwdev, false);
3521
3522 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL);
3523
3524 rtw89_phy_dm_init(rtwdev);
3525
3526 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
3527 rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0);
3528
3529 ret = rtw89_hci_start(rtwdev);
3530 if (ret) {
3531 rtw89_err(rtwdev, "failed to start hci\n");
3532 return ret;
3533 }
3534
3535 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work,
3536 RTW89_TRACK_WORK_PERIOD);
3537
3538 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
3539
3540 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON);
3541 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable);
3542 rtw89_fw_h2c_init_ba_cam(rtwdev);
3543
3544 return 0;
3545 }
3546
rtw89_core_stop(struct rtw89_dev * rtwdev)3547 void rtw89_core_stop(struct rtw89_dev *rtwdev)
3548 {
3549 struct rtw89_btc *btc = &rtwdev->btc;
3550
3551 /* Prvent to stop twice; enter_ips and ops_stop */
3552 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
3553 return;
3554
3555 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF);
3556
3557 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
3558
3559 mutex_unlock(&rtwdev->mutex);
3560
3561 cancel_work_sync(&rtwdev->c2h_work);
3562 cancel_work_sync(&rtwdev->cancel_6ghz_probe_work);
3563 cancel_work_sync(&btc->eapol_notify_work);
3564 cancel_work_sync(&btc->arp_notify_work);
3565 cancel_work_sync(&btc->dhcp_notify_work);
3566 cancel_work_sync(&btc->icmp_notify_work);
3567 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work);
3568 cancel_delayed_work_sync(&rtwdev->track_work);
3569 cancel_delayed_work_sync(&rtwdev->coex_act1_work);
3570 cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work);
3571 cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work);
3572 cancel_delayed_work_sync(&rtwdev->cfo_track_work);
3573 cancel_delayed_work_sync(&rtwdev->forbid_ba_work);
3574 cancel_delayed_work_sync(&rtwdev->antdiv_work);
3575
3576 mutex_lock(&rtwdev->mutex);
3577
3578 rtw89_btc_ntfy_poweroff(rtwdev);
3579 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true);
3580 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true);
3581 rtw89_hci_stop(rtwdev);
3582 rtw89_hci_deinit(rtwdev);
3583 rtw89_mac_pwr_off(rtwdev);
3584 rtw89_hci_reset(rtwdev);
3585 }
3586
rtw89_core_init(struct rtw89_dev * rtwdev)3587 int rtw89_core_init(struct rtw89_dev *rtwdev)
3588 {
3589 struct rtw89_btc *btc = &rtwdev->btc;
3590 u8 band;
3591
3592 INIT_LIST_HEAD(&rtwdev->ba_list);
3593 INIT_LIST_HEAD(&rtwdev->forbid_ba_list);
3594 INIT_LIST_HEAD(&rtwdev->rtwvifs_list);
3595 INIT_LIST_HEAD(&rtwdev->early_h2c_list);
3596 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) {
3597 if (!(rtwdev->chip->support_bands & BIT(band)))
3598 continue;
3599 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]);
3600 }
3601 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work);
3602 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work);
3603 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work);
3604 INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work);
3605 INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work);
3606 INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work);
3607 INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work);
3608 INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work);
3609 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work);
3610 INIT_DELAYED_WORK(&rtwdev->antdiv_work, rtw89_phy_antdiv_work);
3611 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);
3612 if (!rtwdev->txq_wq)
3613 return -ENOMEM;
3614 spin_lock_init(&rtwdev->ba_lock);
3615 spin_lock_init(&rtwdev->rpwm_lock);
3616 mutex_init(&rtwdev->mutex);
3617 mutex_init(&rtwdev->rf_mutex);
3618 rtwdev->total_sta_assoc = 0;
3619
3620 rtw89_init_wait(&rtwdev->mcc.wait);
3621 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait);
3622
3623 INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work);
3624 INIT_WORK(&rtwdev->ips_work, rtw89_ips_work);
3625 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work);
3626 INIT_WORK(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work);
3627
3628 skb_queue_head_init(&rtwdev->c2h_queue);
3629 rtw89_core_ppdu_sts_init(rtwdev);
3630 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats);
3631
3632 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR;
3633
3634 INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work);
3635 INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work);
3636 INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work);
3637 INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work);
3638
3639 init_completion(&rtwdev->fw.req.completion);
3640
3641 schedule_work(&rtwdev->load_firmware_work);
3642
3643 rtw89_ser_init(rtwdev);
3644 rtw89_entity_init(rtwdev);
3645
3646 return 0;
3647 }
3648 EXPORT_SYMBOL(rtw89_core_init);
3649
rtw89_core_deinit(struct rtw89_dev * rtwdev)3650 void rtw89_core_deinit(struct rtw89_dev *rtwdev)
3651 {
3652 rtw89_ser_deinit(rtwdev);
3653 rtw89_unload_firmware(rtwdev);
3654 rtw89_fw_free_all_early_h2c(rtwdev);
3655
3656 destroy_workqueue(rtwdev->txq_wq);
3657 mutex_destroy(&rtwdev->rf_mutex);
3658 mutex_destroy(&rtwdev->mutex);
3659 }
3660 EXPORT_SYMBOL(rtw89_core_deinit);
3661
rtw89_core_scan_start(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,const u8 * mac_addr,bool hw_scan)3662 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
3663 const u8 *mac_addr, bool hw_scan)
3664 {
3665 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
3666
3667 rtwdev->scanning = true;
3668 rtw89_leave_lps(rtwdev);
3669 if (hw_scan)
3670 rtw89_leave_ips_by_hwflags(rtwdev);
3671
3672 ether_addr_copy(rtwvif->mac_addr, mac_addr);
3673 rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, chan->band_type);
3674 rtw89_chip_rfk_scan(rtwdev, true);
3675 rtw89_hci_recalc_int_mit(rtwdev);
3676 rtw89_phy_config_edcca(rtwdev, true);
3677
3678 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, mac_addr);
3679 }
3680
rtw89_core_scan_complete(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,bool hw_scan)3681 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
3682 struct ieee80211_vif *vif, bool hw_scan)
3683 {
3684 struct rtw89_vif *rtwvif = vif ? (struct rtw89_vif *)vif->drv_priv : NULL;
3685
3686 if (!rtwvif)
3687 return;
3688
3689 ether_addr_copy(rtwvif->mac_addr, vif->addr);
3690 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL);
3691
3692 rtw89_chip_rfk_scan(rtwdev, false);
3693 rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0);
3694 rtw89_phy_config_edcca(rtwdev, false);
3695
3696 rtwdev->scanning = false;
3697 rtwdev->dig.bypass_dig = true;
3698 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE))
3699 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work);
3700 }
3701
rtw89_read_chip_ver(struct rtw89_dev * rtwdev)3702 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev)
3703 {
3704 const struct rtw89_chip_info *chip = rtwdev->chip;
3705 int ret;
3706 u8 val;
3707 u8 cv;
3708
3709 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK);
3710 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) {
3711 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD)
3712 cv = CHIP_CAV;
3713 else
3714 cv = CHIP_CBV;
3715 }
3716
3717 rtwdev->hal.cv = cv;
3718
3719 if (chip->chip_id == RTL8852B || chip->chip_id == RTL8851B) {
3720 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val);
3721 if (ret)
3722 return;
3723
3724 rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK);
3725 }
3726 }
3727
rtw89_core_setup_phycap(struct rtw89_dev * rtwdev)3728 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev)
3729 {
3730 rtwdev->hal.support_cckpd =
3731 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) &&
3732 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV);
3733 rtwdev->hal.support_igi =
3734 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV;
3735 }
3736
rtw89_core_setup_rfe_parms(struct rtw89_dev * rtwdev)3737 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev)
3738 {
3739 const struct rtw89_chip_info *chip = rtwdev->chip;
3740 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf;
3741 struct rtw89_efuse *efuse = &rtwdev->efuse;
3742 u8 rfe_type = efuse->rfe_type;
3743
3744 if (!conf)
3745 goto out;
3746
3747 while (conf->rfe_parms) {
3748 if (rfe_type == conf->rfe_type) {
3749 rtwdev->rfe_parms = conf->rfe_parms;
3750 return;
3751 }
3752 conf++;
3753 }
3754
3755 out:
3756 rtwdev->rfe_parms = chip->dflt_parms;
3757 }
3758
rtw89_chip_efuse_info_setup(struct rtw89_dev * rtwdev)3759 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev)
3760 {
3761 int ret;
3762
3763 ret = rtw89_mac_partial_init(rtwdev);
3764 if (ret)
3765 return ret;
3766
3767 ret = rtw89_parse_efuse_map(rtwdev);
3768 if (ret)
3769 return ret;
3770
3771 ret = rtw89_parse_phycap_map(rtwdev);
3772 if (ret)
3773 return ret;
3774
3775 ret = rtw89_mac_setup_phycap(rtwdev);
3776 if (ret)
3777 return ret;
3778
3779 rtw89_core_setup_phycap(rtwdev);
3780 rtw89_core_setup_rfe_parms(rtwdev);
3781
3782 rtw89_mac_pwr_off(rtwdev);
3783
3784 return 0;
3785 }
3786
rtw89_chip_board_info_setup(struct rtw89_dev * rtwdev)3787 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev)
3788 {
3789 rtw89_chip_fem_setup(rtwdev);
3790
3791 return 0;
3792 }
3793
rtw89_chip_info_setup(struct rtw89_dev * rtwdev)3794 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev)
3795 {
3796 int ret;
3797
3798 rtw89_read_chip_ver(rtwdev);
3799
3800 ret = rtw89_wait_firmware_completion(rtwdev);
3801 if (ret) {
3802 rtw89_err(rtwdev, "failed to wait firmware completion\n");
3803 return ret;
3804 }
3805
3806 ret = rtw89_fw_recognize(rtwdev);
3807 if (ret) {
3808 rtw89_err(rtwdev, "failed to recognize firmware\n");
3809 return ret;
3810 }
3811
3812 ret = rtw89_fw_recognize_elements(rtwdev);
3813 if (ret) {
3814 rtw89_err(rtwdev, "failed to recognize firmware elements\n");
3815 return ret;
3816 }
3817
3818 ret = rtw89_chip_efuse_info_setup(rtwdev);
3819 if (ret)
3820 return ret;
3821
3822 ret = rtw89_chip_board_info_setup(rtwdev);
3823 if (ret)
3824 return ret;
3825
3826 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev);
3827
3828 return 0;
3829 }
3830 EXPORT_SYMBOL(rtw89_chip_info_setup);
3831
rtw89_core_register_hw(struct rtw89_dev * rtwdev)3832 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev)
3833 {
3834 struct ieee80211_hw *hw = rtwdev->hw;
3835 struct rtw89_efuse *efuse = &rtwdev->efuse;
3836 struct rtw89_hal *hal = &rtwdev->hal;
3837 int ret;
3838 int tx_headroom = IEEE80211_HT_CTL_LEN;
3839
3840 hw->vif_data_size = sizeof(struct rtw89_vif);
3841 hw->sta_data_size = sizeof(struct rtw89_sta);
3842 hw->txq_data_size = sizeof(struct rtw89_txq);
3843 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg);
3844
3845 SET_IEEE80211_PERM_ADDR(hw, efuse->addr);
3846
3847 hw->extra_tx_headroom = tx_headroom;
3848 hw->queues = IEEE80211_NUM_ACS;
3849 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM;
3850 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM;
3851 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL;
3852
3853 ieee80211_hw_set(hw, SIGNAL_DBM);
3854 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
3855 ieee80211_hw_set(hw, MFP_CAPABLE);
3856 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
3857 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
3858 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
3859 ieee80211_hw_set(hw, TX_AMSDU);
3860 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
3861 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
3862 ieee80211_hw_set(hw, SUPPORTS_PS);
3863 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
3864 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
3865 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
3866 ieee80211_hw_set(hw, WANT_MONITOR_VIF);
3867 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw))
3868 ieee80211_hw_set(hw, CONNECTION_MONITOR);
3869
3870 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
3871 BIT(NL80211_IFTYPE_AP) |
3872 BIT(NL80211_IFTYPE_P2P_CLIENT) |
3873 BIT(NL80211_IFTYPE_P2P_GO);
3874
3875 if (hal->ant_diversity) {
3876 hw->wiphy->available_antennas_tx = 0x3;
3877 hw->wiphy->available_antennas_rx = 0x3;
3878 } else {
3879 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1;
3880 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1;
3881 }
3882
3883 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
3884 WIPHY_FLAG_TDLS_EXTERNAL_SETUP |
3885 WIPHY_FLAG_AP_UAPSD | WIPHY_FLAG_SPLIT_SCAN_6GHZ;
3886 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
3887
3888 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID;
3889 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN;
3890
3891 #ifdef CONFIG_PM
3892 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
3893 #endif
3894
3895 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
3896 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
3897 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
3898 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
3899 hw->wiphy->max_remain_on_channel_duration = 1000;
3900
3901 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
3902
3903 ret = rtw89_core_set_supported_band(rtwdev);
3904 if (ret) {
3905 rtw89_err(rtwdev, "failed to set supported band\n");
3906 return ret;
3907 }
3908
3909 ret = rtw89_regd_setup(rtwdev);
3910 if (ret) {
3911 rtw89_err(rtwdev, "failed to set up regd\n");
3912 goto err_free_supported_band;
3913 }
3914
3915 hw->wiphy->sar_capa = &rtw89_sar_capa;
3916
3917 ret = ieee80211_register_hw(hw);
3918 if (ret) {
3919 rtw89_err(rtwdev, "failed to register hw\n");
3920 goto err_free_supported_band;
3921 }
3922
3923 ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier);
3924 if (ret) {
3925 rtw89_err(rtwdev, "failed to init regd\n");
3926 goto err_unregister_hw;
3927 }
3928
3929 return 0;
3930
3931 err_unregister_hw:
3932 ieee80211_unregister_hw(hw);
3933 err_free_supported_band:
3934 rtw89_core_clr_supported_band(rtwdev);
3935
3936 return ret;
3937 }
3938
rtw89_core_unregister_hw(struct rtw89_dev * rtwdev)3939 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev)
3940 {
3941 struct ieee80211_hw *hw = rtwdev->hw;
3942
3943 ieee80211_unregister_hw(hw);
3944 rtw89_core_clr_supported_band(rtwdev);
3945 }
3946
rtw89_core_register(struct rtw89_dev * rtwdev)3947 int rtw89_core_register(struct rtw89_dev *rtwdev)
3948 {
3949 int ret;
3950
3951 ret = rtw89_core_register_hw(rtwdev);
3952 if (ret) {
3953 rtw89_err(rtwdev, "failed to register core hw\n");
3954 return ret;
3955 }
3956
3957 rtw89_debugfs_init(rtwdev);
3958
3959 return 0;
3960 }
3961 EXPORT_SYMBOL(rtw89_core_register);
3962
rtw89_core_unregister(struct rtw89_dev * rtwdev)3963 void rtw89_core_unregister(struct rtw89_dev *rtwdev)
3964 {
3965 rtw89_core_unregister_hw(rtwdev);
3966 }
3967 EXPORT_SYMBOL(rtw89_core_unregister);
3968
rtw89_alloc_ieee80211_hw(struct device * device,u32 bus_data_size,const struct rtw89_chip_info * chip)3969 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
3970 u32 bus_data_size,
3971 const struct rtw89_chip_info *chip)
3972 {
3973 struct rtw89_fw_info early_fw = {};
3974 const struct firmware *firmware;
3975 struct ieee80211_hw *hw;
3976 struct rtw89_dev *rtwdev;
3977 struct ieee80211_ops *ops;
3978 u32 driver_data_size;
3979 int fw_format = -1;
3980 bool no_chanctx;
3981
3982 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format);
3983
3984 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL);
3985 if (!ops)
3986 goto err;
3987
3988 no_chanctx = chip->support_chanctx_num == 0 ||
3989 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) ||
3990 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw);
3991
3992 if (no_chanctx) {
3993 ops->add_chanctx = NULL;
3994 ops->remove_chanctx = NULL;
3995 ops->change_chanctx = NULL;
3996 ops->assign_vif_chanctx = NULL;
3997 ops->unassign_vif_chanctx = NULL;
3998 ops->remain_on_channel = NULL;
3999 ops->cancel_remain_on_channel = NULL;
4000 }
4001
4002 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size;
4003 hw = ieee80211_alloc_hw(driver_data_size, ops);
4004 if (!hw)
4005 goto err;
4006
4007 hw->wiphy->iface_combinations = rtw89_iface_combs;
4008 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs);
4009
4010 rtwdev = hw->priv;
4011 rtwdev->hw = hw;
4012 rtwdev->dev = device;
4013 rtwdev->ops = ops;
4014 rtwdev->chip = chip;
4015 rtwdev->fw.req.firmware = firmware;
4016 rtwdev->fw.fw_format = fw_format;
4017
4018 rtw89_debug(rtwdev, RTW89_DBG_FW, "probe driver %s chanctx\n",
4019 no_chanctx ? "without" : "with");
4020
4021 return rtwdev;
4022
4023 err:
4024 kfree(ops);
4025 release_firmware(firmware);
4026 return NULL;
4027 }
4028 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw);
4029
rtw89_free_ieee80211_hw(struct rtw89_dev * rtwdev)4030 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev)
4031 {
4032 kfree(rtwdev->ops);
4033 release_firmware(rtwdev->fw.req.firmware);
4034 ieee80211_free_hw(rtwdev->hw);
4035 }
4036 EXPORT_SYMBOL(rtw89_free_ieee80211_hw);
4037
4038 MODULE_AUTHOR("Realtek Corporation");
4039 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module");
4040 MODULE_LICENSE("Dual BSD/GPL");
4041