1 /* $NetBSD: radeon_rv770.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $ */
2
3 /*
4 * Copyright 2008 Advanced Micro Devices, Inc.
5 * Copyright 2008 Red Hat Inc.
6 * Copyright 2009 Jerome Glisse.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 * OTHER DEALINGS IN THE SOFTWARE.
25 *
26 * Authors: Dave Airlie
27 * Alex Deucher
28 * Jerome Glisse
29 */
30
31 #include <sys/cdefs.h>
32 __KERNEL_RCSID(0, "$NetBSD: radeon_rv770.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $");
33
34 #include <linux/firmware.h>
35 #include <linux/pci.h>
36 #include <linux/slab.h>
37
38 #include <drm/drm_device.h>
39 #include <drm/radeon_drm.h>
40
41 #include "atom.h"
42 #include "avivod.h"
43 #include "radeon.h"
44 #include "radeon_asic.h"
45 #include "radeon_audio.h"
46 #include "rv770d.h"
47
48 #define R700_PFP_UCODE_SIZE 848
49 #define R700_PM4_UCODE_SIZE 1360
50
51 static void rv770_gpu_init(struct radeon_device *rdev);
52 void rv770_fini(struct radeon_device *rdev);
53 static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
54 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
55
rv770_set_uvd_clocks(struct radeon_device * rdev,u32 vclk,u32 dclk)56 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
57 {
58 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
59 int r;
60
61 /* RV740 uses evergreen uvd clk programming */
62 if (rdev->family == CHIP_RV740)
63 return evergreen_set_uvd_clocks(rdev, vclk, dclk);
64
65 /* bypass vclk and dclk with bclk */
66 WREG32_P(CG_UPLL_FUNC_CNTL_2,
67 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
68 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
69
70 if (!vclk || !dclk) {
71 /* keep the Bypass mode, put PLL to sleep */
72 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
73 return 0;
74 }
75
76 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
77 43663, 0x03FFFFFE, 1, 30, ~0,
78 &fb_div, &vclk_div, &dclk_div);
79 if (r)
80 return r;
81
82 fb_div |= 1;
83 vclk_div -= 1;
84 dclk_div -= 1;
85
86 /* set UPLL_FB_DIV to 0x50000 */
87 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK);
88
89 /* deassert UPLL_RESET and UPLL_SLEEP */
90 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK));
91
92 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */
93 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
94 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1));
95
96 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
97 if (r)
98 return r;
99
100 /* assert PLL_RESET */
101 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
102
103 /* set the required FB_DIV, REF_DIV, Post divder values */
104 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK);
105 WREG32_P(CG_UPLL_FUNC_CNTL_2,
106 UPLL_SW_HILEN(vclk_div >> 1) |
107 UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
108 UPLL_SW_HILEN2(dclk_div >> 1) |
109 UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)),
110 ~UPLL_SW_MASK);
111
112 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div),
113 ~UPLL_FB_DIV_MASK);
114
115 /* give the PLL some time to settle */
116 mdelay(15);
117
118 /* deassert PLL_RESET */
119 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
120
121 mdelay(15);
122
123 /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */
124 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
125 WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1));
126
127 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
128 if (r)
129 return r;
130
131 /* switch VCLK and DCLK selection */
132 WREG32_P(CG_UPLL_FUNC_CNTL_2,
133 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
134 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
135
136 mdelay(100);
137
138 return 0;
139 }
140
141 static const u32 r7xx_golden_registers[] =
142 {
143 0x8d00, 0xffffffff, 0x0e0e0074,
144 0x8d04, 0xffffffff, 0x013a2b34,
145 0x9508, 0xffffffff, 0x00000002,
146 0x8b20, 0xffffffff, 0,
147 0x88c4, 0xffffffff, 0x000000c2,
148 0x28350, 0xffffffff, 0,
149 0x9058, 0xffffffff, 0x0fffc40f,
150 0x240c, 0xffffffff, 0x00000380,
151 0x733c, 0xffffffff, 0x00000002,
152 0x2650, 0x00040000, 0,
153 0x20bc, 0x00040000, 0,
154 0x7300, 0xffffffff, 0x001000f0
155 };
156
157 static const u32 r7xx_golden_dyn_gpr_registers[] =
158 {
159 0x8db0, 0xffffffff, 0x98989898,
160 0x8db4, 0xffffffff, 0x98989898,
161 0x8db8, 0xffffffff, 0x98989898,
162 0x8dbc, 0xffffffff, 0x98989898,
163 0x8dc0, 0xffffffff, 0x98989898,
164 0x8dc4, 0xffffffff, 0x98989898,
165 0x8dc8, 0xffffffff, 0x98989898,
166 0x8dcc, 0xffffffff, 0x98989898,
167 0x88c4, 0xffffffff, 0x00000082
168 };
169
170 static const u32 rv770_golden_registers[] =
171 {
172 0x562c, 0xffffffff, 0,
173 0x3f90, 0xffffffff, 0,
174 0x9148, 0xffffffff, 0,
175 0x3f94, 0xffffffff, 0,
176 0x914c, 0xffffffff, 0,
177 0x9698, 0x18000000, 0x18000000
178 };
179
180 static const u32 rv770ce_golden_registers[] =
181 {
182 0x562c, 0xffffffff, 0,
183 0x3f90, 0xffffffff, 0x00cc0000,
184 0x9148, 0xffffffff, 0x00cc0000,
185 0x3f94, 0xffffffff, 0x00cc0000,
186 0x914c, 0xffffffff, 0x00cc0000,
187 0x9b7c, 0xffffffff, 0x00fa0000,
188 0x3f8c, 0xffffffff, 0x00fa0000,
189 0x9698, 0x18000000, 0x18000000
190 };
191
192 static const u32 rv770_mgcg_init[] =
193 {
194 0x8bcc, 0xffffffff, 0x130300f9,
195 0x5448, 0xffffffff, 0x100,
196 0x55e4, 0xffffffff, 0x100,
197 0x160c, 0xffffffff, 0x100,
198 0x5644, 0xffffffff, 0x100,
199 0xc164, 0xffffffff, 0x100,
200 0x8a18, 0xffffffff, 0x100,
201 0x897c, 0xffffffff, 0x8000100,
202 0x8b28, 0xffffffff, 0x3c000100,
203 0x9144, 0xffffffff, 0x100,
204 0x9a1c, 0xffffffff, 0x10000,
205 0x9a50, 0xffffffff, 0x100,
206 0x9a1c, 0xffffffff, 0x10001,
207 0x9a50, 0xffffffff, 0x100,
208 0x9a1c, 0xffffffff, 0x10002,
209 0x9a50, 0xffffffff, 0x100,
210 0x9a1c, 0xffffffff, 0x10003,
211 0x9a50, 0xffffffff, 0x100,
212 0x9a1c, 0xffffffff, 0x0,
213 0x9870, 0xffffffff, 0x100,
214 0x8d58, 0xffffffff, 0x100,
215 0x9500, 0xffffffff, 0x0,
216 0x9510, 0xffffffff, 0x100,
217 0x9500, 0xffffffff, 0x1,
218 0x9510, 0xffffffff, 0x100,
219 0x9500, 0xffffffff, 0x2,
220 0x9510, 0xffffffff, 0x100,
221 0x9500, 0xffffffff, 0x3,
222 0x9510, 0xffffffff, 0x100,
223 0x9500, 0xffffffff, 0x4,
224 0x9510, 0xffffffff, 0x100,
225 0x9500, 0xffffffff, 0x5,
226 0x9510, 0xffffffff, 0x100,
227 0x9500, 0xffffffff, 0x6,
228 0x9510, 0xffffffff, 0x100,
229 0x9500, 0xffffffff, 0x7,
230 0x9510, 0xffffffff, 0x100,
231 0x9500, 0xffffffff, 0x8,
232 0x9510, 0xffffffff, 0x100,
233 0x9500, 0xffffffff, 0x9,
234 0x9510, 0xffffffff, 0x100,
235 0x9500, 0xffffffff, 0x8000,
236 0x9490, 0xffffffff, 0x0,
237 0x949c, 0xffffffff, 0x100,
238 0x9490, 0xffffffff, 0x1,
239 0x949c, 0xffffffff, 0x100,
240 0x9490, 0xffffffff, 0x2,
241 0x949c, 0xffffffff, 0x100,
242 0x9490, 0xffffffff, 0x3,
243 0x949c, 0xffffffff, 0x100,
244 0x9490, 0xffffffff, 0x4,
245 0x949c, 0xffffffff, 0x100,
246 0x9490, 0xffffffff, 0x5,
247 0x949c, 0xffffffff, 0x100,
248 0x9490, 0xffffffff, 0x6,
249 0x949c, 0xffffffff, 0x100,
250 0x9490, 0xffffffff, 0x7,
251 0x949c, 0xffffffff, 0x100,
252 0x9490, 0xffffffff, 0x8,
253 0x949c, 0xffffffff, 0x100,
254 0x9490, 0xffffffff, 0x9,
255 0x949c, 0xffffffff, 0x100,
256 0x9490, 0xffffffff, 0x8000,
257 0x9604, 0xffffffff, 0x0,
258 0x9654, 0xffffffff, 0x100,
259 0x9604, 0xffffffff, 0x1,
260 0x9654, 0xffffffff, 0x100,
261 0x9604, 0xffffffff, 0x2,
262 0x9654, 0xffffffff, 0x100,
263 0x9604, 0xffffffff, 0x3,
264 0x9654, 0xffffffff, 0x100,
265 0x9604, 0xffffffff, 0x4,
266 0x9654, 0xffffffff, 0x100,
267 0x9604, 0xffffffff, 0x5,
268 0x9654, 0xffffffff, 0x100,
269 0x9604, 0xffffffff, 0x6,
270 0x9654, 0xffffffff, 0x100,
271 0x9604, 0xffffffff, 0x7,
272 0x9654, 0xffffffff, 0x100,
273 0x9604, 0xffffffff, 0x8,
274 0x9654, 0xffffffff, 0x100,
275 0x9604, 0xffffffff, 0x9,
276 0x9654, 0xffffffff, 0x100,
277 0x9604, 0xffffffff, 0x80000000,
278 0x9030, 0xffffffff, 0x100,
279 0x9034, 0xffffffff, 0x100,
280 0x9038, 0xffffffff, 0x100,
281 0x903c, 0xffffffff, 0x100,
282 0x9040, 0xffffffff, 0x100,
283 0xa200, 0xffffffff, 0x100,
284 0xa204, 0xffffffff, 0x100,
285 0xa208, 0xffffffff, 0x100,
286 0xa20c, 0xffffffff, 0x100,
287 0x971c, 0xffffffff, 0x100,
288 0x915c, 0xffffffff, 0x00020001,
289 0x9160, 0xffffffff, 0x00040003,
290 0x916c, 0xffffffff, 0x00060005,
291 0x9170, 0xffffffff, 0x00080007,
292 0x9174, 0xffffffff, 0x000a0009,
293 0x9178, 0xffffffff, 0x000c000b,
294 0x917c, 0xffffffff, 0x000e000d,
295 0x9180, 0xffffffff, 0x0010000f,
296 0x918c, 0xffffffff, 0x00120011,
297 0x9190, 0xffffffff, 0x00140013,
298 0x9194, 0xffffffff, 0x00020001,
299 0x9198, 0xffffffff, 0x00040003,
300 0x919c, 0xffffffff, 0x00060005,
301 0x91a8, 0xffffffff, 0x00080007,
302 0x91ac, 0xffffffff, 0x000a0009,
303 0x91b0, 0xffffffff, 0x000c000b,
304 0x91b4, 0xffffffff, 0x000e000d,
305 0x91b8, 0xffffffff, 0x0010000f,
306 0x91c4, 0xffffffff, 0x00120011,
307 0x91c8, 0xffffffff, 0x00140013,
308 0x91cc, 0xffffffff, 0x00020001,
309 0x91d0, 0xffffffff, 0x00040003,
310 0x91d4, 0xffffffff, 0x00060005,
311 0x91e0, 0xffffffff, 0x00080007,
312 0x91e4, 0xffffffff, 0x000a0009,
313 0x91e8, 0xffffffff, 0x000c000b,
314 0x91ec, 0xffffffff, 0x00020001,
315 0x91f0, 0xffffffff, 0x00040003,
316 0x91f4, 0xffffffff, 0x00060005,
317 0x9200, 0xffffffff, 0x00080007,
318 0x9204, 0xffffffff, 0x000a0009,
319 0x9208, 0xffffffff, 0x000c000b,
320 0x920c, 0xffffffff, 0x000e000d,
321 0x9210, 0xffffffff, 0x0010000f,
322 0x921c, 0xffffffff, 0x00120011,
323 0x9220, 0xffffffff, 0x00140013,
324 0x9224, 0xffffffff, 0x00020001,
325 0x9228, 0xffffffff, 0x00040003,
326 0x922c, 0xffffffff, 0x00060005,
327 0x9238, 0xffffffff, 0x00080007,
328 0x923c, 0xffffffff, 0x000a0009,
329 0x9240, 0xffffffff, 0x000c000b,
330 0x9244, 0xffffffff, 0x000e000d,
331 0x9248, 0xffffffff, 0x0010000f,
332 0x9254, 0xffffffff, 0x00120011,
333 0x9258, 0xffffffff, 0x00140013,
334 0x925c, 0xffffffff, 0x00020001,
335 0x9260, 0xffffffff, 0x00040003,
336 0x9264, 0xffffffff, 0x00060005,
337 0x9270, 0xffffffff, 0x00080007,
338 0x9274, 0xffffffff, 0x000a0009,
339 0x9278, 0xffffffff, 0x000c000b,
340 0x927c, 0xffffffff, 0x000e000d,
341 0x9280, 0xffffffff, 0x0010000f,
342 0x928c, 0xffffffff, 0x00120011,
343 0x9290, 0xffffffff, 0x00140013,
344 0x9294, 0xffffffff, 0x00020001,
345 0x929c, 0xffffffff, 0x00040003,
346 0x92a0, 0xffffffff, 0x00060005,
347 0x92a4, 0xffffffff, 0x00080007
348 };
349
350 static const u32 rv710_golden_registers[] =
351 {
352 0x3f90, 0x00ff0000, 0x00fc0000,
353 0x9148, 0x00ff0000, 0x00fc0000,
354 0x3f94, 0x00ff0000, 0x00fc0000,
355 0x914c, 0x00ff0000, 0x00fc0000,
356 0xb4c, 0x00000020, 0x00000020,
357 0xa180, 0xffffffff, 0x00003f3f
358 };
359
360 static const u32 rv710_mgcg_init[] =
361 {
362 0x8bcc, 0xffffffff, 0x13030040,
363 0x5448, 0xffffffff, 0x100,
364 0x55e4, 0xffffffff, 0x100,
365 0x160c, 0xffffffff, 0x100,
366 0x5644, 0xffffffff, 0x100,
367 0xc164, 0xffffffff, 0x100,
368 0x8a18, 0xffffffff, 0x100,
369 0x897c, 0xffffffff, 0x8000100,
370 0x8b28, 0xffffffff, 0x3c000100,
371 0x9144, 0xffffffff, 0x100,
372 0x9a1c, 0xffffffff, 0x10000,
373 0x9a50, 0xffffffff, 0x100,
374 0x9a1c, 0xffffffff, 0x0,
375 0x9870, 0xffffffff, 0x100,
376 0x8d58, 0xffffffff, 0x100,
377 0x9500, 0xffffffff, 0x0,
378 0x9510, 0xffffffff, 0x100,
379 0x9500, 0xffffffff, 0x1,
380 0x9510, 0xffffffff, 0x100,
381 0x9500, 0xffffffff, 0x8000,
382 0x9490, 0xffffffff, 0x0,
383 0x949c, 0xffffffff, 0x100,
384 0x9490, 0xffffffff, 0x1,
385 0x949c, 0xffffffff, 0x100,
386 0x9490, 0xffffffff, 0x8000,
387 0x9604, 0xffffffff, 0x0,
388 0x9654, 0xffffffff, 0x100,
389 0x9604, 0xffffffff, 0x1,
390 0x9654, 0xffffffff, 0x100,
391 0x9604, 0xffffffff, 0x80000000,
392 0x9030, 0xffffffff, 0x100,
393 0x9034, 0xffffffff, 0x100,
394 0x9038, 0xffffffff, 0x100,
395 0x903c, 0xffffffff, 0x100,
396 0x9040, 0xffffffff, 0x100,
397 0xa200, 0xffffffff, 0x100,
398 0xa204, 0xffffffff, 0x100,
399 0xa208, 0xffffffff, 0x100,
400 0xa20c, 0xffffffff, 0x100,
401 0x971c, 0xffffffff, 0x100,
402 0x915c, 0xffffffff, 0x00020001,
403 0x9174, 0xffffffff, 0x00000003,
404 0x9178, 0xffffffff, 0x00050001,
405 0x917c, 0xffffffff, 0x00030002,
406 0x918c, 0xffffffff, 0x00000004,
407 0x9190, 0xffffffff, 0x00070006,
408 0x9194, 0xffffffff, 0x00050001,
409 0x9198, 0xffffffff, 0x00030002,
410 0x91a8, 0xffffffff, 0x00000004,
411 0x91ac, 0xffffffff, 0x00070006,
412 0x91e8, 0xffffffff, 0x00000001,
413 0x9294, 0xffffffff, 0x00000001,
414 0x929c, 0xffffffff, 0x00000002,
415 0x92a0, 0xffffffff, 0x00040003,
416 0x9150, 0xffffffff, 0x4d940000
417 };
418
419 static const u32 rv730_golden_registers[] =
420 {
421 0x3f90, 0x00ff0000, 0x00f00000,
422 0x9148, 0x00ff0000, 0x00f00000,
423 0x3f94, 0x00ff0000, 0x00f00000,
424 0x914c, 0x00ff0000, 0x00f00000,
425 0x900c, 0xffffffff, 0x003b033f,
426 0xb4c, 0x00000020, 0x00000020,
427 0xa180, 0xffffffff, 0x00003f3f
428 };
429
430 static const u32 rv730_mgcg_init[] =
431 {
432 0x8bcc, 0xffffffff, 0x130300f9,
433 0x5448, 0xffffffff, 0x100,
434 0x55e4, 0xffffffff, 0x100,
435 0x160c, 0xffffffff, 0x100,
436 0x5644, 0xffffffff, 0x100,
437 0xc164, 0xffffffff, 0x100,
438 0x8a18, 0xffffffff, 0x100,
439 0x897c, 0xffffffff, 0x8000100,
440 0x8b28, 0xffffffff, 0x3c000100,
441 0x9144, 0xffffffff, 0x100,
442 0x9a1c, 0xffffffff, 0x10000,
443 0x9a50, 0xffffffff, 0x100,
444 0x9a1c, 0xffffffff, 0x10001,
445 0x9a50, 0xffffffff, 0x100,
446 0x9a1c, 0xffffffff, 0x0,
447 0x9870, 0xffffffff, 0x100,
448 0x8d58, 0xffffffff, 0x100,
449 0x9500, 0xffffffff, 0x0,
450 0x9510, 0xffffffff, 0x100,
451 0x9500, 0xffffffff, 0x1,
452 0x9510, 0xffffffff, 0x100,
453 0x9500, 0xffffffff, 0x2,
454 0x9510, 0xffffffff, 0x100,
455 0x9500, 0xffffffff, 0x3,
456 0x9510, 0xffffffff, 0x100,
457 0x9500, 0xffffffff, 0x4,
458 0x9510, 0xffffffff, 0x100,
459 0x9500, 0xffffffff, 0x5,
460 0x9510, 0xffffffff, 0x100,
461 0x9500, 0xffffffff, 0x6,
462 0x9510, 0xffffffff, 0x100,
463 0x9500, 0xffffffff, 0x7,
464 0x9510, 0xffffffff, 0x100,
465 0x9500, 0xffffffff, 0x8000,
466 0x9490, 0xffffffff, 0x0,
467 0x949c, 0xffffffff, 0x100,
468 0x9490, 0xffffffff, 0x1,
469 0x949c, 0xffffffff, 0x100,
470 0x9490, 0xffffffff, 0x2,
471 0x949c, 0xffffffff, 0x100,
472 0x9490, 0xffffffff, 0x3,
473 0x949c, 0xffffffff, 0x100,
474 0x9490, 0xffffffff, 0x4,
475 0x949c, 0xffffffff, 0x100,
476 0x9490, 0xffffffff, 0x5,
477 0x949c, 0xffffffff, 0x100,
478 0x9490, 0xffffffff, 0x6,
479 0x949c, 0xffffffff, 0x100,
480 0x9490, 0xffffffff, 0x7,
481 0x949c, 0xffffffff, 0x100,
482 0x9490, 0xffffffff, 0x8000,
483 0x9604, 0xffffffff, 0x0,
484 0x9654, 0xffffffff, 0x100,
485 0x9604, 0xffffffff, 0x1,
486 0x9654, 0xffffffff, 0x100,
487 0x9604, 0xffffffff, 0x2,
488 0x9654, 0xffffffff, 0x100,
489 0x9604, 0xffffffff, 0x3,
490 0x9654, 0xffffffff, 0x100,
491 0x9604, 0xffffffff, 0x4,
492 0x9654, 0xffffffff, 0x100,
493 0x9604, 0xffffffff, 0x5,
494 0x9654, 0xffffffff, 0x100,
495 0x9604, 0xffffffff, 0x6,
496 0x9654, 0xffffffff, 0x100,
497 0x9604, 0xffffffff, 0x7,
498 0x9654, 0xffffffff, 0x100,
499 0x9604, 0xffffffff, 0x80000000,
500 0x9030, 0xffffffff, 0x100,
501 0x9034, 0xffffffff, 0x100,
502 0x9038, 0xffffffff, 0x100,
503 0x903c, 0xffffffff, 0x100,
504 0x9040, 0xffffffff, 0x100,
505 0xa200, 0xffffffff, 0x100,
506 0xa204, 0xffffffff, 0x100,
507 0xa208, 0xffffffff, 0x100,
508 0xa20c, 0xffffffff, 0x100,
509 0x971c, 0xffffffff, 0x100,
510 0x915c, 0xffffffff, 0x00020001,
511 0x916c, 0xffffffff, 0x00040003,
512 0x9170, 0xffffffff, 0x00000005,
513 0x9178, 0xffffffff, 0x00050001,
514 0x917c, 0xffffffff, 0x00030002,
515 0x918c, 0xffffffff, 0x00000004,
516 0x9190, 0xffffffff, 0x00070006,
517 0x9194, 0xffffffff, 0x00050001,
518 0x9198, 0xffffffff, 0x00030002,
519 0x91a8, 0xffffffff, 0x00000004,
520 0x91ac, 0xffffffff, 0x00070006,
521 0x91b0, 0xffffffff, 0x00050001,
522 0x91b4, 0xffffffff, 0x00030002,
523 0x91c4, 0xffffffff, 0x00000004,
524 0x91c8, 0xffffffff, 0x00070006,
525 0x91cc, 0xffffffff, 0x00050001,
526 0x91d0, 0xffffffff, 0x00030002,
527 0x91e0, 0xffffffff, 0x00000004,
528 0x91e4, 0xffffffff, 0x00070006,
529 0x91e8, 0xffffffff, 0x00000001,
530 0x91ec, 0xffffffff, 0x00050001,
531 0x91f0, 0xffffffff, 0x00030002,
532 0x9200, 0xffffffff, 0x00000004,
533 0x9204, 0xffffffff, 0x00070006,
534 0x9208, 0xffffffff, 0x00050001,
535 0x920c, 0xffffffff, 0x00030002,
536 0x921c, 0xffffffff, 0x00000004,
537 0x9220, 0xffffffff, 0x00070006,
538 0x9224, 0xffffffff, 0x00050001,
539 0x9228, 0xffffffff, 0x00030002,
540 0x9238, 0xffffffff, 0x00000004,
541 0x923c, 0xffffffff, 0x00070006,
542 0x9240, 0xffffffff, 0x00050001,
543 0x9244, 0xffffffff, 0x00030002,
544 0x9254, 0xffffffff, 0x00000004,
545 0x9258, 0xffffffff, 0x00070006,
546 0x9294, 0xffffffff, 0x00000001,
547 0x929c, 0xffffffff, 0x00000002,
548 0x92a0, 0xffffffff, 0x00040003,
549 0x92a4, 0xffffffff, 0x00000005
550 };
551
552 static const u32 rv740_golden_registers[] =
553 {
554 0x88c4, 0xffffffff, 0x00000082,
555 0x28a50, 0xfffffffc, 0x00000004,
556 0x2650, 0x00040000, 0,
557 0x20bc, 0x00040000, 0,
558 0x733c, 0xffffffff, 0x00000002,
559 0x7300, 0xffffffff, 0x001000f0,
560 0x3f90, 0x00ff0000, 0,
561 0x9148, 0x00ff0000, 0,
562 0x3f94, 0x00ff0000, 0,
563 0x914c, 0x00ff0000, 0,
564 0x240c, 0xffffffff, 0x00000380,
565 0x8a14, 0x00000007, 0x00000007,
566 0x8b24, 0xffffffff, 0x00ff0fff,
567 0x28a4c, 0xffffffff, 0x00004000,
568 0xa180, 0xffffffff, 0x00003f3f,
569 0x8d00, 0xffffffff, 0x0e0e003a,
570 0x8d04, 0xffffffff, 0x013a0e2a,
571 0x8c00, 0xffffffff, 0xe400000f,
572 0x8db0, 0xffffffff, 0x98989898,
573 0x8db4, 0xffffffff, 0x98989898,
574 0x8db8, 0xffffffff, 0x98989898,
575 0x8dbc, 0xffffffff, 0x98989898,
576 0x8dc0, 0xffffffff, 0x98989898,
577 0x8dc4, 0xffffffff, 0x98989898,
578 0x8dc8, 0xffffffff, 0x98989898,
579 0x8dcc, 0xffffffff, 0x98989898,
580 0x9058, 0xffffffff, 0x0fffc40f,
581 0x900c, 0xffffffff, 0x003b033f,
582 0x28350, 0xffffffff, 0,
583 0x8cf0, 0x1fffffff, 0x08e00420,
584 0x9508, 0xffffffff, 0x00000002,
585 0x88c4, 0xffffffff, 0x000000c2,
586 0x9698, 0x18000000, 0x18000000
587 };
588
589 static const u32 rv740_mgcg_init[] =
590 {
591 0x8bcc, 0xffffffff, 0x13030100,
592 0x5448, 0xffffffff, 0x100,
593 0x55e4, 0xffffffff, 0x100,
594 0x160c, 0xffffffff, 0x100,
595 0x5644, 0xffffffff, 0x100,
596 0xc164, 0xffffffff, 0x100,
597 0x8a18, 0xffffffff, 0x100,
598 0x897c, 0xffffffff, 0x100,
599 0x8b28, 0xffffffff, 0x100,
600 0x9144, 0xffffffff, 0x100,
601 0x9a1c, 0xffffffff, 0x10000,
602 0x9a50, 0xffffffff, 0x100,
603 0x9a1c, 0xffffffff, 0x10001,
604 0x9a50, 0xffffffff, 0x100,
605 0x9a1c, 0xffffffff, 0x10002,
606 0x9a50, 0xffffffff, 0x100,
607 0x9a1c, 0xffffffff, 0x10003,
608 0x9a50, 0xffffffff, 0x100,
609 0x9a1c, 0xffffffff, 0x0,
610 0x9870, 0xffffffff, 0x100,
611 0x8d58, 0xffffffff, 0x100,
612 0x9500, 0xffffffff, 0x0,
613 0x9510, 0xffffffff, 0x100,
614 0x9500, 0xffffffff, 0x1,
615 0x9510, 0xffffffff, 0x100,
616 0x9500, 0xffffffff, 0x2,
617 0x9510, 0xffffffff, 0x100,
618 0x9500, 0xffffffff, 0x3,
619 0x9510, 0xffffffff, 0x100,
620 0x9500, 0xffffffff, 0x4,
621 0x9510, 0xffffffff, 0x100,
622 0x9500, 0xffffffff, 0x5,
623 0x9510, 0xffffffff, 0x100,
624 0x9500, 0xffffffff, 0x6,
625 0x9510, 0xffffffff, 0x100,
626 0x9500, 0xffffffff, 0x7,
627 0x9510, 0xffffffff, 0x100,
628 0x9500, 0xffffffff, 0x8000,
629 0x9490, 0xffffffff, 0x0,
630 0x949c, 0xffffffff, 0x100,
631 0x9490, 0xffffffff, 0x1,
632 0x949c, 0xffffffff, 0x100,
633 0x9490, 0xffffffff, 0x2,
634 0x949c, 0xffffffff, 0x100,
635 0x9490, 0xffffffff, 0x3,
636 0x949c, 0xffffffff, 0x100,
637 0x9490, 0xffffffff, 0x4,
638 0x949c, 0xffffffff, 0x100,
639 0x9490, 0xffffffff, 0x5,
640 0x949c, 0xffffffff, 0x100,
641 0x9490, 0xffffffff, 0x6,
642 0x949c, 0xffffffff, 0x100,
643 0x9490, 0xffffffff, 0x7,
644 0x949c, 0xffffffff, 0x100,
645 0x9490, 0xffffffff, 0x8000,
646 0x9604, 0xffffffff, 0x0,
647 0x9654, 0xffffffff, 0x100,
648 0x9604, 0xffffffff, 0x1,
649 0x9654, 0xffffffff, 0x100,
650 0x9604, 0xffffffff, 0x2,
651 0x9654, 0xffffffff, 0x100,
652 0x9604, 0xffffffff, 0x3,
653 0x9654, 0xffffffff, 0x100,
654 0x9604, 0xffffffff, 0x4,
655 0x9654, 0xffffffff, 0x100,
656 0x9604, 0xffffffff, 0x5,
657 0x9654, 0xffffffff, 0x100,
658 0x9604, 0xffffffff, 0x6,
659 0x9654, 0xffffffff, 0x100,
660 0x9604, 0xffffffff, 0x7,
661 0x9654, 0xffffffff, 0x100,
662 0x9604, 0xffffffff, 0x80000000,
663 0x9030, 0xffffffff, 0x100,
664 0x9034, 0xffffffff, 0x100,
665 0x9038, 0xffffffff, 0x100,
666 0x903c, 0xffffffff, 0x100,
667 0x9040, 0xffffffff, 0x100,
668 0xa200, 0xffffffff, 0x100,
669 0xa204, 0xffffffff, 0x100,
670 0xa208, 0xffffffff, 0x100,
671 0xa20c, 0xffffffff, 0x100,
672 0x971c, 0xffffffff, 0x100,
673 0x915c, 0xffffffff, 0x00020001,
674 0x9160, 0xffffffff, 0x00040003,
675 0x916c, 0xffffffff, 0x00060005,
676 0x9170, 0xffffffff, 0x00080007,
677 0x9174, 0xffffffff, 0x000a0009,
678 0x9178, 0xffffffff, 0x000c000b,
679 0x917c, 0xffffffff, 0x000e000d,
680 0x9180, 0xffffffff, 0x0010000f,
681 0x918c, 0xffffffff, 0x00120011,
682 0x9190, 0xffffffff, 0x00140013,
683 0x9194, 0xffffffff, 0x00020001,
684 0x9198, 0xffffffff, 0x00040003,
685 0x919c, 0xffffffff, 0x00060005,
686 0x91a8, 0xffffffff, 0x00080007,
687 0x91ac, 0xffffffff, 0x000a0009,
688 0x91b0, 0xffffffff, 0x000c000b,
689 0x91b4, 0xffffffff, 0x000e000d,
690 0x91b8, 0xffffffff, 0x0010000f,
691 0x91c4, 0xffffffff, 0x00120011,
692 0x91c8, 0xffffffff, 0x00140013,
693 0x91cc, 0xffffffff, 0x00020001,
694 0x91d0, 0xffffffff, 0x00040003,
695 0x91d4, 0xffffffff, 0x00060005,
696 0x91e0, 0xffffffff, 0x00080007,
697 0x91e4, 0xffffffff, 0x000a0009,
698 0x91e8, 0xffffffff, 0x000c000b,
699 0x91ec, 0xffffffff, 0x00020001,
700 0x91f0, 0xffffffff, 0x00040003,
701 0x91f4, 0xffffffff, 0x00060005,
702 0x9200, 0xffffffff, 0x00080007,
703 0x9204, 0xffffffff, 0x000a0009,
704 0x9208, 0xffffffff, 0x000c000b,
705 0x920c, 0xffffffff, 0x000e000d,
706 0x9210, 0xffffffff, 0x0010000f,
707 0x921c, 0xffffffff, 0x00120011,
708 0x9220, 0xffffffff, 0x00140013,
709 0x9224, 0xffffffff, 0x00020001,
710 0x9228, 0xffffffff, 0x00040003,
711 0x922c, 0xffffffff, 0x00060005,
712 0x9238, 0xffffffff, 0x00080007,
713 0x923c, 0xffffffff, 0x000a0009,
714 0x9240, 0xffffffff, 0x000c000b,
715 0x9244, 0xffffffff, 0x000e000d,
716 0x9248, 0xffffffff, 0x0010000f,
717 0x9254, 0xffffffff, 0x00120011,
718 0x9258, 0xffffffff, 0x00140013,
719 0x9294, 0xffffffff, 0x00020001,
720 0x929c, 0xffffffff, 0x00040003,
721 0x92a0, 0xffffffff, 0x00060005,
722 0x92a4, 0xffffffff, 0x00080007
723 };
724
rv770_init_golden_registers(struct radeon_device * rdev)725 static void rv770_init_golden_registers(struct radeon_device *rdev)
726 {
727 switch (rdev->family) {
728 case CHIP_RV770:
729 radeon_program_register_sequence(rdev,
730 r7xx_golden_registers,
731 (const u32)ARRAY_SIZE(r7xx_golden_registers));
732 radeon_program_register_sequence(rdev,
733 r7xx_golden_dyn_gpr_registers,
734 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
735 if (rdev->pdev->device == 0x994e)
736 radeon_program_register_sequence(rdev,
737 rv770ce_golden_registers,
738 (const u32)ARRAY_SIZE(rv770ce_golden_registers));
739 else
740 radeon_program_register_sequence(rdev,
741 rv770_golden_registers,
742 (const u32)ARRAY_SIZE(rv770_golden_registers));
743 radeon_program_register_sequence(rdev,
744 rv770_mgcg_init,
745 (const u32)ARRAY_SIZE(rv770_mgcg_init));
746 break;
747 case CHIP_RV730:
748 radeon_program_register_sequence(rdev,
749 r7xx_golden_registers,
750 (const u32)ARRAY_SIZE(r7xx_golden_registers));
751 radeon_program_register_sequence(rdev,
752 r7xx_golden_dyn_gpr_registers,
753 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
754 radeon_program_register_sequence(rdev,
755 rv730_golden_registers,
756 (const u32)ARRAY_SIZE(rv730_golden_registers));
757 radeon_program_register_sequence(rdev,
758 rv730_mgcg_init,
759 (const u32)ARRAY_SIZE(rv730_mgcg_init));
760 break;
761 case CHIP_RV710:
762 radeon_program_register_sequence(rdev,
763 r7xx_golden_registers,
764 (const u32)ARRAY_SIZE(r7xx_golden_registers));
765 radeon_program_register_sequence(rdev,
766 r7xx_golden_dyn_gpr_registers,
767 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
768 radeon_program_register_sequence(rdev,
769 rv710_golden_registers,
770 (const u32)ARRAY_SIZE(rv710_golden_registers));
771 radeon_program_register_sequence(rdev,
772 rv710_mgcg_init,
773 (const u32)ARRAY_SIZE(rv710_mgcg_init));
774 break;
775 case CHIP_RV740:
776 radeon_program_register_sequence(rdev,
777 rv740_golden_registers,
778 (const u32)ARRAY_SIZE(rv740_golden_registers));
779 radeon_program_register_sequence(rdev,
780 rv740_mgcg_init,
781 (const u32)ARRAY_SIZE(rv740_mgcg_init));
782 break;
783 default:
784 break;
785 }
786 }
787
788 #define PCIE_BUS_CLK 10000
789 #define TCLK (PCIE_BUS_CLK / 10)
790
791 /**
792 * rv770_get_xclk - get the xclk
793 *
794 * @rdev: radeon_device pointer
795 *
796 * Returns the reference clock used by the gfx engine
797 * (r7xx-cayman).
798 */
rv770_get_xclk(struct radeon_device * rdev)799 u32 rv770_get_xclk(struct radeon_device *rdev)
800 {
801 u32 reference_clock = rdev->clock.spll.reference_freq;
802 u32 tmp = RREG32(CG_CLKPIN_CNTL);
803
804 if (tmp & MUX_TCLK_TO_XCLK)
805 return TCLK;
806
807 if (tmp & XTALIN_DIVIDE)
808 return reference_clock / 4;
809
810 return reference_clock;
811 }
812
rv770_page_flip(struct radeon_device * rdev,int crtc_id,u64 crtc_base,bool async)813 void rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
814 {
815 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
816 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
817 int i;
818
819 /* Lock the graphics update lock */
820 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
821 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
822
823 /* update the scanout addresses */
824 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,
825 async ? AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0);
826 if (radeon_crtc->crtc_id) {
827 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
828 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
829 } else {
830 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
831 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
832 }
833 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
834 (u32)crtc_base);
835 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
836 (u32)crtc_base);
837
838 /* Wait for update_pending to go high. */
839 for (i = 0; i < rdev->usec_timeout; i++) {
840 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
841 break;
842 udelay(1);
843 }
844 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
845
846 /* Unlock the lock, so double-buffering can take place inside vblank */
847 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
848 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
849 }
850
rv770_page_flip_pending(struct radeon_device * rdev,int crtc_id)851 bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc_id)
852 {
853 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
854
855 /* Return current update_pending status: */
856 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
857 AVIVO_D1GRPH_SURFACE_UPDATE_PENDING);
858 }
859
860 /* get temperature in millidegrees */
rv770_get_temp(struct radeon_device * rdev)861 int rv770_get_temp(struct radeon_device *rdev)
862 {
863 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
864 ASIC_T_SHIFT;
865 int actual_temp;
866
867 if (temp & 0x400)
868 actual_temp = -256;
869 else if (temp & 0x200)
870 actual_temp = 255;
871 else if (temp & 0x100) {
872 actual_temp = temp & 0x1ff;
873 actual_temp |= ~0x1ff;
874 } else
875 actual_temp = temp & 0xff;
876
877 return (actual_temp * 1000) / 2;
878 }
879
rv770_pm_misc(struct radeon_device * rdev)880 void rv770_pm_misc(struct radeon_device *rdev)
881 {
882 int req_ps_idx = rdev->pm.requested_power_state_index;
883 int req_cm_idx = rdev->pm.requested_clock_mode_index;
884 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
885 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
886
887 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
888 /* 0xff01 is a flag rather then an actual voltage */
889 if (voltage->voltage == 0xff01)
890 return;
891 if (voltage->voltage != rdev->pm.current_vddc) {
892 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
893 rdev->pm.current_vddc = voltage->voltage;
894 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
895 }
896 }
897 }
898
899 /*
900 * GART
901 */
rv770_pcie_gart_enable(struct radeon_device * rdev)902 static int rv770_pcie_gart_enable(struct radeon_device *rdev)
903 {
904 u32 tmp;
905 int r, i;
906
907 if (rdev->gart.robj == NULL) {
908 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
909 return -EINVAL;
910 }
911 r = radeon_gart_table_vram_pin(rdev);
912 if (r)
913 return r;
914 /* Setup L2 cache */
915 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
916 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
917 EFFECTIVE_L2_QUEUE_SIZE(7));
918 WREG32(VM_L2_CNTL2, 0);
919 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
920 /* Setup TLB control */
921 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
922 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
923 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
924 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
925 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
926 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
927 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
928 if (rdev->family == CHIP_RV740)
929 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
930 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
931 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
932 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
933 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
934 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
935 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
936 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
937 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
938 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
939 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
940 (u32)(rdev->dummy_page.addr >> 12));
941 for (i = 1; i < 7; i++)
942 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
943
944 r600_pcie_gart_tlb_flush(rdev);
945 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
946 (unsigned)(rdev->mc.gtt_size >> 20),
947 (unsigned long long)rdev->gart.table_addr);
948 rdev->gart.ready = true;
949 return 0;
950 }
951
rv770_pcie_gart_disable(struct radeon_device * rdev)952 static void rv770_pcie_gart_disable(struct radeon_device *rdev)
953 {
954 u32 tmp;
955 int i;
956
957 /* Disable all tables */
958 for (i = 0; i < 7; i++)
959 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
960
961 /* Setup L2 cache */
962 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
963 EFFECTIVE_L2_QUEUE_SIZE(7));
964 WREG32(VM_L2_CNTL2, 0);
965 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
966 /* Setup TLB control */
967 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
968 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
969 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
970 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
971 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
972 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
973 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
974 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
975 radeon_gart_table_vram_unpin(rdev);
976 }
977
rv770_pcie_gart_fini(struct radeon_device * rdev)978 static void rv770_pcie_gart_fini(struct radeon_device *rdev)
979 {
980 radeon_gart_fini(rdev);
981 rv770_pcie_gart_disable(rdev);
982 radeon_gart_table_vram_free(rdev);
983 }
984
985
rv770_agp_enable(struct radeon_device * rdev)986 static void rv770_agp_enable(struct radeon_device *rdev)
987 {
988 u32 tmp;
989 int i;
990
991 /* Setup L2 cache */
992 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
993 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
994 EFFECTIVE_L2_QUEUE_SIZE(7));
995 WREG32(VM_L2_CNTL2, 0);
996 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
997 /* Setup TLB control */
998 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
999 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1000 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1001 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1002 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1003 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1004 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1005 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1006 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1007 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1008 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1009 for (i = 0; i < 7; i++)
1010 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1011 }
1012
rv770_mc_program(struct radeon_device * rdev)1013 static void rv770_mc_program(struct radeon_device *rdev)
1014 {
1015 struct rv515_mc_save save;
1016 u32 tmp;
1017 int i, j;
1018
1019 /* Initialize HDP */
1020 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1021 WREG32((0x2c14 + j), 0x00000000);
1022 WREG32((0x2c18 + j), 0x00000000);
1023 WREG32((0x2c1c + j), 0x00000000);
1024 WREG32((0x2c20 + j), 0x00000000);
1025 WREG32((0x2c24 + j), 0x00000000);
1026 }
1027 /* r7xx hw bug. Read from HDP_DEBUG1 rather
1028 * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
1029 */
1030 tmp = RREG32(HDP_DEBUG1);
1031
1032 rv515_mc_stop(rdev, &save);
1033 if (r600_mc_wait_for_idle(rdev)) {
1034 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1035 }
1036 /* Lockout access through VGA aperture*/
1037 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1038 /* Update configuration */
1039 if (rdev->flags & RADEON_IS_AGP) {
1040 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1041 /* VRAM before AGP */
1042 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1043 rdev->mc.vram_start >> 12);
1044 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1045 rdev->mc.gtt_end >> 12);
1046 } else {
1047 /* VRAM after AGP */
1048 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1049 rdev->mc.gtt_start >> 12);
1050 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1051 rdev->mc.vram_end >> 12);
1052 }
1053 } else {
1054 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1055 rdev->mc.vram_start >> 12);
1056 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1057 rdev->mc.vram_end >> 12);
1058 }
1059 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1060 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1061 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1062 WREG32(MC_VM_FB_LOCATION, tmp);
1063 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1064 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1065 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1066 if (rdev->flags & RADEON_IS_AGP) {
1067 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1068 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1069 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1070 } else {
1071 WREG32(MC_VM_AGP_BASE, 0);
1072 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1073 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1074 }
1075 if (r600_mc_wait_for_idle(rdev)) {
1076 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1077 }
1078 rv515_mc_resume(rdev, &save);
1079 /* we need to own VRAM, so turn off the VGA renderer here
1080 * to stop it overwriting our objects */
1081 rv515_vga_render_disable(rdev);
1082 }
1083
1084
1085 /*
1086 * CP.
1087 */
r700_cp_stop(struct radeon_device * rdev)1088 void r700_cp_stop(struct radeon_device *rdev)
1089 {
1090 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1091 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1092 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1093 WREG32(SCRATCH_UMSK, 0);
1094 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1095 }
1096
rv770_cp_load_microcode(struct radeon_device * rdev)1097 static int rv770_cp_load_microcode(struct radeon_device *rdev)
1098 {
1099 const __be32 *fw_data;
1100 int i;
1101
1102 if (!rdev->me_fw || !rdev->pfp_fw)
1103 return -EINVAL;
1104
1105 r700_cp_stop(rdev);
1106 WREG32(CP_RB_CNTL,
1107 #ifdef __BIG_ENDIAN
1108 BUF_SWAP_32BIT |
1109 #endif
1110 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1111
1112 /* Reset cp */
1113 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1114 RREG32(GRBM_SOFT_RESET);
1115 mdelay(15);
1116 WREG32(GRBM_SOFT_RESET, 0);
1117
1118 fw_data = (const __be32 *)rdev->pfp_fw->data;
1119 WREG32(CP_PFP_UCODE_ADDR, 0);
1120 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
1121 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1122 WREG32(CP_PFP_UCODE_ADDR, 0);
1123
1124 fw_data = (const __be32 *)rdev->me_fw->data;
1125 WREG32(CP_ME_RAM_WADDR, 0);
1126 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
1127 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1128
1129 WREG32(CP_PFP_UCODE_ADDR, 0);
1130 WREG32(CP_ME_RAM_WADDR, 0);
1131 WREG32(CP_ME_RAM_RADDR, 0);
1132 return 0;
1133 }
1134
r700_cp_fini(struct radeon_device * rdev)1135 void r700_cp_fini(struct radeon_device *rdev)
1136 {
1137 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1138 r700_cp_stop(rdev);
1139 radeon_ring_fini(rdev, ring);
1140 radeon_scratch_free(rdev, ring->rptr_save_reg);
1141 }
1142
rv770_set_clk_bypass_mode(struct radeon_device * rdev)1143 void rv770_set_clk_bypass_mode(struct radeon_device *rdev)
1144 {
1145 u32 tmp, i;
1146
1147 if (rdev->flags & RADEON_IS_IGP)
1148 return;
1149
1150 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
1151 tmp &= SCLK_MUX_SEL_MASK;
1152 tmp |= SCLK_MUX_SEL(1) | SCLK_MUX_UPDATE;
1153 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
1154
1155 for (i = 0; i < rdev->usec_timeout; i++) {
1156 if (RREG32(CG_SPLL_STATUS) & SPLL_CHG_STATUS)
1157 break;
1158 udelay(1);
1159 }
1160
1161 tmp &= ~SCLK_MUX_UPDATE;
1162 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
1163
1164 tmp = RREG32(MPLL_CNTL_MODE);
1165 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730))
1166 tmp &= ~RV730_MPLL_MCLK_SEL;
1167 else
1168 tmp &= ~MPLL_MCLK_SEL;
1169 WREG32(MPLL_CNTL_MODE, tmp);
1170 }
1171
1172 /*
1173 * Core functions
1174 */
rv770_gpu_init(struct radeon_device * rdev)1175 static void rv770_gpu_init(struct radeon_device *rdev)
1176 {
1177 int i, j, num_qd_pipes;
1178 u32 ta_aux_cntl;
1179 u32 sx_debug_1;
1180 u32 smx_dc_ctl0;
1181 u32 db_debug3;
1182 u32 num_gs_verts_per_thread;
1183 u32 vgt_gs_per_es;
1184 u32 gs_prim_buffer_depth = 0;
1185 u32 sq_ms_fifo_sizes;
1186 u32 sq_config;
1187 u32 sq_thread_resource_mgmt;
1188 u32 hdp_host_path_cntl;
1189 u32 sq_dyn_gpr_size_simd_ab_0;
1190 u32 gb_tiling_config = 0;
1191 u32 cc_gc_shader_pipe_config = 0;
1192 u32 mc_arb_ramcfg;
1193 u32 db_debug4, tmp;
1194 u32 inactive_pipes, shader_pipe_config;
1195 u32 disabled_rb_mask;
1196 unsigned active_number;
1197
1198 /* setup chip specs */
1199 rdev->config.rv770.tiling_group_size = 256;
1200 switch (rdev->family) {
1201 case CHIP_RV770:
1202 rdev->config.rv770.max_pipes = 4;
1203 rdev->config.rv770.max_tile_pipes = 8;
1204 rdev->config.rv770.max_simds = 10;
1205 rdev->config.rv770.max_backends = 4;
1206 rdev->config.rv770.max_gprs = 256;
1207 rdev->config.rv770.max_threads = 248;
1208 rdev->config.rv770.max_stack_entries = 512;
1209 rdev->config.rv770.max_hw_contexts = 8;
1210 rdev->config.rv770.max_gs_threads = 16 * 2;
1211 rdev->config.rv770.sx_max_export_size = 128;
1212 rdev->config.rv770.sx_max_export_pos_size = 16;
1213 rdev->config.rv770.sx_max_export_smx_size = 112;
1214 rdev->config.rv770.sq_num_cf_insts = 2;
1215
1216 rdev->config.rv770.sx_num_of_sets = 7;
1217 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
1218 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1219 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1220 break;
1221 case CHIP_RV730:
1222 rdev->config.rv770.max_pipes = 2;
1223 rdev->config.rv770.max_tile_pipes = 4;
1224 rdev->config.rv770.max_simds = 8;
1225 rdev->config.rv770.max_backends = 2;
1226 rdev->config.rv770.max_gprs = 128;
1227 rdev->config.rv770.max_threads = 248;
1228 rdev->config.rv770.max_stack_entries = 256;
1229 rdev->config.rv770.max_hw_contexts = 8;
1230 rdev->config.rv770.max_gs_threads = 16 * 2;
1231 rdev->config.rv770.sx_max_export_size = 256;
1232 rdev->config.rv770.sx_max_export_pos_size = 32;
1233 rdev->config.rv770.sx_max_export_smx_size = 224;
1234 rdev->config.rv770.sq_num_cf_insts = 2;
1235
1236 rdev->config.rv770.sx_num_of_sets = 7;
1237 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
1238 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1239 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1240 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
1241 rdev->config.rv770.sx_max_export_pos_size -= 16;
1242 rdev->config.rv770.sx_max_export_smx_size += 16;
1243 }
1244 break;
1245 case CHIP_RV710:
1246 rdev->config.rv770.max_pipes = 2;
1247 rdev->config.rv770.max_tile_pipes = 2;
1248 rdev->config.rv770.max_simds = 2;
1249 rdev->config.rv770.max_backends = 1;
1250 rdev->config.rv770.max_gprs = 256;
1251 rdev->config.rv770.max_threads = 192;
1252 rdev->config.rv770.max_stack_entries = 256;
1253 rdev->config.rv770.max_hw_contexts = 4;
1254 rdev->config.rv770.max_gs_threads = 8 * 2;
1255 rdev->config.rv770.sx_max_export_size = 128;
1256 rdev->config.rv770.sx_max_export_pos_size = 16;
1257 rdev->config.rv770.sx_max_export_smx_size = 112;
1258 rdev->config.rv770.sq_num_cf_insts = 1;
1259
1260 rdev->config.rv770.sx_num_of_sets = 7;
1261 rdev->config.rv770.sc_prim_fifo_size = 0x40;
1262 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1263 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1264 break;
1265 case CHIP_RV740:
1266 rdev->config.rv770.max_pipes = 4;
1267 rdev->config.rv770.max_tile_pipes = 4;
1268 rdev->config.rv770.max_simds = 8;
1269 rdev->config.rv770.max_backends = 4;
1270 rdev->config.rv770.max_gprs = 256;
1271 rdev->config.rv770.max_threads = 248;
1272 rdev->config.rv770.max_stack_entries = 512;
1273 rdev->config.rv770.max_hw_contexts = 8;
1274 rdev->config.rv770.max_gs_threads = 16 * 2;
1275 rdev->config.rv770.sx_max_export_size = 256;
1276 rdev->config.rv770.sx_max_export_pos_size = 32;
1277 rdev->config.rv770.sx_max_export_smx_size = 224;
1278 rdev->config.rv770.sq_num_cf_insts = 2;
1279
1280 rdev->config.rv770.sx_num_of_sets = 7;
1281 rdev->config.rv770.sc_prim_fifo_size = 0x100;
1282 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1283 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1284
1285 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
1286 rdev->config.rv770.sx_max_export_pos_size -= 16;
1287 rdev->config.rv770.sx_max_export_smx_size += 16;
1288 }
1289 break;
1290 default:
1291 break;
1292 }
1293
1294 /* Initialize HDP */
1295 j = 0;
1296 for (i = 0; i < 32; i++) {
1297 WREG32((0x2c14 + j), 0x00000000);
1298 WREG32((0x2c18 + j), 0x00000000);
1299 WREG32((0x2c1c + j), 0x00000000);
1300 WREG32((0x2c20 + j), 0x00000000);
1301 WREG32((0x2c24 + j), 0x00000000);
1302 j += 0x18;
1303 }
1304
1305 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1306
1307 /* setup tiling, simd, pipe config */
1308 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1309
1310 shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
1311 inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
1312 for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) {
1313 if (!(inactive_pipes & tmp)) {
1314 active_number++;
1315 }
1316 tmp <<= 1;
1317 }
1318 if (active_number == 1) {
1319 WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1);
1320 } else {
1321 WREG32(SPI_CONFIG_CNTL, 0);
1322 }
1323
1324 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1325 tmp = rdev->config.rv770.max_simds -
1326 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK);
1327 rdev->config.rv770.active_simds = tmp;
1328
1329 switch (rdev->config.rv770.max_tile_pipes) {
1330 case 1:
1331 default:
1332 gb_tiling_config = PIPE_TILING(0);
1333 break;
1334 case 2:
1335 gb_tiling_config = PIPE_TILING(1);
1336 break;
1337 case 4:
1338 gb_tiling_config = PIPE_TILING(2);
1339 break;
1340 case 8:
1341 gb_tiling_config = PIPE_TILING(3);
1342 break;
1343 }
1344 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
1345
1346 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK;
1347 tmp = 0;
1348 for (i = 0; i < rdev->config.rv770.max_backends; i++)
1349 tmp |= (1 << i);
1350 /* if all the backends are disabled, fix it up here */
1351 if ((disabled_rb_mask & tmp) == tmp) {
1352 for (i = 0; i < rdev->config.rv770.max_backends; i++)
1353 disabled_rb_mask &= ~(1 << i);
1354 }
1355 tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1356 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,
1357 R7XX_MAX_BACKENDS, disabled_rb_mask);
1358 gb_tiling_config |= tmp << 16;
1359 rdev->config.rv770.backend_map = tmp;
1360
1361 if (rdev->family == CHIP_RV770)
1362 gb_tiling_config |= BANK_TILING(1);
1363 else {
1364 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
1365 gb_tiling_config |= BANK_TILING(1);
1366 else
1367 gb_tiling_config |= BANK_TILING(0);
1368 }
1369 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
1370 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1371 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
1372 gb_tiling_config |= ROW_TILING(3);
1373 gb_tiling_config |= SAMPLE_SPLIT(3);
1374 } else {
1375 gb_tiling_config |=
1376 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
1377 gb_tiling_config |=
1378 SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
1379 }
1380
1381 gb_tiling_config |= BANK_SWAPS(1);
1382 rdev->config.rv770.tile_config = gb_tiling_config;
1383
1384 WREG32(GB_TILING_CONFIG, gb_tiling_config);
1385 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1386 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1387 WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));
1388 WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));
1389 if (rdev->family == CHIP_RV730) {
1390 WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff));
1391 WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff));
1392 WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff));
1393 }
1394
1395 WREG32(CGTS_SYS_TCC_DISABLE, 0);
1396 WREG32(CGTS_TCC_DISABLE, 0);
1397 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1398 WREG32(CGTS_USER_TCC_DISABLE, 0);
1399
1400
1401 num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1402 WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
1403 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1404
1405 /* set HW defaults for 3D engine */
1406 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1407 ROQ_IB2_START(0x2b)));
1408
1409 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1410
1411 ta_aux_cntl = RREG32(TA_CNTL_AUX);
1412 WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
1413
1414 sx_debug_1 = RREG32(SX_DEBUG_1);
1415 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1416 WREG32(SX_DEBUG_1, sx_debug_1);
1417
1418 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1419 smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
1420 smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
1421 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1422
1423 if (rdev->family != CHIP_RV740)
1424 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
1425 GS_FLUSH_CTL(4) |
1426 ACK_FLUSH_CTL(3) |
1427 SYNC_FLUSH_CTL));
1428
1429 if (rdev->family != CHIP_RV770)
1430 WREG32(SMX_SAR_CTL0, 0x00003f3f);
1431
1432 db_debug3 = RREG32(DB_DEBUG3);
1433 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
1434 switch (rdev->family) {
1435 case CHIP_RV770:
1436 case CHIP_RV740:
1437 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
1438 break;
1439 case CHIP_RV710:
1440 case CHIP_RV730:
1441 default:
1442 db_debug3 |= DB_CLK_OFF_DELAY(2);
1443 break;
1444 }
1445 WREG32(DB_DEBUG3, db_debug3);
1446
1447 if (rdev->family != CHIP_RV770) {
1448 db_debug4 = RREG32(DB_DEBUG4);
1449 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
1450 WREG32(DB_DEBUG4, db_debug4);
1451 }
1452
1453 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
1454 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
1455 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
1456
1457 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
1458 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
1459 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
1460
1461 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1462
1463 WREG32(VGT_NUM_INSTANCES, 1);
1464
1465 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1466
1467 WREG32(CP_PERFMON_CNTL, 0);
1468
1469 sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
1470 DONE_FIFO_HIWATER(0xe0) |
1471 ALU_UPDATE_FIFO_HIWATER(0x8));
1472 switch (rdev->family) {
1473 case CHIP_RV770:
1474 case CHIP_RV730:
1475 case CHIP_RV710:
1476 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
1477 break;
1478 case CHIP_RV740:
1479 default:
1480 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
1481 break;
1482 }
1483 WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1484
1485 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1486 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1487 */
1488 sq_config = RREG32(SQ_CONFIG);
1489 sq_config &= ~(PS_PRIO(3) |
1490 VS_PRIO(3) |
1491 GS_PRIO(3) |
1492 ES_PRIO(3));
1493 sq_config |= (DX9_CONSTS |
1494 VC_ENABLE |
1495 EXPORT_SRC_C |
1496 PS_PRIO(0) |
1497 VS_PRIO(1) |
1498 GS_PRIO(2) |
1499 ES_PRIO(3));
1500 if (rdev->family == CHIP_RV710)
1501 /* no vertex cache */
1502 sq_config &= ~VC_ENABLE;
1503
1504 WREG32(SQ_CONFIG, sq_config);
1505
1506 WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
1507 NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
1508 NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
1509
1510 WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
1511 NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
1512
1513 sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
1514 NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
1515 NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
1516 if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
1517 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
1518 else
1519 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
1520 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1521
1522 WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
1523 NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
1524
1525 WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
1526 NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
1527
1528 sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
1529 SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
1530 SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
1531 SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
1532
1533 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1534 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1535 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1536 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1537 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1538 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1539 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1540 WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1541
1542 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1543 FORCE_EOV_MAX_REZ_CNT(255)));
1544
1545 if (rdev->family == CHIP_RV710)
1546 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
1547 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
1548 else
1549 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
1550 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
1551
1552 switch (rdev->family) {
1553 case CHIP_RV770:
1554 case CHIP_RV730:
1555 case CHIP_RV740:
1556 gs_prim_buffer_depth = 384;
1557 break;
1558 case CHIP_RV710:
1559 gs_prim_buffer_depth = 128;
1560 break;
1561 default:
1562 break;
1563 }
1564
1565 num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
1566 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1567 /* Max value for this is 256 */
1568 if (vgt_gs_per_es > 256)
1569 vgt_gs_per_es = 256;
1570
1571 WREG32(VGT_ES_PER_GS, 128);
1572 WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
1573 WREG32(VGT_GS_PER_VS, 2);
1574
1575 /* more default values. 2D/3D driver should adjust as needed */
1576 WREG32(VGT_GS_VERTEX_REUSE, 16);
1577 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1578 WREG32(VGT_STRMOUT_EN, 0);
1579 WREG32(SX_MISC, 0);
1580 WREG32(PA_SC_MODE_CNTL, 0);
1581 WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
1582 WREG32(PA_SC_AA_CONFIG, 0);
1583 WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
1584 WREG32(PA_SC_LINE_STIPPLE, 0);
1585 WREG32(SPI_INPUT_Z, 0);
1586 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1587 WREG32(CB_COLOR7_FRAG, 0);
1588
1589 /* clear render buffer base addresses */
1590 WREG32(CB_COLOR0_BASE, 0);
1591 WREG32(CB_COLOR1_BASE, 0);
1592 WREG32(CB_COLOR2_BASE, 0);
1593 WREG32(CB_COLOR3_BASE, 0);
1594 WREG32(CB_COLOR4_BASE, 0);
1595 WREG32(CB_COLOR5_BASE, 0);
1596 WREG32(CB_COLOR6_BASE, 0);
1597 WREG32(CB_COLOR7_BASE, 0);
1598
1599 WREG32(TCP_CNTL, 0);
1600
1601 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1602 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1603
1604 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1605
1606 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1607 NUM_CLIP_SEQ(3)));
1608 WREG32(VC_ENHANCE, 0);
1609 }
1610
r700_vram_gtt_location(struct radeon_device * rdev,struct radeon_mc * mc)1611 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1612 {
1613 u64 size_bf, size_af;
1614
1615 if (mc->mc_vram_size > 0xE0000000) {
1616 /* leave room for at least 512M GTT */
1617 dev_warn(rdev->dev, "limiting VRAM\n");
1618 mc->real_vram_size = 0xE0000000;
1619 mc->mc_vram_size = 0xE0000000;
1620 }
1621 if (rdev->flags & RADEON_IS_AGP) {
1622 size_bf = mc->gtt_start;
1623 size_af = mc->mc_mask - mc->gtt_end;
1624 if (size_bf > size_af) {
1625 if (mc->mc_vram_size > size_bf) {
1626 dev_warn(rdev->dev, "limiting VRAM\n");
1627 mc->real_vram_size = size_bf;
1628 mc->mc_vram_size = size_bf;
1629 }
1630 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1631 } else {
1632 if (mc->mc_vram_size > size_af) {
1633 dev_warn(rdev->dev, "limiting VRAM\n");
1634 mc->real_vram_size = size_af;
1635 mc->mc_vram_size = size_af;
1636 }
1637 mc->vram_start = mc->gtt_end + 1;
1638 }
1639 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1640 dev_info(rdev->dev, "VRAM: %"PRIu64"M 0x%08"PRIX64" - 0x%08"PRIX64" (%"PRIu64"M used)\n",
1641 mc->mc_vram_size >> 20, mc->vram_start,
1642 mc->vram_end, mc->real_vram_size >> 20);
1643 } else {
1644 radeon_vram_location(rdev, &rdev->mc, 0);
1645 rdev->mc.gtt_base_align = 0;
1646 radeon_gtt_location(rdev, mc);
1647 }
1648 }
1649
rv770_mc_init(struct radeon_device * rdev)1650 static int rv770_mc_init(struct radeon_device *rdev)
1651 {
1652 u32 tmp;
1653 int chansize, numchan;
1654
1655 /* Get VRAM informations */
1656 rdev->mc.vram_is_ddr = true;
1657 tmp = RREG32(MC_ARB_RAMCFG);
1658 if (tmp & CHANSIZE_OVERRIDE) {
1659 chansize = 16;
1660 } else if (tmp & CHANSIZE_MASK) {
1661 chansize = 64;
1662 } else {
1663 chansize = 32;
1664 }
1665 tmp = RREG32(MC_SHARED_CHMAP);
1666 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1667 case 0:
1668 default:
1669 numchan = 1;
1670 break;
1671 case 1:
1672 numchan = 2;
1673 break;
1674 case 2:
1675 numchan = 4;
1676 break;
1677 case 3:
1678 numchan = 8;
1679 break;
1680 }
1681 rdev->mc.vram_width = numchan * chansize;
1682 /* Could aper size report 0 ? */
1683 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1684 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1685 /* Setup GPU memory space */
1686 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1687 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1688 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1689 r700_vram_gtt_location(rdev, &rdev->mc);
1690 radeon_update_bandwidth_info(rdev);
1691
1692 return 0;
1693 }
1694
rv770_uvd_init(struct radeon_device * rdev)1695 static void rv770_uvd_init(struct radeon_device *rdev)
1696 {
1697 int r;
1698
1699 if (!rdev->has_uvd)
1700 return;
1701
1702 r = radeon_uvd_init(rdev);
1703 if (r) {
1704 dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
1705 /*
1706 * At this point rdev->uvd.vcpu_bo is NULL which trickles down
1707 * to early fails uvd_v2_2_resume() and thus nothing happens
1708 * there. So it is pointless to try to go through that code
1709 * hence why we disable uvd here.
1710 */
1711 rdev->has_uvd = false;
1712 return;
1713 }
1714 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
1715 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
1716 }
1717
rv770_uvd_start(struct radeon_device * rdev)1718 static void rv770_uvd_start(struct radeon_device *rdev)
1719 {
1720 int r;
1721
1722 if (!rdev->has_uvd)
1723 return;
1724
1725 r = uvd_v2_2_resume(rdev);
1726 if (r) {
1727 dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
1728 goto error;
1729 }
1730 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
1731 if (r) {
1732 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
1733 goto error;
1734 }
1735 return;
1736
1737 error:
1738 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
1739 }
1740
rv770_uvd_resume(struct radeon_device * rdev)1741 static void rv770_uvd_resume(struct radeon_device *rdev)
1742 {
1743 struct radeon_ring *ring;
1744 int r;
1745
1746 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
1747 return;
1748
1749 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
1750 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
1751 if (r) {
1752 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
1753 return;
1754 }
1755 r = uvd_v1_0_init(rdev);
1756 if (r) {
1757 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
1758 return;
1759 }
1760 }
1761
rv770_startup(struct radeon_device * rdev)1762 static int rv770_startup(struct radeon_device *rdev)
1763 {
1764 struct radeon_ring *ring;
1765 int r;
1766
1767 /* enable pcie gen2 link */
1768 rv770_pcie_gen2_enable(rdev);
1769
1770 /* scratch needs to be initialized before MC */
1771 r = r600_vram_scratch_init(rdev);
1772 if (r)
1773 return r;
1774
1775 rv770_mc_program(rdev);
1776
1777 if (rdev->flags & RADEON_IS_AGP) {
1778 rv770_agp_enable(rdev);
1779 } else {
1780 r = rv770_pcie_gart_enable(rdev);
1781 if (r)
1782 return r;
1783 }
1784
1785 rv770_gpu_init(rdev);
1786
1787 /* allocate wb buffer */
1788 r = radeon_wb_init(rdev);
1789 if (r)
1790 return r;
1791
1792 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1793 if (r) {
1794 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1795 return r;
1796 }
1797
1798 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
1799 if (r) {
1800 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1801 return r;
1802 }
1803
1804 rv770_uvd_start(rdev);
1805
1806 /* Enable IRQ */
1807 if (!rdev->irq.installed) {
1808 r = radeon_irq_kms_init(rdev);
1809 if (r)
1810 return r;
1811 }
1812
1813 r = r600_irq_init(rdev);
1814 if (r) {
1815 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1816 radeon_irq_kms_fini(rdev);
1817 return r;
1818 }
1819 r600_irq_set(rdev);
1820
1821 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1822 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1823 RADEON_CP_PACKET2);
1824 if (r)
1825 return r;
1826
1827 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1828 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
1829 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1830 if (r)
1831 return r;
1832
1833 r = rv770_cp_load_microcode(rdev);
1834 if (r)
1835 return r;
1836 r = r600_cp_resume(rdev);
1837 if (r)
1838 return r;
1839
1840 r = r600_dma_resume(rdev);
1841 if (r)
1842 return r;
1843
1844 rv770_uvd_resume(rdev);
1845
1846 r = radeon_ib_pool_init(rdev);
1847 if (r) {
1848 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1849 return r;
1850 }
1851
1852 r = radeon_audio_init(rdev);
1853 if (r) {
1854 DRM_ERROR("radeon: audio init failed\n");
1855 return r;
1856 }
1857
1858 return 0;
1859 }
1860
rv770_resume(struct radeon_device * rdev)1861 int rv770_resume(struct radeon_device *rdev)
1862 {
1863 int r;
1864
1865 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1866 * posting will perform necessary task to bring back GPU into good
1867 * shape.
1868 */
1869 /* post card */
1870 atom_asic_init(rdev->mode_info.atom_context);
1871
1872 /* init golden registers */
1873 rv770_init_golden_registers(rdev);
1874
1875 if (rdev->pm.pm_method == PM_METHOD_DPM)
1876 radeon_pm_resume(rdev);
1877
1878 rdev->accel_working = true;
1879 r = rv770_startup(rdev);
1880 if (r) {
1881 DRM_ERROR("r600 startup failed on resume\n");
1882 rdev->accel_working = false;
1883 return r;
1884 }
1885
1886 return r;
1887
1888 }
1889
rv770_suspend(struct radeon_device * rdev)1890 int rv770_suspend(struct radeon_device *rdev)
1891 {
1892 radeon_pm_suspend(rdev);
1893 radeon_audio_fini(rdev);
1894 if (rdev->has_uvd) {
1895 uvd_v1_0_fini(rdev);
1896 radeon_uvd_suspend(rdev);
1897 }
1898 r700_cp_stop(rdev);
1899 r600_dma_stop(rdev);
1900 r600_irq_suspend(rdev);
1901 radeon_wb_disable(rdev);
1902 rv770_pcie_gart_disable(rdev);
1903
1904 return 0;
1905 }
1906
1907 /* Plan is to move initialization in that function and use
1908 * helper function so that radeon_device_init pretty much
1909 * do nothing more than calling asic specific function. This
1910 * should also allow to remove a bunch of callback function
1911 * like vram_info.
1912 */
rv770_init(struct radeon_device * rdev)1913 int rv770_init(struct radeon_device *rdev)
1914 {
1915 int r;
1916
1917 /* Read BIOS */
1918 if (!radeon_get_bios(rdev)) {
1919 if (ASIC_IS_AVIVO(rdev))
1920 return -EINVAL;
1921 }
1922 /* Must be an ATOMBIOS */
1923 if (!rdev->is_atom_bios) {
1924 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1925 return -EINVAL;
1926 }
1927 r = radeon_atombios_init(rdev);
1928 if (r)
1929 return r;
1930 /* Post card if necessary */
1931 if (!radeon_card_posted(rdev)) {
1932 if (!rdev->bios) {
1933 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1934 return -EINVAL;
1935 }
1936 DRM_INFO("GPU not posted. posting now...\n");
1937 atom_asic_init(rdev->mode_info.atom_context);
1938 }
1939 /* init golden registers */
1940 rv770_init_golden_registers(rdev);
1941 /* Initialize scratch registers */
1942 r600_scratch_init(rdev);
1943 /* Initialize surface registers */
1944 radeon_surface_init(rdev);
1945 /* Initialize clocks */
1946 radeon_get_clock_info(rdev->ddev);
1947 /* Fence driver */
1948 r = radeon_fence_driver_init(rdev);
1949 if (r)
1950 return r;
1951 /* initialize AGP */
1952 if (rdev->flags & RADEON_IS_AGP) {
1953 r = radeon_agp_init(rdev);
1954 if (r)
1955 radeon_agp_disable(rdev);
1956 }
1957 r = rv770_mc_init(rdev);
1958 if (r)
1959 return r;
1960 /* Memory manager */
1961 r = radeon_bo_init(rdev);
1962 if (r)
1963 return r;
1964
1965 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1966 r = r600_init_microcode(rdev);
1967 if (r) {
1968 DRM_ERROR("Failed to load firmware!\n");
1969 return r;
1970 }
1971 }
1972
1973 /* Initialize power management */
1974 radeon_pm_init(rdev);
1975
1976 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
1977 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
1978
1979 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
1980 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
1981
1982 rv770_uvd_init(rdev);
1983
1984 rdev->ih.ring_obj = NULL;
1985 r600_ih_ring_init(rdev, 64 * 1024);
1986
1987 r = r600_pcie_gart_init(rdev);
1988 if (r)
1989 return r;
1990
1991 rdev->accel_working = true;
1992 r = rv770_startup(rdev);
1993 if (r) {
1994 dev_err(rdev->dev, "disabling GPU acceleration\n");
1995 r700_cp_fini(rdev);
1996 r600_dma_fini(rdev);
1997 r600_irq_fini(rdev);
1998 radeon_wb_fini(rdev);
1999 radeon_ib_pool_fini(rdev);
2000 radeon_irq_kms_fini(rdev);
2001 rv770_pcie_gart_fini(rdev);
2002 rdev->accel_working = false;
2003 }
2004
2005 return 0;
2006 }
2007
rv770_fini(struct radeon_device * rdev)2008 void rv770_fini(struct radeon_device *rdev)
2009 {
2010 radeon_pm_fini(rdev);
2011 r700_cp_fini(rdev);
2012 r600_dma_fini(rdev);
2013 r600_irq_fini(rdev);
2014 radeon_wb_fini(rdev);
2015 radeon_ib_pool_fini(rdev);
2016 radeon_irq_kms_fini(rdev);
2017 uvd_v1_0_fini(rdev);
2018 radeon_uvd_fini(rdev);
2019 rv770_pcie_gart_fini(rdev);
2020 r600_vram_scratch_fini(rdev);
2021 radeon_gem_fini(rdev);
2022 radeon_fence_driver_fini(rdev);
2023 radeon_agp_fini(rdev);
2024 radeon_bo_fini(rdev);
2025 radeon_atombios_fini(rdev);
2026 kfree(rdev->bios);
2027 rdev->bios = NULL;
2028 }
2029
rv770_pcie_gen2_enable(struct radeon_device * rdev)2030 static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
2031 {
2032 #ifndef __NetBSD__ /* XXX radeon pcie */
2033 u32 link_width_cntl, lanes, speed_cntl, tmp;
2034 u16 link_cntl2;
2035
2036 if (radeon_pcie_gen2 == 0)
2037 return;
2038
2039 if (rdev->flags & RADEON_IS_IGP)
2040 return;
2041
2042 if (!(rdev->flags & RADEON_IS_PCIE))
2043 return;
2044
2045 /* x2 cards have a special sequence */
2046 if (ASIC_IS_X2(rdev))
2047 return;
2048
2049 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
2050 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
2051 return;
2052
2053 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
2054
2055 /* advertise upconfig capability */
2056 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
2057 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
2058 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2059 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
2060 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
2061 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
2062 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
2063 LC_RECONFIG_ARC_MISSING_ESCAPE);
2064 link_width_cntl |= lanes | LC_RECONFIG_NOW |
2065 LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
2066 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2067 } else {
2068 link_width_cntl |= LC_UPCONFIGURE_DIS;
2069 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2070 }
2071
2072 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2073 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
2074 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
2075
2076 tmp = RREG32(0x541c);
2077 WREG32(0x541c, tmp | 0x8);
2078 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
2079 link_cntl2 = RREG16(0x4088);
2080 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
2081 link_cntl2 |= 0x2;
2082 WREG16(0x4088, link_cntl2);
2083 WREG32(MM_CFGREGS_CNTL, 0);
2084
2085 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2086 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
2087 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2088
2089 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2090 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
2091 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2092
2093 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2094 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
2095 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2096
2097 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2098 speed_cntl |= LC_GEN2_EN_STRAP;
2099 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2100
2101 } else {
2102 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
2103 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
2104 if (1)
2105 link_width_cntl |= LC_UPCONFIGURE_DIS;
2106 else
2107 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
2108 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2109 }
2110 #endif
2111 }
2112