xref: /dragonfly/sys/dev/netif/mn/if_mn.c (revision b272101a)
1 /*
2  * ----------------------------------------------------------------------------
3  * "THE BEER-WARE LICENSE" (Revision 42):
4  * <phk@FreeBSD.org> wrote this file.  As long as you retain this notice you
5  * can do whatever you want with this stuff. If we meet some day, and you think
6  * this stuff is worth it, you can buy me a beer in return.   Poul-Henning Kamp
7  * ----------------------------------------------------------------------------
8  *
9  * $Id: if_mn.c,v 1.1 1999/02/01 13:06:40 phk Exp $
10  *
11  * Driver for Siemens reference design card "Easy321-R1".
12  *
13  * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC
14  * controller.
15  *
16  * The driver supports E1 mode with up to 31 channels.  We send CRC4 but don't
17  * check it coming in.
18  *
19  * The FALC54 and MUNICH32X have far too many registers and weird modes for
20  * comfort, so I have not bothered typing it all into a "fooreg.h" file,
21  * you will (badly!) need the documentation anyway if you want to mess with
22  * this gadget.
23  *
24  * $FreeBSD: src/sys/pci/if_mn.c,v 1.11.2.3 2001/01/23 12:47:09 phk Exp $
25  */
26 
27 /*
28  * Stuff to describe the MUNIC32X and FALC54 chips.
29  */
30 
31 #define M32_CHAN	32	/* We have 32 channels */
32 #define M32_TS		32	/* We have 32 timeslots */
33 
34 #define NG_MN_NODE_TYPE	"mn"
35 
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/sysctl.h>
40 #include <sys/bus.h>
41 #include <sys/mbuf.h>
42 #include <sys/malloc.h>
43 #include <sys/rman.h>
44 
45 #include <bus/pci/pcireg.h>
46 #include <bus/pci/pcivar.h>
47 #include "pci_if.h"
48 
49 #include <machine/clock.h>
50 
51 #include <vm/vm.h>
52 #include <vm/pmap.h>
53 
54 #include <netgraph/ng_message.h>
55 #include <netgraph/netgraph.h>
56 
57 
58 static int mn_maxlatency = 1000;
59 SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW,
60     &mn_maxlatency, 0,
61 	"The number of milliseconds a packet is allowed to spend in the output queue.  "
62 	"If the output queue is longer than this number of milliseconds when the packet "
63 	"arrives for output, the packet will be dropped."
64 );
65 
66 #ifndef NMN
67 /* Most machines don't support more than 4 busmaster PCI slots, if even that many */
68 #define NMN	4
69 #endif
70 
71 /* From: PEB 20321 data sheet, p187, table 22 */
72 struct m32xreg {
73 	u_int32_t conf,    cmd,     stat,    imask;
74 	u_int32_t fill10,  piqba,   piql,    fill1c;
75 	u_int32_t mode1,   mode2,   ccba,    txpoll;
76 	u_int32_t tiqba,   tiql,    riqba,   riql;
77 	u_int32_t lconf,   lccba,   fill48,  ltran;
78 	u_int32_t ltiqba,  ltiql,   lriqba,  lriql;
79 	u_int32_t lreg0,   lreg1,   lreg2,   lreg3;
80 	u_int32_t lreg4,   lreg5,   lre6,    lstat;
81 	u_int32_t gpdir,   gpdata,  gpod,    fill8c;
82 	u_int32_t ssccon,  sscbr,   ssctb,   sscrb;
83 	u_int32_t ssccse,  sscim,   fillab,  fillac;
84 	u_int32_t iomcon1, iomcon2, iomstat, fillbc;
85 	u_int32_t iomcit0, iomcit1, iomcir0, iomcir1;
86 	u_int32_t iomtmo,  iomrmo,  filld8,  filldc;
87 	u_int32_t mbcmd,   mbdata1, mbdata2, mbdata3;
88 	u_int32_t mbdata4, mbdata5, mbdata6, mbdata7;
89 };
90 
91 /* From: PEB 2254 data sheet, p80, table 10 */
92 struct f54wreg {
93 	u_int16_t xfifo;
94 	u_int8_t                  cmdr,   mode,   rah1,   rah2,   ral1,   ral2;
95 	u_int8_t  ipc,    ccr1,   ccr3,   pre,    rtr1,   rtr2,   rtr3,   rtr4;
96 	u_int8_t  ttr1,   ttr2,   ttr3,   ttr4,   imr0,   imr1,   imr2,   imr3;
97 	u_int8_t  imr4,   fill19, fmr0,   fmr1,   fmr2,   loop,   xsw,    xsp;
98 	u_int8_t  xc0,    xc1,    rc0,    rc1,    xpm0,   xpm1,   xpm2,   tswm;
99 	u_int8_t  test1,  idle,   xsa4,   xsa5,   xsa6,   xsa7,   xsa8,   fmr3;
100 	u_int8_t  icb1,   icb2,   icb3,   icb4,   lim0,   lim1,   pcd,    pcr;
101 	u_int8_t  lim2,   fill39[7];
102 	u_int8_t  fill40[8];
103 	u_int8_t  fill48[8];
104 	u_int8_t  fill50[8];
105 	u_int8_t  fill58[8];
106 	u_int8_t  dec,    fill61, test2,  fill63[5];
107 	u_int8_t  fill68[8];
108 	u_int8_t  xs[16];
109 };
110 
111 /* From: PEB 2254 data sheet, p117, table 10 */
112 struct f54rreg {
113 	u_int16_t rfifo;
114 	u_int8_t                  fill2,  mode,   rah1,   rah2,   ral1,   ral2;
115 	u_int8_t  ipc,    ccr1,   ccr3,   pre,    rtr1,   rtr2,   rtr3,   rtr4;
116 	u_int8_t  ttr1,   ttr2,   ttr3,   ttr4,   imr0,   imr1,   imr2,   imr3;
117 	u_int8_t  imr4,   fill19, fmr0,   fmr1,   fmr2,   loop,   xsw,    xsp;
118 	u_int8_t  xc0,    xc1,    rc0,    rc1,    xpm0,   xpm1,   xpm2,   tswm;
119 	u_int8_t  test,   idle,   xsa4,   xsa5,   xsa6,   xsa7,   xsa8,   fmr13;
120 	u_int8_t  icb1,   icb2,   icb3,   icb4,   lim0,   lim1,   pcd,    pcr;
121 	u_int8_t  lim2,   fill39[7];
122 	u_int8_t  fill40[8];
123 	u_int8_t  fill48[4],                      frs0,   frs1,   rsw,    rsp;
124 	u_int16_t fec,            cvc,            cec1,           ebc;
125 	u_int16_t cec2,           cec3;
126 	u_int8_t                                  rsa4,   rsa5,   rsa6,   rsa7;
127 	u_int8_t  rsa8,   rsa6s,  tsr0,   tsr1,   sis,    rsis;
128 	u_int16_t                                                 rbc;
129 	u_int8_t  isr0,   isr1,   isr2,   isr3,   fill6c, fill6d, gis,    vstr;
130 	u_int8_t  rs[16];
131 };
132 
133 /* Transmit & receive descriptors */
134 struct trxd {
135 	u_int32_t	flags;
136 	vm_offset_t	next;
137 	vm_offset_t	data;
138 	u_int32_t	status;	/* only used for receive */
139 	struct mbuf	*m;	/* software use only */
140 	struct trxd	*vnext;	/* software use only */
141 };
142 
143 /* Channel specification */
144 struct cspec {
145 	u_int32_t	flags;
146 	vm_offset_t	rdesc;
147 	vm_offset_t	tdesc;
148 	u_int32_t	itbs;
149 };
150 
151 struct m32_mem {
152 	vm_offset_t	csa;
153 	u_int32_t	ccb;
154 	u_int32_t	reserve1[2];
155 	u_int32_t	ts[M32_TS];
156 	struct cspec	cs[M32_CHAN];
157 	vm_offset_t	crxd[M32_CHAN];
158 	vm_offset_t	ctxd[M32_CHAN];
159 };
160 
161 struct softc;
162 struct sockaddr;
163 struct rtentry;
164 
165 static	int	mn_probe  (device_t self);
166 static	int	mn_attach (device_t self);
167 static	void	mn_create_channel(struct softc *sc, int chan);
168 static	int	mn_reset(struct softc *sc);
169 static	struct trxd * mn_alloc_desc(void);
170 static	void	mn_free_desc(struct trxd *dp);
171 static	void	mn_intr(void *xsc);
172 static	u_int32_t mn_parse_ts(const char *s, int *nbit);
173 #ifdef notyet
174 static	void	m32_dump(struct softc *sc);
175 static	void	f54_dump(struct softc *sc);
176 static	void	mn_fmt_ts(char *p, u_int32_t ts);
177 #endif /* notyet */
178 static	void	f54_init(struct softc *sc);
179 
180 static	ng_constructor_t ngmn_constructor;
181 static	ng_rcvmsg_t ngmn_rcvmsg;
182 static	ng_shutdown_t ngmn_shutdown;
183 static	ng_newhook_t ngmn_newhook;
184 static	ng_connect_t ngmn_connect;
185 static	ng_rcvdata_t ngmn_rcvdata;
186 static	ng_disconnect_t ngmn_disconnect;
187 
188 static struct ng_type mntypestruct = {
189 	NG_VERSION,
190 	NG_MN_NODE_TYPE,
191 	NULL,
192 	ngmn_constructor,
193 	ngmn_rcvmsg,
194 	ngmn_shutdown,
195 	ngmn_newhook,
196 	NULL,
197 	ngmn_connect,
198 	ngmn_rcvdata,
199 	ngmn_rcvdata,
200 	ngmn_disconnect,
201 	NULL
202 };
203 
204 static MALLOC_DEFINE(M_MN, "mn", "Mx driver related");
205 
206 #define NIQB	64
207 
208 struct schan {
209 	enum {DOWN, UP} state;
210 	struct softc	*sc;
211 	int		chan;
212 	u_int32_t	ts;
213 	char		name[8];
214 	struct trxd	*r1, *rl;
215 	struct trxd	*x1, *xl;
216 	hook_p		hook;
217 
218 	time_t		last_recv;
219 	time_t		last_rxerr;
220 	time_t		last_xmit;
221 
222 	u_long		rx_error;
223 
224 	u_long		short_error;
225 	u_long		crc_error;
226 	u_long		dribble_error;
227 	u_long		long_error;
228 	u_long		abort_error;
229 	u_long		overflow_error;
230 
231 	int		last_error;
232 	int		prev_error;
233 
234 	u_long		tx_pending;
235 	u_long		tx_limit;
236 };
237 
238 enum framing {WHOKNOWS, E1, E1U, T1, T1U};
239 
240 struct softc {
241 	int	unit;
242 	device_t	dev;
243 	struct resource *irq;
244 	void *intrhand;
245 	enum framing	framing;
246 	int 		nhooks;
247 	void 		*m0v, *m1v;
248 	vm_offset_t	m0p, m1p;
249 	struct m32xreg	*m32x;
250 	struct f54wreg	*f54w;
251 	struct f54rreg	*f54r;
252 	struct m32_mem	m32_mem;
253 	u_int32_t	tiqb[NIQB];
254 	u_int32_t	riqb[NIQB];
255 	u_int32_t	piqb[NIQB];
256 	u_int32_t	ltiqb[NIQB];
257 	u_int32_t	lriqb[NIQB];
258 	char		name[8];
259 	u_int32_t	falc_irq, falc_state, framer_state;
260 	struct schan *ch[M32_CHAN];
261 	char	nodename[NG_NODESIZ];
262 	node_p	node;
263 
264 	u_long		cnt_fec;
265 	u_long		cnt_cvc;
266 	u_long		cnt_cec1;
267 	u_long		cnt_ebc;
268 	u_long		cnt_cec2;
269 	u_long		cnt_cec3;
270 	u_long		cnt_rbc;
271 };
272 
273 static int
ngmn_constructor(node_p * nodep)274 ngmn_constructor(node_p *nodep)
275 {
276 
277 	return (EINVAL);
278 }
279 
280 static int
ngmn_shutdown(node_p nodep)281 ngmn_shutdown(node_p nodep)
282 {
283 
284 	return (EINVAL);
285 }
286 
287 static void
ngmn_config(node_p node,char * set,char * ret)288 ngmn_config(node_p node, char *set, char *ret)
289 {
290 	struct softc *sc;
291 	enum framing wframing;
292 
293 	sc = node->private;
294 
295 	if (set != NULL) {
296 		if (!strncmp(set, "line ", 5)) {
297 			wframing = sc->framing;
298 			if (!strcmp(set, "line e1")) {
299 				wframing = E1;
300 			} else if (!strcmp(set, "line e1u")) {
301 				wframing = E1U;
302 			} else {
303 				strcat(ret, "ENOGROK\n");
304 				return;
305 			}
306 			if (wframing == sc->framing)
307 				return;
308 			if (sc->nhooks > 0) {
309 				ksprintf(ret, "Cannot change line when %d hooks open\n", sc->nhooks);
310 				return;
311 			}
312 			sc->framing = wframing;
313 #if 1
314 			f54_init(sc);
315 #else
316 			mn_reset(sc);
317 #endif
318 		} else {
319 			kprintf("%s CONFIG SET [%s]\n", sc->nodename, set);
320 			strcat(ret, "ENOGROK\n");
321 			return;
322 		}
323 	}
324 
325 }
326 
327 static int
ngmn_rcvmsg(node_p node,struct ng_mesg * msg,const char * retaddr,struct ng_mesg ** resp)328 ngmn_rcvmsg(node_p node, struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp)
329 {
330 	struct softc *sc;
331 	struct schan *sch;
332 	char *s, *r;
333 	int pos, i;
334 
335 	sc = node->private;
336 
337 	if (msg->header.typecookie != NGM_GENERIC_COOKIE) {
338 		if (resp != NULL)
339 			*resp = NULL;
340 		kfree(msg, M_NETGRAPH);
341 		return (EINVAL);
342 	}
343 
344 	if (msg->header.cmd != NGM_TEXT_CONFIG &&
345 	    msg->header.cmd != NGM_TEXT_STATUS) {
346 		if (resp != NULL)
347 			*resp = NULL;
348 		kfree(msg, M_NETGRAPH);
349 		return (EINVAL);
350 	}
351 
352 	NG_MKRESPONSE(*resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE,
353 	    M_INTWAIT);
354 	if (*resp == NULL) {
355 		kfree(msg, M_NETGRAPH);
356 		return (ENOMEM);
357 	}
358 
359 	if (msg->header.arglen)
360 		s = (char *)msg->data;
361 	else
362 		s = NULL;
363 	r = (char *)(*resp)->data;
364 	*r = '\0';
365 
366 	if (msg->header.cmd == NGM_TEXT_CONFIG) {
367 		ngmn_config(node, s, r);
368 		(*resp)->header.arglen = strlen(r) + 1;
369 		kfree(msg, M_NETGRAPH);
370 		return (0);
371 	}
372 
373 	pos = 0;
374 	pos += ksprintf(pos + r,"Framer status %pb%i;\n", "\20"
375 	    "\40LOS\37AIS\36LFA\35RRA"
376 	    "\34AUXP\33NMF\32LMFA\31frs0.0"
377 	    "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
378 	    "\24TS16LFA\23frs1.2\22XLS\21XLO"
379 	    "\20RS1\17rsw.6\16RRA\15RY0"
380 	    "\14RY1\13RY2\12RY3\11RY4"
381 	    "\10SI1\7SI2\6rsp.5\5rsp.4"
382 	    "\4rsp.3\3RSIF\2RS13\1RS15", sc->framer_state);
383 	pos += ksprintf(pos + r,"    Framing errors: %lu", sc->cnt_fec);
384 	pos += ksprintf(pos + r,"  Code Violations: %lu\n", sc->cnt_cvc);
385 
386 	pos += ksprintf(pos + r,"    Falc State %pb%i;\n", "\20"
387 	    "\40LOS\37AIS\36LFA\35RRA"
388 	    "\34AUXP\33NMF\32LMFA\31frs0.0"
389 	    "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
390 	    "\24TS16LFA\23frs1.2\22XLS\21XLO"
391 	    "\20RS1\17rsw.6\16RRA\15RY0"
392 	    "\14RY1\13RY2\12RY3\11RY4"
393 	    "\10SI1\7SI2\6rsp.5\5rsp.4"
394 	    "\4rsp.3\3RSIF\2RS13\1RS15", sc->falc_state);
395 	pos += ksprintf(pos + r, "    Falc IRQ %pb%i\n", "\20"
396 	    "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
397 	    "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
398 	    "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
399 	    "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP",
400 	    sc->falc_irq);
401 	for (i = 0; i < M32_CHAN; i++) {
402 		if (!sc->ch[i])
403 			continue;
404 		sch = sc->ch[i];
405 
406 		pos += ksprintf(r + pos, "  Chan %d <%s> ",
407 		    i, sch->hook->name);
408 
409 		pos += ksprintf(r + pos, "  Last Rx: ");
410 		if (sch->last_recv)
411 			pos += ksprintf(r + pos, "%lu s", time_uptime - sch->last_recv);
412 		else
413 			pos += ksprintf(r + pos, "never");
414 
415 		pos += ksprintf(r + pos, ", last RxErr: ");
416 		if (sch->last_rxerr)
417 			pos += ksprintf(r + pos, "%lu s", time_uptime - sch->last_rxerr);
418 		else
419 			pos += ksprintf(r + pos, "never");
420 
421 		pos += ksprintf(r + pos, ", last Tx: ");
422 		if (sch->last_xmit)
423 			pos += ksprintf(r + pos, "%lu s\n", time_uptime - sch->last_xmit);
424 		else
425 			pos += ksprintf(r + pos, "never\n");
426 
427 		pos += ksprintf(r + pos, "    RX error(s) %lu", sch->rx_error);
428 		pos += ksprintf(r + pos, " Short: %lu", sch->short_error);
429 		pos += ksprintf(r + pos, " CRC: %lu", sch->crc_error);
430 		pos += ksprintf(r + pos, " Mod8: %lu", sch->dribble_error);
431 		pos += ksprintf(r + pos, " Long: %lu", sch->long_error);
432 		pos += ksprintf(r + pos, " Abort: %lu", sch->abort_error);
433 		pos += ksprintf(r + pos, " Overflow: %lu\n", sch->overflow_error);
434 
435 		pos += ksprintf(r + pos, "    Last error: %pb%i  Prev error: %pb%i\n",
436 		    "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN", sch->last_error,
437 		    "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN", sch->prev_error);
438 		pos += ksprintf(r + pos, "    Xmit bytes pending %ld\n",
439 		    sch->tx_pending);
440 	}
441 	(*resp)->header.arglen = pos + 1;
442 	kfree(msg, M_NETGRAPH);
443 	return (0);
444 }
445 
446 static int
ngmn_newhook(node_p node,hook_p hook,const char * name)447 ngmn_newhook(node_p node, hook_p hook, const char *name)
448 {
449 	u_int32_t ts, chan;
450 	struct softc *sc;
451 	int nbit;
452 
453 	sc = node->private;
454 
455 	if (name[0] != 't' || name[1] != 's')
456 		return (EINVAL);
457 
458 	ts = mn_parse_ts(name + 2, &nbit);
459 	kprintf("%d bits %x\n", nbit, ts);
460 	if (sc->framing == E1 && (ts & 1))
461 		return (EINVAL);
462 	if (sc->framing == E1U && nbit != 32)
463 		return (EINVAL);
464 	if (ts == 0)
465 		return (EINVAL);
466 	if (sc->framing == E1)
467 		chan = ffs(ts) - 1;
468 	else
469 		chan = 1;
470 	if (!sc->ch[chan])
471 		mn_create_channel(sc, chan);
472 	else if (sc->ch[chan]->state == UP)
473 		return (EBUSY);
474 	sc->ch[chan]->ts = ts;
475 	sc->ch[chan]->hook = hook;
476 	sc->ch[chan]->tx_limit = nbit * 8;
477 	hook->private = sc->ch[chan];
478 	sc->nhooks++;
479 	return(0);
480 }
481 
482 
483 static struct trxd *mn_desc_free;
484 
485 static struct trxd *
mn_alloc_desc(void)486 mn_alloc_desc(void)
487 {
488 	struct trxd *dp;
489 
490 	dp = mn_desc_free;
491 	if (dp)
492 		mn_desc_free = dp->vnext;
493 	else
494 		dp = (struct trxd *)kmalloc(sizeof *dp, M_MN, M_INTWAIT);
495 	return (dp);
496 }
497 
498 static void
mn_free_desc(struct trxd * dp)499 mn_free_desc(struct trxd *dp)
500 {
501 	dp->vnext =  mn_desc_free;
502 	mn_desc_free = dp;
503 }
504 
505 static u_int32_t
mn_parse_ts(const char * s,int * nbit)506 mn_parse_ts(const char *s, int *nbit)
507 {
508 	unsigned r;
509 	int i, j;
510 	char *p;
511 
512 	r = 0;
513 	j = -1;
514 	*nbit = 0;
515 	while(*s) {
516 		i = strtol(s, &p, 0);
517 		if (i < 0 || i > 31)
518 			return (0);
519 		while (j != -1 && j < i) {
520 			r |= 1 << j++;
521 			(*nbit)++;
522 		}
523 		j = -1;
524 		r |= 1 << i;
525 		(*nbit)++;
526 		if (*p == ',') {
527 			s = p + 1;
528 			continue;
529 		} else if (*p == '-') {
530 			j = i + 1;
531 			s = p + 1;
532 			continue;
533 		} else if (!*p) {
534 			break;
535 		} else {
536 			return (0);
537 		}
538 	}
539 	return (r);
540 }
541 
542 #ifdef notyet
543 static void
mn_fmt_ts(char * p,u_int32_t ts)544 mn_fmt_ts(char *p, u_int32_t ts)
545 {
546 	char *s;
547 	int j;
548 
549 	s = "";
550 	ts &= 0xffffffff;
551 	for (j = 0; j < 32; j++) {
552 		if (!(ts & (1 << j)))
553 			continue;
554 		ksprintf(p, "%s%d", s, j);
555 		p += strlen(p);
556 		s = ",";
557 		if (!(ts & (1 << (j+1))))
558 			continue;
559 		for (; j < 32; j++)
560 			if (!(ts & (1 << (j+1))))
561 				break;
562 		ksprintf(p, "-%d", j);
563 		p += strlen(p);
564 		s = ",";
565 	}
566 }
567 #endif /* notyet */
568 
569 /*
570  * OUTPUT
571  */
572 
573 static int
ngmn_rcvdata(hook_p hook,struct mbuf * m,meta_p meta)574 ngmn_rcvdata(hook_p hook, struct mbuf *m, meta_p meta)
575 {
576 	struct mbuf  *m2;
577 	struct trxd *dp, *dp2;
578 	struct schan *sch;
579 	struct softc *sc;
580 	int chan, pitch, len;
581 
582 	sch = hook->private;
583 	sc = sch->sc;
584 	chan = sch->chan;
585 
586 	if (sch->state != UP) {
587 		NG_FREE_DATA(m, meta);
588 		return (0);
589 	}
590 	if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) {
591 		NG_FREE_DATA(m, meta);
592 		return (0);
593 	}
594 	NG_FREE_META(meta);
595 	pitch = 0;
596 	m2 = m;
597 	dp2 = sc->ch[chan]->xl;
598 	len = m->m_pkthdr.len;
599 	while (len) {
600 		dp = mn_alloc_desc();
601 		if (!dp) {
602 			pitch++;
603 			m_freem(m);
604 			sc->ch[chan]->xl = dp2;
605 			dp = dp2->vnext;
606 			while (dp) {
607 				dp2 = dp->vnext;
608 				mn_free_desc(dp);
609 				dp = dp2;
610 			}
611 			sc->ch[chan]->xl->vnext = NULL;
612 			break;
613 		}
614 		dp->data = vtophys(m2->m_data);
615 		dp->flags = m2->m_len << 16;
616 		dp->flags += 1;
617 		len -= m2->m_len;
618 		dp->next = vtophys(dp);
619 		dp->vnext = NULL;
620 		sc->ch[chan]->xl->next = vtophys(dp);
621 		sc->ch[chan]->xl->vnext = dp;
622 		sc->ch[chan]->xl = dp;
623 		if (!len) {
624 			dp->m = m;
625 			dp->flags |= 0xc0000000;
626 			dp2->flags &= ~0x40000000;
627 		} else {
628 			dp->m = NULL;
629 			m2 = m2->m_next;
630 		}
631 	}
632 	if (pitch)
633 		kprintf("%s%d: Short on mem, pitched %d packets\n",
634 		    sc->name, chan, pitch);
635 	else {
636 #if 0
637 		kprintf("%d = %d + %d (%p)\n",
638 		    sch->tx_pending + m->m_pkthdr.len,
639 		    sch->tx_pending , m->m_pkthdr.len, m);
640 #endif
641 		sch->tx_pending += m->m_pkthdr.len;
642 		sc->m32x->txpoll &= ~(1 << chan);
643 	}
644 	return (0);
645 }
646 
647 /*
648  * OPEN
649  */
650 static int
ngmn_connect(hook_p hook)651 ngmn_connect(hook_p hook)
652 {
653 	int i, nts, chan;
654 	struct trxd *dp, *dp2;
655 	struct mbuf *m;
656 	struct softc *sc;
657 	struct schan *sch;
658 	u_int32_t u;
659 
660 	sch = hook->private;
661 	chan = sch->chan;
662 	sc = sch->sc;
663 
664 	if (sch->state == UP)
665 		return (0);
666 	sch->state = UP;
667 
668 	/* Count and configure the timeslots for this channel */
669 	for (nts = i = 0; i < 32; i++)
670 		if (sch->ts & (1 << i)) {
671 			sc->m32_mem.ts[i] = 0x00ff00ff |
672 				(chan << 24) | (chan << 8);
673 			nts++;
674 		}
675 
676 	/* Init the receiver & xmitter to HDLC */
677 	sc->m32_mem.cs[chan].flags = 0x80e90006;
678 	/* Allocate two buffers per timeslot */
679 	if (nts == 32)
680 		sc->m32_mem.cs[chan].itbs = 63;
681 	else
682 		sc->m32_mem.cs[chan].itbs = nts * 2;
683 
684 	/* Setup a transmit chain with one descriptor */
685 	/* XXX: we actually send a 1 byte packet */
686 	dp = mn_alloc_desc();
687 	MGETHDR(m, M_WAITOK, MT_DATA);
688 	m->m_pkthdr.len = 0;
689 	dp->m = m;
690 	dp->flags = 0xc0000000 + (1 << 16);
691 	dp->next = vtophys(dp);
692 	dp->vnext = NULL;
693 	dp->data = vtophys(sc->name);
694 	sc->m32_mem.cs[chan].tdesc = vtophys(dp);
695 	sc->ch[chan]->x1 = dp;
696 	sc->ch[chan]->xl = dp;
697 
698 	/* Setup a receive chain with 5 + NTS descriptors */
699 
700 	dp = mn_alloc_desc();
701 	m = NULL;
702 	MGETHDR(m, M_WAITOK, MT_DATA);
703 	MCLGET(m, M_WAITOK);
704 	dp->m = m;
705 	dp->data = vtophys(m->m_data);
706 	dp->flags = 0x40000000;
707 	dp->flags += 1600 << 16;
708 	dp->next = vtophys(dp);
709 	dp->vnext = NULL;
710 	sc->ch[chan]->rl = dp;
711 
712 	for (i = 0; i < (nts + 10); i++) {
713 		dp2 = dp;
714 		dp = mn_alloc_desc();
715 		m = NULL;
716 		MGETHDR(m, M_WAITOK, MT_DATA);
717 		MCLGET(m, M_WAITOK);
718 		dp->m = m;
719 		dp->data = vtophys(m->m_data);
720 		dp->flags = 0x00000000;
721 		dp->flags += 1600 << 16;
722 		dp->next = vtophys(dp2);
723 		dp->vnext = dp2;
724 	}
725 	sc->m32_mem.cs[chan].rdesc = vtophys(dp);
726 	sc->ch[chan]->r1 = dp;
727 
728 	/* Initialize this channel */
729 	sc->m32_mem.ccb = 0x00008000 + (chan << 8);
730 	sc->m32x->cmd = 0x1;
731 	DELAY(1000);
732 	u = sc->m32x->stat;
733 	if (!(u & 1))
734 		kprintf("%s: init chan %d stat %08x\n", sc->name, chan, u);
735 	sc->m32x->stat = 1;
736 
737 	return (0);
738 }
739 
740 /*
741  * CLOSE
742  */
743 static int
ngmn_disconnect(hook_p hook)744 ngmn_disconnect(hook_p hook)
745 {
746 	int chan, i;
747 	struct softc *sc;
748 	struct schan *sch;
749 	struct trxd *dp, *dp2;
750 	u_int32_t u;
751 
752 	sch = hook->private;
753 	chan = sch->chan;
754 	sc = sch->sc;
755 
756 	if (sch->state == DOWN)
757 		return (0);
758 	sch->state = DOWN;
759 
760 	/* Set receiver & transmitter off */
761 	sc->m32_mem.cs[chan].flags = 0x80920006;
762 	sc->m32_mem.cs[chan].itbs = 0;
763 
764 	/* free the timeslots */
765 	for (i = 0; i < 32; i++)
766 		if (sc->ch[chan]->ts & (1 << i))
767 			sc->m32_mem.ts[i] = 0x20002000;
768 
769 	/* Initialize this channel */
770 	sc->m32_mem.ccb = 0x00008000 + (chan << 8);
771 	sc->m32x->cmd = 0x1;
772 	DELAY(30);
773 	u = sc->m32x->stat;
774 	if (!(u & 1))
775 		kprintf("%s: zap chan %d stat %08x\n", sc->name, chan, u);
776 	sc->m32x->stat = 1;
777 
778 	/* Free all receive descriptors and mbufs */
779 	for (dp = sc->ch[chan]->r1; dp ; dp = dp2) {
780 		if (dp->m)
781 			m_freem(dp->m);
782 		sc->ch[chan]->r1 = dp2 = dp->vnext;
783 		mn_free_desc(dp);
784 	}
785 
786 	/* Free all transmit descriptors and mbufs */
787 	for (dp = sc->ch[chan]->x1; dp ; dp = dp2) {
788 		if (dp->m) {
789 			sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len;
790 			m_freem(dp->m);
791 		}
792 		sc->ch[chan]->x1 = dp2 = dp->vnext;
793 		mn_free_desc(dp);
794 	}
795 	sc->nhooks--;
796 	return(0);
797 }
798 
799 /*
800  * Create a new channel.
801  */
802 static void
mn_create_channel(struct softc * sc,int chan)803 mn_create_channel(struct softc *sc, int chan)
804 {
805 	struct schan *sch;
806 
807 	sch = sc->ch[chan] = (struct schan *)kmalloc(sizeof *sc->ch[chan],
808 	    M_MN, M_WAITOK | M_ZERO);
809 	sch->sc = sc;
810 	sch->state = DOWN;
811 	sch->chan = chan;
812 	ksprintf(sch->name, "%s%d", sc->name, chan);
813 	return;
814 }
815 
816 #ifdef notyet
817 /*
818  * Dump Munich32x state
819  */
820 static void
m32_dump(struct softc * sc)821 m32_dump(struct softc *sc)
822 {
823 	u_int32_t *tp4;
824 	int i, j;
825 
826 	kprintf("mn%d: MUNICH32X dump\n", sc->unit);
827 	tp4 = (u_int32_t *)sc->m0v;
828 	for(j = 0; j < 64; j += 8) {
829 		kprintf("%02x", j * sizeof *tp4);
830 		for(i = 0; i < 8; i++)
831 			kprintf(" %08x", tp4[i+j]);
832 		kprintf("\n");
833 	}
834 	for(j = 0; j < M32_CHAN; j++) {
835 		if (!sc->ch[j])
836 			continue;
837 		kprintf("CH%d: state %d ts %08x",
838 			j, sc->ch[j]->state, sc->ch[j]->ts);
839 		kprintf("  %08x %08x %08x %08x %08x %08x\n",
840 			sc->m32_mem.cs[j].flags,
841 			sc->m32_mem.cs[j].rdesc,
842 			sc->m32_mem.cs[j].tdesc,
843 			sc->m32_mem.cs[j].itbs,
844 			sc->m32_mem.crxd[j],
845 			sc->m32_mem.ctxd[j] );
846 	}
847 }
848 
849 /*
850  * Dump Falch54 state
851  */
852 static void
f54_dump(struct softc * sc)853 f54_dump(struct softc *sc)
854 {
855 	u_int8_t *tp1;
856 	int i, j;
857 
858 	kprintf("%s: FALC54 dump\n", sc->name);
859 	tp1 = (u_int8_t *)sc->m1v;
860 	for(j = 0; j < 128; j += 16) {
861 		kprintf("%s: %02x |", sc->name, j * sizeof *tp1);
862 		for(i = 0; i < 16; i++)
863 			kprintf(" %02x", tp1[i+j]);
864 		kprintf("\n");
865 	}
866 }
867 #endif /* notyet */
868 
869 /*
870  * Init Munich32x
871  */
872 static void
m32_init(struct softc * sc)873 m32_init(struct softc *sc)
874 {
875 
876 	sc->m32x->conf =  0x00000000;
877 	sc->m32x->mode1 = 0x81048000 + 1600; 	/* XXX: temp */
878 #if 1
879 	sc->m32x->mode2 = 0x00000081;
880 	sc->m32x->txpoll = 0xffffffff;
881 #elif 1
882 	sc->m32x->mode2 = 0x00000081;
883 	sc->m32x->txpoll = 0xffffffff;
884 #else
885 	sc->m32x->mode2 = 0x00000101;
886 #endif
887 	sc->m32x->lconf = 0x6060009B;
888 	sc->m32x->imask = 0x00000000;
889 }
890 
891 /*
892  * Init the Falc54
893  */
894 static void
f54_init(struct softc * sc)895 f54_init(struct softc *sc)
896 {
897 	sc->f54w->ipc  = 0x07;
898 
899 	sc->f54w->xpm0 = 0xbd;
900 	sc->f54w->xpm1 = 0x03;
901 	sc->f54w->xpm2 = 0x00;
902 
903 	sc->f54w->imr0 = 0x18; /* RMB, CASC */
904 	sc->f54w->imr1 = 0x08; /* XMB */
905 	sc->f54w->imr2 = 0x00;
906 	sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */
907 	sc->f54w->imr4 = 0x00;
908 
909 	sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */
910 	sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */
911 	if (sc->framing == E1)
912 		sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */
913 	else if (sc->framing == E1U)
914 		sc->f54w->fmr2 = 0x33; /* dais, rtm, Auto Rem-Alarm, Auto resync */
915 
916 	sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */
917 	sc->f54w->pcd =  0x0a;
918 	sc->f54w->pcr =  0x15;
919 	sc->f54w->xsw =  0x9f; /* fmr4 */
920 	if (sc->framing == E1)
921 		sc->f54w->xsp =  0x1c; /* fmr5 */
922 	else if (sc->framing == E1U)
923 		sc->f54w->xsp =  0x3c; /* tt0, fmr5 */
924 	sc->f54w->xc0 =  0x07;
925 	sc->f54w->xc1 =  0x3d;
926 	sc->f54w->rc0 =  0x05;
927 	sc->f54w->rc1 =  0x00;
928 	sc->f54w->cmdr = 0x51;
929 }
930 
931 static int
mn_reset(struct softc * sc)932 mn_reset(struct softc *sc)
933 {
934 	u_int32_t u;
935 	int i;
936 
937 	sc->m32x->ccba = vtophys(&sc->m32_mem.csa);
938 	sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb);
939 
940 	bzero(sc->tiqb, sizeof sc->tiqb);
941 	sc->m32x->tiqba = vtophys(&sc->tiqb);
942 	sc->m32x->tiql = NIQB / 16 - 1;
943 
944 	bzero(sc->riqb, sizeof sc->riqb);
945 	sc->m32x->riqba = vtophys(&sc->riqb);
946 	sc->m32x->riql = NIQB / 16 - 1;
947 
948 	bzero(sc->ltiqb, sizeof sc->ltiqb);
949 	sc->m32x->ltiqba = vtophys(&sc->ltiqb);
950 	sc->m32x->ltiql = NIQB / 16 - 1;
951 
952 	bzero(sc->lriqb, sizeof sc->lriqb);
953 	sc->m32x->lriqba = vtophys(&sc->lriqb);
954 	sc->m32x->lriql = NIQB / 16 - 1;
955 
956 	bzero(sc->piqb, sizeof sc->piqb);
957 	sc->m32x->piqba = vtophys(&sc->piqb);
958 	sc->m32x->piql = NIQB / 16 - 1;
959 
960 	m32_init(sc);
961 	f54_init(sc);
962 
963 	u = sc->m32x->stat;
964 	sc->m32x->stat = u;
965 	sc->m32_mem.ccb = 0x4;
966 	sc->m32x->cmd = 0x1;
967 	DELAY(1000);
968 	u = sc->m32x->stat;
969 	sc->m32x->stat = u;
970 
971 	/* set all timeslots to known state */
972 	for (i = 0; i < 32; i++)
973 		sc->m32_mem.ts[i] = 0x20002000;
974 
975 	if (!(u & 1)) {
976 		kprintf(
977 "mn%d: WARNING: Controller failed the PCI bus-master test.\n"
978 "mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n",
979 		    sc->unit, sc->unit);
980 		return  (0);
981 	}
982 	return (1);
983 }
984 
985 /*
986  * FALC54 interrupt handling
987  */
988 static void
f54_intr(struct softc * sc)989 f54_intr(struct softc *sc)
990 {
991 	unsigned u, s;
992 #if 0
993 	unsigned g;
994 	g = sc->f54r->gis;
995 #endif
996 	u = sc->f54r->isr0 << 24;
997 	u |= sc->f54r->isr1 << 16;
998 	u |= sc->f54r->isr2 <<  8;
999 	u |= sc->f54r->isr3;
1000 	sc->falc_irq = u;
1001 	/* don't chat about the 1 sec heart beat */
1002 	if (u & ~0x40) {
1003 #if 0
1004 		kprintf("%s*: FALC54 IRQ GIS:%02x %pb%i\n", sc->name, g, "\20"
1005 		    "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
1006 		    "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
1007 		    "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
1008 		    "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP", u);
1009 #endif
1010 		s = sc->f54r->frs0 << 24;
1011 		s |= sc->f54r->frs1 << 16;
1012 		s |= sc->f54r->rsw <<  8;
1013 		s |= sc->f54r->rsp;
1014 		sc->falc_state = s;
1015 
1016 		s &= ~0x01844038;	/* undefined or static bits */
1017 		s &= ~0x00009fc7;	/* bits we don't care about */
1018 		s &= ~0x00780000;	/* XXX: TS16 related */
1019 		s &= ~0x06000000;	/* XXX: Multiframe related */
1020 #if 0
1021 		kprintf("%s*: FALC54 Status %pb%i\n", sc->name, "\20"
1022 		    "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0"
1023 		    "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO"
1024 		    "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4"
1025 		    "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15", s);
1026 #endif
1027 		if (s != sc->framer_state) {
1028 #if 0
1029 			for (i = 0; i < M32_CHAN; i++) {
1030 				if (!sc->ch[i])
1031 					continue;
1032 			        sp = &sc->ch[i]->ifsppp;
1033 				if (!(sp->pp_if.if_flags & IFF_UP))
1034 					continue;
1035 				if (s)
1036 					timeout((timeout_t *)sp->pp_down, sp, 1 * hz);
1037 				else
1038 					timeout((timeout_t *)sp->pp_up, sp, 1 * hz);
1039 			}
1040 #endif
1041 			sc->framer_state = s;
1042 		}
1043 	}
1044 	/* Once per second check error counters */
1045 	/* XXX: not clear if this is actually ok */
1046 	if (!(u & 0x40))
1047 		return;
1048 	sc->cnt_fec  += sc->f54r->fec;
1049 	sc->cnt_cvc  += sc->f54r->cvc;
1050 	sc->cnt_cec1 += sc->f54r->cec1;
1051 	sc->cnt_ebc  += sc->f54r->ebc;
1052 	sc->cnt_cec2 += sc->f54r->cec2;
1053 	sc->cnt_cec3 += sc->f54r->cec3;
1054 	sc->cnt_rbc  += sc->f54r->rbc;
1055 }
1056 
1057 /*
1058  * Transmit interrupt for one channel
1059  */
1060 static void
mn_tx_intr(struct softc * sc,u_int32_t vector)1061 mn_tx_intr(struct softc *sc, u_int32_t vector)
1062 {
1063 	u_int32_t chan;
1064 	struct trxd *dp;
1065 	struct mbuf *m;
1066 
1067 	chan = vector & 0x1f;
1068 	if (!sc->ch[chan])
1069 		return;
1070 	if (sc->ch[chan]->state != UP) {
1071 		kprintf("%s: tx_intr when not UP\n", sc->name);
1072 		return;
1073 	}
1074 	for (;;) {
1075 		dp = sc->ch[chan]->x1;
1076 		if (vtophys(dp) == sc->m32_mem.ctxd[chan])
1077 			return;
1078 		m = dp->m;
1079 		if (m) {
1080 #if 0
1081 			kprintf("%d = %d - %d (%p)\n",
1082 			    sc->ch[chan]->tx_pending - m->m_pkthdr.len,
1083 			    sc->ch[chan]->tx_pending , m->m_pkthdr.len, m);
1084 #endif
1085 			sc->ch[chan]->tx_pending -= m->m_pkthdr.len;
1086 			m_freem(m);
1087 		}
1088 		sc->ch[chan]->last_xmit = time_uptime;
1089 		sc->ch[chan]->x1 = dp->vnext;
1090 		mn_free_desc(dp);
1091 	}
1092 }
1093 
1094 /*
1095  * Receive interrupt for one channel
1096  */
1097 static void
mn_rx_intr(struct softc * sc,u_int32_t vector)1098 mn_rx_intr(struct softc *sc, u_int32_t vector)
1099 {
1100 	u_int32_t chan, err;
1101 	struct trxd *dp;
1102 	struct mbuf *m;
1103 	struct schan *sch;
1104 
1105 	chan = vector & 0x1f;
1106 	if (!sc->ch[chan])
1107 		return;
1108 	sch = sc->ch[chan];
1109 	if (sch->state != UP) {
1110 		kprintf("%s: rx_intr when not UP\n", sc->name);
1111 		return;
1112 	}
1113 	vector &= ~0x1f;
1114 	if (vector == 0x30000b00)
1115 		sch->rx_error++;
1116 	for (;;) {
1117 		dp = sch->r1;
1118 		if (vtophys(dp) == sc->m32_mem.crxd[chan])
1119 			return;
1120 		m = dp->m;
1121 		dp->m = NULL;
1122 		m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff;
1123 		err = (dp->status >> 8) & 0xff;
1124 		if (!err) {
1125 			ng_queue_data(sch->hook, m, NULL);
1126 			sch->last_recv = time_uptime;
1127 			m = NULL;
1128 			/* we could be down by now... */
1129 			if (sch->state != UP)
1130 				return;
1131 		} else if (err & 0x40) {
1132 			sch->short_error++;
1133 		} else if (err & 0x10) {
1134 			sch->crc_error++;
1135 		} else if (err & 0x08) {
1136 			sch->dribble_error++;
1137 		} else if (err & 0x04) {
1138 			sch->long_error++;
1139 		} else if (err & 0x02) {
1140 			sch->abort_error++;
1141 		} else if (err & 0x01) {
1142 			sch->overflow_error++;
1143 		}
1144 		if (err) {
1145 			sch->last_rxerr = time_uptime;
1146 			sch->prev_error = sch->last_error;
1147 			sch->last_error = err;
1148 		}
1149 
1150 		sc->ch[chan]->r1 = dp->vnext;
1151 
1152 		/* Replenish desc + mbuf supplies */
1153 		if (!m) {
1154 			MGETHDR(m, M_NOWAIT, MT_DATA);
1155 			if (m == NULL) {
1156 				mn_free_desc(dp);
1157 				return; /* ENOBUFS */
1158 			}
1159 			MCLGET(m, M_NOWAIT);
1160 			if((m->m_flags & M_EXT) == 0) {
1161 				mn_free_desc(dp);
1162 				m_freem(m);
1163 				return; /* ENOBUFS */
1164 			}
1165 		}
1166 		dp->m = m;
1167 		dp->data = vtophys(m->m_data);
1168 		dp->flags = 0x40000000;
1169 		dp->flags += 1600 << 16;
1170 		dp->next = vtophys(dp);
1171 		dp->vnext = NULL;
1172 		sc->ch[chan]->rl->next = vtophys(dp);
1173 		sc->ch[chan]->rl->vnext = dp;
1174 		sc->ch[chan]->rl->flags &= ~0x40000000;
1175 		sc->ch[chan]->rl = dp;
1176 	}
1177 }
1178 
1179 
1180 /*
1181  * Interupt handler
1182  */
1183 
1184 static void
mn_intr(void * xsc)1185 mn_intr(void *xsc)
1186 {
1187 	struct softc *sc;
1188 	u_int32_t stat, lstat, u;
1189 	int i, j;
1190 
1191 	sc = xsc;
1192 	stat =  sc->m32x->stat;
1193 	lstat =  sc->m32x->lstat;
1194 #if 0
1195 	if (!stat && !(lstat & 2))
1196 		return;
1197 #endif
1198 
1199 	if (stat & ~0xc200) {
1200 		kprintf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat);
1201 	}
1202 
1203 	if ((stat & 0x200) || (lstat & 2))
1204 		f54_intr(sc);
1205 
1206 	for (j = i = 0; i < 64; i ++) {
1207 		u = sc->riqb[i];
1208 		if (u) {
1209 			sc->riqb[i] = 0;
1210 			mn_rx_intr(sc, u);
1211 			if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00)
1212 				continue;
1213 			u &= ~0x30000400;	/* bits we don't care about */
1214 			if ((u & ~0x1f) == 0x00000900)
1215 				continue;
1216 			if (!(u & ~0x1f))
1217 				continue;
1218 			if (!j)
1219 				kprintf("%s*: RIQB:", sc->name);
1220 			kprintf(" [%d]=%08x", i, u);
1221 			j++;
1222 		}
1223 	}
1224 	if (j)
1225 	    kprintf("\n");
1226 
1227 	for (j = i = 0; i < 64; i ++) {
1228 		u = sc->tiqb[i];
1229 		if (u) {
1230 			sc->tiqb[i] = 0;
1231 			mn_tx_intr(sc, u);
1232 			if ((u & ~0x1f) == 0x20000800)
1233 				continue;
1234 			u &= ~0x20000000;	/* bits we don't care about */
1235 			if (!u)
1236 				continue;
1237 			if (!j)
1238 				kprintf("%s*: TIQB:", sc->name);
1239 			kprintf(" [%d]=%08x", i, u);
1240 			j++;
1241 		}
1242 	}
1243 	if (j)
1244 		kprintf("\n");
1245 	sc->m32x->stat = stat;
1246 }
1247 
1248 /*
1249  * PCI initialization stuff
1250  */
1251 
1252 static int
mn_probe(device_t self)1253 mn_probe (device_t self)
1254 {
1255 	u_int id = pci_get_devid(self);
1256 
1257 	if (sizeof (struct m32xreg) != 256) {
1258 		kprintf("MN: sizeof(struct m32xreg) = %zd, should have been 256\n", sizeof (struct m32xreg));
1259 		return (ENXIO);
1260 	}
1261 	if (sizeof (struct f54rreg) != 128) {
1262 		kprintf("MN: sizeof(struct f54rreg) = %zd, should have been 128\n", sizeof (struct f54rreg));
1263 		return (ENXIO);
1264 	}
1265 	if (sizeof (struct f54wreg) != 128) {
1266 		kprintf("MN: sizeof(struct f54wreg) = %zd, should have been 128\n", sizeof (struct f54wreg));
1267 		return (ENXIO);
1268 	}
1269 
1270 	if (id != 0x2101110a)
1271 		return (ENXIO);
1272 
1273 	device_set_desc_copy(self, "Munich32X E1/T1 HDLC Controller");
1274 	return (0);
1275 }
1276 
1277 static int
mn_attach(device_t self)1278 mn_attach (device_t self)
1279 {
1280 	struct softc *sc;
1281 	u_int32_t u;
1282 	u_int32_t ver;
1283 	static int once;
1284 	int rid, error;
1285 	struct resource *res;
1286 
1287 	if (!once) {
1288 		if (ng_newtype(&mntypestruct))
1289 			kprintf("ng_newtype failed\n");
1290 		once++;
1291 	}
1292 
1293 	sc = (struct softc *)kmalloc(sizeof *sc, M_MN, M_WAITOK | M_ZERO);
1294 	device_set_softc(self, sc);
1295 
1296 	sc->dev = self;
1297 	sc->unit = device_get_unit(self);
1298 	sc->framing = E1;
1299 	ksprintf(sc->name, "mn%d", sc->unit);
1300 
1301         rid = PCIR_MAPS;
1302         res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
1303         if (res == NULL) {
1304                 device_printf(self, "Could not map memory\n");
1305                 return ENXIO;
1306         }
1307         sc->m0v = rman_get_virtual(res);
1308         sc->m0p = rman_get_start(res);
1309 
1310         rid = PCIR_MAPS + 4;
1311         res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
1312         if (res == NULL) {
1313                 device_printf(self, "Could not map memory\n");
1314                 return ENXIO;
1315         }
1316         sc->m1v = rman_get_virtual(res);
1317         sc->m1p = rman_get_start(res);
1318 
1319 	/* Allocate interrupt */
1320 	rid = 0;
1321 	sc->irq = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
1322 	    RF_SHAREABLE | RF_ACTIVE);
1323 
1324 	if (sc->irq == NULL) {
1325 		kprintf("couldn't map interrupt\n");
1326 		return(ENXIO);
1327 	}
1328 
1329 	error = bus_setup_intr(self, sc->irq, INTR_MPSAFE, mn_intr, sc,
1330 			       &sc->intrhand, NULL);
1331 
1332 	if (error) {
1333 		kprintf("couldn't set up irq\n");
1334 		return(ENXIO);
1335 	}
1336 
1337 	u = pci_read_config(self, PCIR_COMMAND, 1);
1338 	kprintf("%x\n", u);
1339 	pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN, 1);
1340 #if 0
1341 	pci_write_config(self, PCIR_COMMAND, 0x02800046, 4);
1342 #endif
1343 	u = pci_read_config(self, PCIR_COMMAND, 1);
1344 	kprintf("%x\n", u);
1345 
1346 	ver = pci_get_revid(self);
1347 
1348 	sc->m32x = (struct m32xreg *) sc->m0v;
1349 	sc->f54w = (struct f54wreg *) sc->m1v;
1350 	sc->f54r = (struct f54rreg *) sc->m1v;
1351 
1352 	/* We must reset before poking at FALC54 registers */
1353 	u = mn_reset(sc);
1354 	if (!u)
1355 		return (0);
1356 
1357 	kprintf("mn%d: Munich32X", sc->unit);
1358 	switch (ver) {
1359 	case 0x13:
1360 		kprintf(" Rev 2.2");
1361 		break;
1362 	default:
1363 		kprintf(" Rev 0x%x\n", ver);
1364 	}
1365 	kprintf(", Falc54");
1366 	switch (sc->f54r->vstr) {
1367 	case 0:
1368 		kprintf(" Rev < 1.3\n");
1369 		break;
1370 	case 1:
1371 		kprintf(" Rev 1.3\n");
1372 		break;
1373 	case 2:
1374 		kprintf(" Rev 1.4\n");
1375 		break;
1376 	case 0x10:
1377 		kprintf("-LH Rev 1.1\n");
1378 		break;
1379 	case 0x13:
1380 		kprintf("-LH Rev 1.3\n");
1381 		break;
1382 	default:
1383 		kprintf(" Rev 0x%x\n", sc->f54r->vstr);
1384 	}
1385 
1386 	if (ng_make_node_common(&mntypestruct, &sc->node) != 0) {
1387 		kprintf("ng_make_node_common failed\n");
1388 		return (0);
1389 	}
1390 	sc->node->private = sc;
1391 	ksprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit);
1392 	if (ng_name_node(sc->node, sc->nodename)) {
1393 		ng_rmnode(sc->node);
1394 		ng_unref(sc->node);
1395 		return (0);
1396 	}
1397 
1398 	return (0);
1399 }
1400 
1401 
1402 static device_method_t mn_methods[] = {
1403         /* Device interface */
1404         DEVMETHOD(device_probe,         mn_probe),
1405         DEVMETHOD(device_attach,        mn_attach),
1406         DEVMETHOD(device_suspend,       bus_generic_suspend),
1407         DEVMETHOD(device_resume,        bus_generic_resume),
1408         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
1409 
1410         DEVMETHOD_END
1411 };
1412 
1413 static driver_t mn_driver = {
1414         "mn",
1415         mn_methods,
1416         0
1417 };
1418 
1419 static devclass_t mn_devclass;
1420 
1421 DECLARE_DUMMY_MODULE(if_mn);
1422 DRIVER_MODULE(if_mn, pci, mn_driver, mn_devclass, NULL, NULL);
1423 
1424