1 /*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $
33 */
34
35 /*
36 * RealTek 8129/8139 PCI NIC driver
37 *
38 * Supports several extremely cheap PCI 10/100 adapters based on
39 * the RealTek chipset. Datasheets can be obtained from
40 * www.realtek.com.tw.
41 *
42 * Written by Bill Paul <wpaul@ctr.columbia.edu>
43 * Electrical Engineering Department
44 * Columbia University, New York City
45 */
46
47 /*
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
53 *
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
56 * on a longword (32-bit) boundary. This means we almost always have to
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
62 *
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
68 * levels.
69 *
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
73 *
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
78 * filter.
79 *
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
84 */
85
86 #include "opt_ifpoll.h"
87
88 #include <sys/param.h>
89 #include <sys/endian.h>
90 #include <sys/systm.h>
91 #include <sys/sockio.h>
92 #include <sys/mbuf.h>
93 #include <sys/malloc.h>
94 #include <sys/kernel.h>
95 #include <sys/module.h>
96 #include <sys/socket.h>
97 #include <sys/serialize.h>
98 #include <sys/bus.h>
99 #include <sys/rman.h>
100 #include <sys/interrupt.h>
101
102 #include <net/if.h>
103 #include <net/ifq_var.h>
104 #include <net/if_arp.h>
105 #include <net/ethernet.h>
106 #include <net/if_dl.h>
107 #include <net/if_media.h>
108 #include <net/if_poll.h>
109
110 #include <net/bpf.h>
111
112 #include <dev/netif/mii_layer/mii.h>
113 #include <dev/netif/mii_layer/miivar.h>
114
115 #include "pcidevs.h"
116 #include <bus/pci/pcireg.h>
117 #include <bus/pci/pcivar.h>
118
119 /* "controller miibus0" required. See GENERIC if you get errors here. */
120 #include "miibus_if.h"
121
122 /*
123 * Default to using PIO access for this driver. On SMP systems,
124 * there appear to be problems with memory mapped mode: it looks like
125 * doing too many memory mapped access back to back in rapid succession
126 * can hang the bus. I'm inclined to blame this on crummy design/construction
127 * on the part of RealTek. Memory mapped mode does appear to work on
128 * uniprocessor systems though.
129 */
130 #define RL_USEIOSPACE
131
132 #include <dev/netif/rl/if_rlreg.h>
133
134 /*
135 * Various supported device vendors/types and their names.
136 */
137 static struct rl_type {
138 uint16_t rl_vid;
139 uint16_t rl_did;
140 const char *rl_name;
141 } rl_devs[] = {
142 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8129,
143 "RealTek 8129 10/100BaseTX" },
144 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139,
145 "RealTek 8139 10/100BaseTX" },
146 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139B,
147 "RealTek 8139 10/100BaseTX CardBus" },
148 { PCI_VENDOR_ACCTON, PCI_PRODUCT_ACCTON_MPX5030,
149 "Accton MPX 5030/5038 10/100BaseTX" },
150 { PCI_VENDOR_DELTA, PCI_PRODUCT_DELTA_8139,
151 "Delta Electronics 8139 10/100BaseTX" },
152 { PCI_VENDOR_ADDTRON, PCI_PRODUCT_ADDTRON_8139,
153 "Addtron Technology 8139 10/100BaseTX" },
154 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE520TX_C1,
155 "D-Link DFE-520TX C1 10/100BaseTX" },
156 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE530TXPLUS,
157 "D-Link DFE-530TX+ 10/100BaseTX" },
158 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE690TXD,
159 "D-Link DFE-690TX 10/100BaseTX" },
160 { PCI_VENDOR_NORTEL, PCI_PRODUCT_NORTEL_BAYSTACK_21,
161 "Nortel Networks 10/100BaseTX" },
162 { PCI_VENDOR_PEPPERCON, PCI_PRODUCT_PEPPERCON_ROLF,
163 "Peppercon AG ROL/F" },
164 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CB_TXD,
165 "Corega FEther CB-TXD" },
166 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_2CB_TXD,
167 "Corega FEtherII CB-TXD" },
168 { PCI_VENDOR_PLANEX, PCI_PRODUCT_PLANEX_FNW_3800_TX,
169 "Planex FNW-3800-TX" },
170 { 0, 0, NULL }
171 };
172
173 static int rl_probe(device_t);
174 static int rl_attach(device_t);
175 static int rl_detach(device_t);
176
177 static int rl_encap(struct rl_softc *, struct mbuf * );
178
179 static void rl_rxeof(struct rl_softc *);
180 static void rl_txeof(struct rl_softc *);
181 static void rl_intr(void *);
182 static void rl_tick(void *);
183 static void rl_start(struct ifnet *, struct ifaltq_subque *);
184 static int rl_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
185 static void rl_init(void *);
186 static void rl_stop (struct rl_softc *);
187 static void rl_watchdog(struct ifnet *);
188 static int rl_suspend(device_t);
189 static int rl_resume(device_t);
190 static void rl_shutdown(device_t);
191 static int rl_ifmedia_upd(struct ifnet *);
192 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
193
194 static void rl_eeprom_putbyte(struct rl_softc *, int);
195 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
196 static void rl_read_eeprom(struct rl_softc *, caddr_t, int, int, int);
197 static void rl_mii_sync(struct rl_softc *);
198 static void rl_mii_send(struct rl_softc *, uint32_t, int);
199 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
200 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
201
202 static int rl_miibus_readreg(device_t, int, int);
203 static int rl_miibus_writereg(device_t, int, int, int);
204 static void rl_miibus_statchg(device_t);
205
206 static void rl_setmulti(struct rl_softc *);
207 static void rl_reset(struct rl_softc *);
208 static void rl_list_tx_init(struct rl_softc *);
209
210 #ifdef IFPOLL_ENABLE
211 static void rl_npoll(struct ifnet *, struct ifpoll_info *);
212 static void rl_npoll_compat(struct ifnet *, void *, int);
213 #endif
214
215 static int rl_dma_alloc(struct rl_softc *);
216 static void rl_dma_free(struct rl_softc *);
217
218 #ifdef RL_USEIOSPACE
219 #define RL_RES SYS_RES_IOPORT
220 #define RL_RID RL_PCI_LOIO
221 #else
222 #define RL_RES SYS_RES_MEMORY
223 #define RL_RID RL_PCI_LOMEM
224 #endif
225
226 static device_method_t rl_methods[] = {
227 /* Device interface */
228 DEVMETHOD(device_probe, rl_probe),
229 DEVMETHOD(device_attach, rl_attach),
230 DEVMETHOD(device_detach, rl_detach),
231 DEVMETHOD(device_suspend, rl_suspend),
232 DEVMETHOD(device_resume, rl_resume),
233 DEVMETHOD(device_shutdown, rl_shutdown),
234
235 /* bus interface */
236 DEVMETHOD(bus_print_child, bus_generic_print_child),
237 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
238
239 /* MII interface */
240 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
241 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
242 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
243
244 DEVMETHOD_END
245 };
246
247 static DEFINE_CLASS_0(rl, rl_driver, rl_methods, sizeof(struct rl_softc));
248 static devclass_t rl_devclass;
249
250 DECLARE_DUMMY_MODULE(if_rl);
251 DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, NULL, NULL);
252 DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, NULL, NULL);
253 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, NULL, NULL);
254 MODULE_DEPEND(if_rl, miibus, 1, 1, 1);
255
256 #define EE_SET(x) \
257 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) | (x))
258
259 #define EE_CLR(x) \
260 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) & ~(x))
261
262 /*
263 * Send a read command and address to the EEPROM, check for ACK.
264 */
265 static void
rl_eeprom_putbyte(struct rl_softc * sc,int addr)266 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
267 {
268 int d, i;
269
270 d = addr | sc->rl_eecmd_read;
271
272 /*
273 * Feed in each bit and strobe the clock.
274 */
275 for (i = 0x400; i; i >>= 1) {
276 if (d & i)
277 EE_SET(RL_EE_DATAIN);
278 else
279 EE_CLR(RL_EE_DATAIN);
280 DELAY(100);
281 EE_SET(RL_EE_CLK);
282 DELAY(150);
283 EE_CLR(RL_EE_CLK);
284 DELAY(100);
285 }
286 }
287
288 /*
289 * Read a word of data stored in the EEPROM at address 'addr.'
290 */
291 static void
rl_eeprom_getword(struct rl_softc * sc,int addr,uint16_t * dest)292 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
293 {
294 int i;
295 uint16_t word = 0;
296
297 /* Enter EEPROM access mode. */
298 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
299
300 /*
301 * Send address of word we want to read.
302 */
303 rl_eeprom_putbyte(sc, addr);
304
305 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
306
307 /*
308 * Start reading bits from EEPROM.
309 */
310 for (i = 0x8000; i; i >>= 1) {
311 EE_SET(RL_EE_CLK);
312 DELAY(100);
313 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
314 word |= i;
315 EE_CLR(RL_EE_CLK);
316 DELAY(100);
317 }
318
319 /* Turn off EEPROM access mode. */
320 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
321
322 *dest = word;
323 }
324
325 /*
326 * Read a sequence of words from the EEPROM.
327 */
328 static void
rl_read_eeprom(struct rl_softc * sc,caddr_t dest,int off,int cnt,int swap)329 rl_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt, int swap)
330 {
331 int i;
332 u_int16_t word = 0, *ptr;
333
334 for (i = 0; i < cnt; i++) {
335 rl_eeprom_getword(sc, off + i, &word);
336 ptr = (u_int16_t *)(dest + (i * 2));
337 if (swap)
338 *ptr = ntohs(word);
339 else
340 *ptr = word;
341 }
342 }
343
344
345 /*
346 * MII access routines are provided for the 8129, which
347 * doesn't have a built-in PHY. For the 8139, we fake things
348 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
349 * direct access PHY registers.
350 */
351 #define MII_SET(x) \
352 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) | x)
353
354 #define MII_CLR(x) \
355 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) & ~x)
356
357 /*
358 * Sync the PHYs by setting data bit and strobing the clock 32 times.
359 */
360 static void
rl_mii_sync(struct rl_softc * sc)361 rl_mii_sync(struct rl_softc *sc)
362 {
363 int i;
364
365 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
366
367 for (i = 0; i < 32; i++) {
368 MII_SET(RL_MII_CLK);
369 DELAY(1);
370 MII_CLR(RL_MII_CLK);
371 DELAY(1);
372 }
373 }
374
375 /*
376 * Clock a series of bits through the MII.
377 */
378 static void
rl_mii_send(struct rl_softc * sc,uint32_t bits,int cnt)379 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
380 {
381 int i;
382
383 MII_CLR(RL_MII_CLK);
384
385 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
386 if (bits & i)
387 MII_SET(RL_MII_DATAOUT);
388 else
389 MII_CLR(RL_MII_DATAOUT);
390 DELAY(1);
391 MII_CLR(RL_MII_CLK);
392 DELAY(1);
393 MII_SET(RL_MII_CLK);
394 }
395 }
396
397 /*
398 * Read an PHY register through the MII.
399 */
400 static int
rl_mii_readreg(struct rl_softc * sc,struct rl_mii_frame * frame)401 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
402 {
403 int ack, i;
404
405 /*
406 * Set up frame for RX.
407 */
408 frame->mii_stdelim = RL_MII_STARTDELIM;
409 frame->mii_opcode = RL_MII_READOP;
410 frame->mii_turnaround = 0;
411 frame->mii_data = 0;
412
413 CSR_WRITE_2(sc, RL_MII, 0);
414
415 /*
416 * Turn on data xmit.
417 */
418 MII_SET(RL_MII_DIR);
419
420 rl_mii_sync(sc);
421
422 /*
423 * Send command/address info.
424 */
425 rl_mii_send(sc, frame->mii_stdelim, 2);
426 rl_mii_send(sc, frame->mii_opcode, 2);
427 rl_mii_send(sc, frame->mii_phyaddr, 5);
428 rl_mii_send(sc, frame->mii_regaddr, 5);
429
430 /* Idle bit */
431 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
432 DELAY(1);
433 MII_SET(RL_MII_CLK);
434 DELAY(1);
435
436 /* Turn off xmit. */
437 MII_CLR(RL_MII_DIR);
438
439 /* Check for ack */
440 MII_CLR(RL_MII_CLK);
441 DELAY(1);
442 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
443 MII_SET(RL_MII_CLK);
444 DELAY(1);
445
446 /*
447 * Now try reading data bits. If the ack failed, we still
448 * need to clock through 16 cycles to keep the PHY(s) in sync.
449 */
450 if (ack) {
451 for(i = 0; i < 16; i++) {
452 MII_CLR(RL_MII_CLK);
453 DELAY(1);
454 MII_SET(RL_MII_CLK);
455 DELAY(1);
456 }
457 } else {
458 for (i = 0x8000; i; i >>= 1) {
459 MII_CLR(RL_MII_CLK);
460 DELAY(1);
461 if (!ack) {
462 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
463 frame->mii_data |= i;
464 DELAY(1);
465 }
466 MII_SET(RL_MII_CLK);
467 DELAY(1);
468 }
469 }
470
471 MII_CLR(RL_MII_CLK);
472 DELAY(1);
473 MII_SET(RL_MII_CLK);
474 DELAY(1);
475
476 return(ack ? 1 : 0);
477 }
478
479 /*
480 * Write to a PHY register through the MII.
481 */
482 static int
rl_mii_writereg(struct rl_softc * sc,struct rl_mii_frame * frame)483 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
484 {
485 /*
486 * Set up frame for TX.
487 */
488 frame->mii_stdelim = RL_MII_STARTDELIM;
489 frame->mii_opcode = RL_MII_WRITEOP;
490 frame->mii_turnaround = RL_MII_TURNAROUND;
491
492 /*
493 * Turn on data output.
494 */
495 MII_SET(RL_MII_DIR);
496
497 rl_mii_sync(sc);
498
499 rl_mii_send(sc, frame->mii_stdelim, 2);
500 rl_mii_send(sc, frame->mii_opcode, 2);
501 rl_mii_send(sc, frame->mii_phyaddr, 5);
502 rl_mii_send(sc, frame->mii_regaddr, 5);
503 rl_mii_send(sc, frame->mii_turnaround, 2);
504 rl_mii_send(sc, frame->mii_data, 16);
505
506 /* Idle bit. */
507 MII_SET(RL_MII_CLK);
508 DELAY(1);
509 MII_CLR(RL_MII_CLK);
510 DELAY(1);
511
512 /*
513 * Turn off xmit.
514 */
515 MII_CLR(RL_MII_DIR);
516
517 return(0);
518 }
519
520 static int
rl_miibus_readreg(device_t dev,int phy,int reg)521 rl_miibus_readreg(device_t dev, int phy, int reg)
522 {
523 struct rl_softc *sc;
524 struct rl_mii_frame frame;
525 uint16_t rval = 0;
526 uint16_t rl8139_reg = 0;
527
528 sc = device_get_softc(dev);
529
530 if (sc->rl_type == RL_8139) {
531 /* Pretend the internal PHY is only at address 0 */
532 if (phy)
533 return(0);
534 switch (reg) {
535 case MII_BMCR:
536 rl8139_reg = RL_BMCR;
537 break;
538 case MII_BMSR:
539 rl8139_reg = RL_BMSR;
540 break;
541 case MII_ANAR:
542 rl8139_reg = RL_ANAR;
543 break;
544 case MII_ANER:
545 rl8139_reg = RL_ANER;
546 break;
547 case MII_ANLPAR:
548 rl8139_reg = RL_LPAR;
549 break;
550 case MII_PHYIDR1:
551 case MII_PHYIDR2:
552 return(0);
553 break;
554 /*
555 * Allow the rlphy driver to read the media status
556 * register. If we have a link partner which does not
557 * support NWAY, this is the register which will tell
558 * us the results of parallel detection.
559 */
560 case RL_MEDIASTAT:
561 rval = CSR_READ_1(sc, RL_MEDIASTAT);
562 return(rval);
563 default:
564 device_printf(dev, "bad phy register\n");
565 return(0);
566 }
567 rval = CSR_READ_2(sc, rl8139_reg);
568 return(rval);
569 }
570
571 bzero(&frame, sizeof(frame));
572
573 frame.mii_phyaddr = phy;
574 frame.mii_regaddr = reg;
575 rl_mii_readreg(sc, &frame);
576
577 return(frame.mii_data);
578 }
579
580 static int
rl_miibus_writereg(device_t dev,int phy,int reg,int data)581 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
582 {
583 struct rl_softc *sc;
584 struct rl_mii_frame frame;
585 u_int16_t rl8139_reg = 0;
586
587 sc = device_get_softc(dev);
588
589 if (sc->rl_type == RL_8139) {
590 /* Pretend the internal PHY is only at address 0 */
591 if (phy)
592 return(0);
593 switch (reg) {
594 case MII_BMCR:
595 rl8139_reg = RL_BMCR;
596 break;
597 case MII_BMSR:
598 rl8139_reg = RL_BMSR;
599 break;
600 case MII_ANAR:
601 rl8139_reg = RL_ANAR;
602 break;
603 case MII_ANER:
604 rl8139_reg = RL_ANER;
605 break;
606 case MII_ANLPAR:
607 rl8139_reg = RL_LPAR;
608 break;
609 case MII_PHYIDR1:
610 case MII_PHYIDR2:
611 return(0);
612 default:
613 device_printf(dev, "bad phy register\n");
614 return(0);
615 }
616 CSR_WRITE_2(sc, rl8139_reg, data);
617 return(0);
618 }
619
620 bzero(&frame, sizeof(frame));
621
622 frame.mii_phyaddr = phy;
623 frame.mii_regaddr = reg;
624 frame.mii_data = data;
625
626 rl_mii_writereg(sc, &frame);
627
628 return(0);
629 }
630
631 static void
rl_miibus_statchg(device_t dev)632 rl_miibus_statchg(device_t dev)
633 {
634 }
635
636 /*
637 * Program the 64-bit multicast hash filter.
638 */
639 static void
rl_setmulti(struct rl_softc * sc)640 rl_setmulti(struct rl_softc *sc)
641 {
642 struct ifnet *ifp;
643 int h = 0;
644 uint32_t hashes[2] = { 0, 0 };
645 struct ifmultiaddr *ifma;
646 uint32_t rxfilt;
647 int mcnt = 0;
648
649 ifp = &sc->arpcom.ac_if;
650
651 rxfilt = CSR_READ_4(sc, RL_RXCFG);
652
653 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
654 rxfilt |= RL_RXCFG_RX_MULTI;
655 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
656 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
657 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
658 return;
659 }
660
661 /* first, zot all the existing hash bits */
662 CSR_WRITE_4(sc, RL_MAR0, 0);
663 CSR_WRITE_4(sc, RL_MAR4, 0);
664
665 /* now program new ones */
666 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
667 if (ifma->ifma_addr->sa_family != AF_LINK)
668 continue;
669 h = ether_crc32_be(
670 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
671 ETHER_ADDR_LEN) >> 26;
672 if (h < 32)
673 hashes[0] |= (1 << h);
674 else
675 hashes[1] |= (1 << (h - 32));
676 mcnt++;
677 }
678
679 if (mcnt)
680 rxfilt |= RL_RXCFG_RX_MULTI;
681 else
682 rxfilt &= ~RL_RXCFG_RX_MULTI;
683
684 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
685 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
686 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
687 }
688
689 static void
rl_reset(struct rl_softc * sc)690 rl_reset(struct rl_softc *sc)
691 {
692 int i;
693
694 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
695
696 for (i = 0; i < RL_TIMEOUT; i++) {
697 DELAY(10);
698 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
699 break;
700 }
701 if (i == RL_TIMEOUT)
702 device_printf(sc->rl_dev, "reset never completed!\n");
703 }
704
705 /*
706 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
707 * IDs against our list and return a device name if we find a match.
708 *
709 * Return with a value < 0 to give re(4) a change to attach.
710 */
711 static int
rl_probe(device_t dev)712 rl_probe(device_t dev)
713 {
714 struct rl_type *t;
715 uint16_t product = pci_get_device(dev);
716 uint16_t vendor = pci_get_vendor(dev);
717
718 for (t = rl_devs; t->rl_name != NULL; t++) {
719 if (vendor == t->rl_vid && product == t->rl_did) {
720 device_set_desc(dev, t->rl_name);
721 return(-100);
722 }
723 }
724
725 return(ENXIO);
726 }
727
728 /*
729 * Attach the interface. Allocate softc structures, do ifmedia
730 * setup and ethernet/BPF attach.
731 */
732 static int
rl_attach(device_t dev)733 rl_attach(device_t dev)
734 {
735 uint8_t eaddr[ETHER_ADDR_LEN];
736 uint16_t as[3];
737 struct rl_softc *sc;
738 struct ifnet *ifp;
739 uint16_t rl_did = 0;
740 int error = 0, rid, i;
741
742 sc = device_get_softc(dev);
743 sc->rl_dev = dev;
744
745 /*
746 * Handle power management nonsense.
747 */
748
749 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
750 uint32_t iobase, membase, irq;
751
752 /* Save important PCI config data. */
753 iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
754 membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
755 irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
756
757 /* Reset the power state. */
758 device_printf(dev, "chip is in D%d power mode "
759 "-- setting to D0\n", pci_get_powerstate(dev));
760 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
761
762 /* Restore PCI config data. */
763 pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
764 pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
765 pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
766 }
767
768 pci_enable_busmaster(dev);
769
770 rid = RL_RID;
771 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
772
773 if (sc->rl_res == NULL) {
774 device_printf(dev, "couldn't map ports/memory\n");
775 error = ENXIO;
776 goto fail;
777 }
778
779 sc->rl_btag = rman_get_bustag(sc->rl_res);
780 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
781
782 rid = 0;
783 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
784 RF_SHAREABLE | RF_ACTIVE);
785
786 if (sc->rl_irq == NULL) {
787 device_printf(dev, "couldn't map interrupt\n");
788 error = ENXIO;
789 goto fail;
790 }
791
792 callout_init(&sc->rl_stat_timer);
793
794 /* Reset the adapter. */
795 rl_reset(sc);
796
797 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
798 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
799 if (rl_did != 0x8129)
800 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
801
802 /*
803 * Get station address from the EEPROM.
804 */
805 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0);
806 for (i = 0; i < 3; i++) {
807 eaddr[(i * 2) + 0] = as[i] & 0xff;
808 eaddr[(i * 2) + 1] = as[i] >> 8;
809 }
810
811 /*
812 * Now read the exact device type from the EEPROM to find
813 * out if it's an 8129 or 8139.
814 */
815 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
816
817 if (rl_did == PCI_PRODUCT_REALTEK_RT8139 ||
818 rl_did == PCI_PRODUCT_ACCTON_MPX5030 ||
819 rl_did == PCI_PRODUCT_DELTA_8139 ||
820 rl_did == PCI_PRODUCT_ADDTRON_8139 ||
821 rl_did == PCI_PRODUCT_DLINK_DFE530TXPLUS ||
822 rl_did == PCI_PRODUCT_REALTEK_RT8139B ||
823 rl_did == PCI_PRODUCT_DLINK_DFE690TXD ||
824 rl_did == PCI_PRODUCT_COREGA_CB_TXD ||
825 rl_did == PCI_PRODUCT_COREGA_2CB_TXD ||
826 rl_did == PCI_PRODUCT_PLANEX_FNW_3800_TX) {
827 sc->rl_type = RL_8139;
828 } else if (rl_did == PCI_PRODUCT_REALTEK_RT8129) {
829 sc->rl_type = RL_8129;
830 } else {
831 device_printf(dev, "unknown device ID: %x\n", rl_did);
832 sc->rl_type = RL_8139;
833 /*
834 * Read RL_IDR register to get ethernet address as accessing
835 * EEPROM may not extract correct address.
836 */
837 for (i = 0; i < ETHER_ADDR_LEN; i++)
838 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
839 }
840
841 error = rl_dma_alloc(sc);
842 if (error)
843 goto fail;
844
845 /* Do MII setup */
846 if (mii_phy_probe(dev, &sc->rl_miibus, rl_ifmedia_upd,
847 rl_ifmedia_sts)) {
848 device_printf(dev, "MII without any phy!\n");
849 error = ENXIO;
850 goto fail;
851 }
852
853 ifp = &sc->arpcom.ac_if;
854 ifp->if_softc = sc;
855 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
856 ifp->if_mtu = ETHERMTU;
857 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
858 ifp->if_ioctl = rl_ioctl;
859 ifp->if_start = rl_start;
860 ifp->if_watchdog = rl_watchdog;
861 ifp->if_init = rl_init;
862 ifp->if_baudrate = 10000000;
863 ifp->if_capabilities = IFCAP_VLAN_MTU;
864 #ifdef IFPOLL_ENABLE
865 ifp->if_npoll = rl_npoll;
866 #endif
867 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
868 ifq_set_ready(&ifp->if_snd);
869
870 /*
871 * Call MI attach routine.
872 */
873 ether_ifattach(ifp, eaddr, NULL);
874
875 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->rl_irq));
876
877 #ifdef IFPOLL_ENABLE
878 ifpoll_compat_setup(&sc->rl_npoll, NULL, NULL, device_get_unit(dev),
879 ifp->if_serializer);
880 #endif
881
882 error = bus_setup_intr(dev, sc->rl_irq, INTR_MPSAFE, rl_intr,
883 sc, &sc->rl_intrhand, ifp->if_serializer);
884
885 if (error) {
886 device_printf(dev, "couldn't set up irq\n");
887 ether_ifdetach(ifp);
888 goto fail;
889 }
890
891 return(0);
892
893 fail:
894 rl_detach(dev);
895 return(error);
896 }
897
898 static int
rl_detach(device_t dev)899 rl_detach(device_t dev)
900 {
901 struct rl_softc *sc;
902 struct ifnet *ifp;
903
904 sc = device_get_softc(dev);
905 ifp = &sc->arpcom.ac_if;
906
907 if (device_is_attached(dev)) {
908 lwkt_serialize_enter(ifp->if_serializer);
909 rl_stop(sc);
910 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
911 lwkt_serialize_exit(ifp->if_serializer);
912
913 ether_ifdetach(ifp);
914 }
915
916 if (sc->rl_miibus)
917 device_delete_child(dev, sc->rl_miibus);
918 bus_generic_detach(dev);
919
920 if (sc->rl_irq)
921 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
922 if (sc->rl_res)
923 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
924
925 rl_dma_free(sc);
926
927 return(0);
928 }
929
930 /*
931 * Initialize the transmit descriptors.
932 */
933 static void
rl_list_tx_init(struct rl_softc * sc)934 rl_list_tx_init(struct rl_softc *sc)
935 {
936 struct rl_chain_data *cd;
937 int i;
938
939 cd = &sc->rl_cdata;
940 for (i = 0; i < RL_TX_LIST_CNT; i++) {
941 cd->rl_tx_chain[i] = NULL;
942 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
943 0x0000000);
944 }
945
946 sc->rl_cdata.cur_tx = 0;
947 sc->rl_cdata.last_tx = 0;
948 }
949
950 /*
951 * A frame has been uploaded: pass the resulting mbuf chain up to
952 * the higher level protocols.
953 *
954 * You know there's something wrong with a PCI bus-master chip design
955 * when you have to use m_devget().
956 *
957 * The receive operation is badly documented in the datasheet, so I'll
958 * attempt to document it here. The driver provides a buffer area and
959 * places its base address in the RX buffer start address register.
960 * The chip then begins copying frames into the RX buffer. Each frame
961 * is preceded by a 32-bit RX status word which specifies the length
962 * of the frame and certain other status bits. Each frame (starting with
963 * the status word) is also 32-bit aligned. The frame length is in the
964 * first 16 bits of the status word; the lower 15 bits correspond with
965 * the 'rx status register' mentioned in the datasheet.
966 *
967 * Note: to make the Alpha happy, the frame payload needs to be aligned
968 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from
969 * the ring buffer starting at an address two bytes before the actual
970 * data location. We can then shave off the first two bytes using m_adj().
971 * The reason we do this is because m_devget() doesn't let us specify an
972 * offset into the mbuf storage space, so we have to artificially create
973 * one. The ring is allocated in such a way that there are a few unused
974 * bytes of space preceecing it so that it will be safe for us to do the
975 * 2-byte backstep even if reading from the ring at offset 0.
976 */
977 static void
rl_rxeof(struct rl_softc * sc)978 rl_rxeof(struct rl_softc *sc)
979 {
980 struct mbuf *m;
981 struct ifnet *ifp;
982 int total_len = 0;
983 uint32_t rxstat;
984 caddr_t rxbufpos;
985 int wrap = 0, done = 0;
986 uint16_t cur_rx = 0, max_bytes = 0, rx_bytes = 0;
987
988 ifp = &sc->arpcom.ac_if;
989
990 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
991 if (!done) {
992 uint16_t limit;
993
994 done = 1;
995
996 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) %
997 RL_RXBUFLEN;
998
999 /* Do not try to read past this point. */
1000 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1001 if (limit < cur_rx)
1002 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1003 else
1004 max_bytes = limit - cur_rx;
1005 }
1006 #ifdef IFPOLL_ENABLE
1007 if (ifp->if_flags & IFF_NPOLLING) {
1008 if (sc->rxcycles <= 0)
1009 break;
1010 sc->rxcycles--;
1011 }
1012 #endif /* IFPOLL_ENABLE */
1013 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1014 rxstat = le32toh(*(uint32_t *)rxbufpos);
1015
1016 /*
1017 * Here's a totally undocumented fact for you. When the
1018 * RealTek chip is in the process of copying a packet into
1019 * RAM for you, the length will be 0xfff0. If you spot a
1020 * packet header with this value, you need to stop. The
1021 * datasheet makes absolutely no mention of this and
1022 * RealTek should be shot for this.
1023 */
1024 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1025 break;
1026
1027 if ((rxstat & RL_RXSTAT_RXOK) == 0) {
1028 IFNET_STAT_INC(ifp, ierrors, 1);
1029 rl_init(sc);
1030 return;
1031 }
1032
1033 /* No errors; receive the packet. */
1034 total_len = rxstat >> 16;
1035 rx_bytes += total_len + 4;
1036
1037 /*
1038 * XXX The RealTek chip includes the CRC with every
1039 * received frame, and there's no way to turn this
1040 * behavior off (at least, I can't find anything in
1041 * the manual that explains how to do it) so we have
1042 * to trim off the CRC manually.
1043 */
1044 total_len -= ETHER_CRC_LEN;
1045
1046 /*
1047 * Avoid trying to read more bytes than we know
1048 * the chip has prepared for us.
1049 */
1050 if (rx_bytes > max_bytes)
1051 break;
1052
1053 rxbufpos = sc->rl_cdata.rl_rx_buf +
1054 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1055
1056 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1057 rxbufpos = sc->rl_cdata.rl_rx_buf;
1058
1059 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1060
1061 if (total_len > wrap) {
1062 /*
1063 * Fool m_devget() into thinking we want to copy
1064 * the whole buffer so we don't end up fragmenting
1065 * the data.
1066 */
1067 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1068 wrap + RL_ETHER_ALIGN, 0, ifp);
1069 if (m == NULL) {
1070 IFNET_STAT_INC(ifp, ierrors, 1);
1071 } else {
1072 m_adj(m, RL_ETHER_ALIGN);
1073 m_copyback(m, wrap, total_len - wrap,
1074 sc->rl_cdata.rl_rx_buf);
1075 }
1076 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1077 } else {
1078 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1079 total_len + RL_ETHER_ALIGN, 0, ifp);
1080 if (m == NULL) {
1081 IFNET_STAT_INC(ifp, ierrors, 1);
1082 } else
1083 m_adj(m, RL_ETHER_ALIGN);
1084 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1085 }
1086
1087 /*
1088 * Round up to 32-bit boundary.
1089 */
1090 cur_rx = (cur_rx + 3) & ~3;
1091 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1092
1093 if (m == NULL)
1094 continue;
1095
1096 IFNET_STAT_INC(ifp, ipackets, 1);
1097
1098 ifp->if_input(ifp, m, NULL, -1);
1099 }
1100 }
1101
1102 /*
1103 * A frame was downloaded to the chip. It's safe for us to clean up
1104 * the list buffers.
1105 */
1106 static void
rl_txeof(struct rl_softc * sc)1107 rl_txeof(struct rl_softc *sc)
1108 {
1109 struct ifnet *ifp;
1110 uint32_t txstat;
1111
1112 ifp = &sc->arpcom.ac_if;
1113
1114 /*
1115 * Go through our tx list and free mbufs for those
1116 * frames that have been uploaded.
1117 */
1118 do {
1119 if (RL_LAST_TXMBUF(sc) == NULL)
1120 break;
1121 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1122 if ((txstat & (RL_TXSTAT_TX_OK | RL_TXSTAT_TX_UNDERRUN |
1123 RL_TXSTAT_TXABRT)) == 0)
1124 break;
1125
1126 IFNET_STAT_INC(ifp, collisions,
1127 (txstat & RL_TXSTAT_COLLCNT) >> 24);
1128
1129 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc));
1130 m_freem(RL_LAST_TXMBUF(sc));
1131 RL_LAST_TXMBUF(sc) = NULL;
1132 RL_INC(sc->rl_cdata.last_tx);
1133
1134 if (txstat & RL_TXSTAT_TX_UNDERRUN) {
1135 sc->rl_txthresh += 32;
1136 if (sc->rl_txthresh > RL_TX_THRESH_MAX)
1137 sc->rl_txthresh = RL_TX_THRESH_MAX;
1138 }
1139
1140 if (txstat & RL_TXSTAT_TX_OK) {
1141 IFNET_STAT_INC(ifp, opackets, 1);
1142 } else {
1143 IFNET_STAT_INC(ifp, oerrors, 1);
1144 if (txstat & (RL_TXSTAT_TXABRT | RL_TXSTAT_OUTOFWIN))
1145 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1146 }
1147 ifq_clr_oactive(&ifp->if_snd);
1148 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1149
1150 if (RL_LAST_TXMBUF(sc) == NULL)
1151 ifp->if_timer = 0;
1152 else if (ifp->if_timer == 0)
1153 ifp->if_timer = 5;
1154 }
1155
1156 static void
rl_tick(void * xsc)1157 rl_tick(void *xsc)
1158 {
1159 struct rl_softc *sc = xsc;
1160 struct mii_data *mii;
1161
1162 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1163
1164 mii = device_get_softc(sc->rl_miibus);
1165 mii_tick(mii);
1166
1167 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc);
1168
1169 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1170 }
1171
1172 #ifdef IFPOLL_ENABLE
1173
1174 static void
rl_npoll_compat(struct ifnet * ifp,void * arg __unused,int count)1175 rl_npoll_compat(struct ifnet *ifp, void *arg __unused, int count)
1176 {
1177 struct rl_softc *sc = ifp->if_softc;
1178
1179 ASSERT_SERIALIZED(ifp->if_serializer);
1180
1181 sc->rxcycles = count;
1182 rl_rxeof(sc);
1183 rl_txeof(sc);
1184 if (!ifq_is_empty(&ifp->if_snd))
1185 if_devstart(ifp);
1186
1187 if (sc->rl_npoll.ifpc_stcount-- == 0) {
1188 uint16_t status;
1189
1190 sc->rl_npoll.ifpc_stcount = sc->rl_npoll.ifpc_stfrac;
1191
1192 status = CSR_READ_2(sc, RL_ISR);
1193 if (status == 0xffff)
1194 return;
1195 if (status)
1196 CSR_WRITE_2(sc, RL_ISR, status);
1197
1198 /*
1199 * XXX check behaviour on receiver stalls.
1200 */
1201
1202 if (status & RL_ISR_SYSTEM_ERR) {
1203 rl_reset(sc);
1204 rl_init(sc);
1205 }
1206 }
1207 }
1208
1209 static void
rl_npoll(struct ifnet * ifp,struct ifpoll_info * info)1210 rl_npoll(struct ifnet *ifp, struct ifpoll_info *info)
1211 {
1212 struct rl_softc *sc = ifp->if_softc;
1213
1214 ASSERT_SERIALIZED(ifp->if_serializer);
1215
1216 if (info != NULL) {
1217 int cpuid = sc->rl_npoll.ifpc_cpuid;
1218
1219 info->ifpi_rx[cpuid].poll_func = rl_npoll_compat;
1220 info->ifpi_rx[cpuid].arg = NULL;
1221 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
1222
1223 if (ifp->if_flags & IFF_RUNNING) {
1224 /* disable interrupts */
1225 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1226 sc->rl_npoll.ifpc_stcount = 0;
1227 }
1228 ifq_set_cpuid(&ifp->if_snd, cpuid);
1229 } else {
1230 if (ifp->if_flags & IFF_RUNNING) {
1231 /* enable interrupts */
1232 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1233 }
1234 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->rl_irq));
1235 }
1236 }
1237
1238 #endif /* IFPOLL_ENABLE */
1239
1240 static void
rl_intr(void * arg)1241 rl_intr(void *arg)
1242 {
1243 struct rl_softc *sc;
1244 struct ifnet *ifp;
1245 uint16_t status;
1246
1247 sc = arg;
1248
1249 if (sc->suspended)
1250 return;
1251
1252 ifp = &sc->arpcom.ac_if;
1253
1254 for (;;) {
1255 status = CSR_READ_2(sc, RL_ISR);
1256 /* If the card has gone away, the read returns 0xffff. */
1257 if (status == 0xffff)
1258 break;
1259
1260 if (status != 0)
1261 CSR_WRITE_2(sc, RL_ISR, status);
1262
1263 if ((status & RL_INTRS) == 0)
1264 break;
1265
1266 if (status & RL_ISR_RX_OK)
1267 rl_rxeof(sc);
1268
1269 if (status & RL_ISR_RX_ERR)
1270 rl_rxeof(sc);
1271
1272 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1273 rl_txeof(sc);
1274
1275 if (status & RL_ISR_SYSTEM_ERR) {
1276 rl_reset(sc);
1277 rl_init(sc);
1278 }
1279
1280 }
1281
1282 if (!ifq_is_empty(&ifp->if_snd))
1283 if_devstart(ifp);
1284 }
1285
1286 /*
1287 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1288 * pointers to the fragment pointers.
1289 */
1290 static int
rl_encap(struct rl_softc * sc,struct mbuf * m_head)1291 rl_encap(struct rl_softc *sc, struct mbuf *m_head)
1292 {
1293 struct mbuf *m_new = NULL;
1294 bus_dma_segment_t seg;
1295 int nseg, error;
1296
1297 /*
1298 * The RealTek is brain damaged and wants longword-aligned
1299 * TX buffers, plus we can only have one fragment buffer
1300 * per packet. We have to copy pretty much all the time.
1301 */
1302 m_new = m_defrag(m_head, M_NOWAIT);
1303 if (m_new == NULL) {
1304 m_freem(m_head);
1305 return ENOBUFS;
1306 }
1307 m_head = m_new;
1308
1309 /* Pad frames to at least 60 bytes. */
1310 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1311 error = m_devpad(m_head, RL_MIN_FRAMELEN);
1312 if (error) {
1313 m_freem(m_head);
1314 return error;
1315 }
1316 }
1317
1318 /* Extract physical address. */
1319 error = bus_dmamap_load_mbuf_segment(sc->rl_cdata.rl_tx_tag,
1320 RL_CUR_DMAMAP(sc), m_head,
1321 &seg, 1, &nseg, BUS_DMA_NOWAIT);
1322 if (error) {
1323 m_freem(m_head);
1324 return error;
1325 }
1326
1327 /* Sync the loaded TX buffer. */
1328 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc),
1329 BUS_DMASYNC_PREWRITE);
1330
1331 /* Transmit */
1332 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), seg.ds_addr);
1333 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1334 RL_TXTHRESH(sc->rl_txthresh) | seg.ds_len);
1335
1336 RL_CUR_TXMBUF(sc) = m_head;
1337 return 0;
1338 }
1339
1340 /*
1341 * Main transmit routine.
1342 */
1343
1344 static void
rl_start(struct ifnet * ifp,struct ifaltq_subque * ifsq)1345 rl_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1346 {
1347 struct rl_softc *sc = ifp->if_softc;
1348 struct mbuf *m_head = NULL;
1349
1350 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1351
1352 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1353 return;
1354
1355 while (RL_CUR_TXMBUF(sc) == NULL) {
1356 m_head = ifq_dequeue(&ifp->if_snd);
1357 if (m_head == NULL)
1358 break;
1359
1360 if (rl_encap(sc, m_head))
1361 continue;
1362
1363 /*
1364 * If there's a BPF listener, bounce a copy of this frame
1365 * to him.
1366 */
1367 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1368
1369 RL_INC(sc->rl_cdata.cur_tx);
1370
1371 /*
1372 * Set a timeout in case the chip goes out to lunch.
1373 */
1374 ifp->if_timer = 5;
1375 }
1376
1377 /*
1378 * We broke out of the loop because all our TX slots are
1379 * full. Mark the NIC as busy until it drains some of the
1380 * packets from the queue.
1381 */
1382 if (RL_CUR_TXMBUF(sc) != NULL)
1383 ifq_set_oactive(&ifp->if_snd);
1384 }
1385
1386 static void
rl_init(void * xsc)1387 rl_init(void *xsc)
1388 {
1389 struct rl_softc *sc = xsc;
1390 struct ifnet *ifp = &sc->arpcom.ac_if;
1391 struct mii_data *mii;
1392 uint32_t rxcfg = 0;
1393
1394 mii = device_get_softc(sc->rl_miibus);
1395
1396 /*
1397 * Cancel pending I/O and free all RX/TX buffers.
1398 */
1399 rl_stop(sc);
1400
1401 /*
1402 * Init our MAC address. Even though the chipset documentation
1403 * doesn't mention it, we need to enter "Config register write enable"
1404 * mode to modify the ID registers.
1405 */
1406 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1407 CSR_WRITE_STREAM_4(sc, RL_IDR0,
1408 *(uint32_t *)(&sc->arpcom.ac_enaddr[0]));
1409 CSR_WRITE_STREAM_4(sc, RL_IDR4,
1410 *(uint32_t *)(&sc->arpcom.ac_enaddr[4]));
1411 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1412
1413 /* Init the RX buffer pointer register. */
1414 CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr);
1415
1416 /* Init TX descriptors. */
1417 rl_list_tx_init(sc);
1418
1419 /*
1420 * Enable transmit and receive.
1421 */
1422 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1423
1424 /*
1425 * Set the initial TX and RX configuration.
1426 */
1427 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1428 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1429
1430 /* Set the individual bit to receive frames for this host only. */
1431 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1432 rxcfg |= RL_RXCFG_RX_INDIV;
1433
1434 /* If we want promiscuous mode, set the allframes bit. */
1435 if (ifp->if_flags & IFF_PROMISC) {
1436 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1437 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1438 } else {
1439 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1440 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1441 }
1442
1443 /*
1444 * Set capture broadcast bit to capture broadcast frames.
1445 */
1446 if (ifp->if_flags & IFF_BROADCAST) {
1447 rxcfg |= RL_RXCFG_RX_BROAD;
1448 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1449 } else {
1450 rxcfg &= ~RL_RXCFG_RX_BROAD;
1451 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1452 }
1453
1454 /*
1455 * Program the multicast filter, if necessary.
1456 */
1457 rl_setmulti(sc);
1458
1459 #ifdef IFPOLL_ENABLE
1460 /*
1461 * Only enable interrupts if we are polling, keep them off otherwise.
1462 */
1463 if (ifp->if_flags & IFF_NPOLLING) {
1464 CSR_WRITE_2(sc, RL_IMR, 0);
1465 sc->rl_npoll.ifpc_stcount = 0;
1466 } else
1467 #endif /* IFPOLL_ENABLE */
1468 /*
1469 * Enable interrupts.
1470 */
1471 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1472
1473 /* Set initial TX threshold */
1474 sc->rl_txthresh = RL_TX_THRESH_INIT;
1475
1476 /* Start RX/TX process. */
1477 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1478
1479 /* Enable receiver and transmitter. */
1480 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1481
1482 mii_mediachg(mii);
1483
1484 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1485
1486 ifp->if_flags |= IFF_RUNNING;
1487 ifq_clr_oactive(&ifp->if_snd);
1488
1489 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc);
1490 }
1491
1492 /*
1493 * Set media options.
1494 */
1495 static int
rl_ifmedia_upd(struct ifnet * ifp)1496 rl_ifmedia_upd(struct ifnet *ifp)
1497 {
1498 struct rl_softc *sc;
1499 struct mii_data *mii;
1500
1501 sc = ifp->if_softc;
1502 mii = device_get_softc(sc->rl_miibus);
1503 mii_mediachg(mii);
1504
1505 return(0);
1506 }
1507
1508 /*
1509 * Report current media status.
1510 */
1511 static void
rl_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)1512 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1513 {
1514 struct rl_softc *sc = ifp->if_softc;
1515 struct mii_data *mii = device_get_softc(sc->rl_miibus);
1516
1517 mii_pollstat(mii);
1518 ifmr->ifm_active = mii->mii_media_active;
1519 ifmr->ifm_status = mii->mii_media_status;
1520 }
1521
1522 static int
rl_ioctl(struct ifnet * ifp,u_long command,caddr_t data,struct ucred * cr)1523 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1524 {
1525 struct rl_softc *sc = ifp->if_softc;
1526 struct ifreq *ifr = (struct ifreq *) data;
1527 struct mii_data *mii;
1528 int error = 0;
1529
1530 switch (command) {
1531 case SIOCSIFFLAGS:
1532 if (ifp->if_flags & IFF_UP) {
1533 rl_init(sc);
1534 } else {
1535 if (ifp->if_flags & IFF_RUNNING)
1536 rl_stop(sc);
1537 }
1538 error = 0;
1539 break;
1540 case SIOCADDMULTI:
1541 case SIOCDELMULTI:
1542 rl_setmulti(sc);
1543 error = 0;
1544 break;
1545 case SIOCGIFMEDIA:
1546 case SIOCSIFMEDIA:
1547 mii = device_get_softc(sc->rl_miibus);
1548 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1549 break;
1550 case SIOCSIFCAP:
1551 break;
1552 default:
1553 error = ether_ioctl(ifp, command, data);
1554 break;
1555 }
1556
1557 return(error);
1558 }
1559
1560 static void
rl_watchdog(struct ifnet * ifp)1561 rl_watchdog(struct ifnet *ifp)
1562 {
1563 struct rl_softc *sc = ifp->if_softc;
1564
1565 device_printf(sc->rl_dev, "watchdog timeout\n");
1566
1567 IFNET_STAT_INC(ifp, oerrors, 1);
1568
1569 rl_txeof(sc);
1570 rl_rxeof(sc);
1571 rl_init(sc);
1572 }
1573
1574 /*
1575 * Stop the adapter and free any mbufs allocated to the
1576 * RX and TX lists.
1577 */
1578 static void
rl_stop(struct rl_softc * sc)1579 rl_stop(struct rl_softc *sc)
1580 {
1581 struct ifnet *ifp = &sc->arpcom.ac_if;
1582 int i;
1583
1584 ifp->if_timer = 0;
1585
1586 callout_stop(&sc->rl_stat_timer);
1587 ifp->if_flags &= ~IFF_RUNNING;
1588 ifq_clr_oactive(&ifp->if_snd);
1589
1590 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1591 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1592
1593 /*
1594 * Free the TX list buffers.
1595 */
1596 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1597 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1598 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag,
1599 sc->rl_cdata.rl_tx_dmamap[i]);
1600 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1601 sc->rl_cdata.rl_tx_chain[i] = NULL;
1602 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1603 0x0000000);
1604 }
1605 }
1606 }
1607
1608 /*
1609 * Stop all chip I/O so that the kernel's probe routines don't
1610 * get confused by errant DMAs when rebooting.
1611 */
1612 static void
rl_shutdown(device_t dev)1613 rl_shutdown(device_t dev)
1614 {
1615 struct rl_softc *sc;
1616
1617 sc = device_get_softc(dev);
1618 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1619 rl_stop(sc);
1620 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1621 }
1622
1623 /*
1624 * Device suspend routine. Stop the interface and save some PCI
1625 * settings in case the BIOS doesn't restore them properly on
1626 * resume.
1627 */
1628 static int
rl_suspend(device_t dev)1629 rl_suspend(device_t dev)
1630 {
1631 struct rl_softc *sc = device_get_softc(dev);
1632 int i;
1633
1634 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1635 rl_stop(sc);
1636
1637 for (i = 0; i < 5; i++)
1638 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
1639 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
1640 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
1641 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
1642 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
1643
1644 sc->suspended = 1;
1645
1646 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1647 return (0);
1648 }
1649
1650 /*
1651 * Device resume routine. Restore some PCI settings in case the BIOS
1652 * doesn't, re-enable busmastering, and restart the interface if
1653 * appropriate.
1654 */
1655 static int
rl_resume(device_t dev)1656 rl_resume(device_t dev)
1657 {
1658 struct rl_softc *sc = device_get_softc(dev);
1659 struct ifnet *ifp = &sc->arpcom.ac_if;
1660 int i;
1661
1662 lwkt_serialize_enter(ifp->if_serializer);
1663
1664 /* better way to do this? */
1665 for (i = 0; i < 5; i++)
1666 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
1667 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
1668 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
1669 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
1670 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
1671
1672 /* reenable busmastering */
1673 pci_enable_busmaster(dev);
1674 pci_enable_io(dev, RL_RES);
1675
1676 /* reinitialize interface if necessary */
1677 if (ifp->if_flags & IFF_UP)
1678 rl_init(sc);
1679
1680 sc->suspended = 0;
1681 lwkt_serialize_exit(ifp->if_serializer);
1682 return (0);
1683 }
1684
1685 static int
rl_dma_alloc(struct rl_softc * sc)1686 rl_dma_alloc(struct rl_softc *sc)
1687 {
1688 bus_dmamem_t dmem;
1689 int error, i;
1690
1691 error = bus_dma_tag_create(NULL, /* parent */
1692 1, 0, /* alignment, boundary */
1693 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1694 BUS_SPACE_MAXADDR, /* highaddr */
1695 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
1696 0, /* nsegments */
1697 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1698 0, /* flags */
1699 &sc->rl_parent_tag);
1700 if (error) {
1701 device_printf(sc->rl_dev, "can't create parent tag\n");
1702 return error;
1703 }
1704
1705 /* Allocate a chunk of coherent memory for RX */
1706 error = bus_dmamem_coherent(sc->rl_parent_tag, 1, 0,
1707 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1708 RL_RXBUFLEN + 1518, BUS_DMA_WAITOK, &dmem);
1709 if (error)
1710 return error;
1711
1712 sc->rl_cdata.rl_rx_tag = dmem.dmem_tag;
1713 sc->rl_cdata.rl_rx_dmamap = dmem.dmem_map;
1714 sc->rl_cdata.rl_rx_buf_ptr = dmem.dmem_addr;
1715
1716 /* NOTE: Apply same adjustment to vaddr and paddr */
1717 sc->rl_cdata.rl_rx_buf = sc->rl_cdata.rl_rx_buf_ptr + sizeof(uint64_t);
1718 sc->rl_cdata.rl_rx_buf_paddr = dmem.dmem_busaddr + sizeof(uint64_t);
1719
1720 /*
1721 * Allocate TX mbuf's DMA tag and maps
1722 */
1723 error = bus_dma_tag_create(sc->rl_parent_tag,/* parent */
1724 RL_TXBUF_ALIGN, 0, /* alignment, boundary */
1725 BUS_SPACE_MAXADDR, /* lowaddr */
1726 BUS_SPACE_MAXADDR, /* highaddr */
1727 MCLBYTES, /* maxsize */
1728 1, /* nsegments */
1729 MCLBYTES, /* maxsegsize */
1730 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
1731 BUS_DMA_ALIGNED, /* flags */
1732 &sc->rl_cdata.rl_tx_tag);
1733 if (error) {
1734 device_printf(sc->rl_dev, "can't create TX mbuf tag\n");
1735 return error;
1736 }
1737
1738 for (i = 0; i < RL_TX_LIST_CNT; ++i) {
1739 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag,
1740 BUS_DMA_WAITOK, &sc->rl_cdata.rl_tx_dmamap[i]);
1741 if (error) {
1742 int j;
1743
1744 for (j = 0; j < i; ++j) {
1745 bus_dmamap_destroy(sc->rl_cdata.rl_tx_tag,
1746 sc->rl_cdata.rl_tx_dmamap[j]);
1747 }
1748 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag);
1749 sc->rl_cdata.rl_tx_tag = NULL;
1750
1751 device_printf(sc->rl_dev, "can't create TX mbuf map\n");
1752 return error;
1753 }
1754 }
1755 return 0;
1756 }
1757
1758 static void
rl_dma_free(struct rl_softc * sc)1759 rl_dma_free(struct rl_softc *sc)
1760 {
1761 if (sc->rl_cdata.rl_tx_tag != NULL) {
1762 int i;
1763
1764 for (i = 0; i < RL_TX_LIST_CNT; ++i) {
1765 bus_dmamap_destroy(sc->rl_cdata.rl_tx_tag,
1766 sc->rl_cdata.rl_tx_dmamap[i]);
1767 }
1768 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag);
1769 }
1770
1771 if (sc->rl_cdata.rl_rx_tag != NULL) {
1772 bus_dmamap_unload(sc->rl_cdata.rl_rx_tag,
1773 sc->rl_cdata.rl_rx_dmamap);
1774 /* NOTE: Use rl_rx_buf_ptr here */
1775 bus_dmamem_free(sc->rl_cdata.rl_rx_tag,
1776 sc->rl_cdata.rl_rx_buf_ptr,
1777 sc->rl_cdata.rl_rx_dmamap);
1778 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag);
1779 }
1780
1781 if (sc->rl_parent_tag)
1782 bus_dma_tag_destroy(sc->rl_parent_tag);
1783 }
1784