xref: /netbsd/sys/arch/arm/s3c2xx0/s3c2xx0_intr.c (revision 71034770)
1 /* $NetBSD: s3c2xx0_intr.c,v 1.19 2022/09/27 06:36:43 skrll Exp $ */
2 
3 /*
4  * Copyright (c) 2002, 2003 Fujitsu Component Limited
5  * Copyright (c) 2002, 2003 Genetec Corporation
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. Neither the name of The Fujitsu Component Limited nor the name of
17  *    Genetec corporation may not be used to endorse or promote products
18  *    derived from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
21  * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
22  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24  * DISCLAIMED.  IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
25  * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
29  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32  * SUCH DAMAGE.
33  */
34 
35 /*
36  * Common part of IRQ handlers for Samsung S3C2800/2400/2410 processors.
37  * derived from i80321_icu.c
38  */
39 
40 /*
41  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
42  * All rights reserved.
43  *
44  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
45  *
46  * Redistribution and use in source and binary forms, with or without
47  * modification, are permitted provided that the following conditions
48  * are met:
49  * 1. Redistributions of source code must retain the above copyright
50  *    notice, this list of conditions and the following disclaimer.
51  * 2. Redistributions in binary form must reproduce the above copyright
52  *    notice, this list of conditions and the following disclaimer in the
53  *    documentation and/or other materials provided with the distribution.
54  * 3. All advertising materials mentioning features or use of this software
55  *    must display the following acknowledgement:
56  *	This product includes software developed for the NetBSD Project by
57  *	Wasabi Systems, Inc.
58  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
59  *    or promote products derived from this software without specific prior
60  *    written permission.
61  *
62  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
63  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
64  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
65  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
66  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
67  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
68  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
69  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
70  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
71  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
72  * POSSIBILITY OF SUCH DAMAGE.
73  */
74 
75 #include <sys/cdefs.h>
76 __KERNEL_RCSID(0, "$NetBSD: s3c2xx0_intr.c,v 1.19 2022/09/27 06:36:43 skrll Exp $");
77 
78 #include <sys/param.h>
79 #include <sys/systm.h>
80 
81 #include <sys/bus.h>
82 #include <machine/intr.h>
83 
84 #include <arm/cpufunc.h>
85 
86 #include <arm/s3c2xx0/s3c2xx0reg.h>
87 #include <arm/s3c2xx0/s3c2xx0var.h>
88 
89 volatile uint32_t *s3c2xx0_intr_mask_reg;
90 
91 /*
92  * modify interrupt mask table for SPL levels
93  */
94 void
s3c2xx0_update_intr_masks(int irqno,int level)95 s3c2xx0_update_intr_masks(int irqno, int level)
96 {
97 	int mask = 1 << irqno;
98 	int i;
99 
100 
101 	s3c2xx0_ilevel[irqno] = level;
102 
103 	for (i = 0; i < level; ++i)
104 		s3c2xx0_imask[i] |= mask;	/* Enable interrupt at lower
105 						 * level */
106 	for (; i < NIPL - 1; ++i)
107 		s3c2xx0_imask[i] &= ~mask;	/* Disable interrupt at upper
108 						 * level */
109 
110 	/*
111 	 * Enforce a hierarchy that gives "slow" device (or devices with
112 	 * limited input buffer space/"real-time" requirements) a better
113 	 * chance at not dropping data.
114 	 */
115 	s3c2xx0_imask[IPL_VM] &= s3c2xx0_imask[IPL_SOFTSERIAL];
116 	s3c2xx0_imask[IPL_CLOCK] &= s3c2xx0_imask[IPL_VM];
117 	s3c2xx0_imask[IPL_HIGH] &= s3c2xx0_imask[IPL_CLOCK];
118 }
119 
120 static int
stray_interrupt(void * cookie)121 stray_interrupt(void *cookie)
122 {
123 	int save;
124 	int irqno = (int) cookie;
125 	printf("stray interrupt %d\n", irqno);
126 
127 	save = disable_interrupts(I32_bit);
128 	*s3c2xx0_intr_mask_reg &= ~(1U << irqno);
129 	restore_interrupts(save);
130 
131 	return 0;
132 }
133 /*
134  * Initialize interrupt dispatcher.
135  */
136 void
s3c2xx0_intr_init(struct s3c2xx0_intr_dispatch * dispatch_table,int icu_len)137 s3c2xx0_intr_init(struct s3c2xx0_intr_dispatch * dispatch_table, int icu_len)
138 {
139 	int i;
140 
141 	for (i = 0; i < icu_len; ++i) {
142 		dispatch_table[i].func = stray_interrupt;
143 		dispatch_table[i].cookie = (void *) (i);
144 		dispatch_table[i].level = IPL_VM;
145 		snprintf(dispatch_table[i].name,
146 		    sizeof(dispatch_table[i].name), "irq %d", i);
147 		evcnt_attach_dynamic(&dispatch_table[i].ev, EVCNT_TYPE_INTR,
148 				     NULL, "s3c2xx0", dispatch_table[i].name);
149 	}
150 
151 	global_intr_mask = ~0;		/* no intr is globally blocked. */
152 
153 	_splraise(IPL_VM);
154 	enable_interrupts(I32_bit);
155 }
156 
157 /*
158  * initialize variables so that splfoo() doesn't touch illegal address.
159  * called during bootstrap.
160  */
161 void
s3c2xx0_intr_bootstrap(vaddr_t icureg)162 s3c2xx0_intr_bootstrap(vaddr_t icureg)
163 {
164 	s3c2xx0_intr_mask_reg = (volatile uint32_t *)(icureg + INTCTL_INTMSK);
165 }
166 
167 
168 
169 #undef splx
170 void
splx(int ipl)171 splx(int ipl)
172 {
173 	s3c2xx0_splx(ipl);
174 }
175 
176 #undef _splraise
177 int
_splraise(int ipl)178 _splraise(int ipl)
179 {
180 	return s3c2xx0_splraise(ipl);
181 }
182 
183 #undef _spllower
184 int
_spllower(int ipl)185 _spllower(int ipl)
186 {
187 	return s3c2xx0_spllower(ipl);
188 }
189