| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/tools/llvm-mca/AArch64/Cortex/ |
| H A D | A55-neon-instructions.s | 449 saddlp v0.1d, v0.2s label
450 saddlp v0.2d, v0.4s label
451 saddlp v0.2s, v0.4h label
452 saddlp v0.4h, v0.8b label
453 saddlp v0.4s, v0.8h label
454 saddlp v0.8h, v0.16b label
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| /dports/www/firefox-esr/firefox-91.8.0/js/src/jit/arm64/vixl/ |
| H A D | Assembler-vixl.cpp | 3696 void Assembler::saddlp(const VRegister& vd, in saddlp() function in vixl::Assembler
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| H A D | Logic-vixl.cpp | 2055 LogicVRegister Simulator::saddlp(VectorFormat vform, in saddlp() function in vixl::Simulator
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| /dports/www/qt5-webengine/qtwebengine-everywhere-src-5.15.2/src/3rdparty/chromium/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.cc | 1921 void Assembler::saddlp(const VRegister& vd, const VRegister& vn) { in saddlp() function in v8::internal::Assembler
|
| /dports/lang/spidermonkey78/firefox-78.9.0/js/src/jit/arm64/vixl/ |
| H A D | Assembler-vixl.cpp | 3687 void Assembler::saddlp(const VRegister& vd, in saddlp() function in vixl::Assembler
|
| H A D | Logic-vixl.cpp | 2011 LogicVRegister Simulator::saddlp(VectorFormat vform, in saddlp() function in vixl::Simulator
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| /dports/www/firefox/firefox-99.0/js/src/jit/arm64/vixl/ |
| H A D | Assembler-vixl.cpp | 3696 void Assembler::saddlp(const VRegister& vd, in saddlp() function in vixl::Assembler
|
| H A D | Logic-vixl.cpp | 2055 LogicVRegister Simulator::saddlp(VectorFormat vform, in saddlp() function in vixl::Simulator
|
| /dports/lang/v8/v8-9.6.180.12/src/codegen/arm64/ |
| H A D | assembler-arm64.cc | 1997 void Assembler::saddlp(const VRegister& vd, const VRegister& vn) { in saddlp() function in v8::internal::Assembler
|
| /dports/www/firefox-legacy/firefox-52.8.0esr/js/src/jit/arm64/vixl/ |
| H A D | Assembler-vixl.cpp | 3677 void Assembler::saddlp(const VRegister& vd, in saddlp() function in vixl::Assembler
|
| H A D | Logic-vixl.cpp | 2305 LogicVRegister Simulator::saddlp(VectorFormat vform, in saddlp() function in vixl::Simulator
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.cc | 1981 void Assembler::saddlp(const VRegister& vd, const VRegister& vn) { in saddlp() function in v8::internal::Assembler
|
| /dports/lang/spidermonkey60/firefox-60.9.0/js/src/jit/arm64/vixl/ |
| H A D | Assembler-vixl.cpp | 3677 void Assembler::saddlp(const VRegister& vd, in saddlp() function in vixl::Assembler
|
| H A D | Logic-vixl.cpp | 2305 LogicVRegister Simulator::saddlp(VectorFormat vform, in saddlp() function in vixl::Simulator
|
| /dports/mail/thunderbird/thunderbird-91.8.0/js/src/jit/arm64/vixl/ |
| H A D | Assembler-vixl.cpp | 3696 void Assembler::saddlp(const VRegister& vd, in saddlp() function in vixl::Assembler
|
| H A D | Logic-vixl.cpp | 2055 LogicVRegister Simulator::saddlp(VectorFormat vform, in saddlp() function in vixl::Simulator
|
| /dports/www/node10/node-v10.24.1/deps/v8/src/arm64/ |
| H A D | assembler-arm64.cc | 2390 void Assembler::saddlp(const VRegister& vd, const VRegister& vn) { in saddlp() function in v8::internal::Assembler
|
| H A D | simulator-logic-arm64.cc | 1957 LogicVRegister Simulator::saddlp(VectorFormat vform, LogicVRegister dst, in saddlp() function in v8::internal::Simulator
|
| /dports/databases/mongodb36/mongodb-src-r3.6.23/src/third_party/mozjs-45/extract/js/src/jit/arm64/vixl/ |
| H A D | Assembler-vixl.cpp | 3677 void Assembler::saddlp(const VRegister& vd, in saddlp() function in vixl::Assembler
|
| H A D | Logic-vixl.cpp | 2303 LogicVRegister Simulator::saddlp(VectorFormat vform, in saddlp() function in vixl::Simulator
|
| /dports/lang/v8/v8-9.6.180.12/src/execution/arm64/ |
| H A D | simulator-logic-arm64.cc | 1956 LogicVRegister Simulator::saddlp(VectorFormat vform, LogicVRegister dst, in saddlp() function in v8::internal::Simulator
|
| /dports/www/qt5-webengine/qtwebengine-everywhere-src-5.15.2/src/3rdparty/chromium/v8/src/execution/arm64/ |
| H A D | simulator-logic-arm64.cc | 1956 LogicVRegister Simulator::saddlp(VectorFormat vform, LogicVRegister dst, in saddlp() function in v8::internal::Simulator
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/v8/src/execution/arm64/ |
| H A D | simulator-logic-arm64.cc | 1956 LogicVRegister Simulator::saddlp(VectorFormat vform, LogicVRegister dst, in saddlp() function in v8::internal::Simulator
|
| /dports/misc/mxnet/incubator-mxnet-1.9.0/3rdparty/mkldnn/src/cpu/aarch64/xbyak_aarch64/src/ |
| H A D | xbyak_aarch64_mnemonic.h | 1862 void CodeGenerator::saddlp(const VReg4H &vd, const VReg8B &vn) { AdvSimd2RegMisc(0, 2, vd, vn); } function
1863 void CodeGenerator::saddlp(const VReg8H &vd, const VReg16B &vn) { AdvSimd2RegMisc(0, 2, vd, vn); } function
1864 void CodeGenerator::saddlp(const VReg2S &vd, const VReg4H &vn) { AdvSimd2RegMisc(0, 2, vd, vn); } function
1865 void CodeGenerator::saddlp(const VReg4S &vd, const VReg8H &vn) { AdvSimd2RegMisc(0, 2, vd, vn); } function
1866 void CodeGenerator::saddlp(const VReg1D &vd, const VReg2S &vn) { AdvSimd2RegMisc(0, 2, vd, vn); } function
1867 void CodeGenerator::saddlp(const VReg2D &vd, const VReg4S &vn) { AdvSimd2RegMisc(0, 2, vd, vn); } function
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| /dports/math/onednn/oneDNN-2.5.1/src/cpu/aarch64/xbyak_aarch64/src/ |
| H A D | xbyak_aarch64_mnemonic.h | 1862 void CodeGenerator::saddlp(const VReg4H &vd, const VReg8B &vn) { AdvSimd2RegMisc(0, 2, vd, vn); } function
1863 void CodeGenerator::saddlp(const VReg8H &vd, const VReg16B &vn) { AdvSimd2RegMisc(0, 2, vd, vn); } function
1864 void CodeGenerator::saddlp(const VReg2S &vd, const VReg4H &vn) { AdvSimd2RegMisc(0, 2, vd, vn); } function
1865 void CodeGenerator::saddlp(const VReg4S &vd, const VReg8H &vn) { AdvSimd2RegMisc(0, 2, vd, vn); } function
1866 void CodeGenerator::saddlp(const VReg1D &vd, const VReg2S &vn) { AdvSimd2RegMisc(0, 2, vd, vn); } function
1867 void CodeGenerator::saddlp(const VReg2D &vd, const VReg4S &vn) { AdvSimd2RegMisc(0, 2, vd, vn); } function
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