xref: /dragonfly/sys/dev/raid/iir/iir.h (revision 99602340)
1 /* $FreeBSD: src/sys/dev/iir/iir.h,v 1.16 2007/06/17 05:55:50 scottl Exp $ */
2 /*-
3  *       Copyright (c) 2000-04 ICP vortex GmbH
4  *       Copyright (c) 2002-04 Intel Corporation
5  *       Copyright (c) 2003-04 Adaptec Inc.
6  *       All Rights Reserved
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions, and the following disclaimer,
13  *    without modification, immediately at the beginning of the file.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. The name of the author may not be used to endorse or promote products
18  *    derived from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
24  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30  * SUCH DAMAGE.
31  *
32  */
33 
34 /*
35  *
36  * iir.h:       Definitions/Constants used by the Intel Integrated RAID driver
37  *
38  * Written by: 	Achim Leubner <achim_leubner@adaptec.com>
39  * Fixes/Additions:	Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com>
40  *
41  * credits:     Niklas Hallqvist;       OpenBSD driver for the ICP Controllers.
42  *              FreeBSD.ORG;            Great O/S to work on and for.
43  *
44  * $Id: iir.h 1.6 2004/03/30 10:19:44 achim Exp $"
45  */
46 
47 #ifndef _IIR_H
48 #define _IIR_H
49 
50 #include <sys/ioccom.h>
51 
52 #define IIR_DRIVER_VERSION      1
53 #define IIR_DRIVER_SUBVERSION   5
54 
55 /* OEM IDs */
56 #define OEM_ID_ICP              0x941c
57 #define OEM_ID_INTEL            0x8000
58 
59 #define GDT_VENDOR_ID           0x1119
60 #define GDT_DEVICE_ID_MIN       0x100
61 #define GDT_DEVICE_ID_MAX       0x2ff
62 #define GDT_DEVICE_ID_NEWRX     0x300
63 
64 #define INTEL_DEVICE_ID_IIR     0x600
65 
66 #define GDT_MAXBUS              6       /* XXX Why not 5? */
67 #define GDT_MAX_HDRIVES         100     /* max 100 host drives */
68 #define GDT_MAXID_FC            127     /* Fibre-channel IDs */
69 #define GDT_MAXID               16      /* SCSI IDs */
70 #define GDT_MAXOFFSETS          128
71 #define GDT_MAXSG               32      /* Max. s/g elements */
72 #define GDT_PROTOCOL_VERSION    1
73 #define GDT_LINUX_OS            8       /* Used for cache optimization */
74 #define GDT_SCATTER_GATHER      1       /* s/g feature */
75 #define GDT_SECS32              0x1f    /* round capacity */
76 #define GDT_LOCALBOARD          0       /* Board node always 0 */
77 #define GDT_MAXCMDS             124
78 #define GDT_SECTOR_SIZE         0x200   /* Always 512 bytes for cache devs */
79 #define GDT_MAX_EVENTS          0x100   /* event buffer */
80 
81 /* DPMEM constants */
82 #define GDT_MPR_MAGIC           0xc0ffee11
83 #define GDT_IC_HEADER_BYTES     48
84 #define GDT_IC_QUEUE_BYTES      4
85 #define GDT_DPMEM_COMMAND_OFFSET \
86     (GDT_IC_HEADER_BYTES + GDT_IC_QUEUE_BYTES * GDT_MAXOFFSETS)
87 
88 /* geometry constants */
89 #define GDT_MAXCYLS             1024
90 #define GDT_HEADS               64
91 #define GDT_SECS                32      /* mapping 64*32 */
92 #define GDT_MEDHEADS            127
93 #define GDT_MEDSECS             63      /* mapping 127*63 */
94 #define GDT_BIGHEADS            255
95 #define GDT_BIGSECS             63      /* mapping 255*63 */
96 
97 /* data direction raw service */
98 #define GDT_DATA_IN             0x01000000L
99 #define GDT_DATA_OUT            0x00000000L
100 
101 /* Cache/raw service commands */
102 #define GDT_INIT        0               /* service initialization */
103 #define GDT_READ        1               /* read command */
104 #define GDT_WRITE       2               /* write command */
105 #define GDT_INFO        3               /* information about devices */
106 #define GDT_FLUSH       4               /* flush dirty cache buffers */
107 #define GDT_IOCTL       5               /* ioctl command */
108 #define GDT_DEVTYPE     9               /* additional information */
109 #define GDT_MOUNT       10              /* mount cache device */
110 #define GDT_UNMOUNT     11              /* unmount cache device */
111 #define GDT_SET_FEAT    12              /* set features (scatter/gather) */
112 #define GDT_GET_FEAT    13              /* get features */
113 #define GDT_WRITE_THR   16              /* write through */
114 #define GDT_READ_THR    17              /* read through */
115 #define GDT_EXT_INFO    18              /* extended info */
116 #define GDT_RESET       19              /* controller reset */
117 #define GDT_FREEZE_IO   25              /* freeze all IOs */
118 #define GDT_UNFREEZE_IO 26              /* unfreeze all IOs */
119 
120 /* Additional raw service commands */
121 #define GDT_RESERVE     14              /* reserve device to raw service */
122 #define GDT_RELEASE     15              /* release device */
123 #define GDT_RESERVE_ALL 16              /* reserve all devices */
124 #define GDT_RELEASE_ALL 17              /* release all devices */
125 #define GDT_RESET_BUS   18              /* reset bus */
126 #define GDT_SCAN_START  19              /* start device scan */
127 #define GDT_SCAN_END    20              /* stop device scan */
128 
129 /* IOCTL command defines */
130 #define GDT_SCSI_DR_INFO        0x00    /* SCSI drive info */
131 #define GDT_SCSI_CHAN_CNT       0x05    /* SCSI channel count */
132 #define GDT_SCSI_DR_LIST        0x06    /* SCSI drive list */
133 #define GDT_SCSI_DEF_CNT        0x15    /* grown/primary defects */
134 #define GDT_DSK_STATISTICS      0x4b    /* SCSI disk statistics */
135 #define GDT_IOCHAN_DESC         0x5d    /* description of IO channel */
136 #define GDT_IOCHAN_RAW_DESC     0x5e    /* description of raw IO channel */
137 
138 #define GDT_L_CTRL_PATTERN      0x20000000      /* SCSI IOCTL mask */
139 #define GDT_ARRAY_INFO          0x12            /* array drive info */
140 #define GDT_ARRAY_DRV_LIST      0x0f            /* array drive list */
141 #define GDT_LA_CTRL_PATTERN     0x10000000      /* array IOCTL mask */
142 #define GDT_CACHE_DRV_CNT       0x01            /* cache drive count */
143 #define GDT_CACHE_DRV_LIST      0x02            /* cache drive list */
144 #define GDT_CACHE_INFO          0x04            /* cache info */
145 #define GDT_CACHE_CONFIG        0x05            /* cache configuration */
146 #define GDT_CACHE_DRV_INFO      0x07            /* cache drive info */
147 #define GDT_BOARD_FEATURES      0x15            /* controller features */
148 #define GDT_BOARD_INFO          0x28            /* controller info */
149 #define GDT_OEM_STR_RECORD      0x84            /* OEM info */
150 #define GDT_HOST_GET            0x10001         /* get host drive list */
151 #define GDT_IO_CHANNEL          0x20000         /* default IO channel */
152 #define GDT_INVALID_CHANNEL     0xffff          /* invalid channel */
153 
154 /* IOCTLs */
155 #define GDT_IOCTL_GENERAL       _IOWR('J', 0, gdt_ucmd_t) /* general IOCTL */
156 #define GDT_IOCTL_DRVERS        _IOR('J', 1, int)      /* get driver version */
157 #define GDT_IOCTL_CTRTYPE       _IOWR('J', 2, gdt_ctrt_t) /* get ctr. type */
158 #define GDT_IOCTL_DRVERS_OLD    _IOWR('J', 1, int)      /* get driver version */
159 #define GDT_IOCTL_CTRTYPE_OLD   _IOR('J', 2, gdt_ctrt_t) /* get ctr. type */
160 #define GDT_IOCTL_OSVERS        _IOR('J', 3, gdt_osv_t) /* get OS version */
161 #define GDT_IOCTL_CTRCNT        _IOR('J', 5, int)       /* get ctr. count */
162 #define GDT_IOCTL_EVENT         _IOWR('J', 8, gdt_event_t) /* get event */
163 #define GDT_IOCTL_STATIST       _IOR('J', 9, gdt_statist_t) /* get statistics */
164 
165 /* Service errors */
166 #define GDT_S_OK                1       /* no error */
167 #define GDT_S_BSY               7       /* controller busy */
168 #define GDT_S_RAW_SCSI          12      /* raw service: target error */
169 #define GDT_S_RAW_ILL           0xff    /* raw service: illegal */
170 #define GDT_S_NO_STATUS         0x1000  /* got no status (driver-generated) */
171 
172 /* Controller services */
173 #define GDT_SCSIRAWSERVICE      3
174 #define GDT_CACHESERVICE        9
175 #define GDT_SCREENSERVICE       11
176 
177 /* Scatter/gather element */
178 #define GDT_SG_PTR              0x00    /* u_int32_t, address */
179 #define GDT_SG_LEN              0x04    /* u_int32_t, length */
180 #define GDT_SG_SZ               0x08
181 
182 /* Cache service command */
183 #define GDT_CACHE_DEVICENO      0x00    /* u_int16_t, number of cache drive */
184 #define GDT_CACHE_BLOCKNO       0x02    /* u_int32_t, block number */
185 #define GDT_CACHE_BLOCKCNT      0x06    /* u_int32_t, block count */
186 #define GDT_CACHE_DESTADDR      0x0a    /* u_int32_t, dest. addr. (-1: s/g) */
187 #define GDT_CACHE_SG_CANZ       0x0e    /* u_int32_t, s/g element count */
188 #define GDT_CACHE_SG_LST        0x12    /* [GDT_MAXSG], s/g list */
189 #define GDT_CACHE_SZ            (0x12 + GDT_MAXSG * GDT_SG_SZ)
190 
191 /* Ioctl command */
192 #define GDT_IOCTL_PARAM_SIZE    0x00    /* u_int16_t, size of buffer */
193 #define GDT_IOCTL_SUBFUNC       0x02    /* u_int32_t, ioctl function */
194 #define GDT_IOCTL_CHANNEL       0x06    /* u_int32_t, device */
195 #define GDT_IOCTL_P_PARAM       0x0a    /* u_int32_t, buffer */
196 #define GDT_IOCTL_SZ            0x0e
197 
198 /* Screen service defines */
199 #define GDT_MSG_INV_HANDLE      -1      /* special message handle */
200 #define GDT_MSGLEN              16      /* size of message text */
201 #define GDT_MSG_SIZE            34      /* size of message structure */
202 #define GDT_MSG_REQUEST         0       /* async. event. message */
203 
204 /* Screen service command */
205 #define GDT_SCREEN_MSG_HANDLE   0x02    /* u_int32_t, message handle */
206 #define GDT_SCREEN_MSG_ADDR     0x06    /* u_int32_t, message buffer address */
207 #define GDT_SCREEN_SZ           0x0a
208 
209 /* Screen service message */
210 #define GDT_SCR_MSG_HANDLE      0x00    /* u_int32_t, message handle */
211 #define GDT_SCR_MSG_LEN         0x04    /* u_int32_t, size of message */
212 #define GDT_SCR_MSG_ALEN        0x08    /* u_int32_t, answer length */
213 #define GDT_SCR_MSG_ANSWER      0x0c    /* u_int8_t, answer flag */
214 #define GDT_SCR_MSG_EXT         0x0d    /* u_int8_t, more messages? */
215 #define GDT_SCR_MSG_RES         0x0e    /* u_int16_t, reserved */
216 #define GDT_SCR_MSG_TEXT        0x10    /* GDT_MSGLEN+2, message text */
217 #define GDT_SCR_MSG_SZ          (0x12 + GDT_MSGLEN)
218 
219 /* Raw service command */
220 #define GDT_RAW_DIRECTION       0x02    /* u_int32_t, data direction */
221 #define GDT_RAW_MDISC_TIME      0x06    /* u_int32_t, disc. time (0: none) */
222 #define GDT_RAW_MCON_TIME       0x0a    /* u_int32_t, conn. time (0: none) */
223 #define GDT_RAW_SDATA           0x0e    /* u_int32_t, dest. addr. (-1: s/g) */
224 #define GDT_RAW_SDLEN           0x12    /* u_int32_t, data length */
225 #define GDT_RAW_CLEN            0x16    /* u_int32_t, SCSI cmd len (6/10/12) */
226 #define GDT_RAW_CMD             0x1a    /* u_int8_t [12], SCSI command */
227 #define GDT_RAW_TARGET          0x26    /* u_int8_t, target ID */
228 #define GDT_RAW_LUN             0x27    /* u_int8_t, LUN */
229 #define GDT_RAW_BUS             0x28    /* u_int8_t, SCSI bus number */
230 #define GDT_RAW_PRIORITY        0x29    /* u_int8_t, only 0 used */
231 #define GDT_RAW_SENSE_LEN       0x2a    /* u_int32_t, sense data length */
232 #define GDT_RAW_SENSE_DATA      0x2e    /* u_int32_t, sense data address */
233 #define GDT_RAW_SG_RANZ         0x36    /* u_int32_t, s/g element count */
234 #define GDT_RAW_SG_LST          0x3a    /* [GDT_MAXSG], s/g list */
235 #define GDT_RAW_SZ              (0x3a + GDT_MAXSG * GDT_SG_SZ)
236 
237 /* Command structure */
238 #define GDT_CMD_BOARDNODE       0x00    /* u_int32_t, board node (always 0) */
239 #define GDT_CMD_COMMANDINDEX    0x04    /* u_int32_t, command number */
240 #define GDT_CMD_OPCODE          0x08    /* u_int16_t, opcode (READ, ...) */
241 #define GDT_CMD_UNION           0x0a    /* cache/screen/raw service command */
242 #define GDT_CMD_UNION_SZ        GDT_RAW_SZ
243 #define GDT_CMD_SZ              (0x0a + GDT_CMD_UNION_SZ)
244 
245 /* Command queue entries */
246 #define GDT_OFFSET      0x00    /* u_int16_t, command offset in the DP RAM */
247 #define GDT_SERV_ID     0x02    /* u_int16_t, service */
248 #define GDT_COMM_Q_SZ   0x04
249 
250 /* Interface area */
251 #define GDT_S_CMD_INDX  0x00    /* u_int8_t, special command */
252 #define GDT_S_STATUS    0x01    /* volatile u_int8_t, status special command */
253 #define GDT_S_INFO      0x04    /* u_int32_t [4], add. info special command */
254 #define GDT_SEMA0       0x14    /* volatile u_int8_t, command semaphore */
255 #define GDT_CMD_INDEX   0x18    /* u_int8_t, command number */
256 #define GDT_STATUS      0x1c    /* volatile u_int16_t, command status */
257 #define GDT_SERVICE     0x1e    /* u_int16_t, service (for asynch. events) */
258 #define GDT_DPR_INFO    0x20    /* u_int32_t [2], additional info */
259 #define GDT_COMM_QUEUE  0x28    /* command queue */
260 #define GDT_DPR_CMD     (0x30 + GDT_MAXOFFSETS * GDT_COMM_Q_SZ)
261                                 /* u_int8_t [], commands */
262 
263 /* I/O channel header */
264 #define GDT_IOC_VERSION         0x00    /* u_int32_t, version (~0: newest) */
265 #define GDT_IOC_LIST_ENTRIES    0x04    /* u_int8_t, list entry count */
266 #define GDT_IOC_FIRST_CHAN      0x05    /* u_int8_t, first channel number */
267 #define GDT_IOC_LAST_CHAN       0x06    /* u_int8_t, last channel number */
268 #define GDT_IOC_CHAN_COUNT      0x07    /* u_int8_t, (R) channel count */
269 #define GDT_IOC_LIST_OFFSET     0x08    /* u_int32_t, offset of list[0] */
270 #define GDT_IOC_HDR_SZ          0x0c
271 
272 #define GDT_IOC_NEWEST          0xffffffff      /* goes into GDT_IOC_VERSION */
273 
274 /* Get I/O channel description */
275 #define GDT_IOC_ADDRESS         0x00    /* u_int32_t, channel address */
276 #define GDT_IOC_TYPE            0x04    /* u_int8_t, type (SCSI/FCSL) */
277 #define GDT_IOC_LOCAL_NO        0x05    /* u_int8_t, local number */
278 #define GDT_IOC_FEATURES        0x06    /* u_int16_t, channel features */
279 #define GDT_IOC_SZ              0x08
280 
281 /* Get raw I/O channel description */
282 #define GDT_RAWIOC_PROC_ID      0x00    /* u_int8_t, processor id */
283 #define GDT_RAWIOC_PROC_DEFECT  0x01    /* u_int8_t, defect? */
284 #define GDT_RAWIOC_SZ           0x04
285 
286 /* Get SCSI channel count */
287 #define GDT_GETCH_CHANNEL_NO    0x00    /* u_int32_t, channel number */
288 #define GDT_GETCH_DRIVE_CNT     0x04    /* u_int32_t, drive count */
289 #define GDT_GETCH_SIOP_ID       0x08    /* u_int8_t, SCSI processor ID */
290 #define GDT_GETCH_SIOP_STATE    0x09    /* u_int8_t, SCSI processor state */
291 #define GDT_GETCH_SZ            0x0a
292 
293 /* Cache info/config IOCTL structures */
294 #define GDT_CPAR_VERSION        0x00    /* u_int32_t, firmware version */
295 #define GDT_CPAR_STATE          0x04    /* u_int16_t, cache state (on/off) */
296 #define GDT_CPAR_STRATEGY       0x06    /* u_int16_t, cache strategy */
297 #define GDT_CPAR_WRITE_BACK     0x08    /* u_int16_t, write back (on/off) */
298 #define GDT_CPAR_BLOCK_SIZE     0x0a    /* u_int16_t, cache block size */
299 #define GDT_CPAR_SZ             0x0c
300 
301 #define GDT_CSTAT_CSIZE         0x00    /* u_int32_t, cache size */
302 #define GDT_CSTAT_READ_CNT      0x04    /* u_int32_t, read counter */
303 #define GDT_CSTAT_WRITE_CNT     0x08    /* u_int32_t, write counter */
304 #define GDT_CSTAT_TR_HITS       0x0c    /* u_int32_t, track hits */
305 #define GDT_CSTAT_SEC_HITS      0x10    /* u_int32_t, sector hits */
306 #define GDT_CSTAT_SEC_MISS      0x14    /* u_int32_t, sector misses */
307 #define GDT_CSTAT_SZ            0x18
308 
309 /* Get cache info */
310 #define GDT_CINFO_CPAR          0x00
311 #define GDT_CINFO_CSTAT         GDT_CPAR_SZ
312 #define GDT_CINFO_SZ            (GDT_CPAR_SZ + GDT_CSTAT_SZ)
313 
314 /* Get board info */
315 #define GDT_BINFO_SER_NO        0x00    /* u_int32_t, serial number */
316 #define GDT_BINFO_OEM_ID        0x04    /* u_int8_t [2], OEM ID */
317 #define GDT_BINFO_EP_FLAGS      0x06    /* u_int16_t, eprom flags */
318 #define GDT_BINFO_PROC_ID       0x08    /* u_int32_t, processor ID */
319 #define GDT_BINFO_MEMSIZE       0x0c    /* u_int32_t, memory size (bytes) */
320 #define GDT_BINFO_MEM_BANKS     0x10    /* u_int8_t, memory banks */
321 #define GDT_BINFO_CHAN_TYPE     0x11    /* u_int8_t, channel type */
322 #define GDT_BINFO_CHAN_COUNT    0x12    /* u_int8_t, channel count */
323 #define GDT_BINFO_RDONGLE_PRES  0x13    /* u_int8_t, dongle present */
324 #define GDT_BINFO_EPR_FW_VER    0x14    /* u_int32_t, (eprom) firmware ver */
325 #define GDT_BINFO_UPD_FW_VER    0x18    /* u_int32_t, (update) firmware ver */
326 #define GDT_BINFO_UPD_REVISION  0x1c    /* u_int32_t, update revision */
327 #define GDT_BINFO_TYPE_STRING   0x20    /* char [16], controller name */
328 #define GDT_BINFO_RAID_STRING   0x30    /* char [16], RAID firmware name */
329 #define GDT_BINFO_UPDATE_PRES   0x40    /* u_int8_t, update present? */
330 #define GDT_BINFO_XOR_PRES      0x41    /* u_int8_t, XOR engine present */
331 #define GDT_BINFO_PROM_TYPE     0x42    /* u_int8_t, ROM type (eprom/flash) */
332 #define GDT_BINFO_PROM_COUNT    0x43    /* u_int8_t, number of ROM devices */
333 #define GDT_BINFO_DUP_PRES      0x44    /* u_int32_t, duplexing module pres? */
334 #define GDT_BINFO_CHAN_PRES     0x48    /* u_int32_t, # of exp. channels */
335 #define GDT_BINFO_MEM_PRES      0x4c    /* u_int32_t, memory expansion inst? */
336 #define GDT_BINFO_FT_BUS_SYSTEM 0x50    /* u_int8_t, fault bus supported? */
337 #define GDT_BINFO_SUBTYPE_VALID 0x51    /* u_int8_t, board_subtype valid */
338 #define GDT_BINFO_BOARD_SUBTYPE 0x52    /* u_int8_t, subtype/hardware level */
339 #define GDT_BINFO_RAMPAR_PRES   0x53    /* u_int8_t, RAM parity check hw? */
340 #define GDT_BINFO_SZ            0x54
341 
342 /* Get board features */
343 #define GDT_BFEAT_CHAINING      0x00    /* u_int8_t, chaining supported */
344 #define GDT_BFEAT_STRIPING      0x01    /* u_int8_t, striping (RAID-0) supp. */
345 #define GDT_BFEAT_MIRRORING     0x02    /* u_int8_t, mirroring (RAID-1) supp */
346 #define GDT_BFEAT_RAID          0x03    /* u_int8_t, RAID-4/5/10 supported */
347 #define GDT_BFEAT_SZ            0x04
348 
349 /* Other defines */
350 #define GDT_ASYNCINDEX  0       /* command index asynchronous event */
351 #define GDT_SPEZINDEX   1       /* command index unknown service */
352 
353 /* Debugging */
354 #ifdef GDT_DEBUG
355 #define GDT_D_INTR      0x01
356 #define GDT_D_MISC      0x02
357 #define GDT_D_CMD       0x04
358 #define GDT_D_QUEUE     0x08
359 #define GDT_D_TIMEOUT   0x10
360 #define GDT_D_INIT      0x20
361 #define GDT_D_INVALID   0x40
362 #define GDT_D_DEBUG     0x80
363 extern int gdt_debug;
364 #ifdef __SERIAL__
365 extern int ser_printf(const char *fmt, ...);
366 #define GDT_DPRINTF(mask, args) if (gdt_debug & (mask)) ser_kprintf args
367 #else
368 #define GDT_DPRINTF(mask, args) if (gdt_debug & (mask)) kprintf args
369 #endif
370 #else
371 #define GDT_DPRINTF(mask, args)
372 #endif
373 
374 /* Miscellaneous constants */
375 #define GDT_RETRIES             100000000       /* 100000 * 1us = 100s */
376 #define GDT_TIMEOUT             100000000       /* 100000 * 1us = 100s */
377 #define GDT_POLL_TIMEOUT        10000000        /* 10000 * 1us = 10s */
378 #define GDT_WATCH_TIMEOUT       10000000        /* 10000 * 1us = 10s */
379 #define GDT_SCRATCH_SZ          3072            /* 3KB scratch buffer */
380 
381 /* Map minor numbers to device identity */
382 #define LUN_MASK                0x0007
383 #define TARGET_MASK             0x03f8
384 #define BUS_MASK                0x1c00
385 #define HBA_MASK                0xe000
386 
387 #define minor2lun(minor)        ( minor & LUN_MASK )
388 #define minor2target(minor)     ( (minor & TARGET_MASK) >> 3 )
389 #define minor2bus(minor)        ( (minor & BUS_MASK) >> 10 )
390 #define minor2hba(minor)        ( (minor & HBA_MASK) >> 13 )
391 #define hba2minor(hba)          ( (hba << 13) & HBA_MASK )
392 
393 
394 /* struct for GDT_IOCTL_GENERAL */
395 #pragma pack(1)
396 typedef struct gdt_ucmd {
397     u_int16_t   io_node;
398     u_int16_t   service;
399     u_int32_t   timeout;
400     u_int16_t   status;
401     u_int32_t   info;
402 
403     u_int32_t   BoardNode;                      /* board node (always 0) */
404     u_int32_t   CommandIndex;                   /* command number */
405     u_int16_t   OpCode;                         /* the command (READ,..) */
406     union {
407         struct {
408             u_int16_t   DeviceNo;               /* number of cache drive */
409             u_int32_t   BlockNo;                /* block number */
410             u_int32_t   BlockCnt;               /* block count */
411             void        *DestAddr;              /* data */
412         } cache;                                /* cache service cmd. str. */
413         struct {
414             u_int16_t   param_size;             /* size of p_param buffer */
415             u_int32_t   subfunc;                /* IOCTL function */
416             u_int32_t   channel;                /* device */
417             void        *p_param;               /* data */
418         } ioctl;                                /* IOCTL command structure */
419         struct {
420             u_int16_t   reserved;
421             u_int32_t   direction;              /* data direction */
422             u_int32_t   mdisc_time;             /* disc. time (0: no timeout)*/
423             u_int32_t   mcon_time;              /* connect time(0: no to.) */
424             void        *sdata;                 /* dest. addr. (if s/g: -1) */
425             u_int32_t   sdlen;                  /* data length (bytes) */
426             u_int32_t   clen;                   /* SCSI cmd. length(6,10,12) */
427             u_int8_t    cmd[12];                /* SCSI command */
428             u_int8_t    target;                 /* target ID */
429             u_int8_t    lun;                    /* LUN */
430             u_int8_t    bus;                    /* SCSI bus number */
431             u_int8_t    priority;               /* only 0 used */
432             u_int32_t   sense_len;              /* sense data length */
433             void        *sense_data;            /* sense data addr. */
434             u_int32_t   link_p;                 /* linked cmds (not supp.) */
435         } raw;                                  /* raw service cmd. struct. */
436     } u;
437     u_int8_t            data[GDT_SCRATCH_SZ];
438     int                 complete_flag;
439     TAILQ_ENTRY(gdt_ucmd) links;
440 } gdt_ucmd_t;
441 
442 /* struct for GDT_IOCTL_CTRTYPE */
443 typedef struct gdt_ctrt {
444     u_int16_t io_node;
445     u_int16_t oem_id;
446     u_int16_t type;
447     u_int32_t info;
448     u_int8_t  access;
449     u_int8_t  remote;
450     u_int16_t ext_type;
451     u_int16_t device_id;
452     u_int16_t sub_device_id;
453 } gdt_ctrt_t;
454 
455 /* struct for GDT_IOCTL_OSVERS */
456 typedef struct gdt_osv {
457     u_int8_t  oscode;
458     u_int8_t  version;
459     u_int8_t  subversion;
460     u_int16_t revision;
461     char      name[64];
462 } gdt_osv_t;
463 
464 /* OEM */
465 #define GDT_OEM_VERSION     0x00
466 #define GDT_OEM_BUFSIZE     0x0c
467 typedef struct {
468     u_int32_t ctl_version;
469     u_int32_t file_major_version;
470     u_int32_t file_minor_version;
471     u_int32_t buffer_size;
472     u_int32_t cpy_count;
473     u_int32_t ext_error;
474     u_int32_t oem_id;
475     u_int32_t board_id;
476 } gdt_oem_param_t;
477 
478 typedef struct {
479     char      product_0_1_name[16];
480     char      product_4_5_name[16];
481     char      product_cluster_name[16];
482     char      product_reserved[16];
483     char      scsi_cluster_target_vendor_id[16];
484     char      cluster_raid_fw_name[16];
485     char      oem_brand_name[16];
486     char      oem_raid_type[16];
487     char      bios_type[13];
488     char      bios_title[50];
489     char      oem_company_name[37];
490     u_int32_t pci_id_1;
491     u_int32_t pci_id_2;
492     char      validation_status[80];
493     char      reserved_1[4];
494     char      scsi_host_drive_inquiry_vendor_id[16];
495     char      library_file_template[32];
496     char      tool_name_1[32];
497     char      tool_name_2[32];
498     char      tool_name_3[32];
499     char      oem_contact_1[84];
500     char      oem_contact_2[84];
501     char      oem_contact_3[84];
502 } gdt_oem_record_t;
503 
504 typedef struct {
505     gdt_oem_param_t  parameters;
506     gdt_oem_record_t text;
507 } gdt_oem_str_record_t;
508 
509 
510 /* controller event structure */
511 #define GDT_ES_ASYNC    1
512 #define GDT_ES_DRIVER   2
513 #define GDT_ES_TEST     3
514 #define GDT_ES_SYNC     4
515 typedef struct {
516     u_int16_t           size;               /* size of structure */
517     union {
518         char            stream[16];
519         struct {
520             u_int16_t   ionode;
521             u_int16_t   service;
522             u_int32_t   index;
523         } driver;
524         struct {
525             u_int16_t   ionode;
526             u_int16_t   service;
527             u_int16_t   status;
528             u_int32_t   info;
529             u_int8_t    scsi_coord[3];
530         } async;
531         struct {
532             u_int16_t   ionode;
533             u_int16_t   service;
534             u_int16_t   status;
535             u_int32_t   info;
536             u_int16_t   hostdrive;
537             u_int8_t    scsi_coord[3];
538             u_int8_t    sense_key;
539         } sync;
540         struct {
541             u_int32_t   l1, l2, l3, l4;
542         } test;
543     } eu;
544     u_int32_t           severity;
545     u_int8_t            event_string[256];
546 } gdt_evt_data;
547 
548 /* dvrevt structure */
549 typedef struct {
550     u_int32_t           first_stamp;
551     u_int32_t           last_stamp;
552     u_int16_t           same_count;
553     u_int16_t           event_source;
554     u_int16_t           event_idx;
555     u_int8_t            application;
556     u_int8_t            reserved;
557     gdt_evt_data        event_data;
558 } gdt_evt_str;
559 
560 /* struct for GDT_IOCTL_EVENT */
561 typedef struct gdt_event {
562     int erase;
563     int handle;
564     gdt_evt_str dvr;
565 } gdt_event_t;
566 
567 /* struct for GDT_IOCTL_STATIST */
568 typedef struct gdt_statist {
569     u_int16_t io_count_act;
570     u_int16_t io_count_max;
571     u_int16_t req_queue_act;
572     u_int16_t req_queue_max;
573     u_int16_t cmd_index_act;
574     u_int16_t cmd_index_max;
575     u_int16_t sg_count_act;
576     u_int16_t sg_count_max;
577 } gdt_statist_t;
578 
579 #pragma pack()
580 
581 /* Context structure for interrupt services */
582 struct gdt_intr_ctx {
583     u_int32_t info, info2;
584     u_int16_t cmd_status, service;
585     u_int8_t istatus;
586 };
587 
588 /* softc structure */
589 struct gdt_softc {
590     int sc_hanum;
591     int sc_class;               /* Controller class */
592 #define GDT_MPR         0x05
593 #define GDT_CLASS_MASK  0x07
594 #define GDT_FC          0x10
595 #define GDT_CLASS(gdt)  ((gdt)->sc_class & GDT_CLASS_MASK)
596     int sc_bus, sc_slot;
597     u_int16_t sc_vendor;
598     u_int16_t sc_device, sc_subdevice;
599     u_int16_t sc_fw_vers;
600     int sc_init_level;
601     int sc_state;
602 #define GDT_NORMAL      0x00
603 #define GDT_POLLING     0x01
604 #define GDT_SHUTDOWN    0x02
605 #define GDT_POLL_WAIT   0x80
606     cdev_t sc_dev;
607     bus_space_tag_t sc_dpmemt;
608     bus_space_handle_t sc_dpmemh;
609     bus_addr_t sc_dpmembase;
610     bus_dma_tag_t sc_parent_dmat;
611     bus_dma_tag_t sc_buffer_dmat;
612     bus_dma_tag_t sc_gcscratch_dmat;
613     bus_dmamap_t sc_gcscratch_dmamap;
614     bus_addr_t sc_gcscratch_busbase;
615 
616     struct gdt_ccb *sc_gccbs;
617     u_int8_t  *sc_gcscratch;
618     SLIST_HEAD(, gdt_ccb) sc_free_gccb, sc_pending_gccb;
619     TAILQ_HEAD(, ccb_hdr) sc_ccb_queue;
620     TAILQ_HEAD(, gdt_ucmd) sc_ucmd_queue;
621 
622     u_int16_t sc_ic_all_size;
623     u_int16_t sc_cmd_off;
624     u_int16_t sc_cmd_cnt;
625 
626     u_int32_t sc_info;
627     u_int32_t sc_info2;
628     u_int16_t sc_status;
629     u_int16_t sc_service;
630 
631     u_int8_t sc_bus_cnt;
632     u_int8_t sc_virt_bus;
633     u_int8_t sc_bus_id[GDT_MAXBUS];
634     u_int8_t sc_more_proc;
635 
636     struct {
637         u_int8_t hd_present;
638         u_int8_t hd_is_logdrv;
639         u_int8_t hd_is_arraydrv;
640         u_int8_t hd_is_master;
641         u_int8_t hd_is_parity;
642         u_int8_t hd_is_hotfix;
643         u_int8_t hd_master_no;
644         u_int8_t hd_lock;
645         u_int8_t hd_heads;
646         u_int8_t hd_secs;
647         u_int16_t hd_devtype;
648         u_int32_t hd_size;
649         u_int8_t hd_ldr_no;
650         u_int8_t hd_rw_attribs;
651         u_int32_t hd_start_sec;
652     } sc_hdr[GDT_MAX_HDRIVES];
653 
654     u_int16_t sc_raw_feat;
655     u_int16_t sc_cache_feat;
656 
657     gdt_evt_data sc_dvr;
658     char oem_name[8];
659 
660     struct cam_sim *sims[GDT_MAXBUS];
661     struct cam_path *paths[GDT_MAXBUS];
662 
663     void (*sc_copy_cmd)(struct gdt_softc *, struct gdt_ccb *);
664     u_int8_t (*sc_get_status)(struct gdt_softc *);
665     void (*sc_intr)(struct gdt_softc *, struct gdt_intr_ctx *);
666     void (*sc_release_event)(struct gdt_softc *);
667     void (*sc_set_sema0)(struct gdt_softc *);
668     int (*sc_test_busy)(struct gdt_softc *);
669 
670     TAILQ_ENTRY(gdt_softc) links;
671 };
672 
673 /*
674  * A command control block, one for each corresponding command index of the
675  * controller.
676  */
677 struct gdt_ccb {
678     u_int8_t    *gc_scratch;
679     bus_addr_t  gc_scratch_busbase;
680     union ccb   *gc_ccb;
681     gdt_ucmd_t  *gc_ucmd;
682     bus_dmamap_t gc_dmamap;
683     int         gc_map_flag;
684     int         gc_timeout;
685     u_int8_t    gc_service;
686     u_int8_t    gc_cmd_index;
687     u_int8_t    gc_flags;
688 #define GDT_GCF_UNUSED          0
689 #define GDT_GCF_INTERNAL        1
690 #define GDT_GCF_SCREEN          2
691 #define GDT_GCF_SCSI            3
692 #define GDT_GCF_IOCTL           4
693     u_int16_t	gc_cmd_len;
694     u_int8_t	gc_cmd[GDT_CMD_SZ];
695     SLIST_ENTRY(gdt_ccb) sle;
696 };
697 
698 
699 int     iir_init(struct gdt_softc *);
700 void    iir_free(struct gdt_softc *);
701 void    iir_attach(struct gdt_softc *);
702 void    iir_intr(void *arg);
703 
704 #ifdef __GNUC__
705 /* These all require correctly aligned buffers */
706 static __inline__ void gdt_enc16(u_int8_t *, u_int16_t);
707 static __inline__ void gdt_enc32(u_int8_t *, u_int32_t);
708 static __inline__ u_int16_t gdt_dec16(u_int8_t *);
709 static __inline__ u_int32_t gdt_dec32(u_int8_t *);
710 
711 static __inline__ void
gdt_enc16(u_int8_t * addr,u_int16_t value)712 gdt_enc16(u_int8_t *addr, u_int16_t value)
713 {
714         *(u_int16_t *)addr = htole16(value);
715 }
716 
717 static __inline__ void
gdt_enc32(u_int8_t * addr,u_int32_t value)718 gdt_enc32(u_int8_t *addr, u_int32_t value)
719 {
720         *(u_int32_t *)addr = htole32(value);
721 }
722 
723 static __inline__ u_int16_t
gdt_dec16(u_int8_t * addr)724 gdt_dec16(u_int8_t *addr)
725 {
726         return le16toh(*(u_int16_t *)addr);
727 }
728 
729 static __inline__ u_int32_t
gdt_dec32(u_int8_t * addr)730 gdt_dec32(u_int8_t *addr)
731 {
732         return le32toh(*(u_int32_t *)addr);
733 }
734 #endif
735 
736 extern TAILQ_HEAD(gdt_softc_list, gdt_softc) gdt_softcs;
737 extern u_int8_t gdt_polling;
738 
739 cdev_t   gdt_make_dev(int unit);
740 void    gdt_destroy_dev(cdev_t dev);
741 void    gdt_next(struct gdt_softc *gdt);
742 void gdt_free_ccb(struct gdt_softc *gdt, struct gdt_ccb *gccb);
743 
744 gdt_evt_str *gdt_store_event(u_int16_t source, u_int16_t idx,
745                              gdt_evt_data *evt);
746 int gdt_read_event(int handle, gdt_evt_str *estr);
747 void gdt_readapp_event(u_int8_t app, gdt_evt_str *estr);
748 void gdt_clear_events(void);
749 
750 #endif
751