1 /* $OpenBSD: dwqevar.h,v 1.11 2024/02/26 18:57:50 kettenis Exp $ */ 2 /* 3 * Copyright (c) 2008, 2019 Mark Kettenis <kettenis@openbsd.org> 4 * Copyright (c) 2017, 2022 Patrick Wildt <patrick@blueri.se> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 enum dwqe_phy_mode { 20 DWQE_PHY_MODE_UNKNOWN, 21 DWQE_PHY_MODE_RMII, 22 DWQE_PHY_MODE_RGMII, 23 DWQE_PHY_MODE_RGMII_ID, 24 DWQE_PHY_MODE_RGMII_TXID, 25 DWQE_PHY_MODE_RGMII_RXID, 26 DWQE_PHY_MODE_SGMII, 27 }; 28 29 struct dwqe_buf { 30 bus_dmamap_t tb_map; 31 struct mbuf *tb_m; 32 }; 33 34 #define DWQE_NTXDESC 256 35 #define DWQE_NTXSEGS 16 36 37 #define DWQE_NRXDESC 256 38 39 struct dwqe_dmamem { 40 bus_dmamap_t tdm_map; 41 bus_dma_segment_t tdm_seg; 42 size_t tdm_size; 43 caddr_t tdm_kva; 44 }; 45 #define DWQE_DMA_MAP(_tdm) ((_tdm)->tdm_map) 46 #define DWQE_DMA_LEN(_tdm) ((_tdm)->tdm_size) 47 #define DWQE_DMA_DVA(_tdm) ((_tdm)->tdm_map->dm_segs[0].ds_addr) 48 #define DWQE_DMA_KVA(_tdm) ((void *)(_tdm)->tdm_kva) 49 50 struct dwqe_softc { 51 struct device sc_dev; 52 int sc_node; 53 bus_space_tag_t sc_iot; 54 bus_space_handle_t sc_ioh; 55 bus_dma_tag_t sc_dmat; 56 void *sc_ih; 57 58 struct arpcom sc_ac; 59 #define sc_lladdr sc_ac.ac_enaddr 60 struct mii_data sc_mii; 61 #define sc_media sc_mii.mii_media 62 int sc_link; 63 int sc_phyloc; 64 enum dwqe_phy_mode sc_phy_mode; 65 struct timeout sc_phy_tick; 66 int sc_fixed_link; 67 68 struct dwqe_dmamem *sc_txring; 69 struct dwqe_buf *sc_txbuf; 70 struct dwqe_desc *sc_txdesc; 71 int sc_tx_prod; 72 int sc_tx_cons; 73 74 struct dwqe_dmamem *sc_rxring; 75 struct dwqe_buf *sc_rxbuf; 76 struct dwqe_desc *sc_rxdesc; 77 int sc_rx_prod; 78 struct if_rxring sc_rx_ring; 79 int sc_rx_cons; 80 81 struct timeout sc_rxto; 82 struct task sc_statchg_task; 83 84 uint32_t sc_clk; 85 uint32_t sc_clkrate; 86 87 bus_size_t sc_clk_sel; 88 uint32_t sc_clk_sel_125; 89 uint32_t sc_clk_sel_25; 90 uint32_t sc_clk_sel_2_5; 91 92 int sc_hw_feature[4]; 93 94 int sc_force_thresh_dma_mode; 95 int sc_fixed_burst; 96 int sc_mixed_burst; 97 int sc_aal; 98 int sc_8xpbl; 99 int sc_pbl; 100 int sc_txpbl; 101 int sc_rxpbl; 102 int sc_txfifo_size; 103 int sc_rxfifo_size; 104 int sc_axi_config; 105 int sc_lpi_en; 106 int sc_xit_frm; 107 int sc_wr_osr_lmt; 108 int sc_rd_osr_lmt; 109 110 uint32_t sc_blen[7]; 111 }; 112 113 #define DEVNAME(_s) ((_s)->sc_dev.dv_xname) 114 115 int dwqe_attach(struct dwqe_softc *); 116 void dwqe_reset(struct dwqe_softc *); 117 int dwqe_intr(void *); 118 uint32_t dwqe_read(struct dwqe_softc *, bus_addr_t); 119 void dwqe_write(struct dwqe_softc *, bus_addr_t, uint32_t); 120 void dwqe_lladdr_read(struct dwqe_softc *, uint8_t *); 121 void dwqe_lladdr_write(struct dwqe_softc *); 122 void dwqe_mii_statchg(struct device *); 123