1 /* $NetBSD: vr4181aiu.c,v 1.11 2018/09/03 16:29:24 riastradh Exp $ */
2
3 /*
4 * Copyright (c) 2002 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Naoto Shimazaki of YOKOGAWA Electric Corporation.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: vr4181aiu.c,v 1.11 2018/09/03 16:29:24 riastradh Exp $");
34
35 #include <sys/param.h>
36 #include <sys/conf.h>
37 #include <sys/device.h>
38 #include <sys/errno.h>
39 #include <sys/malloc.h>
40 #include <sys/proc.h>
41 #include <sys/systm.h>
42
43 #include <mips/cpuregs.h>
44
45 #include <machine/bus.h>
46
47 #include <hpcmips/vr/vripif.h>
48 #include <hpcmips/vr/vr4181aiureg.h>
49 #include <hpcmips/vr/vr4181dcureg.h>
50
51 #define INBUFLEN 1024 /* length in u_int16_t */
52 #define INPUTLEN 1000
53 #define SAMPLEFREQ 1000
54 #define PICKUPFREQ 100
55 #define PICKUPCOUNT (SAMPLEFREQ / PICKUPFREQ)
56
57 #define ST_BUSY 0x01
58 #define ST_OVERRUN 0x02
59
60 #define INBUF_MASK 0x3ff /* 2Kbyte */
61 #define INBUF_RAW_SIZE (INBUFLEN * 4 + (INBUF_MASK + 1))
62
63 #ifdef VR4181AIU_DEBUG
64 int vr4181aiu_debug = 0;
65 #define DPRINTF(x) if (vr4181aiu_debug) printf x
66 #else
67 #define DPRINTF(x)
68 #endif
69
70
71 struct vr4181aiu_softc {
72 bus_space_tag_t sc_iot;
73 bus_space_handle_t sc_dcu1_ioh;
74 bus_space_handle_t sc_dcu2_ioh;
75 bus_space_handle_t sc_aiu_ioh;
76 u_int16_t *sc_inbuf_head;
77 u_int16_t *sc_inbuf_tail;
78 u_int16_t *sc_inbuf_which;
79 u_int16_t *sc_inbuf1;
80 u_int16_t *sc_inbuf2;
81 u_int16_t *sc_inbuf_raw;
82 int sc_status;
83 };
84
85 static int vr4181aiu_match(device_t, cfdata_t, void *);
86 static void vr4181aiu_attach(device_t, device_t, void *);
87 static int vr4181aiu_intr(void *);
88
89 extern struct cfdriver vr4181aiu_cd;
90
91 CFATTACH_DECL_NEW(vr4181aiu, sizeof(struct vr4181aiu_softc),
92 vr4181aiu_match, vr4181aiu_attach, NULL, NULL);
93
94 dev_type_open(vr4181aiuopen);
95 dev_type_close(vr4181aiuclose);
96 dev_type_read(vr4181aiuread);
97 dev_type_write(vr4181aiuwrite);
98
99 const struct cdevsw vr4181aiu_cdevsw = {
100 .d_open = vr4181aiuopen,
101 .d_close = vr4181aiuclose,
102 .d_read = vr4181aiuread,
103 .d_write = vr4181aiuwrite,
104 .d_ioctl = noioctl,
105 .d_stop = nostop,
106 .d_tty = notty,
107 .d_poll = nopoll,
108 .d_mmap = nommap,
109 .d_kqfilter = nokqfilter,
110 .d_discard = nodiscard,
111 .d_flag = 0
112 };
113
114 static int
vr4181aiu_match(device_t parent,cfdata_t cf,void * aux)115 vr4181aiu_match(device_t parent, cfdata_t cf, void *aux)
116 {
117 return 1;
118 }
119
120 static void
vr4181aiu_init_inbuf(struct vr4181aiu_softc * sc)121 vr4181aiu_init_inbuf(struct vr4181aiu_softc *sc)
122 {
123 /*
124 * XXXXXXXXXXXXXXXXX
125 *
126 * this is just a quick and dirty hack to locate the buffer
127 * in KSEG0 space. the only reason is that i want the physical
128 * address of the buffer.
129 *
130 * bus_dma framework should be used.
131 */
132 static char inbufbase[INBUF_RAW_SIZE];
133
134 sc->sc_inbuf_raw = (u_int16_t *) inbufbase;
135
136 sc->sc_inbuf1 = (u_int16_t *) ((((u_int32_t) sc->sc_inbuf_raw)
137 + INBUF_MASK)
138 & ~INBUF_MASK);
139 sc->sc_inbuf2 = sc->sc_inbuf1 + INBUFLEN;
140 }
141
142 static void
vr4181aiu_disable(struct vr4181aiu_softc * sc)143 vr4181aiu_disable(struct vr4181aiu_softc *sc)
144 {
145 /* irq clear */
146 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh,
147 DCU_DMAITRQ_REG_W, DCU_MICEOP);
148 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh,
149 VR4181AIU_INT_REG_W,
150 VR4181AIU_MIDLEINTR
151 | VR4181AIU_MSTINTR
152 | VR4181AIU_SIDLEINTR);
153
154 /* disable microphone */
155 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh,
156 VR4181AIU_SEQ_REG_W, 0);
157
158 /* disable ADC */
159 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh,
160 VR4181AIU_MCNT_REG_W, 0);
161
162 /* disable DMA */
163 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh,
164 DCU_AIUDMAMSK_REG_W, 0);
165 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh,
166 DCU_DMAITMK_REG_W, 0);
167
168 sc->sc_status = 0;
169 }
170
171 static void
vr4181aiu_attach(device_t parent,device_t self,void * aux)172 vr4181aiu_attach(device_t parent, device_t self, void *aux)
173 {
174 struct vrip_attach_args *va = aux;
175 struct vr4181aiu_softc *sc = device_private(self);
176
177 vr4181aiu_init_inbuf(sc);
178 memset(sc->sc_inbuf1, 0x55, INBUFLEN * 2);
179 memset(sc->sc_inbuf2, 0xaa, INBUFLEN * 2);
180
181 sc->sc_status = 0;
182 sc->sc_iot = va->va_iot;
183
184 if (bus_space_map(sc->sc_iot,
185 VR4181AIU_DCU1_BASE, VR4181AIU_DCU1_SIZE,
186 0, &sc->sc_dcu1_ioh))
187 goto out_dcu1;
188 if (bus_space_map(sc->sc_iot,
189 VR4181AIU_DCU2_BASE, VR4181AIU_DCU2_SIZE,
190 0, &sc->sc_dcu2_ioh))
191 goto out_dcu2;
192 if (bus_space_map(sc->sc_iot,
193 VR4181AIU_AIU_BASE, VR4181AIU_AIU_SIZE,
194 0, &sc->sc_aiu_ioh))
195 goto out_aiu;
196
197 /*
198 * reset AIU
199 */
200 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh,
201 VR4181AIU_SEQ_REG_W, VR4181AIU_AIURST);
202 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh,
203 VR4181AIU_SEQ_REG_W, 0);
204
205 /*
206 * set sample rate (1kHz fixed)
207 * XXXX
208 * assume to PCLK is 32.768MHz
209 */
210 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh,
211 VR4181AIU_MCNVC_END,
212 32768000 / SAMPLEFREQ);
213
214 /*
215 * XXXX
216 * assume to PCLK is 32.768MHz
217 * DAVREF_SETUP = 5usec * PCLK = 163.84
218 */
219 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh,
220 VR4181AIU_DAVREF_SETUP_REG_W, 164);
221
222 vr4181aiu_disable(sc);
223
224 if (vrip_intr_establish(va->va_vc, va->va_unit, 0,
225 IPL_BIO, vr4181aiu_intr, sc) == NULL) {
226 printf("%s: can't establish interrupt\n",
227 device_xname(self));
228 return;
229 }
230
231 printf("\n");
232 return;
233
234 out_aiu:
235 bus_space_unmap(sc->sc_iot, sc->sc_dcu2_ioh, VR4181AIU_DCU2_SIZE);
236 out_dcu2:
237 bus_space_unmap(sc->sc_iot, sc->sc_dcu1_ioh, VR4181AIU_DCU1_SIZE);
238 out_dcu1:
239 printf(": can't map i/o space\n");
240 }
241
242 int
vr4181aiuopen(dev_t dev,int flag,int mode,struct lwp * l)243 vr4181aiuopen(dev_t dev, int flag, int mode, struct lwp *l)
244 {
245 struct vr4181aiu_softc *sc;
246
247 sc = device_lookup_private(&vr4181aiu_cd, minor(dev));
248 if (sc == NULL)
249 return ENXIO;
250
251 if (sc->sc_status & ST_BUSY)
252 return EBUSY;
253
254 sc->sc_inbuf_head = sc->sc_inbuf_tail
255 = sc->sc_inbuf_which = sc->sc_inbuf1;
256 sc->sc_status &= ~ST_OVERRUN;
257
258 /* setup DMA */
259 /* reset */
260 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh,
261 DCU_DMARST_REG_W, 0);
262 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh,
263 DCU_DMARST_REG_W, DCU_DMARST);
264 /* dest1 <- sc_inbuf1 */
265 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh,
266 DCU_MICDEST1REG1_W,
267 MIPS_KSEG0_TO_PHYS(sc->sc_inbuf1) & 0xffff);
268 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh,
269 DCU_MICDEST1REG2_W,
270 MIPS_KSEG0_TO_PHYS(sc->sc_inbuf1) >> 16);
271 /* dest2 <- sc_inbuf2 */
272 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh,
273 DCU_MICDEST2REG1_W,
274 MIPS_KSEG0_TO_PHYS(sc->sc_inbuf2) & 0xffff);
275 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh,
276 DCU_MICDEST2REG2_W,
277 MIPS_KSEG0_TO_PHYS(sc->sc_inbuf2) >> 16);
278 /* record length <- INPUTLEN */
279 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh,
280 DCU_MICRCLEN_REG_W, INPUTLEN);
281 /* config <- auto load */
282 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh,
283 DCU_MICDMACFG_REG_W, DCU_MICLOAD);
284 /* irq <- irq clear */
285 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh,
286 DCU_DMAITRQ_REG_W, DCU_MICEOP);
287 /* control <- INC */
288 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh,
289 DCU_DMACTL_REG_W, DCU_MICCNT_INC);
290 /* irq mask <- microphone end of process */
291 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh,
292 DCU_DMAITMK_REG_W, DCU_MICEOP_ENABLE);
293
294 /* enable DMA */
295 bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh,
296 DCU_AIUDMAMSK_REG_W, DCU_ENABLE_MIC);
297
298 /* enable ADC */
299 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh,
300 VR4181AIU_MCNT_REG_W, VR4181AIU_ADENAIU);
301
302 /* enable microphone */
303 bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh,
304 VR4181AIU_SEQ_REG_W, VR4181AIU_AIUMEN);
305
306 sc->sc_status |= ST_BUSY;
307
308 return 0;
309 }
310
311 int
vr4181aiuclose(dev_t dev,int flag,int mode,struct lwp * l)312 vr4181aiuclose(dev_t dev, int flag, int mode, struct lwp *l)
313 {
314 vr4181aiu_disable(device_lookup_private(&vr4181aiu_cd, minor(dev)));
315 return 0;
316 }
317
318 int
vr4181aiuread(dev_t dev,struct uio * uio,int flag)319 vr4181aiuread(dev_t dev, struct uio *uio, int flag)
320 {
321 struct vr4181aiu_softc *sc;
322 int s;
323 u_int16_t *fence;
324 int avail;
325 int count;
326 u_int8_t tmp[INPUTLEN / PICKUPCOUNT];
327 u_int16_t *src;
328 u_int8_t *dst;
329
330 sc = device_lookup_private(&vr4181aiu_cd, minor(dev));
331
332 src = sc->sc_inbuf_tail;
333 s = splbio();
334 if (src == sc->sc_inbuf_head) {
335 /* wait for DMA to complete writing */
336 tsleep(sc, PRIBIO, "aiu read", 0);
337 /* now sc_inbuf_head points alternate buffer */
338 }
339 splx(s);
340
341 fence = sc->sc_inbuf_which == sc->sc_inbuf1
342 ? &sc->sc_inbuf1[INPUTLEN]
343 : &sc->sc_inbuf2[INPUTLEN];
344 avail = (fence - src) / PICKUPCOUNT;
345 count = uimin(avail, uio->uio_resid);
346 dst = tmp;
347 while (count > 0) {
348 *dst++ = (u_int8_t) (*src >> 2);
349 src += PICKUPCOUNT;
350 count--;
351 }
352
353 if (src < fence) {
354 sc->sc_inbuf_tail = src;
355 } else {
356 /* alter the buffer */
357 sc->sc_inbuf_tail
358 = sc->sc_inbuf_which
359 = sc->sc_inbuf_which == sc->sc_inbuf1
360 ? sc->sc_inbuf2 : sc->sc_inbuf1;
361 }
362
363 return uiomove(tmp, dst - tmp, uio);
364 }
365
366 int
vr4181aiuwrite(dev_t dev,struct uio * uio,int flag)367 vr4181aiuwrite(dev_t dev, struct uio *uio, int flag)
368 {
369 return 0;
370 }
371
372 /*
373 * interrupt handler
374 */
375 static int
vr4181aiu_intr(void * arg)376 vr4181aiu_intr(void *arg)
377 {
378 struct vr4181aiu_softc *sc = arg;
379
380 if (!(sc->sc_status & ST_BUSY)) {
381 printf("vr4181aiu_intr: stray interrupt\n");
382 vr4181aiu_disable(sc);
383 return 0;
384 }
385
386 /* irq clear */
387 bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh,
388 DCU_DMAITRQ_REG_W, DCU_MICEOP);
389
390 if (sc->sc_inbuf_head == sc->sc_inbuf1) {
391 if (sc->sc_inbuf_tail != sc->sc_inbuf1)
392 sc->sc_status |= ST_OVERRUN;
393 sc->sc_inbuf_head = sc->sc_inbuf2;
394 } else {
395 if (sc->sc_inbuf_tail != sc->sc_inbuf2)
396 sc->sc_status |= ST_OVERRUN;
397 sc->sc_inbuf_head = sc->sc_inbuf1;
398 }
399
400 if (sc->sc_status & ST_OVERRUN) {
401 printf("vr4181aiu_intr: overrun\n");
402 }
403
404 DPRINTF(("vr4181aiu_intr: sc_inbuf1 = %04x, sc_inbuf2 = %04x\n",
405 sc->sc_inbuf1[0], sc->sc_inbuf2[0]));
406
407 wakeup(sc);
408
409 return 0;
410 }
411