1 /* $NetBSD: hwmgr.h,v 1.3 2021/12/19 10:59:02 riastradh Exp $ */ 2 3 /* 4 * Copyright 2015 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef _HWMGR_H_ 26 #define _HWMGR_H_ 27 28 #include <linux/seq_file.h> 29 #include "amd_powerplay.h" 30 #include "hardwaremanager.h" 31 #include "hwmgr_ppt.h" 32 #include "ppatomctrl.h" 33 #include "power_state.h" 34 #include "smu_helper.h" 35 36 struct pp_hwmgr; 37 struct phm_fan_speed_info; 38 struct pp_atomctrl_voltage_table; 39 40 #define VOLTAGE_SCALE 4 41 #define VOLTAGE_VID_OFFSET_SCALE1 625 42 #define VOLTAGE_VID_OFFSET_SCALE2 100 43 44 enum DISPLAY_GAP { 45 DISPLAY_GAP_VBLANK_OR_WM = 0, /* Wait for vblank or MCHG watermark. */ 46 DISPLAY_GAP_VBLANK = 1, /* Wait for vblank. */ 47 DISPLAY_GAP_WATERMARK = 2, /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */ 48 DISPLAY_GAP_IGNORE = 3 /* Do not wait. */ 49 }; 50 typedef enum DISPLAY_GAP DISPLAY_GAP; 51 52 enum BACO_STATE { 53 BACO_STATE_OUT = 0, 54 BACO_STATE_IN, 55 }; 56 57 struct vi_dpm_level { 58 bool enabled; 59 uint32_t value; 60 uint32_t param1; 61 }; 62 63 struct vi_dpm_table { 64 uint32_t count; 65 struct vi_dpm_level dpm_level[1]; 66 }; 67 68 #define PCIE_PERF_REQ_REMOVE_REGISTRY 0 69 #define PCIE_PERF_REQ_FORCE_LOWPOWER 1 70 #define PCIE_PERF_REQ_GEN1 2 71 #define PCIE_PERF_REQ_GEN2 3 72 #define PCIE_PERF_REQ_GEN3 4 73 74 enum PHM_BackEnd_Magic { 75 PHM_Dummy_Magic = 0xAA5555AA, 76 PHM_RV770_Magic = 0xDCBAABCD, 77 PHM_Kong_Magic = 0x239478DF, 78 PHM_NIslands_Magic = 0x736C494E, 79 PHM_Sumo_Magic = 0x8339FA11, 80 PHM_SIslands_Magic = 0x369431AC, 81 PHM_Trinity_Magic = 0x96751873, 82 PHM_CIslands_Magic = 0x38AC78B0, 83 PHM_Kv_Magic = 0xDCBBABC0, 84 PHM_VIslands_Magic = 0x20130307, 85 PHM_Cz_Magic = 0x67DCBA25, 86 PHM_Rv_Magic = 0x20161121 87 }; 88 89 struct phm_set_power_state_input { 90 const struct pp_hw_power_state *pcurrent_state; 91 const struct pp_hw_power_state *pnew_state; 92 }; 93 94 struct phm_clock_array { 95 uint32_t count; 96 uint32_t values[1]; 97 }; 98 99 struct phm_clock_voltage_dependency_record { 100 uint32_t clk; 101 uint32_t v; 102 }; 103 104 struct phm_vceclock_voltage_dependency_record { 105 uint32_t ecclk; 106 uint32_t evclk; 107 uint32_t v; 108 }; 109 110 struct phm_uvdclock_voltage_dependency_record { 111 uint32_t vclk; 112 uint32_t dclk; 113 uint32_t v; 114 }; 115 116 struct phm_samuclock_voltage_dependency_record { 117 uint32_t samclk; 118 uint32_t v; 119 }; 120 121 struct phm_acpclock_voltage_dependency_record { 122 uint32_t acpclk; 123 uint32_t v; 124 }; 125 126 struct phm_clock_voltage_dependency_table { 127 uint32_t count; /* Number of entries. */ 128 struct phm_clock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ 129 }; 130 131 struct phm_phase_shedding_limits_record { 132 uint32_t Voltage; 133 uint32_t Sclk; 134 uint32_t Mclk; 135 }; 136 137 struct phm_uvd_clock_voltage_dependency_record { 138 uint32_t vclk; 139 uint32_t dclk; 140 uint32_t v; 141 }; 142 143 struct phm_uvd_clock_voltage_dependency_table { 144 uint8_t count; 145 struct phm_uvd_clock_voltage_dependency_record entries[1]; 146 }; 147 148 struct phm_acp_clock_voltage_dependency_record { 149 uint32_t acpclk; 150 uint32_t v; 151 }; 152 153 struct phm_acp_clock_voltage_dependency_table { 154 uint32_t count; 155 struct phm_acp_clock_voltage_dependency_record entries[1]; 156 }; 157 158 struct phm_vce_clock_voltage_dependency_record { 159 uint32_t ecclk; 160 uint32_t evclk; 161 uint32_t v; 162 }; 163 164 struct phm_phase_shedding_limits_table { 165 uint32_t count; 166 struct phm_phase_shedding_limits_record entries[1]; 167 }; 168 169 struct phm_vceclock_voltage_dependency_table { 170 uint8_t count; /* Number of entries. */ 171 struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ 172 }; 173 174 struct phm_uvdclock_voltage_dependency_table { 175 uint8_t count; /* Number of entries. */ 176 struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ 177 }; 178 179 struct phm_samuclock_voltage_dependency_table { 180 uint8_t count; /* Number of entries. */ 181 struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ 182 }; 183 184 struct phm_acpclock_voltage_dependency_table { 185 uint32_t count; /* Number of entries. */ 186 struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */ 187 }; 188 189 struct phm_vce_clock_voltage_dependency_table { 190 uint8_t count; 191 struct phm_vce_clock_voltage_dependency_record entries[1]; 192 }; 193 194 195 enum SMU_ASIC_RESET_MODE 196 { 197 SMU_ASIC_RESET_MODE_0, 198 SMU_ASIC_RESET_MODE_1, 199 SMU_ASIC_RESET_MODE_2, 200 }; 201 202 struct pp_smumgr_func { 203 const char *name; 204 int (*smu_init)(struct pp_hwmgr *hwmgr); 205 int (*smu_fini)(struct pp_hwmgr *hwmgr); 206 int (*start_smu)(struct pp_hwmgr *hwmgr); 207 int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr, 208 uint32_t firmware); 209 int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr); 210 int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr, 211 uint32_t firmware); 212 uint32_t (*get_argument)(struct pp_hwmgr *hwmgr); 213 int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg); 214 int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr, 215 uint16_t msg, uint32_t parameter); 216 int (*download_pptable_settings)(struct pp_hwmgr *hwmgr, 217 void **table); 218 int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr); 219 int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type); 220 int (*process_firmware_header)(struct pp_hwmgr *hwmgr); 221 int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr); 222 int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr); 223 int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr); 224 int (*init_smc_table)(struct pp_hwmgr *hwmgr); 225 int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr); 226 int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr); 227 int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr); 228 uint32_t (*get_offsetof)(uint32_t type, uint32_t member); 229 uint32_t (*get_mac_definition)(uint32_t value); 230 bool (*is_dpm_running)(struct pp_hwmgr *hwmgr); 231 bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr); 232 int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting); 233 int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */ 234 }; 235 236 struct pp_hwmgr_func { 237 int (*backend_init)(struct pp_hwmgr *hw_mgr); 238 int (*backend_fini)(struct pp_hwmgr *hw_mgr); 239 int (*asic_setup)(struct pp_hwmgr *hw_mgr); 240 int (*get_power_state_size)(struct pp_hwmgr *hw_mgr); 241 242 int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr, 243 struct pp_power_state *prequest_ps, 244 const struct pp_power_state *pcurrent_ps); 245 246 int (*apply_clocks_adjust_rules)(struct pp_hwmgr *hwmgr); 247 248 int (*force_dpm_level)(struct pp_hwmgr *hw_mgr, 249 enum amd_dpm_forced_level level); 250 251 int (*dynamic_state_management_enable)( 252 struct pp_hwmgr *hw_mgr); 253 int (*dynamic_state_management_disable)( 254 struct pp_hwmgr *hw_mgr); 255 256 int (*patch_boot_state)(struct pp_hwmgr *hwmgr, 257 struct pp_hw_power_state *hw_ps); 258 259 int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr, 260 unsigned long, struct pp_power_state *); 261 int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr); 262 int (*powerdown_uvd)(struct pp_hwmgr *hwmgr); 263 void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate); 264 void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate); 265 void (*powergate_acp)(struct pp_hwmgr *hwmgr, bool bgate); 266 uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low); 267 uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low); 268 int (*power_state_set)(struct pp_hwmgr *hwmgr, 269 const void *state); 270 int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr); 271 int (*pre_display_config_changed)(struct pp_hwmgr *hwmgr); 272 int (*display_config_changed)(struct pp_hwmgr *hwmgr); 273 int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr); 274 int (*update_clock_gatings)(struct pp_hwmgr *hwmgr, 275 const uint32_t *msg_id); 276 int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm); 277 int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm); 278 int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr); 279 int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info); 280 void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode); 281 uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr); 282 int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent); 283 int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed); 284 int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent); 285 int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed); 286 int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr); 287 int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr); 288 int (*register_irq_handlers)(struct pp_hwmgr *hwmgr); 289 bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr); 290 int (*check_states_equal)(struct pp_hwmgr *hwmgr, 291 const struct pp_hw_power_state *pstate1, 292 const struct pp_hw_power_state *pstate2, 293 bool *equal); 294 int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr); 295 int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time, 296 bool cc6_disable, bool pstate_disable, 297 bool pstate_switch_disable); 298 int (*get_dal_power_level)(struct pp_hwmgr *hwmgr, 299 struct amd_pp_simple_clock_info *info); 300 int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *, 301 PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *); 302 int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr, 303 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info); 304 int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks); 305 int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr, 306 enum amd_pp_clock_type type, 307 struct pp_clock_levels_with_latency *clocks); 308 int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr, 309 enum amd_pp_clock_type type, 310 struct pp_clock_levels_with_voltage *clocks); 311 int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges); 312 int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr, 313 struct pp_display_clock_request *clock); 314 int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks); 315 int (*power_off_asic)(struct pp_hwmgr *hwmgr); 316 int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask); 317 int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf); 318 int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable); 319 int (*get_sclk_od)(struct pp_hwmgr *hwmgr); 320 int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value); 321 int (*get_mclk_od)(struct pp_hwmgr *hwmgr); 322 int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value); 323 int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size); 324 int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable); 325 int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr); 326 int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count); 327 int (*set_min_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock); 328 int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range); 329 int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr, 330 uint32_t virtual_addr_low, 331 uint32_t virtual_addr_hi, 332 uint32_t mc_addr_low, 333 uint32_t mc_addr_hi, 334 uint32_t size); 335 int (*update_nbdpm_pstate)(struct pp_hwmgr *hwmgr, 336 bool enable, 337 bool lock); 338 int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr, 339 struct PP_TemperatureRange *range); 340 int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf); 341 int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size); 342 int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr, 343 enum PP_OD_DPM_TABLE_COMMAND type, 344 long *input, uint32_t size); 345 int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n); 346 int (*powergate_mmhub)(struct pp_hwmgr *hwmgr); 347 int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr); 348 int (*powergate_sdma)(struct pp_hwmgr *hwmgr, bool bgate); 349 int (*enable_mgpu_fan_boost)(struct pp_hwmgr *hwmgr); 350 int (*set_hard_min_dcefclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock); 351 int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock); 352 int (*get_asic_baco_capability)(struct pp_hwmgr *hwmgr, bool *cap); 353 int (*get_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE *state); 354 int (*set_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE state); 355 int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf); 356 int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks); 357 int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state); 358 int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode); 359 int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire); 360 int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate state); 361 int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate); 362 int (*disable_power_features_for_compute_performance)(struct pp_hwmgr *hwmgr, 363 bool disable); 364 }; 365 366 struct pp_table_func { 367 int (*pptable_init)(struct pp_hwmgr *hw_mgr); 368 int (*pptable_fini)(struct pp_hwmgr *hw_mgr); 369 int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr); 370 int (*pptable_get_vce_state_table_entry)( 371 struct pp_hwmgr *hwmgr, 372 unsigned long i, 373 struct amd_vce_state *vce_state, 374 void **clock_info, 375 unsigned long *flag); 376 }; 377 378 union phm_cac_leakage_record { 379 struct { 380 uint16_t Vddc; /* in CI, we use it for StdVoltageHiSidd */ 381 uint32_t Leakage; /* in CI, we use it for StdVoltageLoSidd */ 382 }; 383 struct { 384 uint16_t Vddc1; 385 uint16_t Vddc2; 386 uint16_t Vddc3; 387 }; 388 }; 389 390 struct phm_cac_leakage_table { 391 uint32_t count; 392 union phm_cac_leakage_record entries[1]; 393 }; 394 395 struct phm_samu_clock_voltage_dependency_record { 396 uint32_t samclk; 397 uint32_t v; 398 }; 399 400 401 struct phm_samu_clock_voltage_dependency_table { 402 uint8_t count; 403 struct phm_samu_clock_voltage_dependency_record entries[1]; 404 }; 405 406 struct phm_cac_tdp_table { 407 uint16_t usTDP; 408 uint16_t usConfigurableTDP; 409 uint16_t usTDC; 410 uint16_t usBatteryPowerLimit; 411 uint16_t usSmallPowerLimit; 412 uint16_t usLowCACLeakage; 413 uint16_t usHighCACLeakage; 414 uint16_t usMaximumPowerDeliveryLimit; 415 uint16_t usEDCLimit; 416 uint16_t usOperatingTempMinLimit; 417 uint16_t usOperatingTempMaxLimit; 418 uint16_t usOperatingTempStep; 419 uint16_t usOperatingTempHyst; 420 uint16_t usDefaultTargetOperatingTemp; 421 uint16_t usTargetOperatingTemp; 422 uint16_t usPowerTuneDataSetID; 423 uint16_t usSoftwareShutdownTemp; 424 uint16_t usClockStretchAmount; 425 uint16_t usTemperatureLimitHotspot; 426 uint16_t usTemperatureLimitLiquid1; 427 uint16_t usTemperatureLimitLiquid2; 428 uint16_t usTemperatureLimitVrVddc; 429 uint16_t usTemperatureLimitVrMvdd; 430 uint16_t usTemperatureLimitPlx; 431 uint8_t ucLiquid1_I2C_address; 432 uint8_t ucLiquid2_I2C_address; 433 uint8_t ucLiquid_I2C_Line; 434 uint8_t ucVr_I2C_address; 435 uint8_t ucVr_I2C_Line; 436 uint8_t ucPlx_I2C_address; 437 uint8_t ucPlx_I2C_Line; 438 uint32_t usBoostPowerLimit; 439 uint8_t ucCKS_LDO_REFSEL; 440 }; 441 442 struct phm_tdp_table { 443 uint16_t usTDP; 444 uint16_t usConfigurableTDP; 445 uint16_t usTDC; 446 uint16_t usBatteryPowerLimit; 447 uint16_t usSmallPowerLimit; 448 uint16_t usLowCACLeakage; 449 uint16_t usHighCACLeakage; 450 uint16_t usMaximumPowerDeliveryLimit; 451 uint16_t usEDCLimit; 452 uint16_t usOperatingTempMinLimit; 453 uint16_t usOperatingTempMaxLimit; 454 uint16_t usOperatingTempStep; 455 uint16_t usOperatingTempHyst; 456 uint16_t usDefaultTargetOperatingTemp; 457 uint16_t usTargetOperatingTemp; 458 uint16_t usPowerTuneDataSetID; 459 uint16_t usSoftwareShutdownTemp; 460 uint16_t usClockStretchAmount; 461 uint16_t usTemperatureLimitTedge; 462 uint16_t usTemperatureLimitHotspot; 463 uint16_t usTemperatureLimitLiquid1; 464 uint16_t usTemperatureLimitLiquid2; 465 uint16_t usTemperatureLimitHBM; 466 uint16_t usTemperatureLimitVrVddc; 467 uint16_t usTemperatureLimitVrMvdd; 468 uint16_t usTemperatureLimitPlx; 469 uint8_t ucLiquid1_I2C_address; 470 uint8_t ucLiquid2_I2C_address; 471 uint8_t ucLiquid_I2C_Line; 472 uint8_t ucVr_I2C_address; 473 uint8_t ucVr_I2C_Line; 474 uint8_t ucPlx_I2C_address; 475 uint8_t ucPlx_I2C_Line; 476 uint8_t ucLiquid_I2C_LineSDA; 477 uint8_t ucVr_I2C_LineSDA; 478 uint8_t ucPlx_I2C_LineSDA; 479 uint32_t usBoostPowerLimit; 480 uint16_t usBoostStartTemperature; 481 uint16_t usBoostStopTemperature; 482 uint32_t ulBoostClock; 483 }; 484 485 struct phm_ppm_table { 486 uint8_t ppm_design; 487 uint16_t cpu_core_number; 488 uint32_t platform_tdp; 489 uint32_t small_ac_platform_tdp; 490 uint32_t platform_tdc; 491 uint32_t small_ac_platform_tdc; 492 uint32_t apu_tdp; 493 uint32_t dgpu_tdp; 494 uint32_t dgpu_ulv_power; 495 uint32_t tj_max; 496 }; 497 498 struct phm_vq_budgeting_record { 499 uint32_t ulCUs; 500 uint32_t ulSustainableSOCPowerLimitLow; 501 uint32_t ulSustainableSOCPowerLimitHigh; 502 uint32_t ulMinSclkLow; 503 uint32_t ulMinSclkHigh; 504 uint8_t ucDispConfig; 505 uint32_t ulDClk; 506 uint32_t ulEClk; 507 uint32_t ulSustainableSclk; 508 uint32_t ulSustainableCUs; 509 }; 510 511 struct phm_vq_budgeting_table { 512 uint8_t numEntries; 513 struct phm_vq_budgeting_record entries[1]; 514 }; 515 516 struct phm_clock_and_voltage_limits { 517 uint32_t sclk; 518 uint32_t mclk; 519 uint32_t gfxclk; 520 uint16_t vddc; 521 uint16_t vddci; 522 uint16_t vddgfx; 523 uint16_t vddmem; 524 }; 525 526 /* Structure to hold PPTable information */ 527 528 struct phm_ppt_v1_information { 529 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk; 530 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk; 531 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk; 532 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk; 533 struct phm_clock_array *valid_sclk_values; 534 struct phm_clock_array *valid_mclk_values; 535 struct phm_clock_array *valid_socclk_values; 536 struct phm_clock_array *valid_dcefclk_values; 537 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc; 538 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac; 539 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl; 540 struct phm_ppm_table *ppm_parameter_table; 541 struct phm_cac_tdp_table *cac_dtp_table; 542 struct phm_tdp_table *tdp_table; 543 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table; 544 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table; 545 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table; 546 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table; 547 struct phm_ppt_v1_pcie_table *pcie_table; 548 struct phm_ppt_v1_gpio_table *gpio_table; 549 uint16_t us_ulv_voltage_offset; 550 uint16_t us_ulv_smnclk_did; 551 uint16_t us_ulv_mp1clk_did; 552 uint16_t us_ulv_gfxclk_bypass; 553 uint16_t us_gfxclk_slew_rate; 554 uint16_t us_min_gfxclk_freq_limit; 555 }; 556 557 struct phm_ppt_v2_information { 558 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk; 559 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk; 560 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk; 561 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk; 562 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk; 563 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk; 564 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk; 565 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table; 566 567 struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl; 568 569 struct phm_clock_array *valid_sclk_values; 570 struct phm_clock_array *valid_mclk_values; 571 struct phm_clock_array *valid_socclk_values; 572 struct phm_clock_array *valid_dcefclk_values; 573 574 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc; 575 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac; 576 577 struct phm_ppm_table *ppm_parameter_table; 578 struct phm_cac_tdp_table *cac_dtp_table; 579 struct phm_tdp_table *tdp_table; 580 581 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table; 582 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table; 583 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table; 584 struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table; 585 586 struct phm_ppt_v1_pcie_table *pcie_table; 587 588 uint16_t us_ulv_voltage_offset; 589 uint16_t us_ulv_smnclk_did; 590 uint16_t us_ulv_mp1clk_did; 591 uint16_t us_ulv_gfxclk_bypass; 592 uint16_t us_gfxclk_slew_rate; 593 uint16_t us_min_gfxclk_freq_limit; 594 595 uint8_t uc_gfx_dpm_voltage_mode; 596 uint8_t uc_soc_dpm_voltage_mode; 597 uint8_t uc_uclk_dpm_voltage_mode; 598 uint8_t uc_uvd_dpm_voltage_mode; 599 uint8_t uc_vce_dpm_voltage_mode; 600 uint8_t uc_mp0_dpm_voltage_mode; 601 uint8_t uc_dcef_dpm_voltage_mode; 602 }; 603 604 struct phm_ppt_v3_information 605 { 606 uint8_t uc_thermal_controller_type; 607 608 uint16_t us_small_power_limit1; 609 uint16_t us_small_power_limit2; 610 uint16_t us_boost_power_limit; 611 612 uint16_t us_od_turbo_power_limit; 613 uint16_t us_od_powersave_power_limit; 614 uint16_t us_software_shutdown_temp; 615 616 uint32_t *power_saving_clock_max; 617 uint32_t *power_saving_clock_min; 618 619 uint8_t *od_feature_capabilities; 620 uint32_t *od_settings_max; 621 uint32_t *od_settings_min; 622 623 void *smc_pptable; 624 }; 625 626 struct phm_dynamic_state_info { 627 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk; 628 struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk; 629 struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk; 630 struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk; 631 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl; 632 struct phm_clock_array *valid_sclk_values; 633 struct phm_clock_array *valid_mclk_values; 634 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc; 635 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac; 636 uint32_t mclk_sclk_ratio; 637 uint32_t sclk_mclk_delta; 638 uint32_t vddc_vddci_delta; 639 uint32_t min_vddc_for_pcie_gen2; 640 struct phm_cac_leakage_table *cac_leakage_table; 641 struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table; 642 643 struct phm_vce_clock_voltage_dependency_table 644 *vce_clock_voltage_dependency_table; 645 struct phm_uvd_clock_voltage_dependency_table 646 *uvd_clock_voltage_dependency_table; 647 struct phm_acp_clock_voltage_dependency_table 648 *acp_clock_voltage_dependency_table; 649 struct phm_samu_clock_voltage_dependency_table 650 *samu_clock_voltage_dependency_table; 651 652 struct phm_ppm_table *ppm_parameter_table; 653 struct phm_cac_tdp_table *cac_dtp_table; 654 struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk; 655 }; 656 657 struct pp_fan_info { 658 bool bNoFan; 659 uint8_t ucTachometerPulsesPerRevolution; 660 uint32_t ulMinRPM; 661 uint32_t ulMaxRPM; 662 }; 663 664 struct pp_advance_fan_control_parameters { 665 uint16_t usTMin; /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */ 666 uint16_t usTMed; /* The middle temperature where we change slopes. */ 667 uint16_t usTHigh; /* The high temperature for setting the second slope. */ 668 uint16_t usPWMMin; /* The minimum PWM value in percent (0.01% increments). */ 669 uint16_t usPWMMed; /* The PWM value (in percent) at TMed. */ 670 uint16_t usPWMHigh; /* The PWM value at THigh. */ 671 uint8_t ucTHyst; /* Temperature hysteresis. Integer. */ 672 uint32_t ulCycleDelay; /* The time between two invocations of the fan control routine in microseconds. */ 673 uint16_t usTMax; /* The max temperature */ 674 uint8_t ucFanControlMode; 675 uint16_t usFanPWMMinLimit; 676 uint16_t usFanPWMMaxLimit; 677 uint16_t usFanPWMStep; 678 uint16_t usDefaultMaxFanPWM; 679 uint16_t usFanOutputSensitivity; 680 uint16_t usDefaultFanOutputSensitivity; 681 uint16_t usMaxFanPWM; /* The max Fan PWM value for Fuzzy Fan Control feature */ 682 uint16_t usFanRPMMinLimit; /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */ 683 uint16_t usFanRPMMaxLimit; /* Maximum limit range in percentage, usually set to 100% by default */ 684 uint16_t usFanRPMStep; /* Step increments/decerements, in percent */ 685 uint16_t usDefaultMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */ 686 uint16_t usMaxFanRPM; /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */ 687 uint16_t usFanCurrentLow; /* Low current */ 688 uint16_t usFanCurrentHigh; /* High current */ 689 uint16_t usFanRPMLow; /* Low RPM */ 690 uint16_t usFanRPMHigh; /* High RPM */ 691 uint32_t ulMinFanSCLKAcousticLimit; /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */ 692 uint8_t ucTargetTemperature; /* Advanced fan controller target temperature. */ 693 uint8_t ucMinimumPWMLimit; /* The minimum PWM that the advanced fan controller can set. This should be set to the highest PWM that will run the fan at its lowest RPM. */ 694 uint16_t usFanGainEdge; /* The following is added for Fiji */ 695 uint16_t usFanGainHotspot; 696 uint16_t usFanGainLiquid; 697 uint16_t usFanGainVrVddc; 698 uint16_t usFanGainVrMvdd; 699 uint16_t usFanGainPlx; 700 uint16_t usFanGainHbm; 701 uint8_t ucEnableZeroRPM; 702 uint8_t ucFanStopTemperature; 703 uint8_t ucFanStartTemperature; 704 uint32_t ulMaxFanSCLKAcousticLimit; /* Maximum Fan Controller SCLK Frequency Acoustic Limit. */ 705 uint32_t ulTargetGfxClk; 706 uint16_t usZeroRPMStartTemperature; 707 uint16_t usZeroRPMStopTemperature; 708 uint16_t usMGpuThrottlingRPMLimit; 709 }; 710 711 struct pp_thermal_controller_info { 712 uint8_t ucType; 713 uint8_t ucI2cLine; 714 uint8_t ucI2cAddress; 715 uint8_t use_hw_fan_control; 716 struct pp_fan_info fanInfo; 717 struct pp_advance_fan_control_parameters advanceFanControlParameters; 718 }; 719 720 struct phm_microcode_version_info { 721 uint32_t SMC; 722 uint32_t DMCU; 723 uint32_t MC; 724 uint32_t NB; 725 }; 726 727 enum PP_TABLE_VERSION { 728 PP_TABLE_V0 = 0, 729 PP_TABLE_V1, 730 PP_TABLE_V2, 731 PP_TABLE_MAX 732 }; 733 734 /** 735 * The main hardware manager structure. 736 */ 737 #define Workload_Policy_Max 6 738 739 struct pp_hwmgr { 740 void *adev; 741 uint32_t chip_family; 742 uint32_t chip_id; 743 uint32_t smu_version; 744 bool not_vf; 745 bool pm_en; 746 bool pp_one_vf; 747 struct mutex smu_lock; 748 749 uint32_t pp_table_version; 750 void *device; 751 struct pp_smumgr *smumgr; 752 const void *soft_pp_table; 753 uint32_t soft_pp_table_size; 754 void *hardcode_pp_table; 755 bool need_pp_table_upload; 756 757 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS]; 758 uint32_t num_vce_state_tables; 759 760 enum amd_dpm_forced_level dpm_level; 761 enum amd_dpm_forced_level saved_dpm_level; 762 enum amd_dpm_forced_level request_dpm_level; 763 uint32_t usec_timeout; 764 void *pptable; 765 struct phm_platform_descriptor platform_descriptor; 766 void *backend; 767 768 void *smu_backend; 769 const struct pp_smumgr_func *smumgr_funcs; 770 bool is_kicker; 771 772 enum PP_DAL_POWERLEVEL dal_power_level; 773 struct phm_dynamic_state_info dyn_state; 774 const struct pp_hwmgr_func *hwmgr_func; 775 const struct pp_table_func *pptable_func; 776 777 struct pp_power_state *ps; 778 uint32_t num_ps; 779 struct pp_thermal_controller_info thermal_controller; 780 bool fan_ctrl_is_in_default_mode; 781 uint32_t fan_ctrl_default_mode; 782 bool fan_ctrl_enabled; 783 uint32_t tmin; 784 struct phm_microcode_version_info microcode_version_info; 785 uint32_t ps_size; 786 struct pp_power_state *current_ps; 787 struct pp_power_state *request_ps; 788 struct pp_power_state *boot_ps; 789 struct pp_power_state *uvd_ps; 790 const struct amd_pp_display_configuration *display_config; 791 uint32_t feature_mask; 792 bool avfs_supported; 793 /* UMD Pstate */ 794 bool en_umd_pstate; 795 uint32_t power_profile_mode; 796 uint32_t default_power_profile_mode; 797 uint32_t pstate_sclk; 798 uint32_t pstate_mclk; 799 bool od_enabled; 800 uint32_t power_limit; 801 uint32_t default_power_limit; 802 uint32_t workload_mask; 803 uint32_t workload_prority[Workload_Policy_Max]; 804 uint32_t workload_setting[Workload_Policy_Max]; 805 bool gfxoff_state_changed_by_workload; 806 }; 807 808 int hwmgr_early_init(struct pp_hwmgr *hwmgr); 809 int hwmgr_sw_init(struct pp_hwmgr *hwmgr); 810 int hwmgr_sw_fini(struct pp_hwmgr *hwmgr); 811 int hwmgr_hw_init(struct pp_hwmgr *hwmgr); 812 int hwmgr_hw_fini(struct pp_hwmgr *hwmgr); 813 int hwmgr_suspend(struct pp_hwmgr *hwmgr); 814 int hwmgr_resume(struct pp_hwmgr *hwmgr); 815 816 int hwmgr_handle_task(struct pp_hwmgr *hwmgr, 817 enum amd_pp_task task_id, 818 enum amd_pm_state_type *user_state); 819 820 821 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU 822 823 824 #endif /* _HWMGR_H_ */ 825