1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2011 Chelsio Communications, Inc.
5 * All rights reserved.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 #include "opt_inet.h"
32 #include "opt_inet6.h"
33 #include "opt_kern_tls.h"
34 #include "opt_ratelimit.h"
35
36 #include <sys/types.h>
37 #include <sys/eventhandler.h>
38 #include <sys/mbuf.h>
39 #include <sys/socket.h>
40 #include <sys/kernel.h>
41 #include <sys/ktls.h>
42 #include <sys/malloc.h>
43 #include <sys/msan.h>
44 #include <sys/queue.h>
45 #include <sys/sbuf.h>
46 #include <sys/taskqueue.h>
47 #include <sys/time.h>
48 #include <sys/sglist.h>
49 #include <sys/sysctl.h>
50 #include <sys/smp.h>
51 #include <sys/socketvar.h>
52 #include <sys/counter.h>
53 #include <net/bpf.h>
54 #include <net/ethernet.h>
55 #include <net/if.h>
56 #include <net/if_vlan_var.h>
57 #include <net/if_vxlan.h>
58 #include <netinet/in.h>
59 #include <netinet/ip.h>
60 #include <netinet/ip6.h>
61 #include <netinet/tcp.h>
62 #include <netinet/udp.h>
63 #include <machine/in_cksum.h>
64 #include <machine/md_var.h>
65 #include <vm/vm.h>
66 #include <vm/pmap.h>
67 #ifdef DEV_NETMAP
68 #include <machine/bus.h>
69 #include <sys/selinfo.h>
70 #include <net/if_var.h>
71 #include <net/netmap.h>
72 #include <dev/netmap/netmap_kern.h>
73 #endif
74
75 #include "common/common.h"
76 #include "common/t4_regs.h"
77 #include "common/t4_regs_values.h"
78 #include "common/t4_msg.h"
79 #include "t4_l2t.h"
80 #include "t4_mp_ring.h"
81
82 #define RX_COPY_THRESHOLD MINCLSIZE
83
84 /*
85 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
86 * 0-7 are valid values.
87 */
88 static int fl_pktshift = 0;
89 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pktshift, CTLFLAG_RDTUN, &fl_pktshift, 0,
90 "payload DMA offset in rx buffer (bytes)");
91
92 /*
93 * Pad ethernet payload up to this boundary.
94 * -1: driver should figure out a good value.
95 * 0: disable padding.
96 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
97 */
98 int fl_pad = -1;
99 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pad, CTLFLAG_RDTUN, &fl_pad, 0,
100 "payload pad boundary (bytes)");
101
102 /*
103 * Status page length.
104 * -1: driver should figure out a good value.
105 * 64 or 128 are the only other valid values.
106 */
107 static int spg_len = -1;
108 SYSCTL_INT(_hw_cxgbe, OID_AUTO, spg_len, CTLFLAG_RDTUN, &spg_len, 0,
109 "status page size (bytes)");
110
111 /*
112 * Congestion drops.
113 * -1: no congestion feedback (not recommended).
114 * 0: backpressure the channel instead of dropping packets right away.
115 * 1: no backpressure, drop packets for the congested queue immediately.
116 * 2: both backpressure and drop.
117 */
118 static int cong_drop = 0;
119 SYSCTL_INT(_hw_cxgbe, OID_AUTO, cong_drop, CTLFLAG_RDTUN, &cong_drop, 0,
120 "Congestion control for NIC RX queues (0 = backpressure, 1 = drop, 2 = both");
121 #ifdef TCP_OFFLOAD
122 static int ofld_cong_drop = 0;
123 SYSCTL_INT(_hw_cxgbe, OID_AUTO, ofld_cong_drop, CTLFLAG_RDTUN, &ofld_cong_drop, 0,
124 "Congestion control for TOE RX queues (0 = backpressure, 1 = drop, 2 = both");
125 #endif
126
127 /*
128 * Deliver multiple frames in the same free list buffer if they fit.
129 * -1: let the driver decide whether to enable buffer packing or not.
130 * 0: disable buffer packing.
131 * 1: enable buffer packing.
132 */
133 static int buffer_packing = -1;
134 SYSCTL_INT(_hw_cxgbe, OID_AUTO, buffer_packing, CTLFLAG_RDTUN, &buffer_packing,
135 0, "Enable buffer packing");
136
137 /*
138 * Start next frame in a packed buffer at this boundary.
139 * -1: driver should figure out a good value.
140 * T4: driver will ignore this and use the same value as fl_pad above.
141 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
142 */
143 static int fl_pack = -1;
144 SYSCTL_INT(_hw_cxgbe, OID_AUTO, fl_pack, CTLFLAG_RDTUN, &fl_pack, 0,
145 "payload pack boundary (bytes)");
146
147 /*
148 * Largest rx cluster size that the driver is allowed to allocate.
149 */
150 static int largest_rx_cluster = MJUM16BYTES;
151 SYSCTL_INT(_hw_cxgbe, OID_AUTO, largest_rx_cluster, CTLFLAG_RDTUN,
152 &largest_rx_cluster, 0, "Largest rx cluster (bytes)");
153
154 /*
155 * Size of cluster allocation that's most likely to succeed. The driver will
156 * fall back to this size if it fails to allocate clusters larger than this.
157 */
158 static int safest_rx_cluster = PAGE_SIZE;
159 SYSCTL_INT(_hw_cxgbe, OID_AUTO, safest_rx_cluster, CTLFLAG_RDTUN,
160 &safest_rx_cluster, 0, "Safe rx cluster (bytes)");
161
162 #ifdef RATELIMIT
163 /*
164 * Knob to control TCP timestamp rewriting, and the granularity of the tick used
165 * for rewriting. -1 and 0-3 are all valid values.
166 * -1: hardware should leave the TCP timestamps alone.
167 * 0: 1ms
168 * 1: 100us
169 * 2: 10us
170 * 3: 1us
171 */
172 static int tsclk = -1;
173 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tsclk, CTLFLAG_RDTUN, &tsclk, 0,
174 "Control TCP timestamp rewriting when using pacing");
175
176 static int eo_max_backlog = 1024 * 1024;
177 SYSCTL_INT(_hw_cxgbe, OID_AUTO, eo_max_backlog, CTLFLAG_RDTUN, &eo_max_backlog,
178 0, "Maximum backlog of ratelimited data per flow");
179 #endif
180
181 /*
182 * The interrupt holdoff timers are multiplied by this value on T6+.
183 * 1 and 3-17 (both inclusive) are legal values.
184 */
185 static int tscale = 1;
186 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tscale, CTLFLAG_RDTUN, &tscale, 0,
187 "Interrupt holdoff timer scale on T6+");
188
189 /*
190 * Number of LRO entries in the lro_ctrl structure per rx queue.
191 */
192 static int lro_entries = TCP_LRO_ENTRIES;
193 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_entries, CTLFLAG_RDTUN, &lro_entries, 0,
194 "Number of LRO entries per RX queue");
195
196 /*
197 * This enables presorting of frames before they're fed into tcp_lro_rx.
198 */
199 static int lro_mbufs = 0;
200 SYSCTL_INT(_hw_cxgbe, OID_AUTO, lro_mbufs, CTLFLAG_RDTUN, &lro_mbufs, 0,
201 "Enable presorting of LRO frames");
202
203 static counter_u64_t pullups;
204 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, pullups, CTLFLAG_RD, &pullups,
205 "Number of mbuf pullups performed");
206
207 static counter_u64_t defrags;
208 SYSCTL_COUNTER_U64(_hw_cxgbe, OID_AUTO, defrags, CTLFLAG_RD, &defrags,
209 "Number of mbuf defrags performed");
210
211 static int t4_tx_coalesce = 1;
212 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce, CTLFLAG_RWTUN, &t4_tx_coalesce, 0,
213 "tx coalescing allowed");
214
215 /*
216 * The driver will make aggressive attempts at tx coalescing if it sees these
217 * many packets eligible for coalescing in quick succession, with no more than
218 * the specified gap in between the eth_tx calls that delivered the packets.
219 */
220 static int t4_tx_coalesce_pkts = 32;
221 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_pkts, CTLFLAG_RWTUN,
222 &t4_tx_coalesce_pkts, 0,
223 "# of consecutive packets (1 - 255) that will trigger tx coalescing");
224 static int t4_tx_coalesce_gap = 5;
225 SYSCTL_INT(_hw_cxgbe, OID_AUTO, tx_coalesce_gap, CTLFLAG_RWTUN,
226 &t4_tx_coalesce_gap, 0, "tx gap (in microseconds)");
227
228 static int service_iq(struct sge_iq *, int);
229 static int service_iq_fl(struct sge_iq *, int);
230 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
231 static int eth_rx(struct adapter *, struct sge_rxq *, const struct iq_desc *,
232 u_int);
233 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int,
234 int, int, int);
235 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
236 static inline void init_eq(struct adapter *, struct sge_eq *, int, int, uint8_t,
237 struct sge_iq *, char *);
238 static int alloc_iq_fl(struct vi_info *, struct sge_iq *, struct sge_fl *,
239 struct sysctl_ctx_list *, struct sysctl_oid *);
240 static void free_iq_fl(struct adapter *, struct sge_iq *, struct sge_fl *);
241 static void add_iq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
242 struct sge_iq *);
243 static void add_fl_sysctls(struct adapter *, struct sysctl_ctx_list *,
244 struct sysctl_oid *, struct sge_fl *);
245 static int alloc_iq_fl_hwq(struct vi_info *, struct sge_iq *, struct sge_fl *);
246 static int free_iq_fl_hwq(struct adapter *, struct sge_iq *, struct sge_fl *);
247 static int alloc_fwq(struct adapter *);
248 static void free_fwq(struct adapter *);
249 static int alloc_ctrlq(struct adapter *, int);
250 static void free_ctrlq(struct adapter *, int);
251 static int alloc_rxq(struct vi_info *, struct sge_rxq *, int, int, int);
252 static void free_rxq(struct vi_info *, struct sge_rxq *);
253 static void add_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
254 struct sge_rxq *);
255 #ifdef TCP_OFFLOAD
256 static int alloc_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *, int, int,
257 int);
258 static void free_ofld_rxq(struct vi_info *, struct sge_ofld_rxq *);
259 static void add_ofld_rxq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
260 struct sge_ofld_rxq *);
261 #endif
262 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
263 static int eth_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
264 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
265 static int ofld_eq_alloc(struct adapter *, struct vi_info *, struct sge_eq *);
266 #endif
267 static int alloc_eq(struct adapter *, struct sge_eq *, struct sysctl_ctx_list *,
268 struct sysctl_oid *);
269 static void free_eq(struct adapter *, struct sge_eq *);
270 static void add_eq_sysctls(struct adapter *, struct sysctl_ctx_list *,
271 struct sysctl_oid *, struct sge_eq *);
272 static int alloc_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *);
273 static int free_eq_hwq(struct adapter *, struct vi_info *, struct sge_eq *);
274 static int alloc_wrq(struct adapter *, struct vi_info *, struct sge_wrq *,
275 struct sysctl_ctx_list *, struct sysctl_oid *);
276 static void free_wrq(struct adapter *, struct sge_wrq *);
277 static void add_wrq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
278 struct sge_wrq *);
279 static int alloc_txq(struct vi_info *, struct sge_txq *, int);
280 static void free_txq(struct vi_info *, struct sge_txq *);
281 static void add_txq_sysctls(struct vi_info *, struct sysctl_ctx_list *,
282 struct sysctl_oid *, struct sge_txq *);
283 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
284 static int alloc_ofld_txq(struct vi_info *, struct sge_ofld_txq *, int);
285 static void free_ofld_txq(struct vi_info *, struct sge_ofld_txq *);
286 static void add_ofld_txq_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
287 struct sge_ofld_txq *);
288 #endif
289 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
290 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
291 static int refill_fl(struct adapter *, struct sge_fl *, int);
292 static void refill_sfl(void *);
293 static int find_refill_source(struct adapter *, int, bool);
294 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
295
296 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
297 static inline u_int txpkt_len16(u_int, const u_int);
298 static inline u_int txpkt_vm_len16(u_int, const u_int);
299 static inline void calculate_mbuf_len16(struct mbuf *, bool);
300 static inline u_int txpkts0_len16(u_int);
301 static inline u_int txpkts1_len16(void);
302 static u_int write_raw_wr(struct sge_txq *, void *, struct mbuf *, u_int);
303 static u_int write_txpkt_wr(struct adapter *, struct sge_txq *, struct mbuf *,
304 u_int);
305 static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *,
306 struct mbuf *);
307 static int add_to_txpkts_vf(struct adapter *, struct sge_txq *, struct mbuf *,
308 int, bool *);
309 static int add_to_txpkts_pf(struct adapter *, struct sge_txq *, struct mbuf *,
310 int, bool *);
311 static u_int write_txpkts_wr(struct adapter *, struct sge_txq *);
312 static u_int write_txpkts_vm_wr(struct adapter *, struct sge_txq *);
313 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
314 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
315 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
316 static inline uint16_t read_hw_cidx(struct sge_eq *);
317 static inline u_int reclaimable_tx_desc(struct sge_eq *);
318 static inline u_int total_available_tx_desc(struct sge_eq *);
319 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
320 static void tx_reclaim(void *, int);
321 static __be64 get_flit(struct sglist_seg *, int, int);
322 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
323 struct mbuf *);
324 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
325 struct mbuf *);
326 static int t4_handle_wrerr_rpl(struct adapter *, const __be64 *);
327 static void wrq_tx_drain(void *, int);
328 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
329
330 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
331 #ifdef RATELIMIT
332 static int ethofld_fw4_ack(struct sge_iq *, const struct rss_header *,
333 struct mbuf *);
334 #if defined(INET) || defined(INET6)
335 static inline u_int txpkt_eo_len16(u_int, u_int, u_int);
336 static int ethofld_transmit(if_t, struct mbuf *);
337 #endif
338 #endif
339
340 static counter_u64_t extfree_refs;
341 static counter_u64_t extfree_rels;
342
343 an_handler_t t4_an_handler;
344 fw_msg_handler_t t4_fw_msg_handler[NUM_FW6_TYPES];
345 cpl_handler_t t4_cpl_handler[NUM_CPL_CMDS];
346 cpl_handler_t set_tcb_rpl_handlers[NUM_CPL_COOKIES];
347 cpl_handler_t l2t_write_rpl_handlers[NUM_CPL_COOKIES];
348 cpl_handler_t act_open_rpl_handlers[NUM_CPL_COOKIES];
349 cpl_handler_t abort_rpl_rss_handlers[NUM_CPL_COOKIES];
350 cpl_handler_t fw4_ack_handlers[NUM_CPL_COOKIES];
351
352 void
t4_register_an_handler(an_handler_t h)353 t4_register_an_handler(an_handler_t h)
354 {
355 uintptr_t *loc;
356
357 MPASS(h == NULL || t4_an_handler == NULL);
358
359 loc = (uintptr_t *)&t4_an_handler;
360 atomic_store_rel_ptr(loc, (uintptr_t)h);
361 }
362
363 void
t4_register_fw_msg_handler(int type,fw_msg_handler_t h)364 t4_register_fw_msg_handler(int type, fw_msg_handler_t h)
365 {
366 uintptr_t *loc;
367
368 MPASS(type < nitems(t4_fw_msg_handler));
369 MPASS(h == NULL || t4_fw_msg_handler[type] == NULL);
370 /*
371 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL
372 * handler dispatch table. Reject any attempt to install a handler for
373 * this subtype.
374 */
375 MPASS(type != FW_TYPE_RSSCPL);
376 MPASS(type != FW6_TYPE_RSSCPL);
377
378 loc = (uintptr_t *)&t4_fw_msg_handler[type];
379 atomic_store_rel_ptr(loc, (uintptr_t)h);
380 }
381
382 void
t4_register_cpl_handler(int opcode,cpl_handler_t h)383 t4_register_cpl_handler(int opcode, cpl_handler_t h)
384 {
385 uintptr_t *loc;
386
387 MPASS(opcode < nitems(t4_cpl_handler));
388 MPASS(h == NULL || t4_cpl_handler[opcode] == NULL);
389
390 loc = (uintptr_t *)&t4_cpl_handler[opcode];
391 atomic_store_rel_ptr(loc, (uintptr_t)h);
392 }
393
394 static int
set_tcb_rpl_handler(struct sge_iq * iq,const struct rss_header * rss,struct mbuf * m)395 set_tcb_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
396 struct mbuf *m)
397 {
398 const struct cpl_set_tcb_rpl *cpl = (const void *)(rss + 1);
399 u_int tid;
400 int cookie;
401
402 MPASS(m == NULL);
403
404 tid = GET_TID(cpl);
405 if (is_hpftid(iq->adapter, tid) || is_ftid(iq->adapter, tid)) {
406 /*
407 * The return code for filter-write is put in the CPL cookie so
408 * we have to rely on the hardware tid (is_ftid) to determine
409 * that this is a response to a filter.
410 */
411 cookie = CPL_COOKIE_FILTER;
412 } else {
413 cookie = G_COOKIE(cpl->cookie);
414 }
415 MPASS(cookie > CPL_COOKIE_RESERVED);
416 MPASS(cookie < nitems(set_tcb_rpl_handlers));
417
418 return (set_tcb_rpl_handlers[cookie](iq, rss, m));
419 }
420
421 static int
l2t_write_rpl_handler(struct sge_iq * iq,const struct rss_header * rss,struct mbuf * m)422 l2t_write_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
423 struct mbuf *m)
424 {
425 const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1);
426 unsigned int cookie;
427
428 MPASS(m == NULL);
429
430 cookie = GET_TID(rpl) & F_SYNC_WR ? CPL_COOKIE_TOM : CPL_COOKIE_FILTER;
431 return (l2t_write_rpl_handlers[cookie](iq, rss, m));
432 }
433
434 static int
act_open_rpl_handler(struct sge_iq * iq,const struct rss_header * rss,struct mbuf * m)435 act_open_rpl_handler(struct sge_iq *iq, const struct rss_header *rss,
436 struct mbuf *m)
437 {
438 const struct cpl_act_open_rpl *cpl = (const void *)(rss + 1);
439 u_int cookie = G_TID_COOKIE(G_AOPEN_ATID(be32toh(cpl->atid_status)));
440
441 MPASS(m == NULL);
442 MPASS(cookie != CPL_COOKIE_RESERVED);
443
444 return (act_open_rpl_handlers[cookie](iq, rss, m));
445 }
446
447 static int
abort_rpl_rss_handler(struct sge_iq * iq,const struct rss_header * rss,struct mbuf * m)448 abort_rpl_rss_handler(struct sge_iq *iq, const struct rss_header *rss,
449 struct mbuf *m)
450 {
451 struct adapter *sc = iq->adapter;
452 u_int cookie;
453
454 MPASS(m == NULL);
455 if (is_hashfilter(sc))
456 cookie = CPL_COOKIE_HASHFILTER;
457 else
458 cookie = CPL_COOKIE_TOM;
459
460 return (abort_rpl_rss_handlers[cookie](iq, rss, m));
461 }
462
463 static int
fw4_ack_handler(struct sge_iq * iq,const struct rss_header * rss,struct mbuf * m)464 fw4_ack_handler(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
465 {
466 struct adapter *sc = iq->adapter;
467 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
468 unsigned int tid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
469 u_int cookie;
470
471 MPASS(m == NULL);
472 if (is_etid(sc, tid))
473 cookie = CPL_COOKIE_ETHOFLD;
474 else
475 cookie = CPL_COOKIE_TOM;
476
477 return (fw4_ack_handlers[cookie](iq, rss, m));
478 }
479
480 static void
t4_init_shared_cpl_handlers(void)481 t4_init_shared_cpl_handlers(void)
482 {
483
484 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl_handler);
485 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl_handler);
486 t4_register_cpl_handler(CPL_ACT_OPEN_RPL, act_open_rpl_handler);
487 t4_register_cpl_handler(CPL_ABORT_RPL_RSS, abort_rpl_rss_handler);
488 t4_register_cpl_handler(CPL_FW4_ACK, fw4_ack_handler);
489 }
490
491 void
t4_register_shared_cpl_handler(int opcode,cpl_handler_t h,int cookie)492 t4_register_shared_cpl_handler(int opcode, cpl_handler_t h, int cookie)
493 {
494 uintptr_t *loc;
495
496 MPASS(opcode < nitems(t4_cpl_handler));
497 MPASS(cookie > CPL_COOKIE_RESERVED);
498 MPASS(cookie < NUM_CPL_COOKIES);
499 MPASS(t4_cpl_handler[opcode] != NULL);
500
501 switch (opcode) {
502 case CPL_SET_TCB_RPL:
503 loc = (uintptr_t *)&set_tcb_rpl_handlers[cookie];
504 break;
505 case CPL_L2T_WRITE_RPL:
506 loc = (uintptr_t *)&l2t_write_rpl_handlers[cookie];
507 break;
508 case CPL_ACT_OPEN_RPL:
509 loc = (uintptr_t *)&act_open_rpl_handlers[cookie];
510 break;
511 case CPL_ABORT_RPL_RSS:
512 loc = (uintptr_t *)&abort_rpl_rss_handlers[cookie];
513 break;
514 case CPL_FW4_ACK:
515 loc = (uintptr_t *)&fw4_ack_handlers[cookie];
516 break;
517 default:
518 MPASS(0);
519 return;
520 }
521 MPASS(h == NULL || *loc == (uintptr_t)NULL);
522 atomic_store_rel_ptr(loc, (uintptr_t)h);
523 }
524
525 /*
526 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
527 */
528 void
t4_sge_modload(void)529 t4_sge_modload(void)
530 {
531
532 if (fl_pktshift < 0 || fl_pktshift > 7) {
533 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
534 " using 0 instead.\n", fl_pktshift);
535 fl_pktshift = 0;
536 }
537
538 if (spg_len != 64 && spg_len != 128) {
539 int len;
540
541 #if defined(__i386__) || defined(__amd64__)
542 len = cpu_clflush_line_size > 64 ? 128 : 64;
543 #else
544 len = 64;
545 #endif
546 if (spg_len != -1) {
547 printf("Invalid hw.cxgbe.spg_len value (%d),"
548 " using %d instead.\n", spg_len, len);
549 }
550 spg_len = len;
551 }
552
553 if (cong_drop < -1 || cong_drop > 2) {
554 printf("Invalid hw.cxgbe.cong_drop value (%d),"
555 " using 0 instead.\n", cong_drop);
556 cong_drop = 0;
557 }
558 #ifdef TCP_OFFLOAD
559 if (ofld_cong_drop < -1 || ofld_cong_drop > 2) {
560 printf("Invalid hw.cxgbe.ofld_cong_drop value (%d),"
561 " using 0 instead.\n", ofld_cong_drop);
562 ofld_cong_drop = 0;
563 }
564 #endif
565
566 if (tscale != 1 && (tscale < 3 || tscale > 17)) {
567 printf("Invalid hw.cxgbe.tscale value (%d),"
568 " using 1 instead.\n", tscale);
569 tscale = 1;
570 }
571
572 if (largest_rx_cluster != MCLBYTES &&
573 largest_rx_cluster != MJUMPAGESIZE &&
574 largest_rx_cluster != MJUM9BYTES &&
575 largest_rx_cluster != MJUM16BYTES) {
576 printf("Invalid hw.cxgbe.largest_rx_cluster value (%d),"
577 " using %d instead.\n", largest_rx_cluster, MJUM16BYTES);
578 largest_rx_cluster = MJUM16BYTES;
579 }
580
581 if (safest_rx_cluster != MCLBYTES &&
582 safest_rx_cluster != MJUMPAGESIZE &&
583 safest_rx_cluster != MJUM9BYTES &&
584 safest_rx_cluster != MJUM16BYTES) {
585 printf("Invalid hw.cxgbe.safest_rx_cluster value (%d),"
586 " using %d instead.\n", safest_rx_cluster, MJUMPAGESIZE);
587 safest_rx_cluster = MJUMPAGESIZE;
588 }
589
590 extfree_refs = counter_u64_alloc(M_WAITOK);
591 extfree_rels = counter_u64_alloc(M_WAITOK);
592 pullups = counter_u64_alloc(M_WAITOK);
593 defrags = counter_u64_alloc(M_WAITOK);
594 counter_u64_zero(extfree_refs);
595 counter_u64_zero(extfree_rels);
596 counter_u64_zero(pullups);
597 counter_u64_zero(defrags);
598
599 t4_init_shared_cpl_handlers();
600 t4_register_cpl_handler(CPL_FW4_MSG, handle_fw_msg);
601 t4_register_cpl_handler(CPL_FW6_MSG, handle_fw_msg);
602 t4_register_cpl_handler(CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
603 #ifdef RATELIMIT
604 t4_register_shared_cpl_handler(CPL_FW4_ACK, ethofld_fw4_ack,
605 CPL_COOKIE_ETHOFLD);
606 #endif
607 t4_register_fw_msg_handler(FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
608 t4_register_fw_msg_handler(FW6_TYPE_WRERR_RPL, t4_handle_wrerr_rpl);
609 }
610
611 void
t4_sge_modunload(void)612 t4_sge_modunload(void)
613 {
614
615 counter_u64_free(extfree_refs);
616 counter_u64_free(extfree_rels);
617 counter_u64_free(pullups);
618 counter_u64_free(defrags);
619 }
620
621 uint64_t
t4_sge_extfree_refs(void)622 t4_sge_extfree_refs(void)
623 {
624 uint64_t refs, rels;
625
626 rels = counter_u64_fetch(extfree_rels);
627 refs = counter_u64_fetch(extfree_refs);
628
629 return (refs - rels);
630 }
631
632 /* max 4096 */
633 #define MAX_PACK_BOUNDARY 512
634
635 static inline void
setup_pad_and_pack_boundaries(struct adapter * sc)636 setup_pad_and_pack_boundaries(struct adapter *sc)
637 {
638 uint32_t v, m;
639 int pad, pack, pad_shift;
640
641 pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT :
642 X_INGPADBOUNDARY_SHIFT;
643 pad = fl_pad;
644 if (fl_pad < (1 << pad_shift) ||
645 fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) ||
646 !powerof2(fl_pad)) {
647 /*
648 * If there is any chance that we might use buffer packing and
649 * the chip is a T4, then pick 64 as the pad/pack boundary. Set
650 * it to the minimum allowed in all other cases.
651 */
652 pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift;
653
654 /*
655 * For fl_pad = 0 we'll still write a reasonable value to the
656 * register but all the freelists will opt out of padding.
657 * We'll complain here only if the user tried to set it to a
658 * value greater than 0 that was invalid.
659 */
660 if (fl_pad > 0) {
661 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
662 " (%d), using %d instead.\n", fl_pad, pad);
663 }
664 }
665 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
666 v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift);
667 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
668
669 if (is_t4(sc)) {
670 if (fl_pack != -1 && fl_pack != pad) {
671 /* Complain but carry on. */
672 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
673 " using %d instead.\n", fl_pack, pad);
674 }
675 return;
676 }
677
678 pack = fl_pack;
679 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
680 !powerof2(fl_pack)) {
681 if (sc->params.pci.mps > MAX_PACK_BOUNDARY)
682 pack = MAX_PACK_BOUNDARY;
683 else
684 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
685 MPASS(powerof2(pack));
686 if (pack < 16)
687 pack = 16;
688 if (pack == 32)
689 pack = 64;
690 if (pack > 4096)
691 pack = 4096;
692 if (fl_pack != -1) {
693 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
694 " (%d), using %d instead.\n", fl_pack, pack);
695 }
696 }
697 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
698 if (pack == 16)
699 v = V_INGPACKBOUNDARY(0);
700 else
701 v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
702
703 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
704 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
705 }
706
707 /*
708 * adap->params.vpd.cclk must be set up before this is called.
709 */
710 void
t4_tweak_chip_settings(struct adapter * sc)711 t4_tweak_chip_settings(struct adapter *sc)
712 {
713 int i, reg;
714 uint32_t v, m;
715 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
716 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
717 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
718 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
719 static int sw_buf_sizes[] = {
720 MCLBYTES,
721 MJUMPAGESIZE,
722 MJUM9BYTES,
723 MJUM16BYTES
724 };
725
726 KASSERT(sc->flags & MASTER_PF,
727 ("%s: trying to change chip settings when not master.", __func__));
728
729 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
730 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
731 V_EGRSTATUSPAGESIZE(spg_len == 128);
732 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
733
734 setup_pad_and_pack_boundaries(sc);
735
736 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
737 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
738 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
739 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
740 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
741 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
742 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
743 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
744 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
745
746 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0, 4096);
747 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE1, 65536);
748 reg = A_SGE_FL_BUFFER_SIZE2;
749 for (i = 0; i < nitems(sw_buf_sizes); i++) {
750 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15);
751 t4_write_reg(sc, reg, sw_buf_sizes[i]);
752 reg += 4;
753 MPASS(reg <= A_SGE_FL_BUFFER_SIZE15);
754 t4_write_reg(sc, reg, sw_buf_sizes[i] - CL_METADATA_SIZE);
755 reg += 4;
756 }
757
758 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
759 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
760 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
761
762 KASSERT(intr_timer[0] <= timer_max,
763 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
764 timer_max));
765 for (i = 1; i < nitems(intr_timer); i++) {
766 KASSERT(intr_timer[i] >= intr_timer[i - 1],
767 ("%s: timers not listed in increasing order (%d)",
768 __func__, i));
769
770 while (intr_timer[i] > timer_max) {
771 if (i == nitems(intr_timer) - 1) {
772 intr_timer[i] = timer_max;
773 break;
774 }
775 intr_timer[i] += intr_timer[i - 1];
776 intr_timer[i] /= 2;
777 }
778 }
779
780 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
781 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
782 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
783 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
784 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
785 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
786 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
787 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
788 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
789
790 if (chip_id(sc) >= CHELSIO_T6) {
791 m = V_TSCALE(M_TSCALE);
792 if (tscale == 1)
793 v = 0;
794 else
795 v = V_TSCALE(tscale - 2);
796 t4_set_reg_field(sc, A_SGE_ITP_CONTROL, m, v);
797
798 if (sc->debug_flags & DF_DISABLE_TCB_CACHE) {
799 m = V_RDTHRESHOLD(M_RDTHRESHOLD) | F_WRTHRTHRESHEN |
800 V_WRTHRTHRESH(M_WRTHRTHRESH);
801 t4_tp_pio_read(sc, &v, 1, A_TP_CMM_CONFIG, 1);
802 v &= ~m;
803 v |= V_RDTHRESHOLD(1) | F_WRTHRTHRESHEN |
804 V_WRTHRTHRESH(16);
805 t4_tp_pio_write(sc, &v, 1, A_TP_CMM_CONFIG, 1);
806 }
807 }
808
809 /* 4K, 16K, 64K, 256K DDP "page sizes" for TDDP */
810 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
811 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
812
813 /*
814 * 4K, 8K, 16K, 64K DDP "page sizes" for iSCSI DDP. These have been
815 * chosen with MAXPHYS = 128K in mind. The largest DDP buffer that we
816 * may have to deal with is MAXPHYS + 1 page.
817 */
818 v = V_HPZ0(0) | V_HPZ1(1) | V_HPZ2(2) | V_HPZ3(4);
819 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, v);
820
821 /* We use multiple DDP page sizes both in plain-TOE and ISCSI modes. */
822 m = v = F_TDDPTAGTCB | F_ISCSITAGTCB;
823 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
824
825 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
826 F_RESETDDPOFFSET;
827 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
828 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
829 }
830
831 /*
832 * SGE wants the buffer to be at least 64B and then a multiple of 16. Its
833 * address mut be 16B aligned. If padding is in use the buffer's start and end
834 * need to be aligned to the pad boundary as well. We'll just make sure that
835 * the size is a multiple of the pad boundary here, it is up to the buffer
836 * allocation code to make sure the start of the buffer is aligned.
837 */
838 static inline int
hwsz_ok(struct adapter * sc,int hwsz)839 hwsz_ok(struct adapter *sc, int hwsz)
840 {
841 int mask = fl_pad ? sc->params.sge.pad_boundary - 1 : 16 - 1;
842
843 return (hwsz >= 64 && (hwsz & mask) == 0);
844 }
845
846 /*
847 * Initialize the rx buffer sizes and figure out which zones the buffers will
848 * be allocated from.
849 */
850 void
t4_init_rx_buf_info(struct adapter * sc)851 t4_init_rx_buf_info(struct adapter *sc)
852 {
853 struct sge *s = &sc->sge;
854 struct sge_params *sp = &sc->params.sge;
855 int i, j, n;
856 static int sw_buf_sizes[] = { /* Sorted by size */
857 MCLBYTES,
858 MJUMPAGESIZE,
859 MJUM9BYTES,
860 MJUM16BYTES
861 };
862 struct rx_buf_info *rxb;
863
864 s->safe_zidx = -1;
865 rxb = &s->rx_buf_info[0];
866 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
867 rxb->size1 = sw_buf_sizes[i];
868 rxb->zone = m_getzone(rxb->size1);
869 rxb->type = m_gettype(rxb->size1);
870 rxb->size2 = 0;
871 rxb->hwidx1 = -1;
872 rxb->hwidx2 = -1;
873 for (j = 0; j < SGE_FLBUF_SIZES; j++) {
874 int hwsize = sp->sge_fl_buffer_size[j];
875
876 if (!hwsz_ok(sc, hwsize))
877 continue;
878
879 /* hwidx for size1 */
880 if (rxb->hwidx1 == -1 && rxb->size1 == hwsize)
881 rxb->hwidx1 = j;
882
883 /* hwidx for size2 (buffer packing) */
884 if (rxb->size1 - CL_METADATA_SIZE < hwsize)
885 continue;
886 n = rxb->size1 - hwsize - CL_METADATA_SIZE;
887 if (n == 0) {
888 rxb->hwidx2 = j;
889 rxb->size2 = hwsize;
890 break; /* stop looking */
891 }
892 if (rxb->hwidx2 != -1) {
893 if (n < sp->sge_fl_buffer_size[rxb->hwidx2] -
894 hwsize - CL_METADATA_SIZE) {
895 rxb->hwidx2 = j;
896 rxb->size2 = hwsize;
897 }
898 } else if (n <= 2 * CL_METADATA_SIZE) {
899 rxb->hwidx2 = j;
900 rxb->size2 = hwsize;
901 }
902 }
903 if (rxb->hwidx2 != -1)
904 sc->flags |= BUF_PACKING_OK;
905 if (s->safe_zidx == -1 && rxb->size1 == safest_rx_cluster)
906 s->safe_zidx = i;
907 }
908 }
909
910 /*
911 * Verify some basic SGE settings for the PF and VF driver, and other
912 * miscellaneous settings for the PF driver.
913 */
914 int
t4_verify_chip_settings(struct adapter * sc)915 t4_verify_chip_settings(struct adapter *sc)
916 {
917 struct sge_params *sp = &sc->params.sge;
918 uint32_t m, v, r;
919 int rc = 0;
920 const uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
921
922 m = F_RXPKTCPLMODE;
923 v = F_RXPKTCPLMODE;
924 r = sp->sge_control;
925 if ((r & m) != v) {
926 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
927 rc = EINVAL;
928 }
929
930 /*
931 * If this changes then every single use of PAGE_SHIFT in the driver
932 * needs to be carefully reviewed for PAGE_SHIFT vs sp->page_shift.
933 */
934 if (sp->page_shift != PAGE_SHIFT) {
935 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
936 rc = EINVAL;
937 }
938
939 if (sc->flags & IS_VF)
940 return (0);
941
942 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
943 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
944 if (r != v) {
945 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
946 if (sc->vres.ddp.size != 0)
947 rc = EINVAL;
948 }
949
950 m = v = F_TDDPTAGTCB;
951 r = t4_read_reg(sc, A_ULP_RX_CTL);
952 if ((r & m) != v) {
953 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
954 if (sc->vres.ddp.size != 0)
955 rc = EINVAL;
956 }
957
958 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
959 F_RESETDDPOFFSET;
960 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
961 r = t4_read_reg(sc, A_TP_PARA_REG5);
962 if ((r & m) != v) {
963 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
964 if (sc->vres.ddp.size != 0)
965 rc = EINVAL;
966 }
967
968 return (rc);
969 }
970
971 int
t4_create_dma_tag(struct adapter * sc)972 t4_create_dma_tag(struct adapter *sc)
973 {
974 int rc;
975
976 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
977 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
978 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
979 NULL, &sc->dmat);
980 if (rc != 0) {
981 device_printf(sc->dev,
982 "failed to create main DMA tag: %d\n", rc);
983 }
984
985 return (rc);
986 }
987
988 void
t4_sge_sysctls(struct adapter * sc,struct sysctl_ctx_list * ctx,struct sysctl_oid_list * children)989 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
990 struct sysctl_oid_list *children)
991 {
992 struct sge_params *sp = &sc->params.sge;
993
994 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
995 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
996 sysctl_bufsizes, "A", "freelist buffer sizes");
997
998 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
999 NULL, sp->fl_pktshift, "payload DMA offset in rx buffer (bytes)");
1000
1001 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
1002 NULL, sp->pad_boundary, "payload pad boundary (bytes)");
1003
1004 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
1005 NULL, sp->spg_len, "status page size (bytes)");
1006
1007 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
1008 NULL, cong_drop, "congestion drop setting");
1009 #ifdef TCP_OFFLOAD
1010 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ofld_cong_drop", CTLFLAG_RD,
1011 NULL, ofld_cong_drop, "congestion drop setting");
1012 #endif
1013
1014 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
1015 NULL, sp->pack_boundary, "payload pack boundary (bytes)");
1016 }
1017
1018 int
t4_destroy_dma_tag(struct adapter * sc)1019 t4_destroy_dma_tag(struct adapter *sc)
1020 {
1021 if (sc->dmat)
1022 bus_dma_tag_destroy(sc->dmat);
1023
1024 return (0);
1025 }
1026
1027 /*
1028 * Allocate and initialize the firmware event queue, control queues, and special
1029 * purpose rx queues owned by the adapter.
1030 *
1031 * Returns errno on failure. Resources allocated up to that point may still be
1032 * allocated. Caller is responsible for cleanup in case this function fails.
1033 */
1034 int
t4_setup_adapter_queues(struct adapter * sc)1035 t4_setup_adapter_queues(struct adapter *sc)
1036 {
1037 int rc, i;
1038
1039 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1040
1041 /*
1042 * Firmware event queue
1043 */
1044 rc = alloc_fwq(sc);
1045 if (rc != 0)
1046 return (rc);
1047
1048 /*
1049 * That's all for the VF driver.
1050 */
1051 if (sc->flags & IS_VF)
1052 return (rc);
1053
1054 /*
1055 * XXX: General purpose rx queues, one per port.
1056 */
1057
1058 /*
1059 * Control queues, one per port.
1060 */
1061 for_each_port(sc, i) {
1062 rc = alloc_ctrlq(sc, i);
1063 if (rc != 0)
1064 return (rc);
1065 }
1066
1067 return (rc);
1068 }
1069
1070 /*
1071 * Idempotent
1072 */
1073 int
t4_teardown_adapter_queues(struct adapter * sc)1074 t4_teardown_adapter_queues(struct adapter *sc)
1075 {
1076 int i;
1077
1078 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1079
1080 if (sc->sge.ctrlq != NULL) {
1081 MPASS(!(sc->flags & IS_VF)); /* VFs don't allocate ctrlq. */
1082 for_each_port(sc, i)
1083 free_ctrlq(sc, i);
1084 }
1085 free_fwq(sc);
1086
1087 return (0);
1088 }
1089
1090 /* Maximum payload that could arrive with a single iq descriptor. */
1091 static inline int
max_rx_payload(struct adapter * sc,if_t ifp,const bool ofld)1092 max_rx_payload(struct adapter *sc, if_t ifp, const bool ofld)
1093 {
1094 int maxp;
1095
1096 /* large enough even when hw VLAN extraction is disabled */
1097 maxp = sc->params.sge.fl_pktshift + ETHER_HDR_LEN +
1098 ETHER_VLAN_ENCAP_LEN + if_getmtu(ifp);
1099 if (ofld && sc->tt.tls && sc->cryptocaps & FW_CAPS_CONFIG_TLSKEYS &&
1100 maxp < sc->params.tp.max_rx_pdu)
1101 maxp = sc->params.tp.max_rx_pdu;
1102 return (maxp);
1103 }
1104
1105 int
t4_setup_vi_queues(struct vi_info * vi)1106 t4_setup_vi_queues(struct vi_info *vi)
1107 {
1108 int rc = 0, i, intr_idx;
1109 struct sge_rxq *rxq;
1110 struct sge_txq *txq;
1111 #ifdef TCP_OFFLOAD
1112 struct sge_ofld_rxq *ofld_rxq;
1113 #endif
1114 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1115 struct sge_ofld_txq *ofld_txq;
1116 #endif
1117 #ifdef DEV_NETMAP
1118 int saved_idx, iqidx;
1119 struct sge_nm_rxq *nm_rxq;
1120 struct sge_nm_txq *nm_txq;
1121 #endif
1122 struct adapter *sc = vi->adapter;
1123 if_t ifp = vi->ifp;
1124 int maxp;
1125
1126 /* Interrupt vector to start from (when using multiple vectors) */
1127 intr_idx = vi->first_intr;
1128
1129 #ifdef DEV_NETMAP
1130 saved_idx = intr_idx;
1131 if (if_getcapabilities(ifp) & IFCAP_NETMAP) {
1132
1133 /* netmap is supported with direct interrupts only. */
1134 MPASS(!forwarding_intr_to_fwq(sc));
1135 MPASS(vi->first_intr >= 0);
1136
1137 /*
1138 * We don't have buffers to back the netmap rx queues
1139 * right now so we create the queues in a way that
1140 * doesn't set off any congestion signal in the chip.
1141 */
1142 for_each_nm_rxq(vi, i, nm_rxq) {
1143 rc = alloc_nm_rxq(vi, nm_rxq, intr_idx, i);
1144 if (rc != 0)
1145 goto done;
1146 intr_idx++;
1147 }
1148
1149 for_each_nm_txq(vi, i, nm_txq) {
1150 iqidx = vi->first_nm_rxq + (i % vi->nnmrxq);
1151 rc = alloc_nm_txq(vi, nm_txq, iqidx, i);
1152 if (rc != 0)
1153 goto done;
1154 }
1155 }
1156
1157 /* Normal rx queues and netmap rx queues share the same interrupts. */
1158 intr_idx = saved_idx;
1159 #endif
1160
1161 /*
1162 * Allocate rx queues first because a default iqid is required when
1163 * creating a tx queue.
1164 */
1165 maxp = max_rx_payload(sc, ifp, false);
1166 for_each_rxq(vi, i, rxq) {
1167 rc = alloc_rxq(vi, rxq, i, intr_idx, maxp);
1168 if (rc != 0)
1169 goto done;
1170 if (!forwarding_intr_to_fwq(sc))
1171 intr_idx++;
1172 }
1173 #ifdef DEV_NETMAP
1174 if (if_getcapabilities(ifp) & IFCAP_NETMAP)
1175 intr_idx = saved_idx + max(vi->nrxq, vi->nnmrxq);
1176 #endif
1177 #ifdef TCP_OFFLOAD
1178 maxp = max_rx_payload(sc, ifp, true);
1179 for_each_ofld_rxq(vi, i, ofld_rxq) {
1180 rc = alloc_ofld_rxq(vi, ofld_rxq, i, intr_idx, maxp);
1181 if (rc != 0)
1182 goto done;
1183 if (!forwarding_intr_to_fwq(sc))
1184 intr_idx++;
1185 }
1186 #endif
1187
1188 /*
1189 * Now the tx queues.
1190 */
1191 for_each_txq(vi, i, txq) {
1192 rc = alloc_txq(vi, txq, i);
1193 if (rc != 0)
1194 goto done;
1195 }
1196 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1197 for_each_ofld_txq(vi, i, ofld_txq) {
1198 rc = alloc_ofld_txq(vi, ofld_txq, i);
1199 if (rc != 0)
1200 goto done;
1201 }
1202 #endif
1203 done:
1204 if (rc)
1205 t4_teardown_vi_queues(vi);
1206
1207 return (rc);
1208 }
1209
1210 /*
1211 * Idempotent
1212 */
1213 int
t4_teardown_vi_queues(struct vi_info * vi)1214 t4_teardown_vi_queues(struct vi_info *vi)
1215 {
1216 int i;
1217 struct sge_rxq *rxq;
1218 struct sge_txq *txq;
1219 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1220 struct sge_ofld_txq *ofld_txq;
1221 #endif
1222 #ifdef TCP_OFFLOAD
1223 struct sge_ofld_rxq *ofld_rxq;
1224 #endif
1225 #ifdef DEV_NETMAP
1226 struct sge_nm_rxq *nm_rxq;
1227 struct sge_nm_txq *nm_txq;
1228 #endif
1229
1230 #ifdef DEV_NETMAP
1231 if (if_getcapabilities(vi->ifp) & IFCAP_NETMAP) {
1232 for_each_nm_txq(vi, i, nm_txq) {
1233 free_nm_txq(vi, nm_txq);
1234 }
1235
1236 for_each_nm_rxq(vi, i, nm_rxq) {
1237 free_nm_rxq(vi, nm_rxq);
1238 }
1239 }
1240 #endif
1241
1242 /*
1243 * Take down all the tx queues first, as they reference the rx queues
1244 * (for egress updates, etc.).
1245 */
1246
1247 for_each_txq(vi, i, txq) {
1248 free_txq(vi, txq);
1249 }
1250 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
1251 for_each_ofld_txq(vi, i, ofld_txq) {
1252 free_ofld_txq(vi, ofld_txq);
1253 }
1254 #endif
1255
1256 /*
1257 * Then take down the rx queues.
1258 */
1259
1260 for_each_rxq(vi, i, rxq) {
1261 free_rxq(vi, rxq);
1262 }
1263 #ifdef TCP_OFFLOAD
1264 for_each_ofld_rxq(vi, i, ofld_rxq) {
1265 free_ofld_rxq(vi, ofld_rxq);
1266 }
1267 #endif
1268
1269 return (0);
1270 }
1271
1272 /*
1273 * Interrupt handler when the driver is using only 1 interrupt. This is a very
1274 * unusual scenario.
1275 *
1276 * a) Deals with errors, if any.
1277 * b) Services firmware event queue, which is taking interrupts for all other
1278 * queues.
1279 */
1280 void
t4_intr_all(void * arg)1281 t4_intr_all(void *arg)
1282 {
1283 struct adapter *sc = arg;
1284 struct sge_iq *fwq = &sc->sge.fwq;
1285
1286 MPASS(sc->intr_count == 1);
1287
1288 if (sc->intr_type == INTR_INTX)
1289 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1290
1291 t4_intr_err(arg);
1292 t4_intr_evt(fwq);
1293 }
1294
1295 /*
1296 * Interrupt handler for errors (installed directly when multiple interrupts are
1297 * being used, or called by t4_intr_all).
1298 */
1299 void
t4_intr_err(void * arg)1300 t4_intr_err(void *arg)
1301 {
1302 struct adapter *sc = arg;
1303 uint32_t v;
1304 const bool verbose = (sc->debug_flags & DF_VERBOSE_SLOWINTR) != 0;
1305
1306 if (atomic_load_int(&sc->error_flags) & ADAP_FATAL_ERR)
1307 return;
1308
1309 v = t4_read_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE));
1310 if (v & F_PFSW) {
1311 sc->swintr++;
1312 t4_write_reg(sc, MYPF_REG(A_PL_PF_INT_CAUSE), v);
1313 }
1314
1315 if (t4_slow_intr_handler(sc, verbose))
1316 t4_fatal_err(sc, false);
1317 }
1318
1319 /*
1320 * Interrupt handler for iq-only queues. The firmware event queue is the only
1321 * such queue right now.
1322 */
1323 void
t4_intr_evt(void * arg)1324 t4_intr_evt(void *arg)
1325 {
1326 struct sge_iq *iq = arg;
1327
1328 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1329 service_iq(iq, 0);
1330 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1331 }
1332 }
1333
1334 /*
1335 * Interrupt handler for iq+fl queues.
1336 */
1337 void
t4_intr(void * arg)1338 t4_intr(void *arg)
1339 {
1340 struct sge_iq *iq = arg;
1341
1342 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1343 service_iq_fl(iq, 0);
1344 (void) atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1345 }
1346 }
1347
1348 #ifdef DEV_NETMAP
1349 /*
1350 * Interrupt handler for netmap rx queues.
1351 */
1352 void
t4_nm_intr(void * arg)1353 t4_nm_intr(void *arg)
1354 {
1355 struct sge_nm_rxq *nm_rxq = arg;
1356
1357 if (atomic_cmpset_int(&nm_rxq->nm_state, NM_ON, NM_BUSY)) {
1358 service_nm_rxq(nm_rxq);
1359 (void) atomic_cmpset_int(&nm_rxq->nm_state, NM_BUSY, NM_ON);
1360 }
1361 }
1362
1363 /*
1364 * Interrupt handler for vectors shared between NIC and netmap rx queues.
1365 */
1366 void
t4_vi_intr(void * arg)1367 t4_vi_intr(void *arg)
1368 {
1369 struct irq *irq = arg;
1370
1371 MPASS(irq->nm_rxq != NULL);
1372 t4_nm_intr(irq->nm_rxq);
1373
1374 MPASS(irq->rxq != NULL);
1375 t4_intr(irq->rxq);
1376 }
1377 #endif
1378
1379 /*
1380 * Deals with interrupts on an iq-only (no freelist) queue.
1381 */
1382 static int
service_iq(struct sge_iq * iq,int budget)1383 service_iq(struct sge_iq *iq, int budget)
1384 {
1385 struct sge_iq *q;
1386 struct adapter *sc = iq->adapter;
1387 struct iq_desc *d = &iq->desc[iq->cidx];
1388 int ndescs = 0, limit;
1389 int rsp_type;
1390 uint32_t lq;
1391 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1392
1393 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1394 KASSERT((iq->flags & IQ_HAS_FL) == 0,
1395 ("%s: called for iq %p with fl (iq->flags 0x%x)", __func__, iq,
1396 iq->flags));
1397 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1398 MPASS((iq->flags & IQ_LRO_ENABLED) == 0);
1399
1400 limit = budget ? budget : iq->qsize / 16;
1401
1402 /*
1403 * We always come back and check the descriptor ring for new indirect
1404 * interrupts and other responses after running a single handler.
1405 */
1406 for (;;) {
1407 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1408
1409 rmb();
1410
1411 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1412 lq = be32toh(d->rsp.pldbuflen_qid);
1413
1414 switch (rsp_type) {
1415 case X_RSPD_TYPE_FLBUF:
1416 panic("%s: data for an iq (%p) with no freelist",
1417 __func__, iq);
1418
1419 /* NOTREACHED */
1420
1421 case X_RSPD_TYPE_CPL:
1422 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1423 ("%s: bad opcode %02x.", __func__,
1424 d->rss.opcode));
1425 t4_cpl_handler[d->rss.opcode](iq, &d->rss, NULL);
1426 break;
1427
1428 case X_RSPD_TYPE_INTR:
1429 /*
1430 * There are 1K interrupt-capable queues (qids 0
1431 * through 1023). A response type indicating a
1432 * forwarded interrupt with a qid >= 1K is an
1433 * iWARP async notification.
1434 */
1435 if (__predict_true(lq >= 1024)) {
1436 t4_an_handler(iq, &d->rsp);
1437 break;
1438 }
1439
1440 q = sc->sge.iqmap[lq - sc->sge.iq_start -
1441 sc->sge.iq_base];
1442 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1443 IQS_BUSY)) {
1444 if (service_iq_fl(q, q->qsize / 16) == 0) {
1445 (void) atomic_cmpset_int(&q->state,
1446 IQS_BUSY, IQS_IDLE);
1447 } else {
1448 STAILQ_INSERT_TAIL(&iql, q,
1449 link);
1450 }
1451 }
1452 break;
1453
1454 default:
1455 KASSERT(0,
1456 ("%s: illegal response type %d on iq %p",
1457 __func__, rsp_type, iq));
1458 log(LOG_ERR,
1459 "%s: illegal response type %d on iq %p",
1460 device_get_nameunit(sc->dev), rsp_type, iq);
1461 break;
1462 }
1463
1464 d++;
1465 if (__predict_false(++iq->cidx == iq->sidx)) {
1466 iq->cidx = 0;
1467 iq->gen ^= F_RSPD_GEN;
1468 d = &iq->desc[0];
1469 }
1470 if (__predict_false(++ndescs == limit)) {
1471 t4_write_reg(sc, sc->sge_gts_reg,
1472 V_CIDXINC(ndescs) |
1473 V_INGRESSQID(iq->cntxt_id) |
1474 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1475 ndescs = 0;
1476
1477 if (budget) {
1478 return (EINPROGRESS);
1479 }
1480 }
1481 }
1482
1483 if (STAILQ_EMPTY(&iql))
1484 break;
1485
1486 /*
1487 * Process the head only, and send it to the back of the list if
1488 * it's still not done.
1489 */
1490 q = STAILQ_FIRST(&iql);
1491 STAILQ_REMOVE_HEAD(&iql, link);
1492 if (service_iq_fl(q, q->qsize / 8) == 0)
1493 (void) atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1494 else
1495 STAILQ_INSERT_TAIL(&iql, q, link);
1496 }
1497
1498 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1499 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1500
1501 return (0);
1502 }
1503
1504 #if defined(INET) || defined(INET6)
1505 static inline int
sort_before_lro(struct lro_ctrl * lro)1506 sort_before_lro(struct lro_ctrl *lro)
1507 {
1508
1509 return (lro->lro_mbuf_max != 0);
1510 }
1511 #endif
1512
1513 #define CGBE_SHIFT_SCALE 10
1514
1515 static inline uint64_t
t4_tstmp_to_ns(struct adapter * sc,uint64_t lf)1516 t4_tstmp_to_ns(struct adapter *sc, uint64_t lf)
1517 {
1518 struct clock_sync *cur, dcur;
1519 uint64_t hw_clocks;
1520 uint64_t hw_clk_div;
1521 sbintime_t sbt_cur_to_prev, sbt;
1522 uint64_t hw_tstmp = lf & 0xfffffffffffffffULL; /* 60b, not 64b. */
1523 seqc_t gen;
1524
1525 for (;;) {
1526 cur = &sc->cal_info[sc->cal_current];
1527 gen = seqc_read(&cur->gen);
1528 if (gen == 0)
1529 return (0);
1530 dcur = *cur;
1531 if (seqc_consistent(&cur->gen, gen))
1532 break;
1533 }
1534
1535 /*
1536 * Our goal here is to have a result that is:
1537 *
1538 * ( (cur_time - prev_time) )
1539 * ((hw_tstmp - hw_prev) * ----------------------------- ) + prev_time
1540 * ( (hw_cur - hw_prev) )
1541 *
1542 * With the constraints that we cannot use float and we
1543 * don't want to overflow the uint64_t numbers we are using.
1544 */
1545 hw_clocks = hw_tstmp - dcur.hw_prev;
1546 sbt_cur_to_prev = (dcur.sbt_cur - dcur.sbt_prev);
1547 hw_clk_div = dcur.hw_cur - dcur.hw_prev;
1548 sbt = hw_clocks * sbt_cur_to_prev / hw_clk_div + dcur.sbt_prev;
1549 return (sbttons(sbt));
1550 }
1551
1552 static inline void
move_to_next_rxbuf(struct sge_fl * fl)1553 move_to_next_rxbuf(struct sge_fl *fl)
1554 {
1555
1556 fl->rx_offset = 0;
1557 if (__predict_false((++fl->cidx & 7) == 0)) {
1558 uint16_t cidx = fl->cidx >> 3;
1559
1560 if (__predict_false(cidx == fl->sidx))
1561 fl->cidx = cidx = 0;
1562 fl->hw_cidx = cidx;
1563 }
1564 }
1565
1566 /*
1567 * Deals with interrupts on an iq+fl queue.
1568 */
1569 static int
service_iq_fl(struct sge_iq * iq,int budget)1570 service_iq_fl(struct sge_iq *iq, int budget)
1571 {
1572 struct sge_rxq *rxq = iq_to_rxq(iq);
1573 struct sge_fl *fl;
1574 struct adapter *sc = iq->adapter;
1575 struct iq_desc *d = &iq->desc[iq->cidx];
1576 int ndescs, limit;
1577 int rsp_type, starved;
1578 uint32_t lq;
1579 uint16_t fl_hw_cidx;
1580 struct mbuf *m0;
1581 #if defined(INET) || defined(INET6)
1582 const struct timeval lro_timeout = {0, sc->lro_timeout};
1583 struct lro_ctrl *lro = &rxq->lro;
1584 #endif
1585
1586 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1587 MPASS(iq->flags & IQ_HAS_FL);
1588
1589 ndescs = 0;
1590 #if defined(INET) || defined(INET6)
1591 if (iq->flags & IQ_ADJ_CREDIT) {
1592 MPASS(sort_before_lro(lro));
1593 iq->flags &= ~IQ_ADJ_CREDIT;
1594 if ((d->rsp.u.type_gen & F_RSPD_GEN) != iq->gen) {
1595 tcp_lro_flush_all(lro);
1596 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(1) |
1597 V_INGRESSQID((u32)iq->cntxt_id) |
1598 V_SEINTARM(iq->intr_params));
1599 return (0);
1600 }
1601 ndescs = 1;
1602 }
1603 #else
1604 MPASS((iq->flags & IQ_ADJ_CREDIT) == 0);
1605 #endif
1606
1607 limit = budget ? budget : iq->qsize / 16;
1608 fl = &rxq->fl;
1609 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1610 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1611
1612 rmb();
1613
1614 m0 = NULL;
1615 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1616 lq = be32toh(d->rsp.pldbuflen_qid);
1617
1618 switch (rsp_type) {
1619 case X_RSPD_TYPE_FLBUF:
1620 if (lq & F_RSPD_NEWBUF) {
1621 if (fl->rx_offset > 0)
1622 move_to_next_rxbuf(fl);
1623 lq = G_RSPD_LEN(lq);
1624 }
1625 if (IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 4) {
1626 FL_LOCK(fl);
1627 refill_fl(sc, fl, 64);
1628 FL_UNLOCK(fl);
1629 fl_hw_cidx = fl->hw_cidx;
1630 }
1631
1632 if (d->rss.opcode == CPL_RX_PKT) {
1633 if (__predict_true(eth_rx(sc, rxq, d, lq) == 0))
1634 break;
1635 goto out;
1636 }
1637 m0 = get_fl_payload(sc, fl, lq);
1638 if (__predict_false(m0 == NULL))
1639 goto out;
1640
1641 /* fall through */
1642
1643 case X_RSPD_TYPE_CPL:
1644 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1645 ("%s: bad opcode %02x.", __func__, d->rss.opcode));
1646 t4_cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1647 break;
1648
1649 case X_RSPD_TYPE_INTR:
1650
1651 /*
1652 * There are 1K interrupt-capable queues (qids 0
1653 * through 1023). A response type indicating a
1654 * forwarded interrupt with a qid >= 1K is an
1655 * iWARP async notification. That is the only
1656 * acceptable indirect interrupt on this queue.
1657 */
1658 if (__predict_false(lq < 1024)) {
1659 panic("%s: indirect interrupt on iq_fl %p "
1660 "with qid %u", __func__, iq, lq);
1661 }
1662
1663 t4_an_handler(iq, &d->rsp);
1664 break;
1665
1666 default:
1667 KASSERT(0, ("%s: illegal response type %d on iq %p",
1668 __func__, rsp_type, iq));
1669 log(LOG_ERR, "%s: illegal response type %d on iq %p",
1670 device_get_nameunit(sc->dev), rsp_type, iq);
1671 break;
1672 }
1673
1674 d++;
1675 if (__predict_false(++iq->cidx == iq->sidx)) {
1676 iq->cidx = 0;
1677 iq->gen ^= F_RSPD_GEN;
1678 d = &iq->desc[0];
1679 }
1680 if (__predict_false(++ndescs == limit)) {
1681 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1682 V_INGRESSQID(iq->cntxt_id) |
1683 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1684
1685 #if defined(INET) || defined(INET6)
1686 if (iq->flags & IQ_LRO_ENABLED &&
1687 !sort_before_lro(lro) &&
1688 sc->lro_timeout != 0) {
1689 tcp_lro_flush_inactive(lro, &lro_timeout);
1690 }
1691 #endif
1692 if (budget)
1693 return (EINPROGRESS);
1694 ndescs = 0;
1695 }
1696 }
1697 out:
1698 #if defined(INET) || defined(INET6)
1699 if (iq->flags & IQ_LRO_ENABLED) {
1700 if (ndescs > 0 && lro->lro_mbuf_count > 8) {
1701 MPASS(sort_before_lro(lro));
1702 /* hold back one credit and don't flush LRO state */
1703 iq->flags |= IQ_ADJ_CREDIT;
1704 ndescs--;
1705 } else {
1706 tcp_lro_flush_all(lro);
1707 }
1708 }
1709 #endif
1710
1711 t4_write_reg(sc, sc->sge_gts_reg, V_CIDXINC(ndescs) |
1712 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1713
1714 FL_LOCK(fl);
1715 starved = refill_fl(sc, fl, 64);
1716 FL_UNLOCK(fl);
1717 if (__predict_false(starved != 0))
1718 add_fl_to_sfl(sc, fl);
1719
1720 return (0);
1721 }
1722
1723 static inline struct cluster_metadata *
cl_metadata(struct fl_sdesc * sd)1724 cl_metadata(struct fl_sdesc *sd)
1725 {
1726
1727 return ((void *)(sd->cl + sd->moff));
1728 }
1729
1730 static void
rxb_free(struct mbuf * m)1731 rxb_free(struct mbuf *m)
1732 {
1733 struct cluster_metadata *clm = m->m_ext.ext_arg1;
1734
1735 uma_zfree(clm->zone, clm->cl);
1736 counter_u64_add(extfree_rels, 1);
1737 }
1738
1739 /*
1740 * The mbuf returned comes from zone_muf and carries the payload in one of these
1741 * ways
1742 * a) complete frame inside the mbuf
1743 * b) m_cljset (for clusters without metadata)
1744 * d) m_extaddref (cluster with metadata)
1745 */
1746 static struct mbuf *
get_scatter_segment(struct adapter * sc,struct sge_fl * fl,int fr_offset,int remaining)1747 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1748 int remaining)
1749 {
1750 struct mbuf *m;
1751 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1752 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx];
1753 struct cluster_metadata *clm;
1754 int len, blen;
1755 caddr_t payload;
1756
1757 if (fl->flags & FL_BUF_PACKING) {
1758 u_int l, pad;
1759
1760 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */
1761 len = min(remaining, blen);
1762 payload = sd->cl + fl->rx_offset;
1763
1764 l = fr_offset + len;
1765 pad = roundup2(l, fl->buf_boundary) - l;
1766 if (fl->rx_offset + len + pad < rxb->size2)
1767 blen = len + pad;
1768 MPASS(fl->rx_offset + blen <= rxb->size2);
1769 } else {
1770 MPASS(fl->rx_offset == 0); /* not packing */
1771 blen = rxb->size1;
1772 len = min(remaining, blen);
1773 payload = sd->cl;
1774 }
1775
1776 if (fr_offset == 0) {
1777 m = m_gethdr(M_NOWAIT, MT_DATA);
1778 if (__predict_false(m == NULL))
1779 return (NULL);
1780 m->m_pkthdr.len = remaining;
1781 } else {
1782 m = m_get(M_NOWAIT, MT_DATA);
1783 if (__predict_false(m == NULL))
1784 return (NULL);
1785 }
1786 m->m_len = len;
1787 kmsan_mark(payload, len, KMSAN_STATE_INITED);
1788
1789 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1790 /* copy data to mbuf */
1791 bcopy(payload, mtod(m, caddr_t), len);
1792 if (fl->flags & FL_BUF_PACKING) {
1793 fl->rx_offset += blen;
1794 MPASS(fl->rx_offset <= rxb->size2);
1795 if (fl->rx_offset < rxb->size2)
1796 return (m); /* without advancing the cidx */
1797 }
1798 } else if (fl->flags & FL_BUF_PACKING) {
1799 clm = cl_metadata(sd);
1800 if (sd->nmbuf++ == 0) {
1801 clm->refcount = 1;
1802 clm->zone = rxb->zone;
1803 clm->cl = sd->cl;
1804 counter_u64_add(extfree_refs, 1);
1805 }
1806 m_extaddref(m, payload, blen, &clm->refcount, rxb_free, clm,
1807 NULL);
1808
1809 fl->rx_offset += blen;
1810 MPASS(fl->rx_offset <= rxb->size2);
1811 if (fl->rx_offset < rxb->size2)
1812 return (m); /* without advancing the cidx */
1813 } else {
1814 m_cljset(m, sd->cl, rxb->type);
1815 sd->cl = NULL; /* consumed, not a recycle candidate */
1816 }
1817
1818 move_to_next_rxbuf(fl);
1819
1820 return (m);
1821 }
1822
1823 static struct mbuf *
get_fl_payload(struct adapter * sc,struct sge_fl * fl,const u_int plen)1824 get_fl_payload(struct adapter *sc, struct sge_fl *fl, const u_int plen)
1825 {
1826 struct mbuf *m0, *m, **pnext;
1827 u_int remaining;
1828
1829 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1830 M_ASSERTPKTHDR(fl->m0);
1831 MPASS(fl->m0->m_pkthdr.len == plen);
1832 MPASS(fl->remaining < plen);
1833
1834 m0 = fl->m0;
1835 pnext = fl->pnext;
1836 remaining = fl->remaining;
1837 fl->flags &= ~FL_BUF_RESUME;
1838 goto get_segment;
1839 }
1840
1841 /*
1842 * Payload starts at rx_offset in the current hw buffer. Its length is
1843 * 'len' and it may span multiple hw buffers.
1844 */
1845
1846 m0 = get_scatter_segment(sc, fl, 0, plen);
1847 if (m0 == NULL)
1848 return (NULL);
1849 remaining = plen - m0->m_len;
1850 pnext = &m0->m_next;
1851 while (remaining > 0) {
1852 get_segment:
1853 MPASS(fl->rx_offset == 0);
1854 m = get_scatter_segment(sc, fl, plen - remaining, remaining);
1855 if (__predict_false(m == NULL)) {
1856 fl->m0 = m0;
1857 fl->pnext = pnext;
1858 fl->remaining = remaining;
1859 fl->flags |= FL_BUF_RESUME;
1860 return (NULL);
1861 }
1862 *pnext = m;
1863 pnext = &m->m_next;
1864 remaining -= m->m_len;
1865 }
1866 *pnext = NULL;
1867
1868 M_ASSERTPKTHDR(m0);
1869 return (m0);
1870 }
1871
1872 static int
skip_scatter_segment(struct adapter * sc,struct sge_fl * fl,int fr_offset,int remaining)1873 skip_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1874 int remaining)
1875 {
1876 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1877 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx];
1878 int len, blen;
1879
1880 if (fl->flags & FL_BUF_PACKING) {
1881 u_int l, pad;
1882
1883 blen = rxb->size2 - fl->rx_offset; /* max possible in this buf */
1884 len = min(remaining, blen);
1885
1886 l = fr_offset + len;
1887 pad = roundup2(l, fl->buf_boundary) - l;
1888 if (fl->rx_offset + len + pad < rxb->size2)
1889 blen = len + pad;
1890 fl->rx_offset += blen;
1891 MPASS(fl->rx_offset <= rxb->size2);
1892 if (fl->rx_offset < rxb->size2)
1893 return (len); /* without advancing the cidx */
1894 } else {
1895 MPASS(fl->rx_offset == 0); /* not packing */
1896 blen = rxb->size1;
1897 len = min(remaining, blen);
1898 }
1899 move_to_next_rxbuf(fl);
1900 return (len);
1901 }
1902
1903 static inline void
skip_fl_payload(struct adapter * sc,struct sge_fl * fl,int plen)1904 skip_fl_payload(struct adapter *sc, struct sge_fl *fl, int plen)
1905 {
1906 int remaining, fr_offset, len;
1907
1908 fr_offset = 0;
1909 remaining = plen;
1910 while (remaining > 0) {
1911 len = skip_scatter_segment(sc, fl, fr_offset, remaining);
1912 fr_offset += len;
1913 remaining -= len;
1914 }
1915 }
1916
1917 static inline int
get_segment_len(struct adapter * sc,struct sge_fl * fl,int plen)1918 get_segment_len(struct adapter *sc, struct sge_fl *fl, int plen)
1919 {
1920 int len;
1921 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1922 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[sd->zidx];
1923
1924 if (fl->flags & FL_BUF_PACKING)
1925 len = rxb->size2 - fl->rx_offset;
1926 else
1927 len = rxb->size1;
1928
1929 return (min(plen, len));
1930 }
1931
1932 static int
eth_rx(struct adapter * sc,struct sge_rxq * rxq,const struct iq_desc * d,u_int plen)1933 eth_rx(struct adapter *sc, struct sge_rxq *rxq, const struct iq_desc *d,
1934 u_int plen)
1935 {
1936 struct mbuf *m0;
1937 if_t ifp = rxq->ifp;
1938 struct sge_fl *fl = &rxq->fl;
1939 struct vi_info *vi = if_getsoftc(ifp);
1940 const struct cpl_rx_pkt *cpl;
1941 #if defined(INET) || defined(INET6)
1942 struct lro_ctrl *lro = &rxq->lro;
1943 #endif
1944 uint16_t err_vec, tnl_type, tnlhdr_len;
1945 static const int sw_hashtype[4][2] = {
1946 {M_HASHTYPE_NONE, M_HASHTYPE_NONE},
1947 {M_HASHTYPE_RSS_IPV4, M_HASHTYPE_RSS_IPV6},
1948 {M_HASHTYPE_RSS_TCP_IPV4, M_HASHTYPE_RSS_TCP_IPV6},
1949 {M_HASHTYPE_RSS_UDP_IPV4, M_HASHTYPE_RSS_UDP_IPV6},
1950 };
1951 static const int sw_csum_flags[2][2] = {
1952 {
1953 /* IP, inner IP */
1954 CSUM_ENCAP_VXLAN |
1955 CSUM_L3_CALC | CSUM_L3_VALID |
1956 CSUM_L4_CALC | CSUM_L4_VALID |
1957 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID |
1958 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1959
1960 /* IP, inner IP6 */
1961 CSUM_ENCAP_VXLAN |
1962 CSUM_L3_CALC | CSUM_L3_VALID |
1963 CSUM_L4_CALC | CSUM_L4_VALID |
1964 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1965 },
1966 {
1967 /* IP6, inner IP */
1968 CSUM_ENCAP_VXLAN |
1969 CSUM_L4_CALC | CSUM_L4_VALID |
1970 CSUM_INNER_L3_CALC | CSUM_INNER_L3_VALID |
1971 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1972
1973 /* IP6, inner IP6 */
1974 CSUM_ENCAP_VXLAN |
1975 CSUM_L4_CALC | CSUM_L4_VALID |
1976 CSUM_INNER_L4_CALC | CSUM_INNER_L4_VALID,
1977 },
1978 };
1979
1980 MPASS(plen > sc->params.sge.fl_pktshift);
1981 if (vi->pfil != NULL && PFIL_HOOKED_IN(vi->pfil) &&
1982 __predict_true((fl->flags & FL_BUF_RESUME) == 0)) {
1983 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1984 caddr_t frame;
1985 int rc, slen;
1986
1987 slen = get_segment_len(sc, fl, plen) -
1988 sc->params.sge.fl_pktshift;
1989 frame = sd->cl + fl->rx_offset + sc->params.sge.fl_pktshift;
1990 CURVNET_SET_QUIET(if_getvnet(ifp));
1991 rc = pfil_mem_in(vi->pfil, frame, slen, ifp, &m0);
1992 CURVNET_RESTORE();
1993 if (rc == PFIL_DROPPED || rc == PFIL_CONSUMED) {
1994 skip_fl_payload(sc, fl, plen);
1995 return (0);
1996 }
1997 if (rc == PFIL_REALLOCED) {
1998 skip_fl_payload(sc, fl, plen);
1999 goto have_mbuf;
2000 }
2001 }
2002
2003 m0 = get_fl_payload(sc, fl, plen);
2004 if (__predict_false(m0 == NULL))
2005 return (ENOMEM);
2006
2007 m0->m_pkthdr.len -= sc->params.sge.fl_pktshift;
2008 m0->m_len -= sc->params.sge.fl_pktshift;
2009 m0->m_data += sc->params.sge.fl_pktshift;
2010
2011 have_mbuf:
2012 m0->m_pkthdr.rcvif = ifp;
2013 M_HASHTYPE_SET(m0, sw_hashtype[d->rss.hash_type][d->rss.ipv6]);
2014 m0->m_pkthdr.flowid = be32toh(d->rss.hash_val);
2015
2016 cpl = (const void *)(&d->rss + 1);
2017 if (sc->params.tp.rx_pkt_encap) {
2018 const uint16_t ev = be16toh(cpl->err_vec);
2019
2020 err_vec = G_T6_COMPR_RXERR_VEC(ev);
2021 tnl_type = G_T6_RX_TNL_TYPE(ev);
2022 tnlhdr_len = G_T6_RX_TNLHDR_LEN(ev);
2023 } else {
2024 err_vec = be16toh(cpl->err_vec);
2025 tnl_type = 0;
2026 tnlhdr_len = 0;
2027 }
2028 if (cpl->csum_calc && err_vec == 0) {
2029 int ipv6 = !!(cpl->l2info & htobe32(F_RXF_IP6));
2030
2031 /* checksum(s) calculated and found to be correct. */
2032
2033 MPASS((cpl->l2info & htobe32(F_RXF_IP)) ^
2034 (cpl->l2info & htobe32(F_RXF_IP6)));
2035 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
2036 if (tnl_type == 0) {
2037 if (!ipv6 && if_getcapenable(ifp) & IFCAP_RXCSUM) {
2038 m0->m_pkthdr.csum_flags = CSUM_L3_CALC |
2039 CSUM_L3_VALID | CSUM_L4_CALC |
2040 CSUM_L4_VALID;
2041 } else if (ipv6 && if_getcapenable(ifp) & IFCAP_RXCSUM_IPV6) {
2042 m0->m_pkthdr.csum_flags = CSUM_L4_CALC |
2043 CSUM_L4_VALID;
2044 }
2045 rxq->rxcsum++;
2046 } else {
2047 MPASS(tnl_type == RX_PKT_TNL_TYPE_VXLAN);
2048
2049 M_HASHTYPE_SETINNER(m0);
2050 if (__predict_false(cpl->ip_frag)) {
2051 /*
2052 * csum_data is for the inner frame (which is an
2053 * IP fragment) and is not 0xffff. There is no
2054 * way to pass the inner csum_data to the stack.
2055 * We don't want the stack to use the inner
2056 * csum_data to validate the outer frame or it
2057 * will get rejected. So we fix csum_data here
2058 * and let sw do the checksum of inner IP
2059 * fragments.
2060 *
2061 * XXX: Need 32b for csum_data2 in an rx mbuf.
2062 * Maybe stuff it into rcv_tstmp?
2063 */
2064 m0->m_pkthdr.csum_data = 0xffff;
2065 if (ipv6) {
2066 m0->m_pkthdr.csum_flags = CSUM_L4_CALC |
2067 CSUM_L4_VALID;
2068 } else {
2069 m0->m_pkthdr.csum_flags = CSUM_L3_CALC |
2070 CSUM_L3_VALID | CSUM_L4_CALC |
2071 CSUM_L4_VALID;
2072 }
2073 } else {
2074 int outer_ipv6;
2075
2076 MPASS(m0->m_pkthdr.csum_data == 0xffff);
2077
2078 outer_ipv6 = tnlhdr_len >=
2079 sizeof(struct ether_header) +
2080 sizeof(struct ip6_hdr);
2081 m0->m_pkthdr.csum_flags =
2082 sw_csum_flags[outer_ipv6][ipv6];
2083 }
2084 rxq->vxlan_rxcsum++;
2085 }
2086 }
2087
2088 if (cpl->vlan_ex) {
2089 if (sc->flags & IS_VF && sc->vlan_id) {
2090 /*
2091 * HW is not setup correctly if extracted vlan_id does
2092 * not match the VF's setting.
2093 */
2094 MPASS(be16toh(cpl->vlan) == sc->vlan_id);
2095 } else {
2096 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
2097 m0->m_flags |= M_VLANTAG;
2098 rxq->vlan_extraction++;
2099 }
2100 }
2101
2102 if (rxq->iq.flags & IQ_RX_TIMESTAMP) {
2103 /*
2104 * Fill up rcv_tstmp but do not set M_TSTMP as
2105 * long as we get a non-zero back from t4_tstmp_to_ns().
2106 */
2107 m0->m_pkthdr.rcv_tstmp = t4_tstmp_to_ns(sc,
2108 be64toh(d->rsp.u.last_flit));
2109 if (m0->m_pkthdr.rcv_tstmp != 0)
2110 m0->m_flags |= M_TSTMP;
2111 }
2112
2113 #ifdef NUMA
2114 m0->m_pkthdr.numa_domain = if_getnumadomain(ifp);
2115 #endif
2116 #if defined(INET) || defined(INET6)
2117 if (rxq->iq.flags & IQ_LRO_ENABLED && tnl_type == 0 &&
2118 (M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV4 ||
2119 M_HASHTYPE_GET(m0) == M_HASHTYPE_RSS_TCP_IPV6)) {
2120 if (sort_before_lro(lro)) {
2121 tcp_lro_queue_mbuf(lro, m0);
2122 return (0); /* queued for sort, then LRO */
2123 }
2124 if (tcp_lro_rx(lro, m0, 0) == 0)
2125 return (0); /* queued for LRO */
2126 }
2127 #endif
2128 if_input(ifp, m0);
2129
2130 return (0);
2131 }
2132
2133 /*
2134 * Must drain the wrq or make sure that someone else will.
2135 */
2136 static void
wrq_tx_drain(void * arg,int n)2137 wrq_tx_drain(void *arg, int n)
2138 {
2139 struct sge_wrq *wrq = arg;
2140 struct sge_eq *eq = &wrq->eq;
2141
2142 EQ_LOCK(eq);
2143 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2144 drain_wrq_wr_list(wrq->adapter, wrq);
2145 EQ_UNLOCK(eq);
2146 }
2147
2148 static void
drain_wrq_wr_list(struct adapter * sc,struct sge_wrq * wrq)2149 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
2150 {
2151 struct sge_eq *eq = &wrq->eq;
2152 u_int available, dbdiff; /* # of hardware descriptors */
2153 u_int n;
2154 struct wrqe *wr;
2155 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
2156
2157 EQ_LOCK_ASSERT_OWNED(eq);
2158 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
2159 wr = STAILQ_FIRST(&wrq->wr_list);
2160 MPASS(wr != NULL); /* Must be called with something useful to do */
2161 MPASS(eq->pidx == eq->dbidx);
2162 dbdiff = 0;
2163
2164 do {
2165 eq->cidx = read_hw_cidx(eq);
2166 if (eq->pidx == eq->cidx)
2167 available = eq->sidx - 1;
2168 else
2169 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2170
2171 MPASS(wr->wrq == wrq);
2172 n = howmany(wr->wr_len, EQ_ESIZE);
2173 if (available < n)
2174 break;
2175
2176 dst = (void *)&eq->desc[eq->pidx];
2177 if (__predict_true(eq->sidx - eq->pidx > n)) {
2178 /* Won't wrap, won't end exactly at the status page. */
2179 bcopy(&wr->wr[0], dst, wr->wr_len);
2180 eq->pidx += n;
2181 } else {
2182 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
2183
2184 bcopy(&wr->wr[0], dst, first_portion);
2185 if (wr->wr_len > first_portion) {
2186 bcopy(&wr->wr[first_portion], &eq->desc[0],
2187 wr->wr_len - first_portion);
2188 }
2189 eq->pidx = n - (eq->sidx - eq->pidx);
2190 }
2191 wrq->tx_wrs_copied++;
2192
2193 if (available < eq->sidx / 4 &&
2194 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2195 /*
2196 * XXX: This is not 100% reliable with some
2197 * types of WRs. But this is a very unusual
2198 * situation for an ofld/ctrl queue anyway.
2199 */
2200 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2201 F_FW_WR_EQUEQ);
2202 }
2203
2204 dbdiff += n;
2205 if (dbdiff >= 16) {
2206 ring_eq_db(sc, eq, dbdiff);
2207 dbdiff = 0;
2208 }
2209
2210 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
2211 free_wrqe(wr);
2212 MPASS(wrq->nwr_pending > 0);
2213 wrq->nwr_pending--;
2214 MPASS(wrq->ndesc_needed >= n);
2215 wrq->ndesc_needed -= n;
2216 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
2217
2218 if (dbdiff)
2219 ring_eq_db(sc, eq, dbdiff);
2220 }
2221
2222 /*
2223 * Doesn't fail. Holds on to work requests it can't send right away.
2224 */
2225 void
t4_wrq_tx_locked(struct adapter * sc,struct sge_wrq * wrq,struct wrqe * wr)2226 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
2227 {
2228 #ifdef INVARIANTS
2229 struct sge_eq *eq = &wrq->eq;
2230 #endif
2231
2232 EQ_LOCK_ASSERT_OWNED(eq);
2233 MPASS(wr != NULL);
2234 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
2235 MPASS((wr->wr_len & 0x7) == 0);
2236
2237 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
2238 wrq->nwr_pending++;
2239 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
2240
2241 if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
2242 return; /* commit_wrq_wr will drain wr_list as well. */
2243
2244 drain_wrq_wr_list(sc, wrq);
2245
2246 /* Doorbell must have caught up to the pidx. */
2247 MPASS(eq->pidx == eq->dbidx);
2248 }
2249
2250 void
t4_update_fl_bufsize(if_t ifp)2251 t4_update_fl_bufsize(if_t ifp)
2252 {
2253 struct vi_info *vi = if_getsoftc(ifp);
2254 struct adapter *sc = vi->adapter;
2255 struct sge_rxq *rxq;
2256 #ifdef TCP_OFFLOAD
2257 struct sge_ofld_rxq *ofld_rxq;
2258 #endif
2259 struct sge_fl *fl;
2260 int i, maxp;
2261
2262 maxp = max_rx_payload(sc, ifp, false);
2263 for_each_rxq(vi, i, rxq) {
2264 fl = &rxq->fl;
2265
2266 FL_LOCK(fl);
2267 fl->zidx = find_refill_source(sc, maxp,
2268 fl->flags & FL_BUF_PACKING);
2269 FL_UNLOCK(fl);
2270 }
2271 #ifdef TCP_OFFLOAD
2272 maxp = max_rx_payload(sc, ifp, true);
2273 for_each_ofld_rxq(vi, i, ofld_rxq) {
2274 fl = &ofld_rxq->fl;
2275
2276 FL_LOCK(fl);
2277 fl->zidx = find_refill_source(sc, maxp,
2278 fl->flags & FL_BUF_PACKING);
2279 FL_UNLOCK(fl);
2280 }
2281 #endif
2282 }
2283
2284 #ifdef RATELIMIT
2285 static inline int
mbuf_eo_nsegs(struct mbuf * m)2286 mbuf_eo_nsegs(struct mbuf *m)
2287 {
2288
2289 M_ASSERTPKTHDR(m);
2290 return (m->m_pkthdr.PH_loc.eight[1]);
2291 }
2292
2293 #if defined(INET) || defined(INET6)
2294 static inline void
set_mbuf_eo_nsegs(struct mbuf * m,uint8_t nsegs)2295 set_mbuf_eo_nsegs(struct mbuf *m, uint8_t nsegs)
2296 {
2297
2298 M_ASSERTPKTHDR(m);
2299 m->m_pkthdr.PH_loc.eight[1] = nsegs;
2300 }
2301 #endif
2302
2303 static inline int
mbuf_eo_len16(struct mbuf * m)2304 mbuf_eo_len16(struct mbuf *m)
2305 {
2306 int n;
2307
2308 M_ASSERTPKTHDR(m);
2309 n = m->m_pkthdr.PH_loc.eight[2];
2310 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
2311
2312 return (n);
2313 }
2314
2315 #if defined(INET) || defined(INET6)
2316 static inline void
set_mbuf_eo_len16(struct mbuf * m,uint8_t len16)2317 set_mbuf_eo_len16(struct mbuf *m, uint8_t len16)
2318 {
2319
2320 M_ASSERTPKTHDR(m);
2321 m->m_pkthdr.PH_loc.eight[2] = len16;
2322 }
2323 #endif
2324
2325 static inline int
mbuf_eo_tsclk_tsoff(struct mbuf * m)2326 mbuf_eo_tsclk_tsoff(struct mbuf *m)
2327 {
2328
2329 M_ASSERTPKTHDR(m);
2330 return (m->m_pkthdr.PH_loc.eight[3]);
2331 }
2332
2333 #if defined(INET) || defined(INET6)
2334 static inline void
set_mbuf_eo_tsclk_tsoff(struct mbuf * m,uint8_t tsclk_tsoff)2335 set_mbuf_eo_tsclk_tsoff(struct mbuf *m, uint8_t tsclk_tsoff)
2336 {
2337
2338 M_ASSERTPKTHDR(m);
2339 m->m_pkthdr.PH_loc.eight[3] = tsclk_tsoff;
2340 }
2341 #endif
2342
2343 static inline int
needs_eo(struct m_snd_tag * mst)2344 needs_eo(struct m_snd_tag *mst)
2345 {
2346
2347 return (mst != NULL && mst->sw->type == IF_SND_TAG_TYPE_RATE_LIMIT);
2348 }
2349 #endif
2350
2351 /*
2352 * Try to allocate an mbuf to contain a raw work request. To make it
2353 * easy to construct the work request, don't allocate a chain but a
2354 * single mbuf.
2355 */
2356 struct mbuf *
alloc_wr_mbuf(int len,int how)2357 alloc_wr_mbuf(int len, int how)
2358 {
2359 struct mbuf *m;
2360
2361 if (len <= MHLEN)
2362 m = m_gethdr(how, MT_DATA);
2363 else if (len <= MCLBYTES)
2364 m = m_getcl(how, MT_DATA, M_PKTHDR);
2365 else
2366 m = NULL;
2367 if (m == NULL)
2368 return (NULL);
2369 m->m_pkthdr.len = len;
2370 m->m_len = len;
2371 set_mbuf_cflags(m, MC_RAW_WR);
2372 set_mbuf_len16(m, howmany(len, 16));
2373 return (m);
2374 }
2375
2376 static inline bool
needs_hwcsum(struct mbuf * m)2377 needs_hwcsum(struct mbuf *m)
2378 {
2379 const uint32_t csum_flags = CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP |
2380 CSUM_IP_TSO | CSUM_INNER_IP | CSUM_INNER_IP_UDP |
2381 CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO | CSUM_IP6_UDP |
2382 CSUM_IP6_TCP | CSUM_IP6_TSO | CSUM_INNER_IP6_UDP |
2383 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO;
2384
2385 M_ASSERTPKTHDR(m);
2386
2387 return (m->m_pkthdr.csum_flags & csum_flags);
2388 }
2389
2390 static inline bool
needs_tso(struct mbuf * m)2391 needs_tso(struct mbuf *m)
2392 {
2393 const uint32_t csum_flags = CSUM_IP_TSO | CSUM_IP6_TSO |
2394 CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO;
2395
2396 M_ASSERTPKTHDR(m);
2397
2398 return (m->m_pkthdr.csum_flags & csum_flags);
2399 }
2400
2401 static inline bool
needs_vxlan_csum(struct mbuf * m)2402 needs_vxlan_csum(struct mbuf *m)
2403 {
2404
2405 M_ASSERTPKTHDR(m);
2406
2407 return (m->m_pkthdr.csum_flags & CSUM_ENCAP_VXLAN);
2408 }
2409
2410 static inline bool
needs_vxlan_tso(struct mbuf * m)2411 needs_vxlan_tso(struct mbuf *m)
2412 {
2413 const uint32_t csum_flags = CSUM_ENCAP_VXLAN | CSUM_INNER_IP_TSO |
2414 CSUM_INNER_IP6_TSO;
2415
2416 M_ASSERTPKTHDR(m);
2417
2418 return ((m->m_pkthdr.csum_flags & csum_flags) != 0 &&
2419 (m->m_pkthdr.csum_flags & csum_flags) != CSUM_ENCAP_VXLAN);
2420 }
2421
2422 #if defined(INET) || defined(INET6)
2423 static inline bool
needs_inner_tcp_csum(struct mbuf * m)2424 needs_inner_tcp_csum(struct mbuf *m)
2425 {
2426 const uint32_t csum_flags = CSUM_INNER_IP_TSO | CSUM_INNER_IP6_TSO;
2427
2428 M_ASSERTPKTHDR(m);
2429
2430 return (m->m_pkthdr.csum_flags & csum_flags);
2431 }
2432 #endif
2433
2434 static inline bool
needs_l3_csum(struct mbuf * m)2435 needs_l3_csum(struct mbuf *m)
2436 {
2437 const uint32_t csum_flags = CSUM_IP | CSUM_IP_TSO | CSUM_INNER_IP |
2438 CSUM_INNER_IP_TSO;
2439
2440 M_ASSERTPKTHDR(m);
2441
2442 return (m->m_pkthdr.csum_flags & csum_flags);
2443 }
2444
2445 static inline bool
needs_outer_tcp_csum(struct mbuf * m)2446 needs_outer_tcp_csum(struct mbuf *m)
2447 {
2448 const uint32_t csum_flags = CSUM_IP_TCP | CSUM_IP_TSO | CSUM_IP6_TCP |
2449 CSUM_IP6_TSO;
2450
2451 M_ASSERTPKTHDR(m);
2452
2453 return (m->m_pkthdr.csum_flags & csum_flags);
2454 }
2455
2456 #ifdef RATELIMIT
2457 static inline bool
needs_outer_l4_csum(struct mbuf * m)2458 needs_outer_l4_csum(struct mbuf *m)
2459 {
2460 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP_TCP | CSUM_IP_TSO |
2461 CSUM_IP6_UDP | CSUM_IP6_TCP | CSUM_IP6_TSO;
2462
2463 M_ASSERTPKTHDR(m);
2464
2465 return (m->m_pkthdr.csum_flags & csum_flags);
2466 }
2467
2468 static inline bool
needs_outer_udp_csum(struct mbuf * m)2469 needs_outer_udp_csum(struct mbuf *m)
2470 {
2471 const uint32_t csum_flags = CSUM_IP_UDP | CSUM_IP6_UDP;
2472
2473 M_ASSERTPKTHDR(m);
2474
2475 return (m->m_pkthdr.csum_flags & csum_flags);
2476 }
2477 #endif
2478
2479 static inline bool
needs_vlan_insertion(struct mbuf * m)2480 needs_vlan_insertion(struct mbuf *m)
2481 {
2482
2483 M_ASSERTPKTHDR(m);
2484
2485 return (m->m_flags & M_VLANTAG);
2486 }
2487
2488 #if defined(INET) || defined(INET6)
2489 static void *
m_advance(struct mbuf ** pm,int * poffset,int len)2490 m_advance(struct mbuf **pm, int *poffset, int len)
2491 {
2492 struct mbuf *m = *pm;
2493 int offset = *poffset;
2494 uintptr_t p = 0;
2495
2496 MPASS(len > 0);
2497
2498 for (;;) {
2499 if (offset + len < m->m_len) {
2500 offset += len;
2501 p = mtod(m, uintptr_t) + offset;
2502 break;
2503 }
2504 len -= m->m_len - offset;
2505 m = m->m_next;
2506 offset = 0;
2507 MPASS(m != NULL);
2508 }
2509 *poffset = offset;
2510 *pm = m;
2511 return ((void *)p);
2512 }
2513 #endif
2514
2515 static inline int
count_mbuf_ext_pgs(struct mbuf * m,int skip,vm_paddr_t * nextaddr)2516 count_mbuf_ext_pgs(struct mbuf *m, int skip, vm_paddr_t *nextaddr)
2517 {
2518 vm_paddr_t paddr;
2519 int i, len, off, pglen, pgoff, seglen, segoff;
2520 int nsegs = 0;
2521
2522 M_ASSERTEXTPG(m);
2523 off = mtod(m, vm_offset_t);
2524 len = m->m_len;
2525 off += skip;
2526 len -= skip;
2527
2528 if (m->m_epg_hdrlen != 0) {
2529 if (off >= m->m_epg_hdrlen) {
2530 off -= m->m_epg_hdrlen;
2531 } else {
2532 seglen = m->m_epg_hdrlen - off;
2533 segoff = off;
2534 seglen = min(seglen, len);
2535 off = 0;
2536 len -= seglen;
2537 paddr = pmap_kextract(
2538 (vm_offset_t)&m->m_epg_hdr[segoff]);
2539 if (*nextaddr != paddr)
2540 nsegs++;
2541 *nextaddr = paddr + seglen;
2542 }
2543 }
2544 pgoff = m->m_epg_1st_off;
2545 for (i = 0; i < m->m_epg_npgs && len > 0; i++) {
2546 pglen = m_epg_pagelen(m, i, pgoff);
2547 if (off >= pglen) {
2548 off -= pglen;
2549 pgoff = 0;
2550 continue;
2551 }
2552 seglen = pglen - off;
2553 segoff = pgoff + off;
2554 off = 0;
2555 seglen = min(seglen, len);
2556 len -= seglen;
2557 paddr = m->m_epg_pa[i] + segoff;
2558 if (*nextaddr != paddr)
2559 nsegs++;
2560 *nextaddr = paddr + seglen;
2561 pgoff = 0;
2562 };
2563 if (len != 0) {
2564 seglen = min(len, m->m_epg_trllen - off);
2565 len -= seglen;
2566 paddr = pmap_kextract((vm_offset_t)&m->m_epg_trail[off]);
2567 if (*nextaddr != paddr)
2568 nsegs++;
2569 *nextaddr = paddr + seglen;
2570 }
2571
2572 return (nsegs);
2573 }
2574
2575
2576 /*
2577 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
2578 * must have at least one mbuf that's not empty. It is possible for this
2579 * routine to return 0 if skip accounts for all the contents of the mbuf chain.
2580 */
2581 static inline int
count_mbuf_nsegs(struct mbuf * m,int skip,uint8_t * cflags)2582 count_mbuf_nsegs(struct mbuf *m, int skip, uint8_t *cflags)
2583 {
2584 vm_paddr_t nextaddr, paddr;
2585 vm_offset_t va;
2586 int len, nsegs;
2587
2588 M_ASSERTPKTHDR(m);
2589 MPASS(m->m_pkthdr.len > 0);
2590 MPASS(m->m_pkthdr.len >= skip);
2591
2592 nsegs = 0;
2593 nextaddr = 0;
2594 for (; m; m = m->m_next) {
2595 len = m->m_len;
2596 if (__predict_false(len == 0))
2597 continue;
2598 if (skip >= len) {
2599 skip -= len;
2600 continue;
2601 }
2602 if ((m->m_flags & M_EXTPG) != 0) {
2603 *cflags |= MC_NOMAP;
2604 nsegs += count_mbuf_ext_pgs(m, skip, &nextaddr);
2605 skip = 0;
2606 continue;
2607 }
2608 va = mtod(m, vm_offset_t) + skip;
2609 len -= skip;
2610 skip = 0;
2611 paddr = pmap_kextract(va);
2612 nsegs += sglist_count((void *)(uintptr_t)va, len);
2613 if (paddr == nextaddr)
2614 nsegs--;
2615 nextaddr = pmap_kextract(va + len - 1) + 1;
2616 }
2617
2618 return (nsegs);
2619 }
2620
2621 /*
2622 * The maximum number of segments that can fit in a WR.
2623 */
2624 static int
max_nsegs_allowed(struct mbuf * m,bool vm_wr)2625 max_nsegs_allowed(struct mbuf *m, bool vm_wr)
2626 {
2627
2628 if (vm_wr) {
2629 if (needs_tso(m))
2630 return (TX_SGL_SEGS_VM_TSO);
2631 return (TX_SGL_SEGS_VM);
2632 }
2633
2634 if (needs_tso(m)) {
2635 if (needs_vxlan_tso(m))
2636 return (TX_SGL_SEGS_VXLAN_TSO);
2637 else
2638 return (TX_SGL_SEGS_TSO);
2639 }
2640
2641 return (TX_SGL_SEGS);
2642 }
2643
2644 static struct timeval txerr_ratecheck = {0};
2645 static const struct timeval txerr_interval = {3, 0};
2646
2647 /*
2648 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change:
2649 * a) caller can assume it's been freed if this function returns with an error.
2650 * b) it may get defragged up if the gather list is too long for the hardware.
2651 */
2652 int
parse_pkt(struct mbuf ** mp,bool vm_wr)2653 parse_pkt(struct mbuf **mp, bool vm_wr)
2654 {
2655 struct mbuf *m0 = *mp, *m;
2656 int rc, nsegs, defragged = 0;
2657 struct ether_header *eh;
2658 #ifdef INET
2659 void *l3hdr;
2660 #endif
2661 #if defined(INET) || defined(INET6)
2662 int offset;
2663 struct tcphdr *tcp;
2664 #endif
2665 #if defined(KERN_TLS) || defined(RATELIMIT)
2666 struct m_snd_tag *mst;
2667 #endif
2668 uint16_t eh_type;
2669 uint8_t cflags;
2670
2671 cflags = 0;
2672 M_ASSERTPKTHDR(m0);
2673 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2674 rc = EINVAL;
2675 fail:
2676 m_freem(m0);
2677 *mp = NULL;
2678 return (rc);
2679 }
2680 restart:
2681 /*
2682 * First count the number of gather list segments in the payload.
2683 * Defrag the mbuf if nsegs exceeds the hardware limit.
2684 */
2685 M_ASSERTPKTHDR(m0);
2686 MPASS(m0->m_pkthdr.len > 0);
2687 nsegs = count_mbuf_nsegs(m0, 0, &cflags);
2688 #if defined(KERN_TLS) || defined(RATELIMIT)
2689 if (m0->m_pkthdr.csum_flags & CSUM_SND_TAG)
2690 mst = m0->m_pkthdr.snd_tag;
2691 else
2692 mst = NULL;
2693 #endif
2694 #ifdef KERN_TLS
2695 if (mst != NULL && mst->sw->type == IF_SND_TAG_TYPE_TLS) {
2696 cflags |= MC_TLS;
2697 set_mbuf_cflags(m0, cflags);
2698 rc = t6_ktls_parse_pkt(m0);
2699 if (rc != 0)
2700 goto fail;
2701 return (EINPROGRESS);
2702 }
2703 #endif
2704 if (nsegs > max_nsegs_allowed(m0, vm_wr)) {
2705 if (defragged++ > 0) {
2706 rc = EFBIG;
2707 goto fail;
2708 }
2709 counter_u64_add(defrags, 1);
2710 if ((m = m_defrag(m0, M_NOWAIT)) == NULL) {
2711 rc = ENOMEM;
2712 goto fail;
2713 }
2714 *mp = m0 = m; /* update caller's copy after defrag */
2715 goto restart;
2716 }
2717
2718 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN &&
2719 !(cflags & MC_NOMAP))) {
2720 counter_u64_add(pullups, 1);
2721 m0 = m_pullup(m0, m0->m_pkthdr.len);
2722 if (m0 == NULL) {
2723 /* Should have left well enough alone. */
2724 rc = EFBIG;
2725 goto fail;
2726 }
2727 *mp = m0; /* update caller's copy after pullup */
2728 goto restart;
2729 }
2730 set_mbuf_nsegs(m0, nsegs);
2731 set_mbuf_cflags(m0, cflags);
2732 calculate_mbuf_len16(m0, vm_wr);
2733
2734 #ifdef RATELIMIT
2735 /*
2736 * Ethofld is limited to TCP and UDP for now, and only when L4 hw
2737 * checksumming is enabled. needs_outer_l4_csum happens to check for
2738 * all the right things.
2739 */
2740 if (__predict_false(needs_eo(mst) && !needs_outer_l4_csum(m0))) {
2741 m_snd_tag_rele(m0->m_pkthdr.snd_tag);
2742 m0->m_pkthdr.snd_tag = NULL;
2743 m0->m_pkthdr.csum_flags &= ~CSUM_SND_TAG;
2744 mst = NULL;
2745 }
2746 #endif
2747
2748 if (!needs_hwcsum(m0)
2749 #ifdef RATELIMIT
2750 && !needs_eo(mst)
2751 #endif
2752 )
2753 return (0);
2754
2755 m = m0;
2756 eh = mtod(m, struct ether_header *);
2757 eh_type = ntohs(eh->ether_type);
2758 if (eh_type == ETHERTYPE_VLAN) {
2759 struct ether_vlan_header *evh = (void *)eh;
2760
2761 eh_type = ntohs(evh->evl_proto);
2762 m0->m_pkthdr.l2hlen = sizeof(*evh);
2763 } else
2764 m0->m_pkthdr.l2hlen = sizeof(*eh);
2765
2766 #if defined(INET) || defined(INET6)
2767 offset = 0;
2768 #ifdef INET
2769 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2770 #else
2771 m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2772 #endif
2773 #endif
2774
2775 switch (eh_type) {
2776 #ifdef INET6
2777 case ETHERTYPE_IPV6:
2778 m0->m_pkthdr.l3hlen = sizeof(struct ip6_hdr);
2779 break;
2780 #endif
2781 #ifdef INET
2782 case ETHERTYPE_IP:
2783 {
2784 struct ip *ip = l3hdr;
2785
2786 if (needs_vxlan_csum(m0)) {
2787 /* Driver will do the outer IP hdr checksum. */
2788 ip->ip_sum = 0;
2789 if (needs_vxlan_tso(m0)) {
2790 const uint16_t ipl = ip->ip_len;
2791
2792 ip->ip_len = 0;
2793 ip->ip_sum = ~in_cksum_hdr(ip);
2794 ip->ip_len = ipl;
2795 } else
2796 ip->ip_sum = in_cksum_hdr(ip);
2797 }
2798 m0->m_pkthdr.l3hlen = ip->ip_hl << 2;
2799 break;
2800 }
2801 #endif
2802 default:
2803 if (ratecheck(&txerr_ratecheck, &txerr_interval)) {
2804 log(LOG_ERR, "%s: ethertype 0x%04x unknown. "
2805 "if_cxgbe must be compiled with the same "
2806 "INET/INET6 options as the kernel.\n", __func__,
2807 eh_type);
2808 }
2809 rc = EINVAL;
2810 goto fail;
2811 }
2812
2813 #if defined(INET) || defined(INET6)
2814 if (needs_vxlan_csum(m0)) {
2815 m0->m_pkthdr.l4hlen = sizeof(struct udphdr);
2816 m0->m_pkthdr.l5hlen = sizeof(struct vxlan_header);
2817
2818 /* Inner headers. */
2819 eh = m_advance(&m, &offset, m0->m_pkthdr.l3hlen +
2820 sizeof(struct udphdr) + sizeof(struct vxlan_header));
2821 eh_type = ntohs(eh->ether_type);
2822 if (eh_type == ETHERTYPE_VLAN) {
2823 struct ether_vlan_header *evh = (void *)eh;
2824
2825 eh_type = ntohs(evh->evl_proto);
2826 m0->m_pkthdr.inner_l2hlen = sizeof(*evh);
2827 } else
2828 m0->m_pkthdr.inner_l2hlen = sizeof(*eh);
2829 #ifdef INET
2830 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen);
2831 #else
2832 m_advance(&m, &offset, m0->m_pkthdr.inner_l2hlen);
2833 #endif
2834
2835 switch (eh_type) {
2836 #ifdef INET6
2837 case ETHERTYPE_IPV6:
2838 m0->m_pkthdr.inner_l3hlen = sizeof(struct ip6_hdr);
2839 break;
2840 #endif
2841 #ifdef INET
2842 case ETHERTYPE_IP:
2843 {
2844 struct ip *ip = l3hdr;
2845
2846 m0->m_pkthdr.inner_l3hlen = ip->ip_hl << 2;
2847 break;
2848 }
2849 #endif
2850 default:
2851 if (ratecheck(&txerr_ratecheck, &txerr_interval)) {
2852 log(LOG_ERR, "%s: VXLAN hw offload requested"
2853 "with unknown ethertype 0x%04x. if_cxgbe "
2854 "must be compiled with the same INET/INET6 "
2855 "options as the kernel.\n", __func__,
2856 eh_type);
2857 }
2858 rc = EINVAL;
2859 goto fail;
2860 }
2861 if (needs_inner_tcp_csum(m0)) {
2862 tcp = m_advance(&m, &offset, m0->m_pkthdr.inner_l3hlen);
2863 m0->m_pkthdr.inner_l4hlen = tcp->th_off * 4;
2864 }
2865 MPASS((m0->m_pkthdr.csum_flags & CSUM_SND_TAG) == 0);
2866 m0->m_pkthdr.csum_flags &= CSUM_INNER_IP6_UDP |
2867 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_TSO | CSUM_INNER_IP |
2868 CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_TSO |
2869 CSUM_ENCAP_VXLAN;
2870 }
2871
2872 if (needs_outer_tcp_csum(m0)) {
2873 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2874 m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2875 #ifdef RATELIMIT
2876 if (tsclk >= 0 && *(uint32_t *)(tcp + 1) == ntohl(0x0101080a)) {
2877 set_mbuf_eo_tsclk_tsoff(m0,
2878 V_FW_ETH_TX_EO_WR_TSCLK(tsclk) |
2879 V_FW_ETH_TX_EO_WR_TSOFF(sizeof(*tcp) / 2 + 1));
2880 } else
2881 set_mbuf_eo_tsclk_tsoff(m0, 0);
2882 } else if (needs_outer_udp_csum(m0)) {
2883 m0->m_pkthdr.l4hlen = sizeof(struct udphdr);
2884 #endif
2885 }
2886 #ifdef RATELIMIT
2887 if (needs_eo(mst)) {
2888 u_int immhdrs;
2889
2890 /* EO WRs have the headers in the WR and not the GL. */
2891 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen +
2892 m0->m_pkthdr.l4hlen;
2893 cflags = 0;
2894 nsegs = count_mbuf_nsegs(m0, immhdrs, &cflags);
2895 MPASS(cflags == mbuf_cflags(m0));
2896 set_mbuf_eo_nsegs(m0, nsegs);
2897 set_mbuf_eo_len16(m0,
2898 txpkt_eo_len16(nsegs, immhdrs, needs_tso(m0)));
2899 rc = ethofld_transmit(mst->ifp, m0);
2900 if (rc != 0)
2901 goto fail;
2902 return (EINPROGRESS);
2903 }
2904 #endif
2905 #endif
2906 MPASS(m0 == *mp);
2907 return (0);
2908 }
2909
2910 void *
start_wrq_wr(struct sge_wrq * wrq,int len16,struct wrq_cookie * cookie)2911 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2912 {
2913 struct sge_eq *eq = &wrq->eq;
2914 struct adapter *sc = wrq->adapter;
2915 int ndesc, available;
2916 struct wrqe *wr;
2917 void *w;
2918
2919 MPASS(len16 > 0);
2920 ndesc = tx_len16_to_desc(len16);
2921 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2922
2923 EQ_LOCK(eq);
2924
2925 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2926 drain_wrq_wr_list(sc, wrq);
2927
2928 if (!STAILQ_EMPTY(&wrq->wr_list)) {
2929 slowpath:
2930 EQ_UNLOCK(eq);
2931 wr = alloc_wrqe(len16 * 16, wrq);
2932 if (__predict_false(wr == NULL))
2933 return (NULL);
2934 cookie->pidx = -1;
2935 cookie->ndesc = ndesc;
2936 return (&wr->wr);
2937 }
2938
2939 eq->cidx = read_hw_cidx(eq);
2940 if (eq->pidx == eq->cidx)
2941 available = eq->sidx - 1;
2942 else
2943 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2944 if (available < ndesc)
2945 goto slowpath;
2946
2947 cookie->pidx = eq->pidx;
2948 cookie->ndesc = ndesc;
2949 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2950
2951 w = &eq->desc[eq->pidx];
2952 IDXINCR(eq->pidx, ndesc, eq->sidx);
2953 if (__predict_false(cookie->pidx + ndesc > eq->sidx)) {
2954 w = &wrq->ss[0];
2955 wrq->ss_pidx = cookie->pidx;
2956 wrq->ss_len = len16 * 16;
2957 }
2958
2959 EQ_UNLOCK(eq);
2960
2961 return (w);
2962 }
2963
2964 void
commit_wrq_wr(struct sge_wrq * wrq,void * w,struct wrq_cookie * cookie)2965 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
2966 {
2967 struct sge_eq *eq = &wrq->eq;
2968 struct adapter *sc = wrq->adapter;
2969 int ndesc, pidx;
2970 struct wrq_cookie *prev, *next;
2971
2972 if (cookie->pidx == -1) {
2973 struct wrqe *wr = __containerof(w, struct wrqe, wr);
2974
2975 t4_wrq_tx(sc, wr);
2976 return;
2977 }
2978
2979 if (__predict_false(w == &wrq->ss[0])) {
2980 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
2981
2982 MPASS(wrq->ss_len > n); /* WR had better wrap around. */
2983 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
2984 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
2985 wrq->tx_wrs_ss++;
2986 } else
2987 wrq->tx_wrs_direct++;
2988
2989 EQ_LOCK(eq);
2990 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */
2991 pidx = cookie->pidx;
2992 MPASS(pidx >= 0 && pidx < eq->sidx);
2993 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
2994 next = TAILQ_NEXT(cookie, link);
2995 if (prev == NULL) {
2996 MPASS(pidx == eq->dbidx);
2997 if (next == NULL || ndesc >= 16) {
2998 int available;
2999 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
3000
3001 /*
3002 * Note that the WR via which we'll request tx updates
3003 * is at pidx and not eq->pidx, which has moved on
3004 * already.
3005 */
3006 dst = (void *)&eq->desc[pidx];
3007 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
3008 if (available < eq->sidx / 4 &&
3009 atomic_cmpset_int(&eq->equiq, 0, 1)) {
3010 /*
3011 * XXX: This is not 100% reliable with some
3012 * types of WRs. But this is a very unusual
3013 * situation for an ofld/ctrl queue anyway.
3014 */
3015 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
3016 F_FW_WR_EQUEQ);
3017 }
3018
3019 ring_eq_db(wrq->adapter, eq, ndesc);
3020 } else {
3021 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
3022 next->pidx = pidx;
3023 next->ndesc += ndesc;
3024 }
3025 } else {
3026 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
3027 prev->ndesc += ndesc;
3028 }
3029 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
3030
3031 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
3032 drain_wrq_wr_list(sc, wrq);
3033
3034 #ifdef INVARIANTS
3035 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
3036 /* Doorbell must have caught up to the pidx. */
3037 MPASS(wrq->eq.pidx == wrq->eq.dbidx);
3038 }
3039 #endif
3040 EQ_UNLOCK(eq);
3041 }
3042
3043 static u_int
can_resume_eth_tx(struct mp_ring * r)3044 can_resume_eth_tx(struct mp_ring *r)
3045 {
3046 struct sge_eq *eq = r->cookie;
3047
3048 return (total_available_tx_desc(eq) > eq->sidx / 8);
3049 }
3050
3051 static inline bool
cannot_use_txpkts(struct mbuf * m)3052 cannot_use_txpkts(struct mbuf *m)
3053 {
3054 /* maybe put a GL limit too, to avoid silliness? */
3055
3056 return (needs_tso(m) || (mbuf_cflags(m) & (MC_RAW_WR | MC_TLS)) != 0);
3057 }
3058
3059 static inline int
discard_tx(struct sge_eq * eq)3060 discard_tx(struct sge_eq *eq)
3061 {
3062
3063 return ((eq->flags & (EQ_ENABLED | EQ_QFLUSH)) != EQ_ENABLED);
3064 }
3065
3066 static inline int
wr_can_update_eq(void * p)3067 wr_can_update_eq(void *p)
3068 {
3069 struct fw_eth_tx_pkts_wr *wr = p;
3070
3071 switch (G_FW_WR_OP(be32toh(wr->op_pkd))) {
3072 case FW_ULPTX_WR:
3073 case FW_ETH_TX_PKT_WR:
3074 case FW_ETH_TX_PKTS_WR:
3075 case FW_ETH_TX_PKTS2_WR:
3076 case FW_ETH_TX_PKT_VM_WR:
3077 case FW_ETH_TX_PKTS_VM_WR:
3078 return (1);
3079 default:
3080 return (0);
3081 }
3082 }
3083
3084 static inline void
set_txupdate_flags(struct sge_txq * txq,u_int avail,struct fw_eth_tx_pkt_wr * wr)3085 set_txupdate_flags(struct sge_txq *txq, u_int avail,
3086 struct fw_eth_tx_pkt_wr *wr)
3087 {
3088 struct sge_eq *eq = &txq->eq;
3089 struct txpkts *txp = &txq->txp;
3090
3091 if ((txp->npkt > 0 || avail < eq->sidx / 2) &&
3092 atomic_cmpset_int(&eq->equiq, 0, 1)) {
3093 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ | F_FW_WR_EQUIQ);
3094 eq->equeqidx = eq->pidx;
3095 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
3096 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
3097 eq->equeqidx = eq->pidx;
3098 }
3099 }
3100
3101 #if defined(__i386__) || defined(__amd64__)
3102 extern uint64_t tsc_freq;
3103 #endif
3104
3105 static inline bool
record_eth_tx_time(struct sge_txq * txq)3106 record_eth_tx_time(struct sge_txq *txq)
3107 {
3108 const uint64_t cycles = get_cyclecount();
3109 const uint64_t last_tx = txq->last_tx;
3110 #if defined(__i386__) || defined(__amd64__)
3111 const uint64_t itg = tsc_freq * t4_tx_coalesce_gap / 1000000;
3112 #else
3113 const uint64_t itg = 0;
3114 #endif
3115
3116 MPASS(cycles >= last_tx);
3117 txq->last_tx = cycles;
3118 return (cycles - last_tx < itg);
3119 }
3120
3121 /*
3122 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
3123 * be consumed. Return the actual number consumed. 0 indicates a stall.
3124 */
3125 static u_int
eth_tx(struct mp_ring * r,u_int cidx,u_int pidx,bool * coalescing)3126 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx, bool *coalescing)
3127 {
3128 struct sge_txq *txq = r->cookie;
3129 if_t ifp = txq->ifp;
3130 struct sge_eq *eq = &txq->eq;
3131 struct txpkts *txp = &txq->txp;
3132 struct vi_info *vi = if_getsoftc(ifp);
3133 struct adapter *sc = vi->adapter;
3134 u_int total, remaining; /* # of packets */
3135 u_int n, avail, dbdiff; /* # of hardware descriptors */
3136 int i, rc;
3137 struct mbuf *m0;
3138 bool snd, recent_tx;
3139 void *wr; /* start of the last WR written to the ring */
3140
3141 TXQ_LOCK_ASSERT_OWNED(txq);
3142 recent_tx = record_eth_tx_time(txq);
3143
3144 remaining = IDXDIFF(pidx, cidx, r->size);
3145 if (__predict_false(discard_tx(eq))) {
3146 for (i = 0; i < txp->npkt; i++)
3147 m_freem(txp->mb[i]);
3148 txp->npkt = 0;
3149 while (cidx != pidx) {
3150 m0 = r->items[cidx];
3151 m_freem(m0);
3152 if (++cidx == r->size)
3153 cidx = 0;
3154 }
3155 reclaim_tx_descs(txq, eq->sidx);
3156 *coalescing = false;
3157 return (remaining); /* emptied */
3158 }
3159
3160 /* How many hardware descriptors do we have readily available. */
3161 if (eq->pidx == eq->cidx)
3162 avail = eq->sidx - 1;
3163 else
3164 avail = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
3165
3166 total = 0;
3167 if (remaining == 0) {
3168 txp->score = 0;
3169 txq->txpkts_flush++;
3170 goto send_txpkts;
3171 }
3172
3173 dbdiff = 0;
3174 MPASS(remaining > 0);
3175 while (remaining > 0) {
3176 m0 = r->items[cidx];
3177 M_ASSERTPKTHDR(m0);
3178 MPASS(m0->m_nextpkt == NULL);
3179
3180 if (avail < 2 * SGE_MAX_WR_NDESC)
3181 avail += reclaim_tx_descs(txq, 64);
3182
3183 if (t4_tx_coalesce == 0 && txp->npkt == 0)
3184 goto skip_coalescing;
3185 if (cannot_use_txpkts(m0))
3186 txp->score = 0;
3187 else if (recent_tx) {
3188 if (++txp->score == 0)
3189 txp->score = UINT8_MAX;
3190 } else
3191 txp->score = 1;
3192 if (txp->npkt > 0 || remaining > 1 ||
3193 txp->score >= t4_tx_coalesce_pkts ||
3194 atomic_load_int(&txq->eq.equiq) != 0) {
3195 if (vi->flags & TX_USES_VM_WR)
3196 rc = add_to_txpkts_vf(sc, txq, m0, avail, &snd);
3197 else
3198 rc = add_to_txpkts_pf(sc, txq, m0, avail, &snd);
3199 } else {
3200 snd = false;
3201 rc = EINVAL;
3202 }
3203 if (snd) {
3204 MPASS(txp->npkt > 0);
3205 for (i = 0; i < txp->npkt; i++)
3206 ETHER_BPF_MTAP(ifp, txp->mb[i]);
3207 if (txp->npkt > 1) {
3208 MPASS(avail >= tx_len16_to_desc(txp->len16));
3209 if (vi->flags & TX_USES_VM_WR)
3210 n = write_txpkts_vm_wr(sc, txq);
3211 else
3212 n = write_txpkts_wr(sc, txq);
3213 } else {
3214 MPASS(avail >=
3215 tx_len16_to_desc(mbuf_len16(txp->mb[0])));
3216 if (vi->flags & TX_USES_VM_WR)
3217 n = write_txpkt_vm_wr(sc, txq,
3218 txp->mb[0]);
3219 else
3220 n = write_txpkt_wr(sc, txq, txp->mb[0],
3221 avail);
3222 }
3223 MPASS(n <= SGE_MAX_WR_NDESC);
3224 avail -= n;
3225 dbdiff += n;
3226 wr = &eq->desc[eq->pidx];
3227 IDXINCR(eq->pidx, n, eq->sidx);
3228 txp->npkt = 0; /* emptied */
3229 }
3230 if (rc == 0) {
3231 /* m0 was coalesced into txq->txpkts. */
3232 goto next_mbuf;
3233 }
3234 if (rc == EAGAIN) {
3235 /*
3236 * m0 is suitable for tx coalescing but could not be
3237 * combined with the existing txq->txpkts, which has now
3238 * been transmitted. Start a new txpkts with m0.
3239 */
3240 MPASS(snd);
3241 MPASS(txp->npkt == 0);
3242 continue;
3243 }
3244
3245 MPASS(rc != 0 && rc != EAGAIN);
3246 MPASS(txp->npkt == 0);
3247 skip_coalescing:
3248 n = tx_len16_to_desc(mbuf_len16(m0));
3249 if (__predict_false(avail < n)) {
3250 avail += reclaim_tx_descs(txq, min(n, 32));
3251 if (avail < n)
3252 break; /* out of descriptors */
3253 }
3254
3255 wr = &eq->desc[eq->pidx];
3256 if (mbuf_cflags(m0) & MC_RAW_WR) {
3257 n = write_raw_wr(txq, wr, m0, avail);
3258 #ifdef KERN_TLS
3259 } else if (mbuf_cflags(m0) & MC_TLS) {
3260 ETHER_BPF_MTAP(ifp, m0);
3261 n = t6_ktls_write_wr(txq, wr, m0, avail);
3262 #endif
3263 } else {
3264 ETHER_BPF_MTAP(ifp, m0);
3265 if (vi->flags & TX_USES_VM_WR)
3266 n = write_txpkt_vm_wr(sc, txq, m0);
3267 else
3268 n = write_txpkt_wr(sc, txq, m0, avail);
3269 }
3270 MPASS(n >= 1 && n <= avail);
3271 if (!(mbuf_cflags(m0) & MC_TLS))
3272 MPASS(n <= SGE_MAX_WR_NDESC);
3273
3274 avail -= n;
3275 dbdiff += n;
3276 IDXINCR(eq->pidx, n, eq->sidx);
3277
3278 if (dbdiff >= 512 / EQ_ESIZE) { /* X_FETCHBURSTMAX_512B */
3279 if (wr_can_update_eq(wr))
3280 set_txupdate_flags(txq, avail, wr);
3281 ring_eq_db(sc, eq, dbdiff);
3282 avail += reclaim_tx_descs(txq, 32);
3283 dbdiff = 0;
3284 }
3285 next_mbuf:
3286 total++;
3287 remaining--;
3288 if (__predict_false(++cidx == r->size))
3289 cidx = 0;
3290 }
3291 if (dbdiff != 0) {
3292 if (wr_can_update_eq(wr))
3293 set_txupdate_flags(txq, avail, wr);
3294 ring_eq_db(sc, eq, dbdiff);
3295 reclaim_tx_descs(txq, 32);
3296 } else if (eq->pidx == eq->cidx && txp->npkt > 0 &&
3297 atomic_load_int(&txq->eq.equiq) == 0) {
3298 /*
3299 * If nothing was submitted to the chip for tx (it was coalesced
3300 * into txpkts instead) and there is no tx update outstanding
3301 * then we need to send txpkts now.
3302 */
3303 send_txpkts:
3304 MPASS(txp->npkt > 0);
3305 for (i = 0; i < txp->npkt; i++)
3306 ETHER_BPF_MTAP(ifp, txp->mb[i]);
3307 if (txp->npkt > 1) {
3308 MPASS(avail >= tx_len16_to_desc(txp->len16));
3309 if (vi->flags & TX_USES_VM_WR)
3310 n = write_txpkts_vm_wr(sc, txq);
3311 else
3312 n = write_txpkts_wr(sc, txq);
3313 } else {
3314 MPASS(avail >=
3315 tx_len16_to_desc(mbuf_len16(txp->mb[0])));
3316 if (vi->flags & TX_USES_VM_WR)
3317 n = write_txpkt_vm_wr(sc, txq, txp->mb[0]);
3318 else
3319 n = write_txpkt_wr(sc, txq, txp->mb[0], avail);
3320 }
3321 MPASS(n <= SGE_MAX_WR_NDESC);
3322 wr = &eq->desc[eq->pidx];
3323 IDXINCR(eq->pidx, n, eq->sidx);
3324 txp->npkt = 0; /* emptied */
3325
3326 MPASS(wr_can_update_eq(wr));
3327 set_txupdate_flags(txq, avail - n, wr);
3328 ring_eq_db(sc, eq, n);
3329 reclaim_tx_descs(txq, 32);
3330 }
3331 *coalescing = txp->npkt > 0;
3332
3333 return (total);
3334 }
3335
3336 static inline void
init_iq(struct sge_iq * iq,struct adapter * sc,int tmr_idx,int pktc_idx,int qsize,int intr_idx,int cong,int qtype)3337 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
3338 int qsize, int intr_idx, int cong, int qtype)
3339 {
3340
3341 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
3342 ("%s: bad tmr_idx %d", __func__, tmr_idx));
3343 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
3344 ("%s: bad pktc_idx %d", __func__, pktc_idx));
3345 KASSERT(intr_idx >= -1 && intr_idx < sc->intr_count,
3346 ("%s: bad intr_idx %d", __func__, intr_idx));
3347 KASSERT(qtype == FW_IQ_IQTYPE_OTHER || qtype == FW_IQ_IQTYPE_NIC ||
3348 qtype == FW_IQ_IQTYPE_OFLD, ("%s: bad qtype %d", __func__, qtype));
3349
3350 iq->flags = 0;
3351 iq->state = IQS_DISABLED;
3352 iq->adapter = sc;
3353 iq->qtype = qtype;
3354 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
3355 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
3356 if (pktc_idx >= 0) {
3357 iq->intr_params |= F_QINTR_CNT_EN;
3358 iq->intr_pktc_idx = pktc_idx;
3359 }
3360 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
3361 iq->sidx = iq->qsize - sc->params.sge.spg_len / IQ_ESIZE;
3362 iq->intr_idx = intr_idx;
3363 iq->cong_drop = cong;
3364 }
3365
3366 static inline void
init_fl(struct adapter * sc,struct sge_fl * fl,int qsize,int maxp,char * name)3367 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
3368 {
3369 struct sge_params *sp = &sc->params.sge;
3370
3371 fl->qsize = qsize;
3372 fl->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
3373 strlcpy(fl->lockname, name, sizeof(fl->lockname));
3374 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
3375 if (sc->flags & BUF_PACKING_OK &&
3376 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
3377 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
3378 fl->flags |= FL_BUF_PACKING;
3379 fl->zidx = find_refill_source(sc, maxp, fl->flags & FL_BUF_PACKING);
3380 fl->safe_zidx = sc->sge.safe_zidx;
3381 if (fl->flags & FL_BUF_PACKING) {
3382 fl->lowat = roundup2(sp->fl_starve_threshold2, 8);
3383 fl->buf_boundary = sp->pack_boundary;
3384 } else {
3385 fl->lowat = roundup2(sp->fl_starve_threshold, 8);
3386 fl->buf_boundary = 16;
3387 }
3388 if (fl_pad && fl->buf_boundary < sp->pad_boundary)
3389 fl->buf_boundary = sp->pad_boundary;
3390 }
3391
3392 static inline void
init_eq(struct adapter * sc,struct sge_eq * eq,int eqtype,int qsize,uint8_t port_id,struct sge_iq * iq,char * name)3393 init_eq(struct adapter *sc, struct sge_eq *eq, int eqtype, int qsize,
3394 uint8_t port_id, struct sge_iq *iq, char *name)
3395 {
3396 KASSERT(eqtype >= EQ_CTRL && eqtype <= EQ_OFLD,
3397 ("%s: bad qtype %d", __func__, eqtype));
3398
3399 eq->type = eqtype;
3400 eq->port_id = port_id;
3401 eq->tx_chan = sc->port[port_id]->tx_chan;
3402 eq->iq = iq;
3403 eq->sidx = qsize - sc->params.sge.spg_len / EQ_ESIZE;
3404 strlcpy(eq->lockname, name, sizeof(eq->lockname));
3405 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
3406 }
3407
3408 int
alloc_ring(struct adapter * sc,size_t len,bus_dma_tag_t * tag,bus_dmamap_t * map,bus_addr_t * pa,void ** va)3409 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
3410 bus_dmamap_t *map, bus_addr_t *pa, void **va)
3411 {
3412 int rc;
3413
3414 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
3415 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
3416 if (rc != 0) {
3417 CH_ERR(sc, "cannot allocate DMA tag: %d\n", rc);
3418 goto done;
3419 }
3420
3421 rc = bus_dmamem_alloc(*tag, va,
3422 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
3423 if (rc != 0) {
3424 CH_ERR(sc, "cannot allocate DMA memory: %d\n", rc);
3425 goto done;
3426 }
3427
3428 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
3429 if (rc != 0) {
3430 CH_ERR(sc, "cannot load DMA map: %d\n", rc);
3431 goto done;
3432 }
3433 done:
3434 if (rc)
3435 free_ring(sc, *tag, *map, *pa, *va);
3436
3437 return (rc);
3438 }
3439
3440 int
free_ring(struct adapter * sc,bus_dma_tag_t tag,bus_dmamap_t map,bus_addr_t pa,void * va)3441 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
3442 bus_addr_t pa, void *va)
3443 {
3444 if (pa)
3445 bus_dmamap_unload(tag, map);
3446 if (va)
3447 bus_dmamem_free(tag, va, map);
3448 if (tag)
3449 bus_dma_tag_destroy(tag);
3450
3451 return (0);
3452 }
3453
3454 /*
3455 * Allocates the software resources (mainly memory and sysctl nodes) for an
3456 * ingress queue and an optional freelist.
3457 *
3458 * Sets IQ_SW_ALLOCATED and returns 0 on success.
3459 */
3460 static int
alloc_iq_fl(struct vi_info * vi,struct sge_iq * iq,struct sge_fl * fl,struct sysctl_ctx_list * ctx,struct sysctl_oid * oid)3461 alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
3462 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid)
3463 {
3464 int rc;
3465 size_t len;
3466 struct adapter *sc = vi->adapter;
3467
3468 MPASS(!(iq->flags & IQ_SW_ALLOCATED));
3469
3470 len = iq->qsize * IQ_ESIZE;
3471 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
3472 (void **)&iq->desc);
3473 if (rc != 0)
3474 return (rc);
3475
3476 if (fl) {
3477 len = fl->qsize * EQ_ESIZE;
3478 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
3479 &fl->ba, (void **)&fl->desc);
3480 if (rc) {
3481 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba,
3482 iq->desc);
3483 return (rc);
3484 }
3485
3486 /* Allocate space for one software descriptor per buffer. */
3487 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc),
3488 M_CXGBE, M_ZERO | M_WAITOK);
3489
3490 add_fl_sysctls(sc, ctx, oid, fl);
3491 iq->flags |= IQ_HAS_FL;
3492 }
3493 add_iq_sysctls(ctx, oid, iq);
3494 iq->flags |= IQ_SW_ALLOCATED;
3495
3496 return (0);
3497 }
3498
3499 /*
3500 * Frees all software resources (memory and locks) associated with an ingress
3501 * queue and an optional freelist.
3502 */
3503 static void
free_iq_fl(struct adapter * sc,struct sge_iq * iq,struct sge_fl * fl)3504 free_iq_fl(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl)
3505 {
3506 MPASS(iq->flags & IQ_SW_ALLOCATED);
3507
3508 if (fl) {
3509 MPASS(iq->flags & IQ_HAS_FL);
3510 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba, fl->desc);
3511 free_fl_buffers(sc, fl);
3512 free(fl->sdesc, M_CXGBE);
3513 mtx_destroy(&fl->fl_lock);
3514 bzero(fl, sizeof(*fl));
3515 }
3516 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
3517 bzero(iq, sizeof(*iq));
3518 }
3519
3520 /*
3521 * Allocates a hardware ingress queue and an optional freelist that will be
3522 * associated with it.
3523 *
3524 * Returns errno on failure. Resources allocated up to that point may still be
3525 * allocated. Caller is responsible for cleanup in case this function fails.
3526 */
3527 static int
alloc_iq_fl_hwq(struct vi_info * vi,struct sge_iq * iq,struct sge_fl * fl)3528 alloc_iq_fl_hwq(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl)
3529 {
3530 int rc, cntxt_id, cong_map;
3531 struct fw_iq_cmd c;
3532 struct adapter *sc = vi->adapter;
3533 struct port_info *pi = vi->pi;
3534 __be32 v = 0;
3535
3536 MPASS (!(iq->flags & IQ_HW_ALLOCATED));
3537
3538 bzero(&c, sizeof(c));
3539 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
3540 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
3541 V_FW_IQ_CMD_VFN(0));
3542
3543 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
3544 FW_LEN16(c));
3545
3546 /* Special handling for firmware event queue */
3547 if (iq == &sc->sge.fwq)
3548 v |= F_FW_IQ_CMD_IQASYNCH;
3549
3550 if (iq->intr_idx < 0) {
3551 /* Forwarded interrupts, all headed to fwq */
3552 v |= F_FW_IQ_CMD_IQANDST;
3553 v |= V_FW_IQ_CMD_IQANDSTINDEX(sc->sge.fwq.cntxt_id);
3554 } else {
3555 KASSERT(iq->intr_idx < sc->intr_count,
3556 ("%s: invalid direct intr_idx %d", __func__, iq->intr_idx));
3557 v |= V_FW_IQ_CMD_IQANDSTINDEX(iq->intr_idx);
3558 }
3559
3560 bzero(iq->desc, iq->qsize * IQ_ESIZE);
3561 c.type_to_iqandstindex = htobe32(v |
3562 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
3563 V_FW_IQ_CMD_VIID(vi->viid) |
3564 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
3565 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
3566 F_FW_IQ_CMD_IQGTSMODE |
3567 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
3568 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
3569 c.iqsize = htobe16(iq->qsize);
3570 c.iqaddr = htobe64(iq->ba);
3571 c.iqns_to_fl0congen = htobe32(V_FW_IQ_CMD_IQTYPE(iq->qtype));
3572 if (iq->cong_drop != -1) {
3573 cong_map = iq->qtype == IQ_ETH ? pi->rx_e_chan_map : 0;
3574 c.iqns_to_fl0congen |= htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
3575 }
3576
3577 if (fl) {
3578 bzero(fl->desc, fl->sidx * EQ_ESIZE + sc->params.sge.spg_len);
3579 c.iqns_to_fl0congen |=
3580 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
3581 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
3582 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
3583 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
3584 0));
3585 if (iq->cong_drop != -1) {
3586 c.iqns_to_fl0congen |=
3587 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong_map) |
3588 F_FW_IQ_CMD_FL0CONGCIF |
3589 F_FW_IQ_CMD_FL0CONGEN);
3590 }
3591 c.fl0dcaen_to_fl0cidxfthresh =
3592 htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
3593 X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B_T6) |
3594 V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
3595 X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
3596 c.fl0size = htobe16(fl->qsize);
3597 c.fl0addr = htobe64(fl->ba);
3598 }
3599
3600 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3601 if (rc != 0) {
3602 CH_ERR(sc, "failed to create hw ingress queue: %d\n", rc);
3603 return (rc);
3604 }
3605
3606 iq->cidx = 0;
3607 iq->gen = F_RSPD_GEN;
3608 iq->cntxt_id = be16toh(c.iqid);
3609 iq->abs_id = be16toh(c.physiqid);
3610
3611 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
3612 if (cntxt_id >= sc->sge.iqmap_sz) {
3613 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
3614 cntxt_id, sc->sge.iqmap_sz - 1);
3615 }
3616 sc->sge.iqmap[cntxt_id] = iq;
3617
3618 if (fl) {
3619 u_int qid;
3620 #ifdef INVARIANTS
3621 int i;
3622
3623 MPASS(!(fl->flags & FL_BUF_RESUME));
3624 for (i = 0; i < fl->sidx * 8; i++)
3625 MPASS(fl->sdesc[i].cl == NULL);
3626 #endif
3627 fl->cntxt_id = be16toh(c.fl0id);
3628 fl->pidx = fl->cidx = fl->hw_cidx = fl->dbidx = 0;
3629 fl->rx_offset = 0;
3630 fl->flags &= ~(FL_STARVING | FL_DOOMED);
3631
3632 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
3633 if (cntxt_id >= sc->sge.eqmap_sz) {
3634 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
3635 __func__, cntxt_id, sc->sge.eqmap_sz - 1);
3636 }
3637 sc->sge.eqmap[cntxt_id] = (void *)fl;
3638
3639 qid = fl->cntxt_id;
3640 if (isset(&sc->doorbells, DOORBELL_UDB)) {
3641 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
3642 uint32_t mask = (1 << s_qpp) - 1;
3643 volatile uint8_t *udb;
3644
3645 udb = sc->udbs_base + UDBS_DB_OFFSET;
3646 udb += (qid >> s_qpp) << PAGE_SHIFT;
3647 qid &= mask;
3648 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
3649 udb += qid << UDBS_SEG_SHIFT;
3650 qid = 0;
3651 }
3652 fl->udb = (volatile void *)udb;
3653 }
3654 fl->dbval = V_QID(qid) | sc->chip_params->sge_fl_db;
3655
3656 FL_LOCK(fl);
3657 /* Enough to make sure the SGE doesn't think it's starved */
3658 refill_fl(sc, fl, fl->lowat);
3659 FL_UNLOCK(fl);
3660 }
3661
3662 if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) &&
3663 iq->cong_drop != -1) {
3664 t4_sge_set_conm_context(sc, iq->cntxt_id, iq->cong_drop,
3665 cong_map);
3666 }
3667
3668 /* Enable IQ interrupts */
3669 atomic_store_rel_int(&iq->state, IQS_IDLE);
3670 t4_write_reg(sc, sc->sge_gts_reg, V_SEINTARM(iq->intr_params) |
3671 V_INGRESSQID(iq->cntxt_id));
3672
3673 iq->flags |= IQ_HW_ALLOCATED;
3674
3675 return (0);
3676 }
3677
3678 static int
free_iq_fl_hwq(struct adapter * sc,struct sge_iq * iq,struct sge_fl * fl)3679 free_iq_fl_hwq(struct adapter *sc, struct sge_iq *iq, struct sge_fl *fl)
3680 {
3681 int rc;
3682
3683 MPASS(iq->flags & IQ_HW_ALLOCATED);
3684 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
3685 iq->cntxt_id, fl ? fl->cntxt_id : 0xffff, 0xffff);
3686 if (rc != 0) {
3687 CH_ERR(sc, "failed to free iq %p: %d\n", iq, rc);
3688 return (rc);
3689 }
3690 iq->flags &= ~IQ_HW_ALLOCATED;
3691
3692 return (0);
3693 }
3694
3695 static void
add_iq_sysctls(struct sysctl_ctx_list * ctx,struct sysctl_oid * oid,struct sge_iq * iq)3696 add_iq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
3697 struct sge_iq *iq)
3698 {
3699 struct sysctl_oid_list *children;
3700
3701 if (ctx == NULL || oid == NULL)
3702 return;
3703
3704 children = SYSCTL_CHILDREN(oid);
3705 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &iq->ba,
3706 "bus address of descriptor ring");
3707 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3708 iq->qsize * IQ_ESIZE, "descriptor ring size in bytes");
3709 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
3710 &iq->abs_id, 0, "absolute id of the queue");
3711 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3712 &iq->cntxt_id, 0, "SGE context id of the queue");
3713 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &iq->cidx,
3714 0, "consumer index");
3715 }
3716
3717 static void
add_fl_sysctls(struct adapter * sc,struct sysctl_ctx_list * ctx,struct sysctl_oid * oid,struct sge_fl * fl)3718 add_fl_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
3719 struct sysctl_oid *oid, struct sge_fl *fl)
3720 {
3721 struct sysctl_oid_list *children;
3722
3723 if (ctx == NULL || oid == NULL)
3724 return;
3725
3726 children = SYSCTL_CHILDREN(oid);
3727 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl",
3728 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "freelist");
3729 children = SYSCTL_CHILDREN(oid);
3730
3731 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD,
3732 &fl->ba, "bus address of descriptor ring");
3733 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
3734 fl->sidx * EQ_ESIZE + sc->params.sge.spg_len,
3735 "desc ring size in bytes");
3736 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3737 &fl->cntxt_id, 0, "SGE context id of the freelist");
3738 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
3739 fl_pad ? 1 : 0, "padding enabled");
3740 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
3741 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
3742 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
3743 0, "consumer index");
3744 if (fl->flags & FL_BUF_PACKING) {
3745 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
3746 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
3747 }
3748 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
3749 0, "producer index");
3750 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
3751 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
3752 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
3753 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
3754 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
3755 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
3756 }
3757
3758 /*
3759 * Idempotent.
3760 */
3761 static int
alloc_fwq(struct adapter * sc)3762 alloc_fwq(struct adapter *sc)
3763 {
3764 int rc, intr_idx;
3765 struct sge_iq *fwq = &sc->sge.fwq;
3766 struct vi_info *vi = &sc->port[0]->vi[0];
3767
3768 if (!(fwq->flags & IQ_SW_ALLOCATED)) {
3769 MPASS(!(fwq->flags & IQ_HW_ALLOCATED));
3770
3771 if (sc->flags & IS_VF)
3772 intr_idx = 0;
3773 else
3774 intr_idx = sc->intr_count > 1 ? 1 : 0;
3775 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE, intr_idx, -1, IQ_OTHER);
3776 rc = alloc_iq_fl(vi, fwq, NULL, &sc->ctx, sc->fwq_oid);
3777 if (rc != 0) {
3778 CH_ERR(sc, "failed to allocate fwq: %d\n", rc);
3779 return (rc);
3780 }
3781 MPASS(fwq->flags & IQ_SW_ALLOCATED);
3782 }
3783
3784 if (!(fwq->flags & IQ_HW_ALLOCATED)) {
3785 MPASS(fwq->flags & IQ_SW_ALLOCATED);
3786
3787 rc = alloc_iq_fl_hwq(vi, fwq, NULL);
3788 if (rc != 0) {
3789 CH_ERR(sc, "failed to create hw fwq: %d\n", rc);
3790 return (rc);
3791 }
3792 MPASS(fwq->flags & IQ_HW_ALLOCATED);
3793 }
3794
3795 return (0);
3796 }
3797
3798 /*
3799 * Idempotent.
3800 */
3801 static void
free_fwq(struct adapter * sc)3802 free_fwq(struct adapter *sc)
3803 {
3804 struct sge_iq *fwq = &sc->sge.fwq;
3805
3806 if (fwq->flags & IQ_HW_ALLOCATED) {
3807 MPASS(fwq->flags & IQ_SW_ALLOCATED);
3808 free_iq_fl_hwq(sc, fwq, NULL);
3809 MPASS(!(fwq->flags & IQ_HW_ALLOCATED));
3810 }
3811
3812 if (fwq->flags & IQ_SW_ALLOCATED) {
3813 MPASS(!(fwq->flags & IQ_HW_ALLOCATED));
3814 free_iq_fl(sc, fwq, NULL);
3815 MPASS(!(fwq->flags & IQ_SW_ALLOCATED));
3816 }
3817 }
3818
3819 /*
3820 * Idempotent.
3821 */
3822 static int
alloc_ctrlq(struct adapter * sc,int idx)3823 alloc_ctrlq(struct adapter *sc, int idx)
3824 {
3825 int rc;
3826 char name[16];
3827 struct sysctl_oid *oid;
3828 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx];
3829
3830 MPASS(idx < sc->params.nports);
3831
3832 if (!(ctrlq->eq.flags & EQ_SW_ALLOCATED)) {
3833 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED));
3834
3835 snprintf(name, sizeof(name), "%d", idx);
3836 oid = SYSCTL_ADD_NODE(&sc->ctx, SYSCTL_CHILDREN(sc->ctrlq_oid),
3837 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
3838 "ctrl queue");
3839
3840 snprintf(name, sizeof(name), "%s ctrlq%d",
3841 device_get_nameunit(sc->dev), idx);
3842 init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, idx,
3843 &sc->sge.fwq, name);
3844 rc = alloc_wrq(sc, NULL, ctrlq, &sc->ctx, oid);
3845 if (rc != 0) {
3846 CH_ERR(sc, "failed to allocate ctrlq%d: %d\n", idx, rc);
3847 sysctl_remove_oid(oid, 1, 1);
3848 return (rc);
3849 }
3850 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED);
3851 }
3852
3853 if (!(ctrlq->eq.flags & EQ_HW_ALLOCATED)) {
3854 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED);
3855
3856 rc = alloc_eq_hwq(sc, NULL, &ctrlq->eq);
3857 if (rc != 0) {
3858 CH_ERR(sc, "failed to create hw ctrlq%d: %d\n", idx, rc);
3859 return (rc);
3860 }
3861 MPASS(ctrlq->eq.flags & EQ_HW_ALLOCATED);
3862 }
3863
3864 return (0);
3865 }
3866
3867 /*
3868 * Idempotent.
3869 */
3870 static void
free_ctrlq(struct adapter * sc,int idx)3871 free_ctrlq(struct adapter *sc, int idx)
3872 {
3873 struct sge_wrq *ctrlq = &sc->sge.ctrlq[idx];
3874
3875 if (ctrlq->eq.flags & EQ_HW_ALLOCATED) {
3876 MPASS(ctrlq->eq.flags & EQ_SW_ALLOCATED);
3877 free_eq_hwq(sc, NULL, &ctrlq->eq);
3878 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED));
3879 }
3880
3881 if (ctrlq->eq.flags & EQ_SW_ALLOCATED) {
3882 MPASS(!(ctrlq->eq.flags & EQ_HW_ALLOCATED));
3883 free_wrq(sc, ctrlq);
3884 MPASS(!(ctrlq->eq.flags & EQ_SW_ALLOCATED));
3885 }
3886 }
3887
3888 int
t4_sge_set_conm_context(struct adapter * sc,int cntxt_id,int cong_drop,int cong_map)3889 t4_sge_set_conm_context(struct adapter *sc, int cntxt_id, int cong_drop,
3890 int cong_map)
3891 {
3892 const int cng_ch_bits_log = sc->chip_params->cng_ch_bits_log;
3893 uint32_t param, val;
3894 uint16_t ch_map;
3895 int cong_mode, rc, i;
3896
3897 if (chip_id(sc) < CHELSIO_T5)
3898 return (ENOTSUP);
3899
3900 /* Convert the driver knob to the mode understood by the firmware. */
3901 switch (cong_drop) {
3902 case -1:
3903 cong_mode = X_CONMCTXT_CNGTPMODE_DISABLE;
3904 break;
3905 case 0:
3906 cong_mode = X_CONMCTXT_CNGTPMODE_CHANNEL;
3907 break;
3908 case 1:
3909 cong_mode = X_CONMCTXT_CNGTPMODE_QUEUE;
3910 break;
3911 case 2:
3912 cong_mode = X_CONMCTXT_CNGTPMODE_BOTH;
3913 break;
3914 default:
3915 MPASS(0);
3916 CH_ERR(sc, "cong_drop = %d is invalid (ingress queue %d).\n",
3917 cong_drop, cntxt_id);
3918 return (EINVAL);
3919 }
3920
3921 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
3922 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
3923 V_FW_PARAMS_PARAM_YZ(cntxt_id);
3924 val = V_CONMCTXT_CNGTPMODE(cong_mode);
3925 if (cong_mode == X_CONMCTXT_CNGTPMODE_CHANNEL ||
3926 cong_mode == X_CONMCTXT_CNGTPMODE_BOTH) {
3927 for (i = 0, ch_map = 0; i < 4; i++) {
3928 if (cong_map & (1 << i))
3929 ch_map |= 1 << (i << cng_ch_bits_log);
3930 }
3931 val |= V_CONMCTXT_CNGCHMAP(ch_map);
3932 }
3933 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3934 if (rc != 0) {
3935 CH_ERR(sc, "failed to set congestion manager context "
3936 "for ingress queue %d: %d\n", cntxt_id, rc);
3937 }
3938
3939 return (rc);
3940 }
3941
3942 /*
3943 * Idempotent.
3944 */
3945 static int
alloc_rxq(struct vi_info * vi,struct sge_rxq * rxq,int idx,int intr_idx,int maxp)3946 alloc_rxq(struct vi_info *vi, struct sge_rxq *rxq, int idx, int intr_idx,
3947 int maxp)
3948 {
3949 int rc;
3950 struct adapter *sc = vi->adapter;
3951 if_t ifp = vi->ifp;
3952 struct sysctl_oid *oid;
3953 char name[16];
3954
3955 if (!(rxq->iq.flags & IQ_SW_ALLOCATED)) {
3956 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED));
3957 #if defined(INET) || defined(INET6)
3958 rc = tcp_lro_init_args(&rxq->lro, ifp, lro_entries, lro_mbufs);
3959 if (rc != 0)
3960 return (rc);
3961 MPASS(rxq->lro.ifp == ifp); /* also indicates LRO init'ed */
3962 #endif
3963 rxq->ifp = ifp;
3964
3965 snprintf(name, sizeof(name), "%d", idx);
3966 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->rxq_oid),
3967 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
3968 "rx queue");
3969
3970 init_iq(&rxq->iq, sc, vi->tmr_idx, vi->pktc_idx, vi->qsize_rxq,
3971 intr_idx, cong_drop, IQ_ETH);
3972 #if defined(INET) || defined(INET6)
3973 if (if_getcapenable(ifp) & IFCAP_LRO)
3974 rxq->iq.flags |= IQ_LRO_ENABLED;
3975 #endif
3976 if (if_getcapenable(ifp) & IFCAP_HWRXTSTMP)
3977 rxq->iq.flags |= IQ_RX_TIMESTAMP;
3978 snprintf(name, sizeof(name), "%s rxq%d-fl",
3979 device_get_nameunit(vi->dev), idx);
3980 init_fl(sc, &rxq->fl, vi->qsize_rxq / 8, maxp, name);
3981 rc = alloc_iq_fl(vi, &rxq->iq, &rxq->fl, &vi->ctx, oid);
3982 if (rc != 0) {
3983 CH_ERR(vi, "failed to allocate rxq%d: %d\n", idx, rc);
3984 sysctl_remove_oid(oid, 1, 1);
3985 #if defined(INET) || defined(INET6)
3986 tcp_lro_free(&rxq->lro);
3987 rxq->lro.ifp = NULL;
3988 #endif
3989 return (rc);
3990 }
3991 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED);
3992 add_rxq_sysctls(&vi->ctx, oid, rxq);
3993 }
3994
3995 if (!(rxq->iq.flags & IQ_HW_ALLOCATED)) {
3996 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED);
3997 rc = alloc_iq_fl_hwq(vi, &rxq->iq, &rxq->fl);
3998 if (rc != 0) {
3999 CH_ERR(vi, "failed to create hw rxq%d: %d\n", idx, rc);
4000 return (rc);
4001 }
4002 MPASS(rxq->iq.flags & IQ_HW_ALLOCATED);
4003
4004 if (idx == 0)
4005 sc->sge.iq_base = rxq->iq.abs_id - rxq->iq.cntxt_id;
4006 else
4007 KASSERT(rxq->iq.cntxt_id + sc->sge.iq_base == rxq->iq.abs_id,
4008 ("iq_base mismatch"));
4009 KASSERT(sc->sge.iq_base == 0 || sc->flags & IS_VF,
4010 ("PF with non-zero iq_base"));
4011
4012 /*
4013 * The freelist is just barely above the starvation threshold
4014 * right now, fill it up a bit more.
4015 */
4016 FL_LOCK(&rxq->fl);
4017 refill_fl(sc, &rxq->fl, 128);
4018 FL_UNLOCK(&rxq->fl);
4019 }
4020
4021 return (0);
4022 }
4023
4024 /*
4025 * Idempotent.
4026 */
4027 static void
free_rxq(struct vi_info * vi,struct sge_rxq * rxq)4028 free_rxq(struct vi_info *vi, struct sge_rxq *rxq)
4029 {
4030 if (rxq->iq.flags & IQ_HW_ALLOCATED) {
4031 MPASS(rxq->iq.flags & IQ_SW_ALLOCATED);
4032 free_iq_fl_hwq(vi->adapter, &rxq->iq, &rxq->fl);
4033 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED));
4034 }
4035
4036 if (rxq->iq.flags & IQ_SW_ALLOCATED) {
4037 MPASS(!(rxq->iq.flags & IQ_HW_ALLOCATED));
4038 #if defined(INET) || defined(INET6)
4039 tcp_lro_free(&rxq->lro);
4040 #endif
4041 free_iq_fl(vi->adapter, &rxq->iq, &rxq->fl);
4042 MPASS(!(rxq->iq.flags & IQ_SW_ALLOCATED));
4043 bzero(rxq, sizeof(*rxq));
4044 }
4045 }
4046
4047 static void
add_rxq_sysctls(struct sysctl_ctx_list * ctx,struct sysctl_oid * oid,struct sge_rxq * rxq)4048 add_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
4049 struct sge_rxq *rxq)
4050 {
4051 struct sysctl_oid_list *children;
4052
4053 if (ctx == NULL || oid == NULL)
4054 return;
4055
4056 children = SYSCTL_CHILDREN(oid);
4057 #if defined(INET) || defined(INET6)
4058 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
4059 &rxq->lro.lro_queued, 0, NULL);
4060 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
4061 &rxq->lro.lro_flushed, 0, NULL);
4062 #endif
4063 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
4064 &rxq->rxcsum, "# of times hardware assisted with checksum");
4065 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_extraction", CTLFLAG_RD,
4066 &rxq->vlan_extraction, "# of times hardware extracted 802.1Q tag");
4067 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_rxcsum", CTLFLAG_RD,
4068 &rxq->vxlan_rxcsum,
4069 "# of times hardware assisted with inner checksum (VXLAN)");
4070 }
4071
4072 #ifdef TCP_OFFLOAD
4073 /*
4074 * Idempotent.
4075 */
4076 static int
alloc_ofld_rxq(struct vi_info * vi,struct sge_ofld_rxq * ofld_rxq,int idx,int intr_idx,int maxp)4077 alloc_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq, int idx,
4078 int intr_idx, int maxp)
4079 {
4080 int rc;
4081 struct adapter *sc = vi->adapter;
4082 struct sysctl_oid *oid;
4083 char name[16];
4084
4085 if (!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED)) {
4086 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED));
4087
4088 snprintf(name, sizeof(name), "%d", idx);
4089 oid = SYSCTL_ADD_NODE(&vi->ctx,
4090 SYSCTL_CHILDREN(vi->ofld_rxq_oid), OID_AUTO, name,
4091 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload rx queue");
4092
4093 init_iq(&ofld_rxq->iq, sc, vi->ofld_tmr_idx, vi->ofld_pktc_idx,
4094 vi->qsize_rxq, intr_idx, ofld_cong_drop, IQ_OFLD);
4095 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
4096 device_get_nameunit(vi->dev), idx);
4097 init_fl(sc, &ofld_rxq->fl, vi->qsize_rxq / 8, maxp, name);
4098 rc = alloc_iq_fl(vi, &ofld_rxq->iq, &ofld_rxq->fl, &vi->ctx,
4099 oid);
4100 if (rc != 0) {
4101 CH_ERR(vi, "failed to allocate ofld_rxq%d: %d\n", idx,
4102 rc);
4103 sysctl_remove_oid(oid, 1, 1);
4104 return (rc);
4105 }
4106 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED);
4107 ofld_rxq->rx_iscsi_ddp_setup_ok = counter_u64_alloc(M_WAITOK);
4108 ofld_rxq->rx_iscsi_ddp_setup_error =
4109 counter_u64_alloc(M_WAITOK);
4110 ofld_rxq->ddp_buffer_alloc = counter_u64_alloc(M_WAITOK);
4111 ofld_rxq->ddp_buffer_reuse = counter_u64_alloc(M_WAITOK);
4112 ofld_rxq->ddp_buffer_free = counter_u64_alloc(M_WAITOK);
4113 add_ofld_rxq_sysctls(&vi->ctx, oid, ofld_rxq);
4114 }
4115
4116 if (!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED)) {
4117 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED);
4118 rc = alloc_iq_fl_hwq(vi, &ofld_rxq->iq, &ofld_rxq->fl);
4119 if (rc != 0) {
4120 CH_ERR(vi, "failed to create hw ofld_rxq%d: %d\n", idx,
4121 rc);
4122 return (rc);
4123 }
4124 MPASS(ofld_rxq->iq.flags & IQ_HW_ALLOCATED);
4125 }
4126 return (rc);
4127 }
4128
4129 /*
4130 * Idempotent.
4131 */
4132 static void
free_ofld_rxq(struct vi_info * vi,struct sge_ofld_rxq * ofld_rxq)4133 free_ofld_rxq(struct vi_info *vi, struct sge_ofld_rxq *ofld_rxq)
4134 {
4135 if (ofld_rxq->iq.flags & IQ_HW_ALLOCATED) {
4136 MPASS(ofld_rxq->iq.flags & IQ_SW_ALLOCATED);
4137 free_iq_fl_hwq(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl);
4138 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED));
4139 }
4140
4141 if (ofld_rxq->iq.flags & IQ_SW_ALLOCATED) {
4142 MPASS(!(ofld_rxq->iq.flags & IQ_HW_ALLOCATED));
4143 free_iq_fl(vi->adapter, &ofld_rxq->iq, &ofld_rxq->fl);
4144 MPASS(!(ofld_rxq->iq.flags & IQ_SW_ALLOCATED));
4145 counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_ok);
4146 counter_u64_free(ofld_rxq->rx_iscsi_ddp_setup_error);
4147 counter_u64_free(ofld_rxq->ddp_buffer_alloc);
4148 counter_u64_free(ofld_rxq->ddp_buffer_reuse);
4149 counter_u64_free(ofld_rxq->ddp_buffer_free);
4150 bzero(ofld_rxq, sizeof(*ofld_rxq));
4151 }
4152 }
4153
4154 static void
add_ofld_rxq_sysctls(struct sysctl_ctx_list * ctx,struct sysctl_oid * oid,struct sge_ofld_rxq * ofld_rxq)4155 add_ofld_rxq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
4156 struct sge_ofld_rxq *ofld_rxq)
4157 {
4158 struct sysctl_oid_list *children;
4159
4160 if (ctx == NULL || oid == NULL)
4161 return;
4162
4163 children = SYSCTL_CHILDREN(oid);
4164 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "rx_aio_ddp_jobs",
4165 CTLFLAG_RD, &ofld_rxq->rx_aio_ddp_jobs, 0,
4166 "# of aio_read(2) jobs completed via DDP");
4167 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "rx_aio_ddp_octets",
4168 CTLFLAG_RD, &ofld_rxq->rx_aio_ddp_octets, 0,
4169 "# of octets placed directly for aio_read(2) jobs");
4170 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
4171 "rx_toe_tls_records", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_records,
4172 "# of TOE TLS records received");
4173 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
4174 "rx_toe_tls_octets", CTLFLAG_RD, &ofld_rxq->rx_toe_tls_octets,
4175 "# of payload octets in received TOE TLS records");
4176 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
4177 "rx_toe_ddp_octets", CTLFLAG_RD, &ofld_rxq->rx_toe_ddp_octets,
4178 "# of payload octets received via TCP DDP");
4179 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO,
4180 "ddp_buffer_alloc", CTLFLAG_RD, &ofld_rxq->ddp_buffer_alloc,
4181 "# of DDP RCV buffers allocated");
4182 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO,
4183 "ddp_buffer_reuse", CTLFLAG_RD, &ofld_rxq->ddp_buffer_reuse,
4184 "# of DDP RCV buffers reused");
4185 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO,
4186 "ddp_buffer_free", CTLFLAG_RD, &ofld_rxq->ddp_buffer_free,
4187 "# of DDP RCV buffers freed");
4188
4189 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "iscsi",
4190 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TOE iSCSI statistics");
4191 children = SYSCTL_CHILDREN(oid);
4192
4193 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_ok",
4194 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_ok,
4195 "# of times DDP buffer was setup successfully.");
4196 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "ddp_setup_error",
4197 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_setup_error,
4198 "# of times DDP buffer setup failed.");
4199 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_octets",
4200 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_octets, 0,
4201 "# of octets placed directly");
4202 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "ddp_pdus",
4203 CTLFLAG_RD, &ofld_rxq->rx_iscsi_ddp_pdus, 0,
4204 "# of PDUs with data placed directly.");
4205 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_octets",
4206 CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_octets, 0,
4207 "# of data octets delivered in freelist");
4208 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "fl_pdus",
4209 CTLFLAG_RD, &ofld_rxq->rx_iscsi_fl_pdus, 0,
4210 "# of PDUs with data delivered in freelist");
4211 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "padding_errors",
4212 CTLFLAG_RD, &ofld_rxq->rx_iscsi_padding_errors, 0,
4213 "# of PDUs with invalid padding");
4214 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "header_digest_errors",
4215 CTLFLAG_RD, &ofld_rxq->rx_iscsi_header_digest_errors, 0,
4216 "# of PDUs with invalid header digests");
4217 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "data_digest_errors",
4218 CTLFLAG_RD, &ofld_rxq->rx_iscsi_data_digest_errors, 0,
4219 "# of PDUs with invalid data digests");
4220 }
4221 #endif
4222
4223 /*
4224 * Returns a reasonable automatic cidx flush threshold for a given queue size.
4225 */
4226 static u_int
qsize_to_fthresh(int qsize)4227 qsize_to_fthresh(int qsize)
4228 {
4229 u_int fthresh;
4230
4231 fthresh = qsize == 0 ? 0 : order_base_2(qsize);
4232 if (fthresh > X_CIDXFLUSHTHRESH_128)
4233 fthresh = X_CIDXFLUSHTHRESH_128;
4234
4235 return (fthresh);
4236 }
4237
4238 static int
ctrl_eq_alloc(struct adapter * sc,struct sge_eq * eq)4239 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
4240 {
4241 int rc, cntxt_id;
4242 struct fw_eq_ctrl_cmd c;
4243 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4244
4245 bzero(&c, sizeof(c));
4246
4247 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
4248 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
4249 V_FW_EQ_CTRL_CMD_VFN(0));
4250 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
4251 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
4252 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
4253 c.physeqid_pkd = htobe32(0);
4254 c.fetchszm_to_iqid =
4255 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
4256 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
4257 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
4258 c.dcaen_to_eqsize =
4259 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
4260 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
4261 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
4262 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
4263 V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
4264 c.eqaddr = htobe64(eq->ba);
4265
4266 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
4267 if (rc != 0) {
4268 CH_ERR(sc, "failed to create hw ctrlq for tx_chan %d: %d\n",
4269 eq->tx_chan, rc);
4270 return (rc);
4271 }
4272
4273 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
4274 eq->abs_id = G_FW_EQ_CTRL_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
4275 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
4276 if (cntxt_id >= sc->sge.eqmap_sz)
4277 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
4278 cntxt_id, sc->sge.eqmap_sz - 1);
4279 sc->sge.eqmap[cntxt_id] = eq;
4280
4281 return (rc);
4282 }
4283
4284 static int
eth_eq_alloc(struct adapter * sc,struct vi_info * vi,struct sge_eq * eq)4285 eth_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
4286 {
4287 int rc, cntxt_id;
4288 struct fw_eq_eth_cmd c;
4289 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4290
4291 bzero(&c, sizeof(c));
4292
4293 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
4294 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
4295 V_FW_EQ_ETH_CMD_VFN(0));
4296 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
4297 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
4298 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
4299 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(vi->viid));
4300 c.fetchszm_to_iqid =
4301 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
4302 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
4303 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
4304 c.dcaen_to_eqsize =
4305 htobe32(V_FW_EQ_ETH_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
4306 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
4307 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
4308 V_FW_EQ_ETH_CMD_EQSIZE(qsize));
4309 c.eqaddr = htobe64(eq->ba);
4310
4311 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
4312 if (rc != 0) {
4313 device_printf(vi->dev,
4314 "failed to create Ethernet egress queue: %d\n", rc);
4315 return (rc);
4316 }
4317
4318 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
4319 eq->abs_id = G_FW_EQ_ETH_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
4320 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
4321 if (cntxt_id >= sc->sge.eqmap_sz)
4322 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
4323 cntxt_id, sc->sge.eqmap_sz - 1);
4324 sc->sge.eqmap[cntxt_id] = eq;
4325
4326 return (rc);
4327 }
4328
4329 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4330 static int
ofld_eq_alloc(struct adapter * sc,struct vi_info * vi,struct sge_eq * eq)4331 ofld_eq_alloc(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
4332 {
4333 int rc, cntxt_id;
4334 struct fw_eq_ofld_cmd c;
4335 int qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4336
4337 bzero(&c, sizeof(c));
4338
4339 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
4340 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
4341 V_FW_EQ_OFLD_CMD_VFN(0));
4342 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
4343 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
4344 c.fetchszm_to_iqid =
4345 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
4346 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
4347 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
4348 c.dcaen_to_eqsize =
4349 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(chip_id(sc) <= CHELSIO_T5 ?
4350 X_FETCHBURSTMIN_64B : X_FETCHBURSTMIN_64B_T6) |
4351 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
4352 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(qsize_to_fthresh(qsize)) |
4353 V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
4354 c.eqaddr = htobe64(eq->ba);
4355
4356 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
4357 if (rc != 0) {
4358 device_printf(vi->dev,
4359 "failed to create egress queue for TCP offload: %d\n", rc);
4360 return (rc);
4361 }
4362
4363 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
4364 eq->abs_id = G_FW_EQ_OFLD_CMD_PHYSEQID(be32toh(c.physeqid_pkd));
4365 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
4366 if (cntxt_id >= sc->sge.eqmap_sz)
4367 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
4368 cntxt_id, sc->sge.eqmap_sz - 1);
4369 sc->sge.eqmap[cntxt_id] = eq;
4370
4371 return (rc);
4372 }
4373 #endif
4374
4375 /* SW only */
4376 static int
alloc_eq(struct adapter * sc,struct sge_eq * eq,struct sysctl_ctx_list * ctx,struct sysctl_oid * oid)4377 alloc_eq(struct adapter *sc, struct sge_eq *eq, struct sysctl_ctx_list *ctx,
4378 struct sysctl_oid *oid)
4379 {
4380 int rc, qsize;
4381 size_t len;
4382
4383 MPASS(!(eq->flags & EQ_SW_ALLOCATED));
4384
4385 qsize = eq->sidx + sc->params.sge.spg_len / EQ_ESIZE;
4386 len = qsize * EQ_ESIZE;
4387 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map, &eq->ba,
4388 (void **)&eq->desc);
4389 if (rc)
4390 return (rc);
4391 if (ctx != NULL && oid != NULL)
4392 add_eq_sysctls(sc, ctx, oid, eq);
4393 eq->flags |= EQ_SW_ALLOCATED;
4394
4395 return (0);
4396 }
4397
4398 /* SW only */
4399 static void
free_eq(struct adapter * sc,struct sge_eq * eq)4400 free_eq(struct adapter *sc, struct sge_eq *eq)
4401 {
4402 MPASS(eq->flags & EQ_SW_ALLOCATED);
4403 if (eq->type == EQ_ETH)
4404 MPASS(eq->pidx == eq->cidx);
4405
4406 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
4407 mtx_destroy(&eq->eq_lock);
4408 bzero(eq, sizeof(*eq));
4409 }
4410
4411 static void
add_eq_sysctls(struct adapter * sc,struct sysctl_ctx_list * ctx,struct sysctl_oid * oid,struct sge_eq * eq)4412 add_eq_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
4413 struct sysctl_oid *oid, struct sge_eq *eq)
4414 {
4415 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
4416
4417 SYSCTL_ADD_UAUTO(ctx, children, OID_AUTO, "ba", CTLFLAG_RD, &eq->ba,
4418 "bus address of descriptor ring");
4419 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dmalen", CTLFLAG_RD, NULL,
4420 eq->sidx * EQ_ESIZE + sc->params.sge.spg_len,
4421 "desc ring size in bytes");
4422 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "abs_id", CTLFLAG_RD,
4423 &eq->abs_id, 0, "absolute id of the queue");
4424 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
4425 &eq->cntxt_id, 0, "SGE context id of the queue");
4426 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &eq->cidx,
4427 0, "consumer index");
4428 SYSCTL_ADD_U16(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &eq->pidx,
4429 0, "producer index");
4430 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sidx", CTLFLAG_RD, NULL,
4431 eq->sidx, "status page index");
4432 }
4433
4434 static int
alloc_eq_hwq(struct adapter * sc,struct vi_info * vi,struct sge_eq * eq)4435 alloc_eq_hwq(struct adapter *sc, struct vi_info *vi, struct sge_eq *eq)
4436 {
4437 int rc;
4438
4439 MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4440
4441 eq->iqid = eq->iq->cntxt_id;
4442 eq->pidx = eq->cidx = eq->dbidx = 0;
4443 /* Note that equeqidx is not used with sge_wrq (OFLD/CTRL) queues. */
4444 eq->equeqidx = 0;
4445 eq->doorbells = sc->doorbells;
4446 bzero(eq->desc, eq->sidx * EQ_ESIZE + sc->params.sge.spg_len);
4447
4448 switch (eq->type) {
4449 case EQ_CTRL:
4450 rc = ctrl_eq_alloc(sc, eq);
4451 break;
4452
4453 case EQ_ETH:
4454 rc = eth_eq_alloc(sc, vi, eq);
4455 break;
4456
4457 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4458 case EQ_OFLD:
4459 rc = ofld_eq_alloc(sc, vi, eq);
4460 break;
4461 #endif
4462
4463 default:
4464 panic("%s: invalid eq type %d.", __func__, eq->type);
4465 }
4466 if (rc != 0) {
4467 CH_ERR(sc, "failed to allocate egress queue(%d): %d\n",
4468 eq->type, rc);
4469 return (rc);
4470 }
4471
4472 if (isset(&eq->doorbells, DOORBELL_UDB) ||
4473 isset(&eq->doorbells, DOORBELL_UDBWC) ||
4474 isset(&eq->doorbells, DOORBELL_WCWR)) {
4475 uint32_t s_qpp = sc->params.sge.eq_s_qpp;
4476 uint32_t mask = (1 << s_qpp) - 1;
4477 volatile uint8_t *udb;
4478
4479 udb = sc->udbs_base + UDBS_DB_OFFSET;
4480 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
4481 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
4482 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
4483 clrbit(&eq->doorbells, DOORBELL_WCWR);
4484 else {
4485 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
4486 eq->udb_qid = 0;
4487 }
4488 eq->udb = (volatile void *)udb;
4489 }
4490
4491 eq->flags |= EQ_HW_ALLOCATED;
4492 return (0);
4493 }
4494
4495 static int
free_eq_hwq(struct adapter * sc,struct vi_info * vi __unused,struct sge_eq * eq)4496 free_eq_hwq(struct adapter *sc, struct vi_info *vi __unused, struct sge_eq *eq)
4497 {
4498 int rc;
4499
4500 MPASS(eq->flags & EQ_HW_ALLOCATED);
4501
4502 switch (eq->type) {
4503 case EQ_CTRL:
4504 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id);
4505 break;
4506 case EQ_ETH:
4507 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id);
4508 break;
4509 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4510 case EQ_OFLD:
4511 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0, eq->cntxt_id);
4512 break;
4513 #endif
4514 default:
4515 panic("%s: invalid eq type %d.", __func__, eq->type);
4516 }
4517 if (rc != 0) {
4518 CH_ERR(sc, "failed to free eq (type %d): %d\n", eq->type, rc);
4519 return (rc);
4520 }
4521 eq->flags &= ~EQ_HW_ALLOCATED;
4522
4523 return (0);
4524 }
4525
4526 static int
alloc_wrq(struct adapter * sc,struct vi_info * vi,struct sge_wrq * wrq,struct sysctl_ctx_list * ctx,struct sysctl_oid * oid)4527 alloc_wrq(struct adapter *sc, struct vi_info *vi, struct sge_wrq *wrq,
4528 struct sysctl_ctx_list *ctx, struct sysctl_oid *oid)
4529 {
4530 struct sge_eq *eq = &wrq->eq;
4531 int rc;
4532
4533 MPASS(!(eq->flags & EQ_SW_ALLOCATED));
4534
4535 rc = alloc_eq(sc, eq, ctx, oid);
4536 if (rc)
4537 return (rc);
4538 MPASS(eq->flags & EQ_SW_ALLOCATED);
4539 /* Can't fail after this. */
4540
4541 wrq->adapter = sc;
4542 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
4543 TAILQ_INIT(&wrq->incomplete_wrs);
4544 STAILQ_INIT(&wrq->wr_list);
4545 wrq->nwr_pending = 0;
4546 wrq->ndesc_needed = 0;
4547 add_wrq_sysctls(ctx, oid, wrq);
4548
4549 return (0);
4550 }
4551
4552 static void
free_wrq(struct adapter * sc,struct sge_wrq * wrq)4553 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
4554 {
4555 free_eq(sc, &wrq->eq);
4556 MPASS(wrq->nwr_pending == 0);
4557 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
4558 MPASS(STAILQ_EMPTY(&wrq->wr_list));
4559 bzero(wrq, sizeof(*wrq));
4560 }
4561
4562 static void
add_wrq_sysctls(struct sysctl_ctx_list * ctx,struct sysctl_oid * oid,struct sge_wrq * wrq)4563 add_wrq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
4564 struct sge_wrq *wrq)
4565 {
4566 struct sysctl_oid_list *children;
4567
4568 if (ctx == NULL || oid == NULL)
4569 return;
4570
4571 children = SYSCTL_CHILDREN(oid);
4572 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
4573 &wrq->tx_wrs_direct, "# of work requests (direct)");
4574 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
4575 &wrq->tx_wrs_copied, "# of work requests (copied)");
4576 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_sspace", CTLFLAG_RD,
4577 &wrq->tx_wrs_ss, "# of work requests (copied from scratch space)");
4578 }
4579
4580 /*
4581 * Idempotent.
4582 */
4583 static int
alloc_txq(struct vi_info * vi,struct sge_txq * txq,int idx)4584 alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx)
4585 {
4586 int rc, iqidx;
4587 struct port_info *pi = vi->pi;
4588 struct adapter *sc = vi->adapter;
4589 struct sge_eq *eq = &txq->eq;
4590 struct txpkts *txp;
4591 char name[16];
4592 struct sysctl_oid *oid;
4593
4594 if (!(eq->flags & EQ_SW_ALLOCATED)) {
4595 MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4596
4597 snprintf(name, sizeof(name), "%d", idx);
4598 oid = SYSCTL_ADD_NODE(&vi->ctx, SYSCTL_CHILDREN(vi->txq_oid),
4599 OID_AUTO, name, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
4600 "tx queue");
4601
4602 iqidx = vi->first_rxq + (idx % vi->nrxq);
4603 snprintf(name, sizeof(name), "%s txq%d",
4604 device_get_nameunit(vi->dev), idx);
4605 init_eq(sc, &txq->eq, EQ_ETH, vi->qsize_txq, pi->port_id,
4606 &sc->sge.rxq[iqidx].iq, name);
4607
4608 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx,
4609 can_resume_eth_tx, M_CXGBE, &eq->eq_lock, M_WAITOK);
4610 if (rc != 0) {
4611 CH_ERR(vi, "failed to allocate mp_ring for txq%d: %d\n",
4612 idx, rc);
4613 failed:
4614 sysctl_remove_oid(oid, 1, 1);
4615 return (rc);
4616 }
4617
4618 rc = alloc_eq(sc, eq, &vi->ctx, oid);
4619 if (rc) {
4620 CH_ERR(vi, "failed to allocate txq%d: %d\n", idx, rc);
4621 mp_ring_free(txq->r);
4622 goto failed;
4623 }
4624 MPASS(eq->flags & EQ_SW_ALLOCATED);
4625 /* Can't fail after this point. */
4626
4627 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
4628 txq->ifp = vi->ifp;
4629 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
4630 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
4631 M_ZERO | M_WAITOK);
4632
4633 add_txq_sysctls(vi, &vi->ctx, oid, txq);
4634 }
4635
4636 if (!(eq->flags & EQ_HW_ALLOCATED)) {
4637 MPASS(eq->flags & EQ_SW_ALLOCATED);
4638 rc = alloc_eq_hwq(sc, vi, eq);
4639 if (rc != 0) {
4640 CH_ERR(vi, "failed to create hw txq%d: %d\n", idx, rc);
4641 return (rc);
4642 }
4643 MPASS(eq->flags & EQ_HW_ALLOCATED);
4644 /* Can't fail after this point. */
4645
4646 if (idx == 0)
4647 sc->sge.eq_base = eq->abs_id - eq->cntxt_id;
4648 else
4649 KASSERT(eq->cntxt_id + sc->sge.eq_base == eq->abs_id,
4650 ("eq_base mismatch"));
4651 KASSERT(sc->sge.eq_base == 0 || sc->flags & IS_VF,
4652 ("PF with non-zero eq_base"));
4653
4654 txp = &txq->txp;
4655 MPASS(nitems(txp->mb) >= sc->params.max_pkts_per_eth_tx_pkts_wr);
4656 txq->txp.max_npkt = min(nitems(txp->mb),
4657 sc->params.max_pkts_per_eth_tx_pkts_wr);
4658 if (vi->flags & TX_USES_VM_WR && !(sc->flags & IS_VF))
4659 txq->txp.max_npkt--;
4660
4661 if (vi->flags & TX_USES_VM_WR)
4662 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
4663 V_TXPKT_INTF(pi->tx_chan));
4664 else
4665 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
4666 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf) |
4667 V_TXPKT_VF(vi->vin) | V_TXPKT_VF_VLD(vi->vfvld));
4668
4669 txq->tc_idx = -1;
4670 }
4671
4672 return (0);
4673 }
4674
4675 /*
4676 * Idempotent.
4677 */
4678 static void
free_txq(struct vi_info * vi,struct sge_txq * txq)4679 free_txq(struct vi_info *vi, struct sge_txq *txq)
4680 {
4681 struct adapter *sc = vi->adapter;
4682 struct sge_eq *eq = &txq->eq;
4683
4684 if (eq->flags & EQ_HW_ALLOCATED) {
4685 MPASS(eq->flags & EQ_SW_ALLOCATED);
4686 free_eq_hwq(sc, NULL, eq);
4687 MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4688 }
4689
4690 if (eq->flags & EQ_SW_ALLOCATED) {
4691 MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4692 sglist_free(txq->gl);
4693 free(txq->sdesc, M_CXGBE);
4694 mp_ring_free(txq->r);
4695 free_eq(sc, eq);
4696 MPASS(!(eq->flags & EQ_SW_ALLOCATED));
4697 bzero(txq, sizeof(*txq));
4698 }
4699 }
4700
4701 static void
add_txq_sysctls(struct vi_info * vi,struct sysctl_ctx_list * ctx,struct sysctl_oid * oid,struct sge_txq * txq)4702 add_txq_sysctls(struct vi_info *vi, struct sysctl_ctx_list *ctx,
4703 struct sysctl_oid *oid, struct sge_txq *txq)
4704 {
4705 struct adapter *sc;
4706 struct sysctl_oid_list *children;
4707
4708 if (ctx == NULL || oid == NULL)
4709 return;
4710
4711 sc = vi->adapter;
4712 children = SYSCTL_CHILDREN(oid);
4713
4714 mp_ring_sysctls(txq->r, ctx, children);
4715
4716 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tc",
4717 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, vi, txq - sc->sge.txq,
4718 sysctl_tc, "I", "traffic class (-1 means none)");
4719
4720 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
4721 &txq->txcsum, "# of times hardware assisted with checksum");
4722 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vlan_insertion", CTLFLAG_RD,
4723 &txq->vlan_insertion, "# of times hardware inserted 802.1Q tag");
4724 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
4725 &txq->tso_wrs, "# of TSO work requests");
4726 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
4727 &txq->imm_wrs, "# of work requests with immediate data");
4728 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
4729 &txq->sgl_wrs, "# of work requests with direct SGL");
4730 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
4731 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
4732 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_wrs", CTLFLAG_RD,
4733 &txq->txpkts0_wrs, "# of txpkts (type 0) work requests");
4734 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_wrs", CTLFLAG_RD,
4735 &txq->txpkts1_wrs, "# of txpkts (type 1) work requests");
4736 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts0_pkts", CTLFLAG_RD,
4737 &txq->txpkts0_pkts,
4738 "# of frames tx'd using type0 txpkts work requests");
4739 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts1_pkts", CTLFLAG_RD,
4740 &txq->txpkts1_pkts,
4741 "# of frames tx'd using type1 txpkts work requests");
4742 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "txpkts_flush", CTLFLAG_RD,
4743 &txq->txpkts_flush,
4744 "# of times txpkts had to be flushed out by an egress-update");
4745 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "raw_wrs", CTLFLAG_RD,
4746 &txq->raw_wrs, "# of raw work requests (non-packets)");
4747 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_tso_wrs", CTLFLAG_RD,
4748 &txq->vxlan_tso_wrs, "# of VXLAN TSO work requests");
4749 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "vxlan_txcsum", CTLFLAG_RD,
4750 &txq->vxlan_txcsum,
4751 "# of times hardware assisted with inner checksums (VXLAN)");
4752
4753 #ifdef KERN_TLS
4754 if (is_ktls(sc)) {
4755 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_records",
4756 CTLFLAG_RD, &txq->kern_tls_records,
4757 "# of NIC TLS records transmitted");
4758 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_short",
4759 CTLFLAG_RD, &txq->kern_tls_short,
4760 "# of short NIC TLS records transmitted");
4761 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_partial",
4762 CTLFLAG_RD, &txq->kern_tls_partial,
4763 "# of partial NIC TLS records transmitted");
4764 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_full",
4765 CTLFLAG_RD, &txq->kern_tls_full,
4766 "# of full NIC TLS records transmitted");
4767 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_octets",
4768 CTLFLAG_RD, &txq->kern_tls_octets,
4769 "# of payload octets in transmitted NIC TLS records");
4770 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_waste",
4771 CTLFLAG_RD, &txq->kern_tls_waste,
4772 "# of octets DMAd but not transmitted in NIC TLS records");
4773 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_options",
4774 CTLFLAG_RD, &txq->kern_tls_options,
4775 "# of NIC TLS options-only packets transmitted");
4776 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_header",
4777 CTLFLAG_RD, &txq->kern_tls_header,
4778 "# of NIC TLS header-only packets transmitted");
4779 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin",
4780 CTLFLAG_RD, &txq->kern_tls_fin,
4781 "# of NIC TLS FIN-only packets transmitted");
4782 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_fin_short",
4783 CTLFLAG_RD, &txq->kern_tls_fin_short,
4784 "# of NIC TLS padded FIN packets on short TLS records");
4785 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_cbc",
4786 CTLFLAG_RD, &txq->kern_tls_cbc,
4787 "# of NIC TLS sessions using AES-CBC");
4788 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "kern_tls_gcm",
4789 CTLFLAG_RD, &txq->kern_tls_gcm,
4790 "# of NIC TLS sessions using AES-GCM");
4791 }
4792 #endif
4793 }
4794
4795 #if defined(TCP_OFFLOAD) || defined(RATELIMIT)
4796 /*
4797 * Idempotent.
4798 */
4799 static int
alloc_ofld_txq(struct vi_info * vi,struct sge_ofld_txq * ofld_txq,int idx)4800 alloc_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq, int idx)
4801 {
4802 struct sysctl_oid *oid;
4803 struct port_info *pi = vi->pi;
4804 struct adapter *sc = vi->adapter;
4805 struct sge_eq *eq = &ofld_txq->wrq.eq;
4806 int rc, iqidx;
4807 char name[16];
4808
4809 MPASS(idx >= 0);
4810 MPASS(idx < vi->nofldtxq);
4811
4812 if (!(eq->flags & EQ_SW_ALLOCATED)) {
4813 snprintf(name, sizeof(name), "%d", idx);
4814 oid = SYSCTL_ADD_NODE(&vi->ctx,
4815 SYSCTL_CHILDREN(vi->ofld_txq_oid), OID_AUTO, name,
4816 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "offload tx queue");
4817
4818 snprintf(name, sizeof(name), "%s ofld_txq%d",
4819 device_get_nameunit(vi->dev), idx);
4820 if (vi->nofldrxq > 0) {
4821 iqidx = vi->first_ofld_rxq + (idx % vi->nofldrxq);
4822 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->port_id,
4823 &sc->sge.ofld_rxq[iqidx].iq, name);
4824 } else {
4825 iqidx = vi->first_rxq + (idx % vi->nrxq);
4826 init_eq(sc, eq, EQ_OFLD, vi->qsize_txq, pi->port_id,
4827 &sc->sge.rxq[iqidx].iq, name);
4828 }
4829
4830 rc = alloc_wrq(sc, vi, &ofld_txq->wrq, &vi->ctx, oid);
4831 if (rc != 0) {
4832 CH_ERR(vi, "failed to allocate ofld_txq%d: %d\n", idx,
4833 rc);
4834 sysctl_remove_oid(oid, 1, 1);
4835 return (rc);
4836 }
4837 MPASS(eq->flags & EQ_SW_ALLOCATED);
4838 /* Can't fail after this point. */
4839
4840 ofld_txq->tx_iscsi_pdus = counter_u64_alloc(M_WAITOK);
4841 ofld_txq->tx_iscsi_octets = counter_u64_alloc(M_WAITOK);
4842 ofld_txq->tx_iscsi_iso_wrs = counter_u64_alloc(M_WAITOK);
4843 ofld_txq->tx_aio_jobs = counter_u64_alloc(M_WAITOK);
4844 ofld_txq->tx_aio_octets = counter_u64_alloc(M_WAITOK);
4845 ofld_txq->tx_toe_tls_records = counter_u64_alloc(M_WAITOK);
4846 ofld_txq->tx_toe_tls_octets = counter_u64_alloc(M_WAITOK);
4847 add_ofld_txq_sysctls(&vi->ctx, oid, ofld_txq);
4848 }
4849
4850 if (!(eq->flags & EQ_HW_ALLOCATED)) {
4851 rc = alloc_eq_hwq(sc, vi, eq);
4852 if (rc != 0) {
4853 CH_ERR(vi, "failed to create hw ofld_txq%d: %d\n", idx,
4854 rc);
4855 return (rc);
4856 }
4857 MPASS(eq->flags & EQ_HW_ALLOCATED);
4858 }
4859
4860 return (0);
4861 }
4862
4863 /*
4864 * Idempotent.
4865 */
4866 static void
free_ofld_txq(struct vi_info * vi,struct sge_ofld_txq * ofld_txq)4867 free_ofld_txq(struct vi_info *vi, struct sge_ofld_txq *ofld_txq)
4868 {
4869 struct adapter *sc = vi->adapter;
4870 struct sge_eq *eq = &ofld_txq->wrq.eq;
4871
4872 if (eq->flags & EQ_HW_ALLOCATED) {
4873 MPASS(eq->flags & EQ_SW_ALLOCATED);
4874 free_eq_hwq(sc, NULL, eq);
4875 MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4876 }
4877
4878 if (eq->flags & EQ_SW_ALLOCATED) {
4879 MPASS(!(eq->flags & EQ_HW_ALLOCATED));
4880 counter_u64_free(ofld_txq->tx_iscsi_pdus);
4881 counter_u64_free(ofld_txq->tx_iscsi_octets);
4882 counter_u64_free(ofld_txq->tx_iscsi_iso_wrs);
4883 counter_u64_free(ofld_txq->tx_aio_jobs);
4884 counter_u64_free(ofld_txq->tx_aio_octets);
4885 counter_u64_free(ofld_txq->tx_toe_tls_records);
4886 counter_u64_free(ofld_txq->tx_toe_tls_octets);
4887 free_wrq(sc, &ofld_txq->wrq);
4888 MPASS(!(eq->flags & EQ_SW_ALLOCATED));
4889 bzero(ofld_txq, sizeof(*ofld_txq));
4890 }
4891 }
4892
4893 static void
add_ofld_txq_sysctls(struct sysctl_ctx_list * ctx,struct sysctl_oid * oid,struct sge_ofld_txq * ofld_txq)4894 add_ofld_txq_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
4895 struct sge_ofld_txq *ofld_txq)
4896 {
4897 struct sysctl_oid_list *children;
4898
4899 if (ctx == NULL || oid == NULL)
4900 return;
4901
4902 children = SYSCTL_CHILDREN(oid);
4903 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_pdus",
4904 CTLFLAG_RD, &ofld_txq->tx_iscsi_pdus,
4905 "# of iSCSI PDUs transmitted");
4906 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_octets",
4907 CTLFLAG_RD, &ofld_txq->tx_iscsi_octets,
4908 "# of payload octets in transmitted iSCSI PDUs");
4909 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_iscsi_iso_wrs",
4910 CTLFLAG_RD, &ofld_txq->tx_iscsi_iso_wrs,
4911 "# of iSCSI segmentation offload work requests");
4912 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_aio_jobs",
4913 CTLFLAG_RD, &ofld_txq->tx_aio_jobs,
4914 "# of zero-copy aio_write(2) jobs transmitted");
4915 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_aio_octets",
4916 CTLFLAG_RD, &ofld_txq->tx_aio_octets,
4917 "# of payload octets in transmitted zero-copy aio_write(2) jobs");
4918 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_records",
4919 CTLFLAG_RD, &ofld_txq->tx_toe_tls_records,
4920 "# of TOE TLS records transmitted");
4921 SYSCTL_ADD_COUNTER_U64(ctx, children, OID_AUTO, "tx_toe_tls_octets",
4922 CTLFLAG_RD, &ofld_txq->tx_toe_tls_octets,
4923 "# of payload octets in transmitted TOE TLS records");
4924 }
4925 #endif
4926
4927 static void
oneseg_dma_callback(void * arg,bus_dma_segment_t * segs,int nseg,int error)4928 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4929 {
4930 bus_addr_t *ba = arg;
4931
4932 KASSERT(nseg == 1,
4933 ("%s meant for single segment mappings only.", __func__));
4934
4935 *ba = error ? 0 : segs->ds_addr;
4936 }
4937
4938 static inline void
ring_fl_db(struct adapter * sc,struct sge_fl * fl)4939 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
4940 {
4941 uint32_t n, v;
4942
4943 n = IDXDIFF(fl->pidx >> 3, fl->dbidx, fl->sidx);
4944 MPASS(n > 0);
4945
4946 wmb();
4947 v = fl->dbval | V_PIDX(n);
4948 if (fl->udb)
4949 *fl->udb = htole32(v);
4950 else
4951 t4_write_reg(sc, sc->sge_kdoorbell_reg, v);
4952 IDXINCR(fl->dbidx, n, fl->sidx);
4953 }
4954
4955 /*
4956 * Fills up the freelist by allocating up to 'n' buffers. Buffers that are
4957 * recycled do not count towards this allocation budget.
4958 *
4959 * Returns non-zero to indicate that this freelist should be added to the list
4960 * of starving freelists.
4961 */
4962 static int
refill_fl(struct adapter * sc,struct sge_fl * fl,int n)4963 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
4964 {
4965 __be64 *d;
4966 struct fl_sdesc *sd;
4967 uintptr_t pa;
4968 caddr_t cl;
4969 struct rx_buf_info *rxb;
4970 struct cluster_metadata *clm;
4971 uint16_t max_pidx, zidx = fl->zidx;
4972 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
4973
4974 FL_LOCK_ASSERT_OWNED(fl);
4975
4976 /*
4977 * We always stop at the beginning of the hardware descriptor that's just
4978 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
4979 * which would mean an empty freelist to the chip.
4980 */
4981 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
4982 if (fl->pidx == max_pidx * 8)
4983 return (0);
4984
4985 d = &fl->desc[fl->pidx];
4986 sd = &fl->sdesc[fl->pidx];
4987 rxb = &sc->sge.rx_buf_info[zidx];
4988
4989 while (n > 0) {
4990
4991 if (sd->cl != NULL) {
4992
4993 if (sd->nmbuf == 0) {
4994 /*
4995 * Fast recycle without involving any atomics on
4996 * the cluster's metadata (if the cluster has
4997 * metadata). This happens when all frames
4998 * received in the cluster were small enough to
4999 * fit within a single mbuf each.
5000 */
5001 fl->cl_fast_recycled++;
5002 goto recycled;
5003 }
5004
5005 /*
5006 * Cluster is guaranteed to have metadata. Clusters
5007 * without metadata always take the fast recycle path
5008 * when they're recycled.
5009 */
5010 clm = cl_metadata(sd);
5011 MPASS(clm != NULL);
5012
5013 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
5014 fl->cl_recycled++;
5015 counter_u64_add(extfree_rels, 1);
5016 goto recycled;
5017 }
5018 sd->cl = NULL; /* gave up my reference */
5019 }
5020 MPASS(sd->cl == NULL);
5021 cl = uma_zalloc(rxb->zone, M_NOWAIT);
5022 if (__predict_false(cl == NULL)) {
5023 if (zidx != fl->safe_zidx) {
5024 zidx = fl->safe_zidx;
5025 rxb = &sc->sge.rx_buf_info[zidx];
5026 cl = uma_zalloc(rxb->zone, M_NOWAIT);
5027 }
5028 if (cl == NULL)
5029 break;
5030 }
5031 fl->cl_allocated++;
5032 n--;
5033
5034 pa = pmap_kextract((vm_offset_t)cl);
5035 sd->cl = cl;
5036 sd->zidx = zidx;
5037
5038 if (fl->flags & FL_BUF_PACKING) {
5039 *d = htobe64(pa | rxb->hwidx2);
5040 sd->moff = rxb->size2;
5041 } else {
5042 *d = htobe64(pa | rxb->hwidx1);
5043 sd->moff = 0;
5044 }
5045 recycled:
5046 sd->nmbuf = 0;
5047 d++;
5048 sd++;
5049 if (__predict_false((++fl->pidx & 7) == 0)) {
5050 uint16_t pidx = fl->pidx >> 3;
5051
5052 if (__predict_false(pidx == fl->sidx)) {
5053 fl->pidx = 0;
5054 pidx = 0;
5055 sd = fl->sdesc;
5056 d = fl->desc;
5057 }
5058 if (n < 8 || pidx == max_pidx)
5059 break;
5060
5061 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
5062 ring_fl_db(sc, fl);
5063 }
5064 }
5065
5066 if ((fl->pidx >> 3) != fl->dbidx)
5067 ring_fl_db(sc, fl);
5068
5069 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
5070 }
5071
5072 /*
5073 * Attempt to refill all starving freelists.
5074 */
5075 static void
refill_sfl(void * arg)5076 refill_sfl(void *arg)
5077 {
5078 struct adapter *sc = arg;
5079 struct sge_fl *fl, *fl_temp;
5080
5081 mtx_assert(&sc->sfl_lock, MA_OWNED);
5082 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
5083 FL_LOCK(fl);
5084 refill_fl(sc, fl, 64);
5085 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
5086 TAILQ_REMOVE(&sc->sfl, fl, link);
5087 fl->flags &= ~FL_STARVING;
5088 }
5089 FL_UNLOCK(fl);
5090 }
5091
5092 if (!TAILQ_EMPTY(&sc->sfl))
5093 callout_schedule(&sc->sfl_callout, hz / 5);
5094 }
5095
5096 /*
5097 * Release the driver's reference on all buffers in the given freelist. Buffers
5098 * with kernel references cannot be freed and will prevent the driver from being
5099 * unloaded safely.
5100 */
5101 void
free_fl_buffers(struct adapter * sc,struct sge_fl * fl)5102 free_fl_buffers(struct adapter *sc, struct sge_fl *fl)
5103 {
5104 struct fl_sdesc *sd;
5105 struct cluster_metadata *clm;
5106 int i;
5107
5108 sd = fl->sdesc;
5109 for (i = 0; i < fl->sidx * 8; i++, sd++) {
5110 if (sd->cl == NULL)
5111 continue;
5112
5113 if (sd->nmbuf == 0)
5114 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone, sd->cl);
5115 else if (fl->flags & FL_BUF_PACKING) {
5116 clm = cl_metadata(sd);
5117 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
5118 uma_zfree(sc->sge.rx_buf_info[sd->zidx].zone,
5119 sd->cl);
5120 counter_u64_add(extfree_rels, 1);
5121 }
5122 }
5123 sd->cl = NULL;
5124 }
5125
5126 if (fl->flags & FL_BUF_RESUME) {
5127 m_freem(fl->m0);
5128 fl->flags &= ~FL_BUF_RESUME;
5129 }
5130 }
5131
5132 static inline void
get_pkt_gl(struct mbuf * m,struct sglist * gl)5133 get_pkt_gl(struct mbuf *m, struct sglist *gl)
5134 {
5135 int rc;
5136
5137 M_ASSERTPKTHDR(m);
5138
5139 sglist_reset(gl);
5140 rc = sglist_append_mbuf(gl, m);
5141 if (__predict_false(rc != 0)) {
5142 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
5143 "with %d.", __func__, m, mbuf_nsegs(m), rc);
5144 }
5145
5146 KASSERT(gl->sg_nseg == mbuf_nsegs(m),
5147 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
5148 mbuf_nsegs(m), gl->sg_nseg));
5149 #if 0 /* vm_wr not readily available here. */
5150 KASSERT(gl->sg_nseg > 0 && gl->sg_nseg <= max_nsegs_allowed(m, vm_wr),
5151 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
5152 gl->sg_nseg, max_nsegs_allowed(m, vm_wr)));
5153 #endif
5154 }
5155
5156 /*
5157 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
5158 */
5159 static inline u_int
txpkt_len16(u_int nsegs,const u_int extra)5160 txpkt_len16(u_int nsegs, const u_int extra)
5161 {
5162 u_int n;
5163
5164 MPASS(nsegs > 0);
5165
5166 nsegs--; /* first segment is part of ulptx_sgl */
5167 n = extra + sizeof(struct fw_eth_tx_pkt_wr) +
5168 sizeof(struct cpl_tx_pkt_core) +
5169 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
5170
5171 return (howmany(n, 16));
5172 }
5173
5174 /*
5175 * len16 for a txpkt_vm WR with a GL. Includes the firmware work
5176 * request header.
5177 */
5178 static inline u_int
txpkt_vm_len16(u_int nsegs,const u_int extra)5179 txpkt_vm_len16(u_int nsegs, const u_int extra)
5180 {
5181 u_int n;
5182
5183 MPASS(nsegs > 0);
5184
5185 nsegs--; /* first segment is part of ulptx_sgl */
5186 n = extra + sizeof(struct fw_eth_tx_pkt_vm_wr) +
5187 sizeof(struct cpl_tx_pkt_core) +
5188 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
5189
5190 return (howmany(n, 16));
5191 }
5192
5193 static inline void
calculate_mbuf_len16(struct mbuf * m,bool vm_wr)5194 calculate_mbuf_len16(struct mbuf *m, bool vm_wr)
5195 {
5196 const int lso = sizeof(struct cpl_tx_pkt_lso_core);
5197 const int tnl_lso = sizeof(struct cpl_tx_tnl_lso);
5198
5199 if (vm_wr) {
5200 if (needs_tso(m))
5201 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), lso));
5202 else
5203 set_mbuf_len16(m, txpkt_vm_len16(mbuf_nsegs(m), 0));
5204 return;
5205 }
5206
5207 if (needs_tso(m)) {
5208 if (needs_vxlan_tso(m))
5209 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), tnl_lso));
5210 else
5211 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), lso));
5212 } else
5213 set_mbuf_len16(m, txpkt_len16(mbuf_nsegs(m), 0));
5214 }
5215
5216 /*
5217 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work
5218 * request header.
5219 */
5220 static inline u_int
txpkts0_len16(u_int nsegs)5221 txpkts0_len16(u_int nsegs)
5222 {
5223 u_int n;
5224
5225 MPASS(nsegs > 0);
5226
5227 nsegs--; /* first segment is part of ulptx_sgl */
5228 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
5229 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
5230 8 * ((3 * nsegs) / 2 + (nsegs & 1));
5231
5232 return (howmany(n, 16));
5233 }
5234
5235 /*
5236 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work
5237 * request header.
5238 */
5239 static inline u_int
txpkts1_len16(void)5240 txpkts1_len16(void)
5241 {
5242 u_int n;
5243
5244 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
5245
5246 return (howmany(n, 16));
5247 }
5248
5249 static inline u_int
imm_payload(u_int ndesc)5250 imm_payload(u_int ndesc)
5251 {
5252 u_int n;
5253
5254 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
5255 sizeof(struct cpl_tx_pkt_core);
5256
5257 return (n);
5258 }
5259
5260 static inline uint64_t
csum_to_ctrl(struct adapter * sc,struct mbuf * m)5261 csum_to_ctrl(struct adapter *sc, struct mbuf *m)
5262 {
5263 uint64_t ctrl;
5264 int csum_type, l2hlen, l3hlen;
5265 int x, y;
5266 static const int csum_types[3][2] = {
5267 {TX_CSUM_TCPIP, TX_CSUM_TCPIP6},
5268 {TX_CSUM_UDPIP, TX_CSUM_UDPIP6},
5269 {TX_CSUM_IP, 0}
5270 };
5271
5272 M_ASSERTPKTHDR(m);
5273
5274 if (!needs_hwcsum(m))
5275 return (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS);
5276
5277 MPASS(m->m_pkthdr.l2hlen >= ETHER_HDR_LEN);
5278 MPASS(m->m_pkthdr.l3hlen >= sizeof(struct ip));
5279
5280 if (needs_vxlan_csum(m)) {
5281 MPASS(m->m_pkthdr.l4hlen > 0);
5282 MPASS(m->m_pkthdr.l5hlen > 0);
5283 MPASS(m->m_pkthdr.inner_l2hlen >= ETHER_HDR_LEN);
5284 MPASS(m->m_pkthdr.inner_l3hlen >= sizeof(struct ip));
5285
5286 l2hlen = m->m_pkthdr.l2hlen + m->m_pkthdr.l3hlen +
5287 m->m_pkthdr.l4hlen + m->m_pkthdr.l5hlen +
5288 m->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN;
5289 l3hlen = m->m_pkthdr.inner_l3hlen;
5290 } else {
5291 l2hlen = m->m_pkthdr.l2hlen - ETHER_HDR_LEN;
5292 l3hlen = m->m_pkthdr.l3hlen;
5293 }
5294
5295 ctrl = 0;
5296 if (!needs_l3_csum(m))
5297 ctrl |= F_TXPKT_IPCSUM_DIS;
5298
5299 if (m->m_pkthdr.csum_flags & (CSUM_IP_TCP | CSUM_INNER_IP_TCP |
5300 CSUM_IP6_TCP | CSUM_INNER_IP6_TCP))
5301 x = 0; /* TCP */
5302 else if (m->m_pkthdr.csum_flags & (CSUM_IP_UDP | CSUM_INNER_IP_UDP |
5303 CSUM_IP6_UDP | CSUM_INNER_IP6_UDP))
5304 x = 1; /* UDP */
5305 else
5306 x = 2;
5307
5308 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_IP_TCP | CSUM_IP_UDP |
5309 CSUM_INNER_IP | CSUM_INNER_IP_TCP | CSUM_INNER_IP_UDP))
5310 y = 0; /* IPv4 */
5311 else {
5312 MPASS(m->m_pkthdr.csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP |
5313 CSUM_INNER_IP6_TCP | CSUM_INNER_IP6_UDP));
5314 y = 1; /* IPv6 */
5315 }
5316 /*
5317 * needs_hwcsum returned true earlier so there must be some kind of
5318 * checksum to calculate.
5319 */
5320 csum_type = csum_types[x][y];
5321 MPASS(csum_type != 0);
5322 if (csum_type == TX_CSUM_IP)
5323 ctrl |= F_TXPKT_L4CSUM_DIS;
5324 ctrl |= V_TXPKT_CSUM_TYPE(csum_type) | V_TXPKT_IPHDR_LEN(l3hlen);
5325 if (chip_id(sc) <= CHELSIO_T5)
5326 ctrl |= V_TXPKT_ETHHDR_LEN(l2hlen);
5327 else
5328 ctrl |= V_T6_TXPKT_ETHHDR_LEN(l2hlen);
5329
5330 return (ctrl);
5331 }
5332
5333 static inline void *
write_lso_cpl(void * cpl,struct mbuf * m0)5334 write_lso_cpl(void *cpl, struct mbuf *m0)
5335 {
5336 struct cpl_tx_pkt_lso_core *lso;
5337 uint32_t ctrl;
5338
5339 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
5340 m0->m_pkthdr.l4hlen > 0,
5341 ("%s: mbuf %p needs TSO but missing header lengths",
5342 __func__, m0));
5343
5344 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) |
5345 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE |
5346 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) |
5347 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) |
5348 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
5349 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
5350 ctrl |= F_LSO_IPV6;
5351
5352 lso = cpl;
5353 lso->lso_ctrl = htobe32(ctrl);
5354 lso->ipid_ofst = htobe16(0);
5355 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
5356 lso->seqno_offset = htobe32(0);
5357 lso->len = htobe32(m0->m_pkthdr.len);
5358
5359 return (lso + 1);
5360 }
5361
5362 static void *
write_tnl_lso_cpl(void * cpl,struct mbuf * m0)5363 write_tnl_lso_cpl(void *cpl, struct mbuf *m0)
5364 {
5365 struct cpl_tx_tnl_lso *tnl_lso = cpl;
5366 uint32_t ctrl;
5367
5368 KASSERT(m0->m_pkthdr.inner_l2hlen > 0 &&
5369 m0->m_pkthdr.inner_l3hlen > 0 && m0->m_pkthdr.inner_l4hlen > 0 &&
5370 m0->m_pkthdr.inner_l5hlen > 0,
5371 ("%s: mbuf %p needs VXLAN_TSO but missing inner header lengths",
5372 __func__, m0));
5373 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
5374 m0->m_pkthdr.l4hlen > 0 && m0->m_pkthdr.l5hlen > 0,
5375 ("%s: mbuf %p needs VXLAN_TSO but missing outer header lengths",
5376 __func__, m0));
5377
5378 /* Outer headers. */
5379 ctrl = V_CPL_TX_TNL_LSO_OPCODE(CPL_TX_TNL_LSO) |
5380 F_CPL_TX_TNL_LSO_FIRST | F_CPL_TX_TNL_LSO_LAST |
5381 V_CPL_TX_TNL_LSO_ETHHDRLENOUT(
5382 (m0->m_pkthdr.l2hlen - ETHER_HDR_LEN) >> 2) |
5383 V_CPL_TX_TNL_LSO_IPHDRLENOUT(m0->m_pkthdr.l3hlen >> 2) |
5384 F_CPL_TX_TNL_LSO_IPLENSETOUT;
5385 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
5386 ctrl |= F_CPL_TX_TNL_LSO_IPV6OUT;
5387 else {
5388 ctrl |= F_CPL_TX_TNL_LSO_IPHDRCHKOUT |
5389 F_CPL_TX_TNL_LSO_IPIDINCOUT;
5390 }
5391 tnl_lso->op_to_IpIdSplitOut = htobe32(ctrl);
5392 tnl_lso->IpIdOffsetOut = 0;
5393 tnl_lso->UdpLenSetOut_to_TnlHdrLen =
5394 htobe16(F_CPL_TX_TNL_LSO_UDPCHKCLROUT |
5395 F_CPL_TX_TNL_LSO_UDPLENSETOUT |
5396 V_CPL_TX_TNL_LSO_TNLHDRLEN(m0->m_pkthdr.l2hlen +
5397 m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen +
5398 m0->m_pkthdr.l5hlen) |
5399 V_CPL_TX_TNL_LSO_TNLTYPE(TX_TNL_TYPE_VXLAN));
5400 tnl_lso->r1 = 0;
5401
5402 /* Inner headers. */
5403 ctrl = V_CPL_TX_TNL_LSO_ETHHDRLEN(
5404 (m0->m_pkthdr.inner_l2hlen - ETHER_HDR_LEN) >> 2) |
5405 V_CPL_TX_TNL_LSO_IPHDRLEN(m0->m_pkthdr.inner_l3hlen >> 2) |
5406 V_CPL_TX_TNL_LSO_TCPHDRLEN(m0->m_pkthdr.inner_l4hlen >> 2);
5407 if (m0->m_pkthdr.inner_l3hlen == sizeof(struct ip6_hdr))
5408 ctrl |= F_CPL_TX_TNL_LSO_IPV6;
5409 tnl_lso->Flow_to_TcpHdrLen = htobe32(ctrl);
5410 tnl_lso->IpIdOffset = 0;
5411 tnl_lso->IpIdSplit_to_Mss =
5412 htobe16(V_CPL_TX_TNL_LSO_MSS(m0->m_pkthdr.tso_segsz));
5413 tnl_lso->TCPSeqOffset = 0;
5414 tnl_lso->EthLenOffset_Size =
5415 htobe32(V_CPL_TX_TNL_LSO_SIZE(m0->m_pkthdr.len));
5416
5417 return (tnl_lso + 1);
5418 }
5419
5420 #define VM_TX_L2HDR_LEN 16 /* ethmacdst to vlantci */
5421
5422 /*
5423 * Write a VM txpkt WR for this packet to the hardware descriptors, update the
5424 * software descriptor, and advance the pidx. It is guaranteed that enough
5425 * descriptors are available.
5426 *
5427 * The return value is the # of hardware descriptors used.
5428 */
5429 static u_int
write_txpkt_vm_wr(struct adapter * sc,struct sge_txq * txq,struct mbuf * m0)5430 write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0)
5431 {
5432 struct sge_eq *eq;
5433 struct fw_eth_tx_pkt_vm_wr *wr;
5434 struct tx_sdesc *txsd;
5435 struct cpl_tx_pkt_core *cpl;
5436 uint32_t ctrl; /* used in many unrelated places */
5437 uint64_t ctrl1;
5438 int len16, ndesc, pktlen;
5439 caddr_t dst;
5440
5441 TXQ_LOCK_ASSERT_OWNED(txq);
5442 M_ASSERTPKTHDR(m0);
5443
5444 len16 = mbuf_len16(m0);
5445 pktlen = m0->m_pkthdr.len;
5446 ctrl = sizeof(struct cpl_tx_pkt_core);
5447 if (needs_tso(m0))
5448 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
5449 ndesc = tx_len16_to_desc(len16);
5450
5451 /* Firmware work request header */
5452 eq = &txq->eq;
5453 wr = (void *)&eq->desc[eq->pidx];
5454 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
5455 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
5456
5457 ctrl = V_FW_WR_LEN16(len16);
5458 wr->equiq_to_len16 = htobe32(ctrl);
5459 wr->r3[0] = 0;
5460 wr->r3[1] = 0;
5461
5462 /*
5463 * Copy over ethmacdst, ethmacsrc, ethtype, and vlantci.
5464 * vlantci is ignored unless the ethtype is 0x8100, so it's
5465 * simpler to always copy it rather than making it
5466 * conditional. Also, it seems that we do not have to set
5467 * vlantci or fake the ethtype when doing VLAN tag insertion.
5468 */
5469 m_copydata(m0, 0, VM_TX_L2HDR_LEN, wr->ethmacdst);
5470
5471 if (needs_tso(m0)) {
5472 cpl = write_lso_cpl(wr + 1, m0);
5473 txq->tso_wrs++;
5474 } else
5475 cpl = (void *)(wr + 1);
5476
5477 /* Checksum offload */
5478 ctrl1 = csum_to_ctrl(sc, m0);
5479 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS))
5480 txq->txcsum++; /* some hardware assistance provided */
5481
5482 /* VLAN tag insertion */
5483 if (needs_vlan_insertion(m0)) {
5484 ctrl1 |= F_TXPKT_VLAN_VLD |
5485 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
5486 txq->vlan_insertion++;
5487 } else if (sc->vlan_id)
5488 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(sc->vlan_id);
5489
5490 /* CPL header */
5491 cpl->ctrl0 = txq->cpl_ctrl0;
5492 cpl->pack = 0;
5493 cpl->len = htobe16(pktlen);
5494 cpl->ctrl1 = htobe64(ctrl1);
5495
5496 /* SGL */
5497 dst = (void *)(cpl + 1);
5498
5499 /*
5500 * A packet using TSO will use up an entire descriptor for the
5501 * firmware work request header, LSO CPL, and TX_PKT_XT CPL.
5502 * If this descriptor is the last descriptor in the ring, wrap
5503 * around to the front of the ring explicitly for the start of
5504 * the sgl.
5505 */
5506 if (dst == (void *)&eq->desc[eq->sidx]) {
5507 dst = (void *)&eq->desc[0];
5508 write_gl_to_txd(txq, m0, &dst, 0);
5509 } else
5510 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
5511 txq->sgl_wrs++;
5512 txq->txpkt_wrs++;
5513
5514 txsd = &txq->sdesc[eq->pidx];
5515 txsd->m = m0;
5516 txsd->desc_used = ndesc;
5517
5518 return (ndesc);
5519 }
5520
5521 /*
5522 * Write a raw WR to the hardware descriptors, update the software
5523 * descriptor, and advance the pidx. It is guaranteed that enough
5524 * descriptors are available.
5525 *
5526 * The return value is the # of hardware descriptors used.
5527 */
5528 static u_int
write_raw_wr(struct sge_txq * txq,void * wr,struct mbuf * m0,u_int available)5529 write_raw_wr(struct sge_txq *txq, void *wr, struct mbuf *m0, u_int available)
5530 {
5531 struct sge_eq *eq = &txq->eq;
5532 struct tx_sdesc *txsd;
5533 struct mbuf *m;
5534 caddr_t dst;
5535 int len16, ndesc;
5536
5537 len16 = mbuf_len16(m0);
5538 ndesc = tx_len16_to_desc(len16);
5539 MPASS(ndesc <= available);
5540
5541 dst = wr;
5542 for (m = m0; m != NULL; m = m->m_next)
5543 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
5544
5545 txq->raw_wrs++;
5546
5547 txsd = &txq->sdesc[eq->pidx];
5548 txsd->m = m0;
5549 txsd->desc_used = ndesc;
5550
5551 return (ndesc);
5552 }
5553
5554 /*
5555 * Write a txpkt WR for this packet to the hardware descriptors, update the
5556 * software descriptor, and advance the pidx. It is guaranteed that enough
5557 * descriptors are available.
5558 *
5559 * The return value is the # of hardware descriptors used.
5560 */
5561 static u_int
write_txpkt_wr(struct adapter * sc,struct sge_txq * txq,struct mbuf * m0,u_int available)5562 write_txpkt_wr(struct adapter *sc, struct sge_txq *txq, struct mbuf *m0,
5563 u_int available)
5564 {
5565 struct sge_eq *eq;
5566 struct fw_eth_tx_pkt_wr *wr;
5567 struct tx_sdesc *txsd;
5568 struct cpl_tx_pkt_core *cpl;
5569 uint32_t ctrl; /* used in many unrelated places */
5570 uint64_t ctrl1;
5571 int len16, ndesc, pktlen, nsegs;
5572 caddr_t dst;
5573
5574 TXQ_LOCK_ASSERT_OWNED(txq);
5575 M_ASSERTPKTHDR(m0);
5576
5577 len16 = mbuf_len16(m0);
5578 nsegs = mbuf_nsegs(m0);
5579 pktlen = m0->m_pkthdr.len;
5580 ctrl = sizeof(struct cpl_tx_pkt_core);
5581 if (needs_tso(m0)) {
5582 if (needs_vxlan_tso(m0))
5583 ctrl += sizeof(struct cpl_tx_tnl_lso);
5584 else
5585 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
5586 } else if (!(mbuf_cflags(m0) & MC_NOMAP) && pktlen <= imm_payload(2) &&
5587 available >= 2) {
5588 /* Immediate data. Recalculate len16 and set nsegs to 0. */
5589 ctrl += pktlen;
5590 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
5591 sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
5592 nsegs = 0;
5593 }
5594 ndesc = tx_len16_to_desc(len16);
5595 MPASS(ndesc <= available);
5596
5597 /* Firmware work request header */
5598 eq = &txq->eq;
5599 wr = (void *)&eq->desc[eq->pidx];
5600 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
5601 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
5602
5603 ctrl = V_FW_WR_LEN16(len16);
5604 wr->equiq_to_len16 = htobe32(ctrl);
5605 wr->r3 = 0;
5606
5607 if (needs_tso(m0)) {
5608 if (needs_vxlan_tso(m0)) {
5609 cpl = write_tnl_lso_cpl(wr + 1, m0);
5610 txq->vxlan_tso_wrs++;
5611 } else {
5612 cpl = write_lso_cpl(wr + 1, m0);
5613 txq->tso_wrs++;
5614 }
5615 } else
5616 cpl = (void *)(wr + 1);
5617
5618 /* Checksum offload */
5619 ctrl1 = csum_to_ctrl(sc, m0);
5620 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) {
5621 /* some hardware assistance provided */
5622 if (needs_vxlan_csum(m0))
5623 txq->vxlan_txcsum++;
5624 else
5625 txq->txcsum++;
5626 }
5627
5628 /* VLAN tag insertion */
5629 if (needs_vlan_insertion(m0)) {
5630 ctrl1 |= F_TXPKT_VLAN_VLD |
5631 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
5632 txq->vlan_insertion++;
5633 }
5634
5635 /* CPL header */
5636 cpl->ctrl0 = txq->cpl_ctrl0;
5637 cpl->pack = 0;
5638 cpl->len = htobe16(pktlen);
5639 cpl->ctrl1 = htobe64(ctrl1);
5640
5641 /* SGL */
5642 dst = (void *)(cpl + 1);
5643 if (__predict_false((uintptr_t)dst == (uintptr_t)&eq->desc[eq->sidx]))
5644 dst = (caddr_t)&eq->desc[0];
5645 if (nsegs > 0) {
5646
5647 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
5648 txq->sgl_wrs++;
5649 } else {
5650 struct mbuf *m;
5651
5652 for (m = m0; m != NULL; m = m->m_next) {
5653 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
5654 #ifdef INVARIANTS
5655 pktlen -= m->m_len;
5656 #endif
5657 }
5658 #ifdef INVARIANTS
5659 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
5660 #endif
5661 txq->imm_wrs++;
5662 }
5663
5664 txq->txpkt_wrs++;
5665
5666 txsd = &txq->sdesc[eq->pidx];
5667 txsd->m = m0;
5668 txsd->desc_used = ndesc;
5669
5670 return (ndesc);
5671 }
5672
5673 static inline bool
cmp_l2hdr(struct txpkts * txp,struct mbuf * m)5674 cmp_l2hdr(struct txpkts *txp, struct mbuf *m)
5675 {
5676 int len;
5677
5678 MPASS(txp->npkt > 0);
5679 MPASS(m->m_len >= VM_TX_L2HDR_LEN);
5680
5681 if (txp->ethtype == be16toh(ETHERTYPE_VLAN))
5682 len = VM_TX_L2HDR_LEN;
5683 else
5684 len = sizeof(struct ether_header);
5685
5686 return (memcmp(m->m_data, &txp->ethmacdst[0], len) != 0);
5687 }
5688
5689 static inline void
save_l2hdr(struct txpkts * txp,struct mbuf * m)5690 save_l2hdr(struct txpkts *txp, struct mbuf *m)
5691 {
5692 MPASS(m->m_len >= VM_TX_L2HDR_LEN);
5693
5694 memcpy(&txp->ethmacdst[0], mtod(m, const void *), VM_TX_L2HDR_LEN);
5695 }
5696
5697 static int
add_to_txpkts_vf(struct adapter * sc,struct sge_txq * txq,struct mbuf * m,int avail,bool * send)5698 add_to_txpkts_vf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m,
5699 int avail, bool *send)
5700 {
5701 struct txpkts *txp = &txq->txp;
5702
5703 /* Cannot have TSO and coalesce at the same time. */
5704 if (cannot_use_txpkts(m)) {
5705 cannot_coalesce:
5706 *send = txp->npkt > 0;
5707 return (EINVAL);
5708 }
5709
5710 /* VF allows coalescing of type 1 (1 GL) only */
5711 if (mbuf_nsegs(m) > 1)
5712 goto cannot_coalesce;
5713
5714 *send = false;
5715 if (txp->npkt > 0) {
5716 MPASS(tx_len16_to_desc(txp->len16) <= avail);
5717 MPASS(txp->npkt < txp->max_npkt);
5718 MPASS(txp->wr_type == 1); /* VF supports type 1 only */
5719
5720 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) > avail) {
5721 retry_after_send:
5722 *send = true;
5723 return (EAGAIN);
5724 }
5725 if (m->m_pkthdr.len + txp->plen > 65535)
5726 goto retry_after_send;
5727 if (cmp_l2hdr(txp, m))
5728 goto retry_after_send;
5729
5730 txp->len16 += txpkts1_len16();
5731 txp->plen += m->m_pkthdr.len;
5732 txp->mb[txp->npkt++] = m;
5733 if (txp->npkt == txp->max_npkt)
5734 *send = true;
5735 } else {
5736 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_vm_wr), 16) +
5737 txpkts1_len16();
5738 if (tx_len16_to_desc(txp->len16) > avail)
5739 goto cannot_coalesce;
5740 txp->npkt = 1;
5741 txp->wr_type = 1;
5742 txp->plen = m->m_pkthdr.len;
5743 txp->mb[0] = m;
5744 save_l2hdr(txp, m);
5745 }
5746 return (0);
5747 }
5748
5749 static int
add_to_txpkts_pf(struct adapter * sc,struct sge_txq * txq,struct mbuf * m,int avail,bool * send)5750 add_to_txpkts_pf(struct adapter *sc, struct sge_txq *txq, struct mbuf *m,
5751 int avail, bool *send)
5752 {
5753 struct txpkts *txp = &txq->txp;
5754 int nsegs;
5755
5756 MPASS(!(sc->flags & IS_VF));
5757
5758 /* Cannot have TSO and coalesce at the same time. */
5759 if (cannot_use_txpkts(m)) {
5760 cannot_coalesce:
5761 *send = txp->npkt > 0;
5762 return (EINVAL);
5763 }
5764
5765 *send = false;
5766 nsegs = mbuf_nsegs(m);
5767 if (txp->npkt == 0) {
5768 if (m->m_pkthdr.len > 65535)
5769 goto cannot_coalesce;
5770 if (nsegs > 1) {
5771 txp->wr_type = 0;
5772 txp->len16 =
5773 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) +
5774 txpkts0_len16(nsegs);
5775 } else {
5776 txp->wr_type = 1;
5777 txp->len16 =
5778 howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) +
5779 txpkts1_len16();
5780 }
5781 if (tx_len16_to_desc(txp->len16) > avail)
5782 goto cannot_coalesce;
5783 txp->npkt = 1;
5784 txp->plen = m->m_pkthdr.len;
5785 txp->mb[0] = m;
5786 } else {
5787 MPASS(tx_len16_to_desc(txp->len16) <= avail);
5788 MPASS(txp->npkt < txp->max_npkt);
5789
5790 if (m->m_pkthdr.len + txp->plen > 65535) {
5791 retry_after_send:
5792 *send = true;
5793 return (EAGAIN);
5794 }
5795
5796 MPASS(txp->wr_type == 0 || txp->wr_type == 1);
5797 if (txp->wr_type == 0) {
5798 if (tx_len16_to_desc(txp->len16 +
5799 txpkts0_len16(nsegs)) > min(avail, SGE_MAX_WR_NDESC))
5800 goto retry_after_send;
5801 txp->len16 += txpkts0_len16(nsegs);
5802 } else {
5803 if (nsegs != 1)
5804 goto retry_after_send;
5805 if (tx_len16_to_desc(txp->len16 + txpkts1_len16()) >
5806 avail)
5807 goto retry_after_send;
5808 txp->len16 += txpkts1_len16();
5809 }
5810
5811 txp->plen += m->m_pkthdr.len;
5812 txp->mb[txp->npkt++] = m;
5813 if (txp->npkt == txp->max_npkt)
5814 *send = true;
5815 }
5816 return (0);
5817 }
5818
5819 /*
5820 * Write a txpkts WR for the packets in txp to the hardware descriptors, update
5821 * the software descriptor, and advance the pidx. It is guaranteed that enough
5822 * descriptors are available.
5823 *
5824 * The return value is the # of hardware descriptors used.
5825 */
5826 static u_int
write_txpkts_wr(struct adapter * sc,struct sge_txq * txq)5827 write_txpkts_wr(struct adapter *sc, struct sge_txq *txq)
5828 {
5829 const struct txpkts *txp = &txq->txp;
5830 struct sge_eq *eq = &txq->eq;
5831 struct fw_eth_tx_pkts_wr *wr;
5832 struct tx_sdesc *txsd;
5833 struct cpl_tx_pkt_core *cpl;
5834 uint64_t ctrl1;
5835 int ndesc, i, checkwrap;
5836 struct mbuf *m, *last;
5837 void *flitp;
5838
5839 TXQ_LOCK_ASSERT_OWNED(txq);
5840 MPASS(txp->npkt > 0);
5841 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
5842
5843 wr = (void *)&eq->desc[eq->pidx];
5844 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
5845 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16));
5846 wr->plen = htobe16(txp->plen);
5847 wr->npkt = txp->npkt;
5848 wr->r3 = 0;
5849 wr->type = txp->wr_type;
5850 flitp = wr + 1;
5851
5852 /*
5853 * At this point we are 16B into a hardware descriptor. If checkwrap is
5854 * set then we know the WR is going to wrap around somewhere. We'll
5855 * check for that at appropriate points.
5856 */
5857 ndesc = tx_len16_to_desc(txp->len16);
5858 last = NULL;
5859 checkwrap = eq->sidx - ndesc < eq->pidx;
5860 for (i = 0; i < txp->npkt; i++) {
5861 m = txp->mb[i];
5862 if (txp->wr_type == 0) {
5863 struct ulp_txpkt *ulpmc;
5864 struct ulptx_idata *ulpsc;
5865
5866 /* ULP master command */
5867 ulpmc = flitp;
5868 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
5869 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
5870 ulpmc->len = htobe32(txpkts0_len16(mbuf_nsegs(m)));
5871
5872 /* ULP subcommand */
5873 ulpsc = (void *)(ulpmc + 1);
5874 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
5875 F_ULP_TX_SC_MORE);
5876 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
5877
5878 cpl = (void *)(ulpsc + 1);
5879 if (checkwrap &&
5880 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
5881 cpl = (void *)&eq->desc[0];
5882 } else {
5883 cpl = flitp;
5884 }
5885
5886 /* Checksum offload */
5887 ctrl1 = csum_to_ctrl(sc, m);
5888 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS)) {
5889 /* some hardware assistance provided */
5890 if (needs_vxlan_csum(m))
5891 txq->vxlan_txcsum++;
5892 else
5893 txq->txcsum++;
5894 }
5895
5896 /* VLAN tag insertion */
5897 if (needs_vlan_insertion(m)) {
5898 ctrl1 |= F_TXPKT_VLAN_VLD |
5899 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
5900 txq->vlan_insertion++;
5901 }
5902
5903 /* CPL header */
5904 cpl->ctrl0 = txq->cpl_ctrl0;
5905 cpl->pack = 0;
5906 cpl->len = htobe16(m->m_pkthdr.len);
5907 cpl->ctrl1 = htobe64(ctrl1);
5908
5909 flitp = cpl + 1;
5910 if (checkwrap &&
5911 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
5912 flitp = (void *)&eq->desc[0];
5913
5914 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
5915
5916 if (last != NULL)
5917 last->m_nextpkt = m;
5918 last = m;
5919 }
5920
5921 txq->sgl_wrs++;
5922 if (txp->wr_type == 0) {
5923 txq->txpkts0_pkts += txp->npkt;
5924 txq->txpkts0_wrs++;
5925 } else {
5926 txq->txpkts1_pkts += txp->npkt;
5927 txq->txpkts1_wrs++;
5928 }
5929
5930 txsd = &txq->sdesc[eq->pidx];
5931 txsd->m = txp->mb[0];
5932 txsd->desc_used = ndesc;
5933
5934 return (ndesc);
5935 }
5936
5937 static u_int
write_txpkts_vm_wr(struct adapter * sc,struct sge_txq * txq)5938 write_txpkts_vm_wr(struct adapter *sc, struct sge_txq *txq)
5939 {
5940 const struct txpkts *txp = &txq->txp;
5941 struct sge_eq *eq = &txq->eq;
5942 struct fw_eth_tx_pkts_vm_wr *wr;
5943 struct tx_sdesc *txsd;
5944 struct cpl_tx_pkt_core *cpl;
5945 uint64_t ctrl1;
5946 int ndesc, i;
5947 struct mbuf *m, *last;
5948 void *flitp;
5949
5950 TXQ_LOCK_ASSERT_OWNED(txq);
5951 MPASS(txp->npkt > 0);
5952 MPASS(txp->wr_type == 1); /* VF supports type 1 only */
5953 MPASS(txp->mb[0] != NULL);
5954 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
5955
5956 wr = (void *)&eq->desc[eq->pidx];
5957 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_VM_WR));
5958 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(txp->len16));
5959 wr->r3 = 0;
5960 wr->plen = htobe16(txp->plen);
5961 wr->npkt = txp->npkt;
5962 wr->r4 = 0;
5963 memcpy(&wr->ethmacdst[0], &txp->ethmacdst[0], 16);
5964 flitp = wr + 1;
5965
5966 /*
5967 * At this point we are 32B into a hardware descriptor. Each mbuf in
5968 * the WR will take 32B so we check for the end of the descriptor ring
5969 * before writing odd mbufs (mb[1], 3, 5, ..)
5970 */
5971 ndesc = tx_len16_to_desc(txp->len16);
5972 last = NULL;
5973 for (i = 0; i < txp->npkt; i++) {
5974 m = txp->mb[i];
5975 if (i & 1 && (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
5976 flitp = &eq->desc[0];
5977 cpl = flitp;
5978
5979 /* Checksum offload */
5980 ctrl1 = csum_to_ctrl(sc, m);
5981 if (ctrl1 != (F_TXPKT_IPCSUM_DIS | F_TXPKT_L4CSUM_DIS))
5982 txq->txcsum++; /* some hardware assistance provided */
5983
5984 /* VLAN tag insertion */
5985 if (needs_vlan_insertion(m)) {
5986 ctrl1 |= F_TXPKT_VLAN_VLD |
5987 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
5988 txq->vlan_insertion++;
5989 } else if (sc->vlan_id)
5990 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(sc->vlan_id);
5991
5992 /* CPL header */
5993 cpl->ctrl0 = txq->cpl_ctrl0;
5994 cpl->pack = 0;
5995 cpl->len = htobe16(m->m_pkthdr.len);
5996 cpl->ctrl1 = htobe64(ctrl1);
5997
5998 flitp = cpl + 1;
5999 MPASS(mbuf_nsegs(m) == 1);
6000 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), 0);
6001
6002 if (last != NULL)
6003 last->m_nextpkt = m;
6004 last = m;
6005 }
6006
6007 txq->sgl_wrs++;
6008 txq->txpkts1_pkts += txp->npkt;
6009 txq->txpkts1_wrs++;
6010
6011 txsd = &txq->sdesc[eq->pidx];
6012 txsd->m = txp->mb[0];
6013 txsd->desc_used = ndesc;
6014
6015 return (ndesc);
6016 }
6017
6018 /*
6019 * If the SGL ends on an address that is not 16 byte aligned, this function will
6020 * add a 0 filled flit at the end.
6021 */
6022 static void
write_gl_to_txd(struct sge_txq * txq,struct mbuf * m,caddr_t * to,int checkwrap)6023 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
6024 {
6025 struct sge_eq *eq = &txq->eq;
6026 struct sglist *gl = txq->gl;
6027 struct sglist_seg *seg;
6028 __be64 *flitp, *wrap;
6029 struct ulptx_sgl *usgl;
6030 int i, nflits, nsegs;
6031
6032 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
6033 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
6034 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
6035 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
6036
6037 get_pkt_gl(m, gl);
6038 nsegs = gl->sg_nseg;
6039 MPASS(nsegs > 0);
6040
6041 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
6042 flitp = (__be64 *)(*to);
6043 wrap = (__be64 *)(&eq->desc[eq->sidx]);
6044 seg = &gl->sg_segs[0];
6045 usgl = (void *)flitp;
6046
6047 /*
6048 * We start at a 16 byte boundary somewhere inside the tx descriptor
6049 * ring, so we're at least 16 bytes away from the status page. There is
6050 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
6051 */
6052
6053 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
6054 V_ULPTX_NSGE(nsegs));
6055 usgl->len0 = htobe32(seg->ss_len);
6056 usgl->addr0 = htobe64(seg->ss_paddr);
6057 seg++;
6058
6059 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
6060
6061 /* Won't wrap around at all */
6062
6063 for (i = 0; i < nsegs - 1; i++, seg++) {
6064 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
6065 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
6066 }
6067 if (i & 1)
6068 usgl->sge[i / 2].len[1] = htobe32(0);
6069 flitp += nflits;
6070 } else {
6071
6072 /* Will wrap somewhere in the rest of the SGL */
6073
6074 /* 2 flits already written, write the rest flit by flit */
6075 flitp = (void *)(usgl + 1);
6076 for (i = 0; i < nflits - 2; i++) {
6077 if (flitp == wrap)
6078 flitp = (void *)eq->desc;
6079 *flitp++ = get_flit(seg, nsegs - 1, i);
6080 }
6081 }
6082
6083 if (nflits & 1) {
6084 MPASS(((uintptr_t)flitp) & 0xf);
6085 *flitp++ = 0;
6086 }
6087
6088 MPASS((((uintptr_t)flitp) & 0xf) == 0);
6089 if (__predict_false(flitp == wrap))
6090 *to = (void *)eq->desc;
6091 else
6092 *to = (void *)flitp;
6093 }
6094
6095 static inline void
copy_to_txd(struct sge_eq * eq,caddr_t from,caddr_t * to,int len)6096 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
6097 {
6098
6099 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
6100 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
6101
6102 if (__predict_true((uintptr_t)(*to) + len <=
6103 (uintptr_t)&eq->desc[eq->sidx])) {
6104 bcopy(from, *to, len);
6105 (*to) += len;
6106 } else {
6107 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
6108
6109 bcopy(from, *to, portion);
6110 from += portion;
6111 portion = len - portion; /* remaining */
6112 bcopy(from, (void *)eq->desc, portion);
6113 (*to) = (caddr_t)eq->desc + portion;
6114 }
6115 }
6116
6117 static inline void
ring_eq_db(struct adapter * sc,struct sge_eq * eq,u_int n)6118 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
6119 {
6120 u_int db;
6121
6122 MPASS(n > 0);
6123
6124 db = eq->doorbells;
6125 if (n > 1)
6126 clrbit(&db, DOORBELL_WCWR);
6127 wmb();
6128
6129 switch (ffs(db) - 1) {
6130 case DOORBELL_UDB:
6131 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
6132 break;
6133
6134 case DOORBELL_WCWR: {
6135 volatile uint64_t *dst, *src;
6136 int i;
6137
6138 /*
6139 * Queues whose 128B doorbell segment fits in the page do not
6140 * use relative qid (udb_qid is always 0). Only queues with
6141 * doorbell segments can do WCWR.
6142 */
6143 KASSERT(eq->udb_qid == 0 && n == 1,
6144 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
6145 __func__, eq->doorbells, n, eq->dbidx, eq));
6146
6147 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
6148 UDBS_DB_OFFSET);
6149 i = eq->dbidx;
6150 src = (void *)&eq->desc[i];
6151 while (src != (void *)&eq->desc[i + 1])
6152 *dst++ = *src++;
6153 wmb();
6154 break;
6155 }
6156
6157 case DOORBELL_UDBWC:
6158 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
6159 wmb();
6160 break;
6161
6162 case DOORBELL_KDB:
6163 t4_write_reg(sc, sc->sge_kdoorbell_reg,
6164 V_QID(eq->cntxt_id) | V_PIDX(n));
6165 break;
6166 }
6167
6168 IDXINCR(eq->dbidx, n, eq->sidx);
6169 }
6170
6171 static inline u_int
reclaimable_tx_desc(struct sge_eq * eq)6172 reclaimable_tx_desc(struct sge_eq *eq)
6173 {
6174 uint16_t hw_cidx;
6175
6176 hw_cidx = read_hw_cidx(eq);
6177 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
6178 }
6179
6180 static inline u_int
total_available_tx_desc(struct sge_eq * eq)6181 total_available_tx_desc(struct sge_eq *eq)
6182 {
6183 uint16_t hw_cidx, pidx;
6184
6185 hw_cidx = read_hw_cidx(eq);
6186 pidx = eq->pidx;
6187
6188 if (pidx == hw_cidx)
6189 return (eq->sidx - 1);
6190 else
6191 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
6192 }
6193
6194 static inline uint16_t
read_hw_cidx(struct sge_eq * eq)6195 read_hw_cidx(struct sge_eq *eq)
6196 {
6197 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
6198 uint16_t cidx = spg->cidx; /* stable snapshot */
6199
6200 return (be16toh(cidx));
6201 }
6202
6203 /*
6204 * Reclaim 'n' descriptors approximately.
6205 */
6206 static u_int
reclaim_tx_descs(struct sge_txq * txq,u_int n)6207 reclaim_tx_descs(struct sge_txq *txq, u_int n)
6208 {
6209 struct tx_sdesc *txsd;
6210 struct sge_eq *eq = &txq->eq;
6211 u_int can_reclaim, reclaimed;
6212
6213 TXQ_LOCK_ASSERT_OWNED(txq);
6214 MPASS(n > 0);
6215
6216 reclaimed = 0;
6217 can_reclaim = reclaimable_tx_desc(eq);
6218 while (can_reclaim && reclaimed < n) {
6219 int ndesc;
6220 struct mbuf *m, *nextpkt;
6221
6222 txsd = &txq->sdesc[eq->cidx];
6223 ndesc = txsd->desc_used;
6224
6225 /* Firmware doesn't return "partial" credits. */
6226 KASSERT(can_reclaim >= ndesc,
6227 ("%s: unexpected number of credits: %d, %d",
6228 __func__, can_reclaim, ndesc));
6229 KASSERT(ndesc != 0,
6230 ("%s: descriptor with no credits: cidx %d",
6231 __func__, eq->cidx));
6232
6233 for (m = txsd->m; m != NULL; m = nextpkt) {
6234 nextpkt = m->m_nextpkt;
6235 m->m_nextpkt = NULL;
6236 m_freem(m);
6237 }
6238 reclaimed += ndesc;
6239 can_reclaim -= ndesc;
6240 IDXINCR(eq->cidx, ndesc, eq->sidx);
6241 }
6242
6243 return (reclaimed);
6244 }
6245
6246 static void
tx_reclaim(void * arg,int n)6247 tx_reclaim(void *arg, int n)
6248 {
6249 struct sge_txq *txq = arg;
6250 struct sge_eq *eq = &txq->eq;
6251
6252 do {
6253 if (TXQ_TRYLOCK(txq) == 0)
6254 break;
6255 n = reclaim_tx_descs(txq, 32);
6256 if (eq->cidx == eq->pidx)
6257 eq->equeqidx = eq->pidx;
6258 TXQ_UNLOCK(txq);
6259 } while (n > 0);
6260 }
6261
6262 static __be64
get_flit(struct sglist_seg * segs,int nsegs,int idx)6263 get_flit(struct sglist_seg *segs, int nsegs, int idx)
6264 {
6265 int i = (idx / 3) * 2;
6266
6267 switch (idx % 3) {
6268 case 0: {
6269 uint64_t rc;
6270
6271 rc = (uint64_t)segs[i].ss_len << 32;
6272 if (i + 1 < nsegs)
6273 rc |= (uint64_t)(segs[i + 1].ss_len);
6274
6275 return (htobe64(rc));
6276 }
6277 case 1:
6278 return (htobe64(segs[i].ss_paddr));
6279 case 2:
6280 return (htobe64(segs[i + 1].ss_paddr));
6281 }
6282
6283 return (0);
6284 }
6285
6286 static int
find_refill_source(struct adapter * sc,int maxp,bool packing)6287 find_refill_source(struct adapter *sc, int maxp, bool packing)
6288 {
6289 int i, zidx = -1;
6290 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0];
6291
6292 if (packing) {
6293 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
6294 if (rxb->hwidx2 == -1)
6295 continue;
6296 if (rxb->size1 < PAGE_SIZE &&
6297 rxb->size1 < largest_rx_cluster)
6298 continue;
6299 if (rxb->size1 > largest_rx_cluster)
6300 break;
6301 MPASS(rxb->size1 - rxb->size2 >= CL_METADATA_SIZE);
6302 if (rxb->size2 >= maxp)
6303 return (i);
6304 zidx = i;
6305 }
6306 } else {
6307 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
6308 if (rxb->hwidx1 == -1)
6309 continue;
6310 if (rxb->size1 > largest_rx_cluster)
6311 break;
6312 if (rxb->size1 >= maxp)
6313 return (i);
6314 zidx = i;
6315 }
6316 }
6317
6318 return (zidx);
6319 }
6320
6321 static void
add_fl_to_sfl(struct adapter * sc,struct sge_fl * fl)6322 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
6323 {
6324 mtx_lock(&sc->sfl_lock);
6325 FL_LOCK(fl);
6326 if ((fl->flags & FL_DOOMED) == 0) {
6327 fl->flags |= FL_STARVING;
6328 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
6329 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
6330 }
6331 FL_UNLOCK(fl);
6332 mtx_unlock(&sc->sfl_lock);
6333 }
6334
6335 static void
handle_wrq_egr_update(struct adapter * sc,struct sge_eq * eq)6336 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
6337 {
6338 struct sge_wrq *wrq = (void *)eq;
6339
6340 atomic_readandclear_int(&eq->equiq);
6341 taskqueue_enqueue(sc->tq[eq->port_id], &wrq->wrq_tx_task);
6342 }
6343
6344 static void
handle_eth_egr_update(struct adapter * sc,struct sge_eq * eq)6345 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
6346 {
6347 struct sge_txq *txq = (void *)eq;
6348
6349 MPASS(eq->type == EQ_ETH);
6350
6351 atomic_readandclear_int(&eq->equiq);
6352 if (mp_ring_is_idle(txq->r))
6353 taskqueue_enqueue(sc->tq[eq->port_id], &txq->tx_reclaim_task);
6354 else
6355 mp_ring_check_drainage(txq->r, 64);
6356 }
6357
6358 static int
handle_sge_egr_update(struct sge_iq * iq,const struct rss_header * rss,struct mbuf * m)6359 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
6360 struct mbuf *m)
6361 {
6362 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
6363 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
6364 struct adapter *sc = iq->adapter;
6365 struct sge *s = &sc->sge;
6366 struct sge_eq *eq;
6367 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
6368 &handle_wrq_egr_update, &handle_eth_egr_update,
6369 &handle_wrq_egr_update};
6370
6371 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
6372 rss->opcode));
6373
6374 eq = s->eqmap[qid - s->eq_start - s->eq_base];
6375 (*h[eq->type])(sc, eq);
6376
6377 return (0);
6378 }
6379
6380 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
6381 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
6382 offsetof(struct cpl_fw6_msg, data));
6383
6384 static int
handle_fw_msg(struct sge_iq * iq,const struct rss_header * rss,struct mbuf * m)6385 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
6386 {
6387 struct adapter *sc = iq->adapter;
6388 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
6389
6390 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
6391 rss->opcode));
6392
6393 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
6394 const struct rss_header *rss2;
6395
6396 rss2 = (const struct rss_header *)&cpl->data[0];
6397 return (t4_cpl_handler[rss2->opcode](iq, rss2, m));
6398 }
6399
6400 return (t4_fw_msg_handler[cpl->type](sc, &cpl->data[0]));
6401 }
6402
6403 /**
6404 * t4_handle_wrerr_rpl - process a FW work request error message
6405 * @adap: the adapter
6406 * @rpl: start of the FW message
6407 */
6408 static int
t4_handle_wrerr_rpl(struct adapter * adap,const __be64 * rpl)6409 t4_handle_wrerr_rpl(struct adapter *adap, const __be64 *rpl)
6410 {
6411 u8 opcode = *(const u8 *)rpl;
6412 const struct fw_error_cmd *e = (const void *)rpl;
6413 unsigned int i;
6414
6415 if (opcode != FW_ERROR_CMD) {
6416 log(LOG_ERR,
6417 "%s: Received WRERR_RPL message with opcode %#x\n",
6418 device_get_nameunit(adap->dev), opcode);
6419 return (EINVAL);
6420 }
6421 log(LOG_ERR, "%s: FW_ERROR (%s) ", device_get_nameunit(adap->dev),
6422 G_FW_ERROR_CMD_FATAL(be32toh(e->op_to_type)) ? "fatal" :
6423 "non-fatal");
6424 switch (G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type))) {
6425 case FW_ERROR_TYPE_EXCEPTION:
6426 log(LOG_ERR, "exception info:\n");
6427 for (i = 0; i < nitems(e->u.exception.info); i++)
6428 log(LOG_ERR, "%s%08x", i == 0 ? "\t" : " ",
6429 be32toh(e->u.exception.info[i]));
6430 log(LOG_ERR, "\n");
6431 break;
6432 case FW_ERROR_TYPE_HWMODULE:
6433 log(LOG_ERR, "HW module regaddr %08x regval %08x\n",
6434 be32toh(e->u.hwmodule.regaddr),
6435 be32toh(e->u.hwmodule.regval));
6436 break;
6437 case FW_ERROR_TYPE_WR:
6438 log(LOG_ERR, "WR cidx %d PF %d VF %d eqid %d hdr:\n",
6439 be16toh(e->u.wr.cidx),
6440 G_FW_ERROR_CMD_PFN(be16toh(e->u.wr.pfn_vfn)),
6441 G_FW_ERROR_CMD_VFN(be16toh(e->u.wr.pfn_vfn)),
6442 be32toh(e->u.wr.eqid));
6443 for (i = 0; i < nitems(e->u.wr.wrhdr); i++)
6444 log(LOG_ERR, "%s%02x", i == 0 ? "\t" : " ",
6445 e->u.wr.wrhdr[i]);
6446 log(LOG_ERR, "\n");
6447 break;
6448 case FW_ERROR_TYPE_ACL:
6449 log(LOG_ERR, "ACL cidx %d PF %d VF %d eqid %d %s",
6450 be16toh(e->u.acl.cidx),
6451 G_FW_ERROR_CMD_PFN(be16toh(e->u.acl.pfn_vfn)),
6452 G_FW_ERROR_CMD_VFN(be16toh(e->u.acl.pfn_vfn)),
6453 be32toh(e->u.acl.eqid),
6454 G_FW_ERROR_CMD_MV(be16toh(e->u.acl.mv_pkd)) ? "vlanid" :
6455 "MAC");
6456 for (i = 0; i < nitems(e->u.acl.val); i++)
6457 log(LOG_ERR, " %02x", e->u.acl.val[i]);
6458 log(LOG_ERR, "\n");
6459 break;
6460 default:
6461 log(LOG_ERR, "type %#x\n",
6462 G_FW_ERROR_CMD_TYPE(be32toh(e->op_to_type)));
6463 return (EINVAL);
6464 }
6465 return (0);
6466 }
6467
6468 static inline bool
bufidx_used(struct adapter * sc,int idx)6469 bufidx_used(struct adapter *sc, int idx)
6470 {
6471 struct rx_buf_info *rxb = &sc->sge.rx_buf_info[0];
6472 int i;
6473
6474 for (i = 0; i < SW_ZONE_SIZES; i++, rxb++) {
6475 if (rxb->size1 > largest_rx_cluster)
6476 continue;
6477 if (rxb->hwidx1 == idx || rxb->hwidx2 == idx)
6478 return (true);
6479 }
6480
6481 return (false);
6482 }
6483
6484 static int
sysctl_bufsizes(SYSCTL_HANDLER_ARGS)6485 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
6486 {
6487 struct adapter *sc = arg1;
6488 struct sge_params *sp = &sc->params.sge;
6489 int i, rc;
6490 struct sbuf sb;
6491 char c;
6492
6493 sbuf_new(&sb, NULL, 128, SBUF_AUTOEXTEND);
6494 for (i = 0; i < SGE_FLBUF_SIZES; i++) {
6495 if (bufidx_used(sc, i))
6496 c = '*';
6497 else
6498 c = '\0';
6499
6500 sbuf_printf(&sb, "%u%c ", sp->sge_fl_buffer_size[i], c);
6501 }
6502 sbuf_trim(&sb);
6503 sbuf_finish(&sb);
6504 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
6505 sbuf_delete(&sb);
6506 return (rc);
6507 }
6508
6509 #ifdef RATELIMIT
6510 #if defined(INET) || defined(INET6)
6511 /*
6512 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
6513 */
6514 static inline u_int
txpkt_eo_len16(u_int nsegs,u_int immhdrs,u_int tso)6515 txpkt_eo_len16(u_int nsegs, u_int immhdrs, u_int tso)
6516 {
6517 u_int n;
6518
6519 MPASS(immhdrs > 0);
6520
6521 n = roundup2(sizeof(struct fw_eth_tx_eo_wr) +
6522 sizeof(struct cpl_tx_pkt_core) + immhdrs, 16);
6523 if (__predict_false(nsegs == 0))
6524 goto done;
6525
6526 nsegs--; /* first segment is part of ulptx_sgl */
6527 n += sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
6528 if (tso)
6529 n += sizeof(struct cpl_tx_pkt_lso_core);
6530
6531 done:
6532 return (howmany(n, 16));
6533 }
6534 #endif
6535
6536 #define ETID_FLOWC_NPARAMS 6
6537 #define ETID_FLOWC_LEN (roundup2((sizeof(struct fw_flowc_wr) + \
6538 ETID_FLOWC_NPARAMS * sizeof(struct fw_flowc_mnemval)), 16))
6539 #define ETID_FLOWC_LEN16 (howmany(ETID_FLOWC_LEN, 16))
6540
6541 #if defined(INET) || defined(INET6)
6542 static int
send_etid_flowc_wr(struct cxgbe_rate_tag * cst,struct port_info * pi,struct vi_info * vi)6543 send_etid_flowc_wr(struct cxgbe_rate_tag *cst, struct port_info *pi,
6544 struct vi_info *vi)
6545 {
6546 struct wrq_cookie cookie;
6547 u_int pfvf = pi->adapter->pf << S_FW_VIID_PFN;
6548 struct fw_flowc_wr *flowc;
6549
6550 mtx_assert(&cst->lock, MA_OWNED);
6551 MPASS((cst->flags & (EO_FLOWC_PENDING | EO_FLOWC_RPL_PENDING)) ==
6552 EO_FLOWC_PENDING);
6553
6554 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLOWC_LEN16, &cookie);
6555 if (__predict_false(flowc == NULL))
6556 return (ENOMEM);
6557
6558 bzero(flowc, ETID_FLOWC_LEN);
6559 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
6560 V_FW_FLOWC_WR_NPARAMS(ETID_FLOWC_NPARAMS) | V_FW_WR_COMPL(0));
6561 flowc->flowid_len16 = htonl(V_FW_WR_LEN16(ETID_FLOWC_LEN16) |
6562 V_FW_WR_FLOWID(cst->etid));
6563 flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN;
6564 flowc->mnemval[0].val = htobe32(pfvf);
6565 flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH;
6566 flowc->mnemval[1].val = htobe32(pi->tx_chan);
6567 flowc->mnemval[2].mnemonic = FW_FLOWC_MNEM_PORT;
6568 flowc->mnemval[2].val = htobe32(pi->tx_chan);
6569 flowc->mnemval[3].mnemonic = FW_FLOWC_MNEM_IQID;
6570 flowc->mnemval[3].val = htobe32(cst->iqid);
6571 flowc->mnemval[4].mnemonic = FW_FLOWC_MNEM_EOSTATE;
6572 flowc->mnemval[4].val = htobe32(FW_FLOWC_MNEM_EOSTATE_ESTABLISHED);
6573 flowc->mnemval[5].mnemonic = FW_FLOWC_MNEM_SCHEDCLASS;
6574 flowc->mnemval[5].val = htobe32(cst->schedcl);
6575
6576 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie);
6577
6578 cst->flags &= ~EO_FLOWC_PENDING;
6579 cst->flags |= EO_FLOWC_RPL_PENDING;
6580 MPASS(cst->tx_credits >= ETID_FLOWC_LEN16); /* flowc is first WR. */
6581 cst->tx_credits -= ETID_FLOWC_LEN16;
6582
6583 return (0);
6584 }
6585 #endif
6586
6587 #define ETID_FLUSH_LEN16 (howmany(sizeof (struct fw_flowc_wr), 16))
6588
6589 void
send_etid_flush_wr(struct cxgbe_rate_tag * cst)6590 send_etid_flush_wr(struct cxgbe_rate_tag *cst)
6591 {
6592 struct fw_flowc_wr *flowc;
6593 struct wrq_cookie cookie;
6594
6595 mtx_assert(&cst->lock, MA_OWNED);
6596
6597 flowc = start_wrq_wr(&cst->eo_txq->wrq, ETID_FLUSH_LEN16, &cookie);
6598 if (__predict_false(flowc == NULL))
6599 CXGBE_UNIMPLEMENTED(__func__);
6600
6601 bzero(flowc, ETID_FLUSH_LEN16 * 16);
6602 flowc->op_to_nparams = htobe32(V_FW_WR_OP(FW_FLOWC_WR) |
6603 V_FW_FLOWC_WR_NPARAMS(0) | F_FW_WR_COMPL);
6604 flowc->flowid_len16 = htobe32(V_FW_WR_LEN16(ETID_FLUSH_LEN16) |
6605 V_FW_WR_FLOWID(cst->etid));
6606
6607 commit_wrq_wr(&cst->eo_txq->wrq, flowc, &cookie);
6608
6609 cst->flags |= EO_FLUSH_RPL_PENDING;
6610 MPASS(cst->tx_credits >= ETID_FLUSH_LEN16);
6611 cst->tx_credits -= ETID_FLUSH_LEN16;
6612 cst->ncompl++;
6613 }
6614
6615 static void
write_ethofld_wr(struct cxgbe_rate_tag * cst,struct fw_eth_tx_eo_wr * wr,struct mbuf * m0,int compl)6616 write_ethofld_wr(struct cxgbe_rate_tag *cst, struct fw_eth_tx_eo_wr *wr,
6617 struct mbuf *m0, int compl)
6618 {
6619 struct cpl_tx_pkt_core *cpl;
6620 uint64_t ctrl1;
6621 uint32_t ctrl; /* used in many unrelated places */
6622 int len16, pktlen, nsegs, immhdrs;
6623 uintptr_t p;
6624 struct ulptx_sgl *usgl;
6625 struct sglist sg;
6626 struct sglist_seg segs[38]; /* XXX: find real limit. XXX: get off the stack */
6627
6628 mtx_assert(&cst->lock, MA_OWNED);
6629 M_ASSERTPKTHDR(m0);
6630 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
6631 m0->m_pkthdr.l4hlen > 0,
6632 ("%s: ethofld mbuf %p is missing header lengths", __func__, m0));
6633
6634 len16 = mbuf_eo_len16(m0);
6635 nsegs = mbuf_eo_nsegs(m0);
6636 pktlen = m0->m_pkthdr.len;
6637 ctrl = sizeof(struct cpl_tx_pkt_core);
6638 if (needs_tso(m0))
6639 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
6640 immhdrs = m0->m_pkthdr.l2hlen + m0->m_pkthdr.l3hlen + m0->m_pkthdr.l4hlen;
6641 ctrl += immhdrs;
6642
6643 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_EO_WR) |
6644 V_FW_ETH_TX_EO_WR_IMMDLEN(ctrl) | V_FW_WR_COMPL(!!compl));
6645 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(len16) |
6646 V_FW_WR_FLOWID(cst->etid));
6647 wr->r3 = 0;
6648 if (needs_outer_udp_csum(m0)) {
6649 wr->u.udpseg.type = FW_ETH_TX_EO_TYPE_UDPSEG;
6650 wr->u.udpseg.ethlen = m0->m_pkthdr.l2hlen;
6651 wr->u.udpseg.iplen = htobe16(m0->m_pkthdr.l3hlen);
6652 wr->u.udpseg.udplen = m0->m_pkthdr.l4hlen;
6653 wr->u.udpseg.rtplen = 0;
6654 wr->u.udpseg.r4 = 0;
6655 wr->u.udpseg.mss = htobe16(pktlen - immhdrs);
6656 wr->u.udpseg.schedpktsize = wr->u.udpseg.mss;
6657 wr->u.udpseg.plen = htobe32(pktlen - immhdrs);
6658 cpl = (void *)(wr + 1);
6659 } else {
6660 MPASS(needs_outer_tcp_csum(m0));
6661 wr->u.tcpseg.type = FW_ETH_TX_EO_TYPE_TCPSEG;
6662 wr->u.tcpseg.ethlen = m0->m_pkthdr.l2hlen;
6663 wr->u.tcpseg.iplen = htobe16(m0->m_pkthdr.l3hlen);
6664 wr->u.tcpseg.tcplen = m0->m_pkthdr.l4hlen;
6665 wr->u.tcpseg.tsclk_tsoff = mbuf_eo_tsclk_tsoff(m0);
6666 wr->u.tcpseg.r4 = 0;
6667 wr->u.tcpseg.r5 = 0;
6668 wr->u.tcpseg.plen = htobe32(pktlen - immhdrs);
6669
6670 if (needs_tso(m0)) {
6671 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
6672
6673 wr->u.tcpseg.mss = htobe16(m0->m_pkthdr.tso_segsz);
6674
6675 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) |
6676 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE |
6677 V_LSO_ETHHDR_LEN((m0->m_pkthdr.l2hlen -
6678 ETHER_HDR_LEN) >> 2) |
6679 V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2) |
6680 V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
6681 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
6682 ctrl |= F_LSO_IPV6;
6683 lso->lso_ctrl = htobe32(ctrl);
6684 lso->ipid_ofst = htobe16(0);
6685 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
6686 lso->seqno_offset = htobe32(0);
6687 lso->len = htobe32(pktlen);
6688
6689 cpl = (void *)(lso + 1);
6690 } else {
6691 wr->u.tcpseg.mss = htobe16(0xffff);
6692 cpl = (void *)(wr + 1);
6693 }
6694 }
6695
6696 /* Checksum offload must be requested for ethofld. */
6697 MPASS(needs_outer_l4_csum(m0));
6698 ctrl1 = csum_to_ctrl(cst->adapter, m0);
6699
6700 /* VLAN tag insertion */
6701 if (needs_vlan_insertion(m0)) {
6702 ctrl1 |= F_TXPKT_VLAN_VLD |
6703 V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
6704 }
6705
6706 /* CPL header */
6707 cpl->ctrl0 = cst->ctrl0;
6708 cpl->pack = 0;
6709 cpl->len = htobe16(pktlen);
6710 cpl->ctrl1 = htobe64(ctrl1);
6711
6712 /* Copy Ethernet, IP & TCP/UDP hdrs as immediate data */
6713 p = (uintptr_t)(cpl + 1);
6714 m_copydata(m0, 0, immhdrs, (void *)p);
6715
6716 /* SGL */
6717 if (nsegs > 0) {
6718 int i, pad;
6719
6720 /* zero-pad upto next 16Byte boundary, if not 16Byte aligned */
6721 p += immhdrs;
6722 pad = 16 - (immhdrs & 0xf);
6723 bzero((void *)p, pad);
6724
6725 usgl = (void *)(p + pad);
6726 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
6727 V_ULPTX_NSGE(nsegs));
6728
6729 sglist_init(&sg, nitems(segs), segs);
6730 for (; m0 != NULL; m0 = m0->m_next) {
6731 if (__predict_false(m0->m_len == 0))
6732 continue;
6733 if (immhdrs >= m0->m_len) {
6734 immhdrs -= m0->m_len;
6735 continue;
6736 }
6737 if (m0->m_flags & M_EXTPG)
6738 sglist_append_mbuf_epg(&sg, m0,
6739 mtod(m0, vm_offset_t), m0->m_len);
6740 else
6741 sglist_append(&sg, mtod(m0, char *) + immhdrs,
6742 m0->m_len - immhdrs);
6743 immhdrs = 0;
6744 }
6745 MPASS(sg.sg_nseg == nsegs);
6746
6747 /*
6748 * Zero pad last 8B in case the WR doesn't end on a 16B
6749 * boundary.
6750 */
6751 *(uint64_t *)((char *)wr + len16 * 16 - 8) = 0;
6752
6753 usgl->len0 = htobe32(segs[0].ss_len);
6754 usgl->addr0 = htobe64(segs[0].ss_paddr);
6755 for (i = 0; i < nsegs - 1; i++) {
6756 usgl->sge[i / 2].len[i & 1] = htobe32(segs[i + 1].ss_len);
6757 usgl->sge[i / 2].addr[i & 1] = htobe64(segs[i + 1].ss_paddr);
6758 }
6759 if (i & 1)
6760 usgl->sge[i / 2].len[1] = htobe32(0);
6761 }
6762
6763 }
6764
6765 static void
ethofld_tx(struct cxgbe_rate_tag * cst)6766 ethofld_tx(struct cxgbe_rate_tag *cst)
6767 {
6768 struct mbuf *m;
6769 struct wrq_cookie cookie;
6770 int next_credits, compl;
6771 struct fw_eth_tx_eo_wr *wr;
6772
6773 mtx_assert(&cst->lock, MA_OWNED);
6774
6775 while ((m = mbufq_first(&cst->pending_tx)) != NULL) {
6776 M_ASSERTPKTHDR(m);
6777
6778 /* How many len16 credits do we need to send this mbuf. */
6779 next_credits = mbuf_eo_len16(m);
6780 MPASS(next_credits > 0);
6781 if (next_credits > cst->tx_credits) {
6782 /*
6783 * Tx will make progress eventually because there is at
6784 * least one outstanding fw4_ack that will return
6785 * credits and kick the tx.
6786 */
6787 MPASS(cst->ncompl > 0);
6788 return;
6789 }
6790 wr = start_wrq_wr(&cst->eo_txq->wrq, next_credits, &cookie);
6791 if (__predict_false(wr == NULL)) {
6792 /* XXX: wishful thinking, not a real assertion. */
6793 MPASS(cst->ncompl > 0);
6794 return;
6795 }
6796 cst->tx_credits -= next_credits;
6797 cst->tx_nocompl += next_credits;
6798 compl = cst->ncompl == 0 || cst->tx_nocompl >= cst->tx_total / 2;
6799 ETHER_BPF_MTAP(cst->com.ifp, m);
6800 write_ethofld_wr(cst, wr, m, compl);
6801 commit_wrq_wr(&cst->eo_txq->wrq, wr, &cookie);
6802 if (compl) {
6803 cst->ncompl++;
6804 cst->tx_nocompl = 0;
6805 }
6806 (void) mbufq_dequeue(&cst->pending_tx);
6807
6808 /*
6809 * Drop the mbuf's reference on the tag now rather
6810 * than waiting until m_freem(). This ensures that
6811 * cxgbe_rate_tag_free gets called when the inp drops
6812 * its reference on the tag and there are no more
6813 * mbufs in the pending_tx queue and can flush any
6814 * pending requests. Otherwise if the last mbuf
6815 * doesn't request a completion the etid will never be
6816 * released.
6817 */
6818 m->m_pkthdr.snd_tag = NULL;
6819 m->m_pkthdr.csum_flags &= ~CSUM_SND_TAG;
6820 m_snd_tag_rele(&cst->com);
6821
6822 mbufq_enqueue(&cst->pending_fwack, m);
6823 }
6824 }
6825
6826 #if defined(INET) || defined(INET6)
6827 static int
ethofld_transmit(if_t ifp,struct mbuf * m0)6828 ethofld_transmit(if_t ifp, struct mbuf *m0)
6829 {
6830 struct cxgbe_rate_tag *cst;
6831 int rc;
6832
6833 MPASS(m0->m_nextpkt == NULL);
6834 MPASS(m0->m_pkthdr.csum_flags & CSUM_SND_TAG);
6835 MPASS(m0->m_pkthdr.snd_tag != NULL);
6836 cst = mst_to_crt(m0->m_pkthdr.snd_tag);
6837
6838 mtx_lock(&cst->lock);
6839 MPASS(cst->flags & EO_SND_TAG_REF);
6840
6841 if (__predict_false(cst->flags & EO_FLOWC_PENDING)) {
6842 struct vi_info *vi = if_getsoftc(ifp);
6843 struct port_info *pi = vi->pi;
6844 struct adapter *sc = pi->adapter;
6845 const uint32_t rss_mask = vi->rss_size - 1;
6846 uint32_t rss_hash;
6847
6848 cst->eo_txq = &sc->sge.ofld_txq[vi->first_ofld_txq];
6849 if (M_HASHTYPE_ISHASH(m0))
6850 rss_hash = m0->m_pkthdr.flowid;
6851 else
6852 rss_hash = arc4random();
6853 /* We assume RSS hashing */
6854 cst->iqid = vi->rss[rss_hash & rss_mask];
6855 cst->eo_txq += rss_hash % vi->nofldtxq;
6856 rc = send_etid_flowc_wr(cst, pi, vi);
6857 if (rc != 0)
6858 goto done;
6859 }
6860
6861 if (__predict_false(cst->plen + m0->m_pkthdr.len > eo_max_backlog)) {
6862 rc = ENOBUFS;
6863 goto done;
6864 }
6865
6866 mbufq_enqueue(&cst->pending_tx, m0);
6867 cst->plen += m0->m_pkthdr.len;
6868
6869 /*
6870 * Hold an extra reference on the tag while generating work
6871 * requests to ensure that we don't try to free the tag during
6872 * ethofld_tx() in case we are sending the final mbuf after
6873 * the inp was freed.
6874 */
6875 m_snd_tag_ref(&cst->com);
6876 ethofld_tx(cst);
6877 mtx_unlock(&cst->lock);
6878 m_snd_tag_rele(&cst->com);
6879 return (0);
6880
6881 done:
6882 mtx_unlock(&cst->lock);
6883 return (rc);
6884 }
6885 #endif
6886
6887 static int
ethofld_fw4_ack(struct sge_iq * iq,const struct rss_header * rss,struct mbuf * m0)6888 ethofld_fw4_ack(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
6889 {
6890 struct adapter *sc = iq->adapter;
6891 const struct cpl_fw4_ack *cpl = (const void *)(rss + 1);
6892 struct mbuf *m;
6893 u_int etid = G_CPL_FW4_ACK_FLOWID(be32toh(OPCODE_TID(cpl)));
6894 struct cxgbe_rate_tag *cst;
6895 uint8_t credits = cpl->credits;
6896
6897 cst = lookup_etid(sc, etid);
6898 mtx_lock(&cst->lock);
6899 if (__predict_false(cst->flags & EO_FLOWC_RPL_PENDING)) {
6900 MPASS(credits >= ETID_FLOWC_LEN16);
6901 credits -= ETID_FLOWC_LEN16;
6902 cst->flags &= ~EO_FLOWC_RPL_PENDING;
6903 }
6904
6905 KASSERT(cst->ncompl > 0,
6906 ("%s: etid %u (%p) wasn't expecting completion.",
6907 __func__, etid, cst));
6908 cst->ncompl--;
6909
6910 while (credits > 0) {
6911 m = mbufq_dequeue(&cst->pending_fwack);
6912 if (__predict_false(m == NULL)) {
6913 /*
6914 * The remaining credits are for the final flush that
6915 * was issued when the tag was freed by the kernel.
6916 */
6917 MPASS((cst->flags &
6918 (EO_FLUSH_RPL_PENDING | EO_SND_TAG_REF)) ==
6919 EO_FLUSH_RPL_PENDING);
6920 MPASS(credits == ETID_FLUSH_LEN16);
6921 MPASS(cst->tx_credits + cpl->credits == cst->tx_total);
6922 MPASS(cst->ncompl == 0);
6923
6924 cst->flags &= ~EO_FLUSH_RPL_PENDING;
6925 cst->tx_credits += cpl->credits;
6926 cxgbe_rate_tag_free_locked(cst);
6927 return (0); /* cst is gone. */
6928 }
6929 KASSERT(m != NULL,
6930 ("%s: too many credits (%u, %u)", __func__, cpl->credits,
6931 credits));
6932 KASSERT(credits >= mbuf_eo_len16(m),
6933 ("%s: too few credits (%u, %u, %u)", __func__,
6934 cpl->credits, credits, mbuf_eo_len16(m)));
6935 credits -= mbuf_eo_len16(m);
6936 cst->plen -= m->m_pkthdr.len;
6937 m_freem(m);
6938 }
6939
6940 cst->tx_credits += cpl->credits;
6941 MPASS(cst->tx_credits <= cst->tx_total);
6942
6943 if (cst->flags & EO_SND_TAG_REF) {
6944 /*
6945 * As with ethofld_transmit(), hold an extra reference
6946 * so that the tag is stable across ethold_tx().
6947 */
6948 m_snd_tag_ref(&cst->com);
6949 m = mbufq_first(&cst->pending_tx);
6950 if (m != NULL && cst->tx_credits >= mbuf_eo_len16(m))
6951 ethofld_tx(cst);
6952 mtx_unlock(&cst->lock);
6953 m_snd_tag_rele(&cst->com);
6954 } else {
6955 /*
6956 * There shouldn't be any pending packets if the tag
6957 * was freed by the kernel since any pending packet
6958 * should hold a reference to the tag.
6959 */
6960 MPASS(mbufq_first(&cst->pending_tx) == NULL);
6961 mtx_unlock(&cst->lock);
6962 }
6963
6964 return (0);
6965 }
6966 #endif
6967