1 #ifndef IVL_PWire_H
2 #define IVL_PWire_H
3 /*
4  * Copyright (c) 1998-2019 Stephen Williams (steve@icarus.com)
5  *
6  *    This source code is free software; you can redistribute it
7  *    and/or modify it in source code form under the terms of the GNU
8  *    General Public License as published by the Free Software
9  *    Foundation; either version 2 of the License, or (at your option)
10  *    any later version.
11  *
12  *    This program is distributed in the hope that it will be useful,
13  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
14  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  *    GNU General Public License for more details.
16  *
17  *    You should have received a copy of the GNU General Public License
18  *    along with this program; if not, write to the Free Software
19  *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20  */
21 
22 # include  "netlist.h"
23 # include  "PNamedItem.h"
24 # include  <list>
25 # include  <map>
26 # include  "StringHeap.h"
27 
28 #ifdef HAVE_IOSFWD
29 # include  <iosfwd>
30 #else
31 class ostream;
32 #endif
33 
34 class PExpr;
35 class Design;
36 class netdarray_t;
37 
38 /*
39  * The different type of PWire::set_range() calls.
40  */
41 enum PWSRType {SR_PORT, SR_NET, SR_BOTH};
42 
43 /*
44  * Wires include nets, registers and ports. A net or register becomes
45  * a port by declaration, so ports are not separate. The module
46  * identifies a port by keeping it in its port list.
47  *
48  * The hname parameter to the constructor is a hierarchical name. It
49  * is the name of the wire within a module, so does not include the
50  * current scope or any instances. Modules contain all the wires, so
51  * from that perspective, sub-scopes within the module are a part of
52  * the wire name.
53  */
54 class PWire : public PNamedItem {
55 
56     public:
57       PWire(perm_string name,
58 	    NetNet::Type t,
59 	    NetNet::PortType pt,
60 	    ivl_variable_type_t dt);
61 
62 	// Return a hierarchical name.
63       perm_string basename() const;
64 
65       NetNet::Type get_wire_type() const;
66       bool set_wire_type(NetNet::Type);
67 
68       NetNet::PortType get_port_type() const;
69       bool set_port_type(NetNet::PortType);
70 
71       void set_signed(bool flag);
72       bool get_signed() const;
73       bool get_isint() const;
74       bool get_scalar() const;
75 
76       bool set_data_type(ivl_variable_type_t dt);
77       ivl_variable_type_t get_data_type() const;
78 
79       void set_range_scalar(PWSRType type);
80       void set_range(const std::list<pform_range_t>&ranges, PWSRType type);
81 
82       void set_unpacked_idx(const std::list<pform_range_t>&ranges);
set_uarray_type(uarray_type_t * type)83       void set_uarray_type(uarray_type_t*type) { uarray_type_ = type; }
84 
85       void set_data_type(data_type_t*type);
86 
87       void set_discipline(ivl_discipline_t);
88       ivl_discipline_t get_discipline(void) const;
89 
90       map<perm_string,PExpr*> attributes;
91 
92 	// Write myself to the specified stream.
93       void dump(ostream&out, unsigned ind=4) const;
94 
95       NetNet* elaborate_sig(Design*, NetScope*scope) const;
96 
97       SymbolType symbol_type() const;
98 
99     private:
100       perm_string name_;
101       NetNet::Type type_;
102       NetNet::PortType port_type_;
103       ivl_variable_type_t data_type_;
104       bool signed_;
105       bool isint_;		// original type of integer
106 
107 	// These members hold expressions for the bit width of the
108 	// wire. If they do not exist, the wire is 1 bit wide. If they
109 	// do exist, they represent the packed dimensions of the
110 	// bit. The first item in the list is the first range, and so
111 	// on. For example "reg [3:0][7:0] ..." will contains the
112 	// range_t object for [3:0] first and [7:0] last.
113       std::list<pform_range_t>port_;
114       bool port_set_;
115       std::list<pform_range_t>net_;
116       bool net_set_;
117       bool is_scalar_;
118       unsigned error_cnt_;
119 
120 	// If this wire is actually a memory, these indices will give
121 	// me the size and address ranges of the memory.
122       std::list<pform_range_t>unpacked_;
123       uarray_type_t*uarray_type_;
124 
125 	// This is the complex type of the wire. the data_type_ may
126 	// modify how this is interpreted.
127       data_type_t*set_data_type_;
128 
129       ivl_discipline_t discipline_;
130 
131     private: // not implemented
132       PWire(const PWire&);
133       PWire& operator= (const PWire&);
134 };
135 
136 #endif /* IVL_PWire_H */
137