1 /*
2 * Copyright (c) 1988 Regents of the University of California.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to Berkeley by
6 * Digital Equipment Corp.
7 *
8 * %sccs.include.redist.c%
9 *
10 * @(#)if_qe.c 7.21 (Berkeley) 05/04/92
11 */
12
13 /* from @(#)if_qe.c 1.15 (ULTRIX) 4/16/86 */
14
15 /****************************************************************
16 * *
17 * Licensed from Digital Equipment Corporation *
18 * Copyright (c) *
19 * Digital Equipment Corporation *
20 * Maynard, Massachusetts *
21 * 1985, 1986 *
22 * All rights reserved. *
23 * *
24 * The Information in this software is subject to change *
25 * without notice and should not be construed as a commitment *
26 * by Digital Equipment Corporation. Digital makes no *
27 * representations about the suitability of this software for *
28 * any purpose. It is supplied "As Is" without expressed or *
29 * implied warranty. *
30 * *
31 * If the Regents of the University of California or its *
32 * licensees modify the software in a manner creating *
33 * derivative copyright rights, appropriate copyright *
34 * legends may be placed on the derivative work in addition *
35 * to that set forth above. *
36 * *
37 ****************************************************************/
38 /* ---------------------------------------------------------------------
39 * Modification History
40 *
41 * 15-Apr-86 -- afd
42 * Rename "unused_multi" to "qunused_multi" for extending Generic
43 * kernel to MicroVAXen.
44 *
45 * 18-mar-86 -- jaw br/cvec changed to NOT use registers.
46 *
47 * 12 March 86 -- Jeff Chase
48 * Modified to handle the new MCLGET macro
49 * Changed if_qe_data.c to use more receive buffers
50 * Added a flag to poke with adb to log qe_restarts on console
51 *
52 * 19 Oct 85 -- rjl
53 * Changed the watch dog timer from 30 seconds to 3. VMS is using
54 * less than 1 second in their's. Also turned the printf into an
55 * mprintf.
56 *
57 * 09/16/85 -- Larry Cohen
58 * Add 43bsd alpha tape changes for subnet routing
59 *
60 * 1 Aug 85 -- rjl
61 * Panic on a non-existent memory interrupt and the case where a packet
62 * was chained. The first should never happen because non-existant
63 * memory interrupts cause a bus reset. The second should never happen
64 * because we hang 2k input buffers on the device.
65 *
66 * 1 Aug 85 -- rich
67 * Fixed the broadcast loopback code to handle Clusters without
68 * wedging the system.
69 *
70 * 27 Feb. 85 -- ejf
71 * Return default hardware address on ioctl request.
72 *
73 * 12 Feb. 85 -- ejf
74 * Added internal extended loopback capability.
75 *
76 * 27 Dec. 84 -- rjl
77 * Fixed bug that caused every other transmit descriptor to be used
78 * instead of every descriptor.
79 *
80 * 21 Dec. 84 -- rjl
81 * Added watchdog timer to mask hardware bug that causes device lockup.
82 *
83 * 18 Dec. 84 -- rjl
84 * Reworked driver to use q-bus mapping routines. MicroVAX-I now does
85 * copying instead of m-buf shuffleing.
86 * A number of deficencies in the hardware/firmware were compensated
87 * for. See comments in qestart and qerint.
88 *
89 * 14 Nov. 84 -- jf
90 * Added usage counts for multicast addresses.
91 * Updated general protocol support to allow access to the Ethernet
92 * header.
93 *
94 * 04 Oct. 84 -- jf
95 * Added support for new ioctls to add and delete multicast addresses
96 * and set the physical address.
97 * Add support for general protocols.
98 *
99 * 14 Aug. 84 -- rjl
100 * Integrated Shannon changes. (allow arp above 1024 and ? )
101 *
102 * 13 Feb. 84 -- rjl
103 *
104 * Initial version of driver. derived from IL driver.
105 *
106 * ---------------------------------------------------------------------
107 */
108
109 #include "qe.h"
110 #if NQE > 0
111 /*
112 * Digital Q-BUS to NI Adapter
113 */
114 #include "sys/param.h"
115 #include "sys/systm.h"
116 #include "sys/mbuf.h"
117 #include "sys/buf.h"
118 #include "sys/protosw.h"
119 #include "sys/socket.h"
120 #include "sys/vmmac.h"
121 #include "sys/ioctl.h"
122 #include "sys/errno.h"
123 #include "sys/syslog.h"
124 #include "sys/time.h"
125 #include "sys/kernel.h"
126
127 #include "net/if.h"
128 #include "net/netisr.h"
129 #include "net/route.h"
130
131 #ifdef INET
132 #include "netinet/in.h"
133 #include "netinet/in_systm.h"
134 #include "netinet/in_var.h"
135 #include "netinet/ip.h"
136 #include "netinet/if_ether.h"
137 #endif
138
139 #ifdef NS
140 #include "netns/ns.h"
141 #include "netns/ns_if.h"
142 #endif
143
144 #ifdef ISO
145 #include "netiso/iso.h"
146 #include "netiso/iso_var.h"
147 extern char all_es_snpa[], all_is_snpa[], all_l1is_snpa[], all_l2is_snpa[];
148 #endif
149
150 #include "../include/pte.h"
151 #include "../include/cpu.h"
152 #include "../include/mtpr.h"
153 #include "if_qereg.h"
154 #include "if_uba.h"
155 #include "../uba/ubareg.h"
156 #include "../uba/ubavar.h"
157
158 #if NQE == 1 && !defined(QNIVERT)
159 #define NRCV 15 /* Receive descriptors */
160 #else
161 #define NRCV 10 /* Receive descriptors */
162 #endif
163 #define NXMT 5 /* Transmit descriptors */
164 #define NTOT (NXMT + NRCV)
165
166 #define QETIMEOUT 2 /* transmit timeout, must be > 1 */
167 #define QESLOWTIMEOUT 40 /* timeout when no xmits in progress */
168
169 #define MINDATA 60
170
171 /*
172 * Ethernet software status per interface.
173 *
174 * Each interface is referenced by a network interface structure,
175 * qe_if, which the routing code uses to locate the interface.
176 * This structure contains the output queue for the interface, its address, ...
177 */
178 struct qe_softc {
179 struct arpcom qe_ac; /* Ethernet common part */
180 #define qe_if qe_ac.ac_if /* network-visible interface */
181 #define qe_addr qe_ac.ac_enaddr /* hardware Ethernet address */
182 struct ifubinfo qe_uba; /* Q-bus resources */
183 struct ifrw qe_ifr[NRCV]; /* for receive buffers; */
184 struct ifxmt qe_ifw[NXMT]; /* for xmit buffers; */
185 int qe_flags; /* software state */
186 #define QEF_RUNNING 0x01
187 #define QEF_SETADDR 0x02
188 #define QEF_FASTTIMEO 0x04
189 int setupaddr; /* mapping info for setup pkts */
190 int ipl; /* interrupt priority */
191 struct qe_ring *rringaddr; /* mapping info for rings */
192 struct qe_ring *tringaddr; /* "" */
193 struct qe_ring rring[NRCV+1]; /* Receive ring descriptors */
194 struct qe_ring tring[NXMT+1]; /* Transmit ring descriptors */
195 u_char setup_pkt[16][8]; /* Setup packet */
196 int rindex; /* Receive index */
197 int tindex; /* Transmit index */
198 int otindex; /* Old transmit index */
199 int qe_intvec; /* Interrupt vector */
200 struct qedevice *addr; /* device addr */
201 int setupqueued; /* setup packet queued */
202 int nxmit; /* Transmits in progress */
203 int qe_restarts; /* timeouts */
204 } qe_softc[NQE];
205
206 struct uba_device *qeinfo[NQE];
207
208 extern struct timeval time;
209
210 int qeprobe(), qeattach(), qeintr(), qetimeout();
211 int qeinit(), qeioctl(), qereset(), qestart();
212
213 u_short qestd[] = { 0 };
214 struct uba_driver qedriver =
215 { qeprobe, 0, qeattach, 0, qestd, "qe", qeinfo };
216
217 #define QEUNIT(x) minor(x)
218 /*
219 * The deqna shouldn't receive more than ETHERMTU + sizeof(struct ether_header)
220 * but will actually take in up to 2048 bytes. To guard against the receiver
221 * chaining buffers (which we aren't prepared to handle) we allocate 2kb
222 * size buffers.
223 */
224 #define MAXPACKETSIZE 2048 /* Should really be ETHERMTU */
225 /*
226 * Probe the QNA to see if it's there
227 */
qeprobe(reg,ui)228 qeprobe(reg, ui)
229 caddr_t reg;
230 struct uba_device *ui;
231 {
232 register int br, cvec; /* r11, r10 value-result */
233 register struct qedevice *addr = (struct qedevice *)reg;
234 register struct qe_ring *rp;
235 register struct qe_ring *prp; /* physical rp */
236 register int i;
237 register struct qe_softc *sc = &qe_softc[ui->ui_unit];
238
239 #ifdef lint
240 br = 0; cvec = br; br = cvec;
241 qeintr(0);
242 #endif
243
244 /*
245 * The QNA interrupts on i/o operations. To do an I/O operation
246 * we have to setup the interface by transmitting a setup packet.
247 */
248 addr->qe_csr = QE_RESET;
249 addr->qe_csr &= ~QE_RESET;
250 addr->qe_vector = (uba_hd[numuba].uh_lastiv -= 4);
251
252 /*
253 * Map the communications area and the setup packet.
254 */
255 sc->setupaddr =
256 uballoc(0, (caddr_t)sc->setup_pkt, sizeof(sc->setup_pkt), 0);
257 sc->rringaddr = (struct qe_ring *) uballoc(0, (caddr_t)sc->rring,
258 sizeof(struct qe_ring) * (NTOT+2), 0);
259 prp = (struct qe_ring *)UBAI_ADDR((int)sc->rringaddr);
260
261 /*
262 * The QNA will loop the setup packet back to the receive ring
263 * for verification, therefore we initialize the first
264 * receive & transmit ring descriptors and link the setup packet
265 * to them.
266 */
267 qeinitdesc(sc->tring, (caddr_t)UBAI_ADDR(sc->setupaddr),
268 sizeof(sc->setup_pkt));
269 qeinitdesc(sc->rring, (caddr_t)UBAI_ADDR(sc->setupaddr),
270 sizeof(sc->setup_pkt));
271
272 rp = (struct qe_ring *)sc->tring;
273 rp->qe_setup = 1;
274 rp->qe_eomsg = 1;
275 rp->qe_flag = rp->qe_status1 = QE_NOTYET;
276 rp->qe_valid = 1;
277
278 rp = (struct qe_ring *)sc->rring;
279 rp->qe_flag = rp->qe_status1 = QE_NOTYET;
280 rp->qe_valid = 1;
281
282 /*
283 * Get the addr off of the interface and place it into the setup
284 * packet. This code looks strange due to the fact that the address
285 * is placed in the setup packet in col. major order.
286 */
287 for( i = 0 ; i < 6 ; i++ )
288 sc->setup_pkt[i][1] = addr->qe_sta_addr[i];
289
290 qesetup( sc );
291 /*
292 * Start the interface and wait for the packet.
293 */
294 (void) spl6();
295 addr->qe_csr = QE_INT_ENABLE | QE_XMIT_INT | QE_RCV_INT;
296 addr->qe_rcvlist_lo = (short)prp;
297 addr->qe_rcvlist_hi = (short)((int)prp >> 16);
298 prp += NRCV+1;
299 addr->qe_xmtlist_lo = (short)prp;
300 addr->qe_xmtlist_hi = (short)((int)prp >> 16);
301 DELAY(10000);
302 /*
303 * All done with the bus resources.
304 */
305 ubarelse(0, &sc->setupaddr);
306 ubarelse(0, (int *)&sc->rringaddr);
307 sc->ipl = br = qbgetpri();
308 return( sizeof(struct qedevice) );
309 }
310
311 /*
312 * Interface exists: make available by filling in network interface
313 * record. System will initialize the interface when it is ready
314 * to accept packets.
315 */
316 qeattach(ui)
317 struct uba_device *ui;
318 {
319 register struct qe_softc *sc = &qe_softc[ui->ui_unit];
320 register struct ifnet *ifp = &sc->qe_if;
321 register struct qedevice *addr = (struct qedevice *)ui->ui_addr;
322 register int i;
323
324 ifp->if_unit = ui->ui_unit;
325 ifp->if_name = "qe";
326 ifp->if_mtu = ETHERMTU;
327 /*
328 * The Deqna is cable of transmitting broadcasts, but
329 * doesn't listen to its own.
330 */
331 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX;
332
333 /*
334 * Read the address from the prom and save it.
335 */
336 for( i=0 ; i<6 ; i++ )
337 sc->setup_pkt[i][1] = sc->qe_addr[i] = addr->qe_sta_addr[i] & 0xff;
338 addr->qe_vector |= 1;
339 printf("qe%d: %s, hardware address %s\n", ui->ui_unit,
340 addr->qe_vector&01 ? "delqa":"deqna",
341 ether_sprintf(sc->qe_addr));
342 addr->qe_vector &= ~1;
343
344 /*
345 * Save the vector for initialization at reset time.
346 */
347 sc->qe_intvec = addr->qe_vector;
348
349 ifp->if_init = qeinit;
350 ifp->if_output = ether_output;
351 ifp->if_start = qestart;
352 ifp->if_ioctl = qeioctl;
353 ifp->if_reset = qereset;
354 ifp->if_watchdog = qetimeout;
355 sc->qe_uba.iff_flags = UBA_CANTWAIT;
356 if_attach(ifp);
357 }
358
359 /*
360 * Reset of interface after UNIBUS reset.
361 * If interface is on specified uba, reset its state.
362 */
qereset(unit,uban)363 qereset(unit, uban)
364 int unit, uban;
365 {
366 register struct uba_device *ui;
367
368 if (unit >= NQE || (ui = qeinfo[unit]) == 0 || ui->ui_alive == 0 ||
369 ui->ui_ubanum != uban)
370 return;
371 printf(" qe%d", unit);
372 qe_softc[unit].qe_if.if_flags &= ~IFF_RUNNING;
373 qeinit(unit);
374 }
375
376 /*
377 * Initialization of interface.
378 */
qeinit(unit)379 qeinit(unit)
380 int unit;
381 {
382 register struct qe_softc *sc = &qe_softc[unit];
383 register struct uba_device *ui = qeinfo[unit];
384 register struct qedevice *addr = (struct qedevice *)ui->ui_addr;
385 register struct ifnet *ifp = &sc->qe_if;
386 register i;
387 int s;
388
389 /* address not known */
390 if (ifp->if_addrlist == (struct ifaddr *)0)
391 return;
392 if (sc->qe_flags & QEF_RUNNING)
393 return;
394
395 if ((ifp->if_flags & IFF_RUNNING) == 0) {
396 /*
397 * map the communications area onto the device
398 */
399 i = uballoc(0, (caddr_t)sc->rring,
400 sizeof(struct qe_ring) * (NTOT+2), 0);
401 if (i == 0)
402 goto fail;
403 sc->rringaddr = (struct qe_ring *)UBAI_ADDR(i);
404 sc->tringaddr = sc->rringaddr + NRCV + 1;
405 i = uballoc(0, (caddr_t)sc->setup_pkt,
406 sizeof(sc->setup_pkt), 0);
407 if (i == 0)
408 goto fail;
409 sc->setupaddr = UBAI_ADDR(i);
410 /*
411 * init buffers and maps
412 */
413 if (if_ubaminit(&sc->qe_uba, ui->ui_ubanum,
414 sizeof (struct ether_header), (int)btoc(MAXPACKETSIZE),
415 sc->qe_ifr, NRCV, sc->qe_ifw, NXMT) == 0) {
416 fail:
417 printf("qe%d: can't allocate uba resources\n", unit);
418 sc->qe_if.if_flags &= ~IFF_UP;
419 return;
420 }
421 }
422 /*
423 * Init the buffer descriptors and indexes for each of the lists and
424 * loop them back to form a ring.
425 */
426 for (i = 0; i < NRCV; i++) {
427 qeinitdesc( &sc->rring[i],
428 (caddr_t)UBAI_ADDR(sc->qe_ifr[i].ifrw_info), MAXPACKETSIZE);
429 sc->rring[i].qe_flag = sc->rring[i].qe_status1 = QE_NOTYET;
430 sc->rring[i].qe_valid = 1;
431 }
432 qeinitdesc(&sc->rring[i], (caddr_t)NULL, 0);
433
434 sc->rring[i].qe_addr_lo = (short)sc->rringaddr;
435 sc->rring[i].qe_addr_hi = (short)((int)sc->rringaddr >> 16);
436 sc->rring[i].qe_chain = 1;
437 sc->rring[i].qe_flag = sc->rring[i].qe_status1 = QE_NOTYET;
438 sc->rring[i].qe_valid = 1;
439
440 for( i = 0 ; i <= NXMT ; i++ )
441 qeinitdesc(&sc->tring[i], (caddr_t)NULL, 0);
442 i--;
443
444 sc->tring[i].qe_addr_lo = (short)sc->tringaddr;
445 sc->tring[i].qe_addr_hi = (short)((int)sc->tringaddr >> 16);
446 sc->tring[i].qe_chain = 1;
447 sc->tring[i].qe_flag = sc->tring[i].qe_status1 = QE_NOTYET;
448 sc->tring[i].qe_valid = 1;
449
450 sc->nxmit = sc->otindex = sc->tindex = sc->rindex = 0;
451
452 /*
453 * Take the interface out of reset, program the vector,
454 * enable interrupts, and tell the world we are up.
455 */
456 s = splimp();
457 addr->qe_vector = sc->qe_intvec;
458 sc->addr = addr;
459 addr->qe_csr = QE_RCV_ENABLE | QE_INT_ENABLE | QE_XMIT_INT |
460 QE_RCV_INT | QE_ILOOP;
461 addr->qe_rcvlist_lo = (short)sc->rringaddr;
462 addr->qe_rcvlist_hi = (short)((int)sc->rringaddr >> 16);
463 ifp->if_flags |= IFF_UP | IFF_RUNNING;
464 sc->qe_flags |= QEF_RUNNING;
465 qesetup( sc );
466 (void) qestart( ifp );
467 sc->qe_if.if_timer = QESLOWTIMEOUT; /* Start watchdog */
468 splx( s );
469 }
470
471 /*
472 * Start output on interface.
473 *
474 */
475 qestart(ifp)
476 struct ifnet *ifp;
477 {
478 int unit = ifp->if_unit;
479 struct uba_device *ui = qeinfo[unit];
480 register struct qe_softc *sc = &qe_softc[unit];
481 register struct qedevice *addr;
482 register struct qe_ring *rp;
483 register index;
484 struct mbuf *m;
485 int buf_addr, len, s;
486
487
488 s = splimp();
489 addr = (struct qedevice *)ui->ui_addr;
490 /*
491 * The deqna doesn't look at anything but the valid bit
492 * to determine if it should transmit this packet. If you have
493 * a ring and fill it the device will loop indefinately on the
494 * packet and continue to flood the net with packets until you
495 * break the ring. For this reason we never queue more than n-1
496 * packets in the transmit ring.
497 *
498 * The microcoders should have obeyed their own defination of the
499 * flag and status words, but instead we have to compensate.
500 */
501 for( index = sc->tindex;
502 sc->tring[index].qe_valid == 0 && sc->nxmit < (NXMT-1) ;
503 sc->tindex = index = ++index % NXMT){
504 rp = &sc->tring[index];
505 if( sc->setupqueued ) {
506 buf_addr = sc->setupaddr;
507 len = 128;
508 rp->qe_setup = 1;
509 sc->setupqueued = 0;
510 } else {
511 IF_DEQUEUE(&sc->qe_if.if_snd, m);
512 if( m == 0 ){
513 splx(s);
514 return (0);
515 }
516 buf_addr = sc->qe_ifw[index].ifw_info;
517 len = if_ubaput(&sc->qe_uba, &sc->qe_ifw[index], m);
518 }
519 if( len < MINDATA )
520 len = MINDATA;
521 /*
522 * Does buffer end on odd byte ?
523 */
524 if( len & 1 ) {
525 len++;
526 rp->qe_odd_end = 1;
527 }
528 rp->qe_buf_len = -(len/2);
529 buf_addr = UBAI_ADDR(buf_addr);
530 rp->qe_flag = rp->qe_status1 = QE_NOTYET;
531 rp->qe_addr_lo = (short)buf_addr;
532 rp->qe_addr_hi = (short)(buf_addr >> 16);
533 rp->qe_eomsg = 1;
534 rp->qe_flag = rp->qe_status1 = QE_NOTYET;
535 rp->qe_valid = 1;
536 if (sc->nxmit++ == 0) {
537 sc->qe_flags |= QEF_FASTTIMEO;
538 sc->qe_if.if_timer = QETIMEOUT;
539 }
540
541 /*
542 * See if the xmit list is invalid.
543 */
544 if( addr->qe_csr & QE_XL_INVALID ) {
545 buf_addr = (int)(sc->tringaddr+index);
546 addr->qe_xmtlist_lo = (short)buf_addr;
547 addr->qe_xmtlist_hi = (short)(buf_addr >> 16);
548 }
549 }
550 splx( s );
551 return (0);
552 }
553
554 /*
555 * Ethernet interface interrupt processor
556 */
qeintr(unit)557 qeintr(unit)
558 int unit;
559 {
560 register struct qe_softc *sc = &qe_softc[unit];
561 struct qedevice *addr = (struct qedevice *)qeinfo[unit]->ui_addr;
562 int buf_addr, csr;
563
564 #ifdef notdef
565 splx(sc->ipl);
566 #else
567 (void) splimp();
568 #endif
569 if (!(sc->qe_flags & QEF_FASTTIMEO))
570 sc->qe_if.if_timer = QESLOWTIMEOUT; /* Restart timer clock */
571 csr = addr->qe_csr;
572 addr->qe_csr = QE_RCV_ENABLE | QE_INT_ENABLE | QE_XMIT_INT | QE_RCV_INT | QE_ILOOP;
573 if( csr & QE_RCV_INT )
574 qerint( unit );
575 if( csr & QE_XMIT_INT )
576 qetint( unit );
577 if( csr & QE_NEX_MEM_INT )
578 printf("qe%d: Nonexistent memory interrupt\n", unit);
579
580 if( addr->qe_csr & QE_RL_INVALID && sc->rring[sc->rindex].qe_status1 == QE_NOTYET ) {
581 buf_addr = (int)&sc->rringaddr[sc->rindex];
582 addr->qe_rcvlist_lo = (short)buf_addr;
583 addr->qe_rcvlist_hi = (short)(buf_addr >> 16);
584 }
585 }
586
587 /*
588 * Ethernet interface transmit interrupt.
589 */
590
qetint(unit)591 qetint(unit)
592 int unit;
593 {
594 register struct qe_softc *sc = &qe_softc[unit];
595 register struct qe_ring *rp;
596 register struct ifxmt *ifxp;
597 int status1, setupflag;
598 short len;
599
600
601 while( sc->otindex != sc->tindex && sc->tring[sc->otindex].qe_status1 != QE_NOTYET && sc->nxmit > 0 ) {
602 /*
603 * Save the status words from the descriptor so that it can
604 * be released.
605 */
606 rp = &sc->tring[sc->otindex];
607 status1 = rp->qe_status1;
608 setupflag = rp->qe_setup;
609 len = (-rp->qe_buf_len) * 2;
610 if( rp->qe_odd_end )
611 len++;
612 /*
613 * Init the buffer descriptor
614 */
615 bzero((caddr_t)rp, sizeof(struct qe_ring));
616 if( --sc->nxmit == 0 ) {
617 sc->qe_flags &= ~QEF_FASTTIMEO;
618 sc->qe_if.if_timer = QESLOWTIMEOUT;
619 }
620 if( !setupflag ) {
621 /*
622 * Do some statistics.
623 */
624 sc->qe_if.if_opackets++;
625 sc->qe_if.if_collisions += ( status1 & QE_CCNT ) >> 4;
626 if (status1 & QE_ERROR)
627 sc->qe_if.if_oerrors++;
628 ifxp = &sc->qe_ifw[sc->otindex];
629 if (ifxp->ifw_xtofree) {
630 m_freem(ifxp->ifw_xtofree);
631 ifxp->ifw_xtofree = 0;
632 }
633 }
634 sc->otindex = ++sc->otindex % NXMT;
635 }
636 (void) qestart( &sc->qe_if );
637 }
638
639 /*
640 * Ethernet interface receiver interrupt.
641 * If can't determine length from type, then have to drop packet.
642 * Othewise decapsulate packet based on type and pass to type specific
643 * higher-level input routine.
644 */
qerint(unit)645 qerint(unit)
646 int unit;
647 {
648 register struct qe_softc *sc = &qe_softc[unit];
649 register struct qe_ring *rp;
650 register int nrcv = 0;
651 int len, status1, status2;
652 int bufaddr;
653
654 /*
655 * Traverse the receive ring looking for packets to pass back.
656 * The search is complete when we find a descriptor not in use.
657 *
658 * As in the transmit case the deqna doesn't honor it's own protocols
659 * so there exists the possibility that the device can beat us around
660 * the ring. The proper way to guard against this is to insure that
661 * there is always at least one invalid descriptor. We chose instead
662 * to make the ring large enough to minimize the problem. With a ring
663 * size of 4 we haven't been able to see the problem. To be safe we
664 * doubled that to 8.
665 *
666 */
667 while (sc->rring[sc->rindex].qe_status1 == QE_NOTYET && nrcv < NRCV) {
668 /*
669 * We got an interrupt but did not find an input packet
670 * where we expected one to be, probably because the ring
671 * was overrun.
672 * We search forward to find a valid packet and start
673 * processing from there. If no valid packet is found it
674 * means we processed all the packets during a previous
675 * interrupt and that the QE_RCV_INT bit was set while
676 * we were processing one of these earlier packets. In
677 * this case we can safely ignore the interrupt (by dropping
678 * through the code below).
679 */
680 sc->rindex = (sc->rindex + 1) % NRCV;
681 nrcv++;
682 }
683 if (nrcv && nrcv < NRCV)
684 log(LOG_ERR, "qe%d: ring overrun, resync'd by skipping %d\n",
685 unit, nrcv);
686
687 for( ; sc->rring[sc->rindex].qe_status1 != QE_NOTYET ; sc->rindex = ++sc->rindex % NRCV ){
688 rp = &sc->rring[sc->rindex];
689 status1 = rp->qe_status1;
690 status2 = rp->qe_status2;
691 bzero((caddr_t)rp, sizeof(struct qe_ring));
692 if( (status1 & QE_MASK) == QE_MASK )
693 panic("qe: chained packet");
694 len = ((status1 & QE_RBL_HI) | (status2 & QE_RBL_LO)) + 60;
695 sc->qe_if.if_ipackets++;
696
697 if (status1 & QE_ERROR) {
698 if ((status1 & QE_RUNT) == 0)
699 sc->qe_if.if_ierrors++;
700 } else {
701 /*
702 * We don't process setup packets.
703 */
704 if( !(status1 & QE_ESETUP) )
705 qeread(sc, &sc->qe_ifr[sc->rindex],
706 len - sizeof(struct ether_header));
707 }
708 /*
709 * Return the buffer to the ring
710 */
711 bufaddr = (int)UBAI_ADDR(sc->qe_ifr[sc->rindex].ifrw_info);
712 rp->qe_buf_len = -((MAXPACKETSIZE)/2);
713 rp->qe_addr_lo = (short)bufaddr;
714 rp->qe_addr_hi = (short)((int)bufaddr >> 16);
715 rp->qe_flag = rp->qe_status1 = QE_NOTYET;
716 rp->qe_valid = 1;
717 }
718 }
719
720 /*
721 * Process an ioctl request.
722 */
qeioctl(ifp,cmd,data)723 qeioctl(ifp, cmd, data)
724 register struct ifnet *ifp;
725 int cmd;
726 caddr_t data;
727 {
728 struct qe_softc *sc = &qe_softc[ifp->if_unit];
729 struct ifaddr *ifa = (struct ifaddr *)data;
730 int s = splimp(), error = 0;
731
732 switch (cmd) {
733
734 case SIOCSIFADDR:
735 ifp->if_flags |= IFF_UP;
736 qeinit(ifp->if_unit);
737 switch(ifa->ifa_addr->sa_family) {
738 #ifdef INET
739 case AF_INET:
740 ((struct arpcom *)ifp)->ac_ipaddr =
741 IA_SIN(ifa)->sin_addr;
742 arpwhohas((struct arpcom *)ifp, &IA_SIN(ifa)->sin_addr);
743 break;
744 #endif
745 #ifdef NS
746 case AF_NS:
747 {
748 register struct ns_addr *ina = &(IA_SNS(ifa)->sns_addr);
749
750 if (ns_nullhost(*ina))
751 ina->x_host = *(union ns_host *)(sc->qe_addr);
752 else
753 qe_setaddr(ina->x_host.c_host, ifp->if_unit);
754 break;
755 }
756 #endif
757 }
758 break;
759
760 case SIOCSIFFLAGS:
761 if ((ifp->if_flags & IFF_UP) == 0 &&
762 sc->qe_flags & QEF_RUNNING) {
763 ((struct qedevice *)
764 (qeinfo[ifp->if_unit]->ui_addr))->qe_csr = QE_RESET;
765 sc->qe_flags &= ~QEF_RUNNING;
766 } else if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) ==
767 IFF_RUNNING && (sc->qe_flags & QEF_RUNNING) == 0)
768 qerestart(sc);
769 break;
770
771 default:
772 error = EINVAL;
773
774 }
775 splx(s);
776 return (error);
777 }
778
779 /*
780 * set ethernet address for unit
781 */
qe_setaddr(physaddr,unit)782 qe_setaddr(physaddr, unit)
783 u_char *physaddr;
784 int unit;
785 {
786 register struct qe_softc *sc = &qe_softc[unit];
787 register int i;
788
789 for (i = 0; i < 6; i++)
790 sc->setup_pkt[i][1] = sc->qe_addr[i] = physaddr[i];
791 sc->qe_flags |= QEF_SETADDR;
792 if (sc->qe_if.if_flags & IFF_RUNNING)
793 qesetup(sc);
794 qeinit(unit);
795 }
796
797
798 /*
799 * Initialize a ring descriptor with mbuf allocation side effects
800 */
qeinitdesc(rp,addr,len)801 qeinitdesc(rp, addr, len)
802 register struct qe_ring *rp;
803 caddr_t addr; /* mapped address */
804 int len;
805 {
806 /*
807 * clear the entire descriptor
808 */
809 bzero((caddr_t)rp, sizeof(struct qe_ring));
810
811 if( len ) {
812 rp->qe_buf_len = -(len/2);
813 rp->qe_addr_lo = (short)addr;
814 rp->qe_addr_hi = (short)((int)addr >> 16);
815 }
816 }
817 /*
818 * Build a setup packet - the physical address will already be present
819 * in first column.
820 */
821 qesetup( sc )
822 struct qe_softc *sc;
823 {
824 register i, j;
825
826 /*
827 * Copy the target address to the rest of the entries in this row.
828 */
829 for ( j = 0; j < 6 ; j++ )
830 for ( i = 2 ; i < 8 ; i++ )
831 sc->setup_pkt[j][i] = sc->setup_pkt[j][1];
832 /*
833 * Duplicate the first half.
834 */
835 bcopy((caddr_t)sc->setup_pkt[0], (caddr_t)sc->setup_pkt[8], 64);
836 /*
837 * Fill in the broadcast (and ISO multicast) address(es).
838 */
839 for ( i = 0; i < 6 ; i++ ) {
840 sc->setup_pkt[i][2] = 0xff;
841 #ifdef ISO
842 sc->setup_pkt[i][3] = all_es_snpa[i];
843 sc->setup_pkt[i][4] = all_is_snpa[i];
844 sc->setup_pkt[i][5] = all_l1is_snpa[i];
845 sc->setup_pkt[i][6] = all_l2is_snpa[i];
846 #endif
847 }
848 sc->setupqueued++;
849 }
850
851 /*
852 * Pass a packet to the higher levels.
853 * We deal with the trailer protocol here.
854 */
qeread(sc,ifrw,len)855 qeread(sc, ifrw, len)
856 register struct qe_softc *sc;
857 struct ifrw *ifrw;
858 int len;
859 {
860 struct ether_header *eh, ehm;
861 struct mbuf *m;
862 int off, resid, s;
863 struct ifqueue *inq;
864
865 /*
866 * Deal with trailer protocol: if type is INET trailer
867 * get true type from first 16-bit word past data.
868 * Remember that type was trailer by setting off.
869 */
870
871 eh = (struct ether_header *)ifrw->ifrw_addr;
872 eh->ether_type = ntohs((u_short)eh->ether_type);
873 #define qedataaddr(eh, off, type) ((type)(((caddr_t)((eh)+1)+(off))))
874 if (eh->ether_type >= ETHERTYPE_TRAIL &&
875 eh->ether_type < ETHERTYPE_TRAIL+ETHERTYPE_NTRAILER) {
876 off = (eh->ether_type - ETHERTYPE_TRAIL) * 512;
877 if (off >= ETHERMTU)
878 return; /* sanity */
879 eh->ether_type = ntohs(*qedataaddr(eh,off, u_short *));
880 resid = ntohs(*(qedataaddr(eh, off+2, u_short *)));
881 if (off + resid > len)
882 return; /* sanity */
883 len = off + resid;
884 } else
885 off = 0;
886 if (len == 0)
887 return;
888
889 /*
890 * Pull packet off interface. Off is nonzero if packet
891 * has trailing header; qeget will then force this header
892 * information to be at the front, but we still have to drop
893 * the type and length which are at the front of any trailer data.
894 */
895 bcopy((caddr_t)eh, (caddr_t)&ehm, sizeof(ehm));
896 m = if_ubaget(&sc->qe_uba, ifrw, len, off, &sc->qe_if);
897
898 if (m)
899 ether_input(&sc->qe_if, &ehm, m);
900 }
901
902 /*
903 * Watchdog timeout routine. There is a condition in the hardware that
904 * causes the board to lock up under heavy load. This routine detects
905 * the hang up and restarts the device.
906 */
qetimeout(unit)907 qetimeout(unit)
908 int unit;
909 {
910 register struct qe_softc *sc;
911
912 sc = &qe_softc[unit];
913 #ifdef notdef
914 log(LOG_ERR, "qe%d: transmit timeout, restarted %d\n",
915 unit, sc->qe_restarts++);
916 #endif
917 qerestart(sc);
918 }
919 /*
920 * Restart for board lockup problem.
921 */
qerestart(sc)922 qerestart(sc)
923 register struct qe_softc *sc;
924 {
925 register struct ifnet *ifp = &sc->qe_if;
926 register struct qedevice *addr = sc->addr;
927 register struct qe_ring *rp;
928 register i;
929
930 addr->qe_csr = QE_RESET;
931 addr->qe_csr &= ~QE_RESET;
932 qesetup( sc );
933 for (i = 0, rp = sc->tring; i < NXMT; rp++, i++) {
934 rp->qe_flag = rp->qe_status1 = QE_NOTYET;
935 rp->qe_valid = 0;
936 }
937 sc->nxmit = sc->otindex = sc->tindex = sc->rindex = 0;
938 addr->qe_csr = QE_RCV_ENABLE | QE_INT_ENABLE | QE_XMIT_INT |
939 QE_RCV_INT | QE_ILOOP;
940 addr->qe_rcvlist_lo = (short)sc->rringaddr;
941 addr->qe_rcvlist_hi = (short)((int)sc->rringaddr >> 16);
942 sc->qe_flags |= QEF_RUNNING;
943 (void) qestart(ifp);
944 }
945 #endif
946