1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org>
5 * Copyright (c) 1997, 1998, 1999
6 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36 #include <sys/cdefs.h>
37 /*
38 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
39 * available from http://www.sis.com.tw.
40 *
41 * This driver also supports the NatSemi DP83815. Datasheets are
42 * available from http://www.national.com.
43 *
44 * Written by Bill Paul <wpaul@ee.columbia.edu>
45 * Electrical Engineering Department
46 * Columbia University, New York City
47 */
48 /*
49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
50 * simple TX and RX descriptors of 3 longwords in size. The receiver
51 * has a single perfect filter entry for the station address and a
52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
53 * transceiver while the 7016 requires an external transceiver chip.
54 * Both chips offer the standard bit-bang MII interface as well as
55 * an enchanced PHY interface which simplifies accessing MII registers.
56 *
57 * The only downside to this chipset is that RX descriptors must be
58 * longword aligned.
59 */
60
61 #ifdef HAVE_KERNEL_OPTION_HEADERS
62 #include "opt_device_polling.h"
63 #endif
64
65 #include <sys/param.h>
66 #include <sys/systm.h>
67 #include <sys/bus.h>
68 #include <sys/endian.h>
69 #include <sys/kernel.h>
70 #include <sys/lock.h>
71 #include <sys/malloc.h>
72 #include <sys/mbuf.h>
73 #include <sys/module.h>
74 #include <sys/socket.h>
75 #include <sys/sockio.h>
76 #include <sys/sysctl.h>
77
78 #include <net/if.h>
79 #include <net/if_var.h>
80 #include <net/if_arp.h>
81 #include <net/ethernet.h>
82 #include <net/if_dl.h>
83 #include <net/if_media.h>
84 #include <net/if_types.h>
85 #include <net/if_vlan_var.h>
86
87 #include <net/bpf.h>
88
89 #include <machine/bus.h>
90 #include <machine/resource.h>
91 #include <sys/rman.h>
92
93 #include <dev/mii/mii.h>
94 #include <dev/mii/mii_bitbang.h>
95 #include <dev/mii/miivar.h>
96
97 #include <dev/pci/pcireg.h>
98 #include <dev/pci/pcivar.h>
99
100 #define SIS_USEIOSPACE
101
102 #include <dev/sis/if_sisreg.h>
103
104 MODULE_DEPEND(sis, pci, 1, 1, 1);
105 MODULE_DEPEND(sis, ether, 1, 1, 1);
106 MODULE_DEPEND(sis, miibus, 1, 1, 1);
107
108 /* "device miibus" required. See GENERIC if you get errors here. */
109 #include "miibus_if.h"
110
111 #define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx)
112 #define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx)
113 #define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED)
114
115 /*
116 * register space access macros
117 */
118 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val)
119
120 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg)
121
122 #define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg)
123
124 #define CSR_BARRIER(sc, reg, length, flags) \
125 bus_barrier(sc->sis_res[0], reg, length, flags)
126
127 /*
128 * Various supported device vendors/types and their names.
129 */
130 static const struct sis_type sis_devs[] = {
131 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
132 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
133 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
134 { 0, 0, NULL }
135 };
136
137 static int sis_detach(device_t);
138 static __inline void sis_discard_rxbuf(struct sis_rxdesc *);
139 static int sis_dma_alloc(struct sis_softc *);
140 static void sis_dma_free(struct sis_softc *);
141 static int sis_dma_ring_alloc(struct sis_softc *, bus_size_t, bus_size_t,
142 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
143 static void sis_dmamap_cb(void *, bus_dma_segment_t *, int, int);
144 #ifndef __NO_STRICT_ALIGNMENT
145 static __inline void sis_fixup_rx(struct mbuf *);
146 #endif
147 static void sis_ifmedia_sts(if_t, struct ifmediareq *);
148 static int sis_ifmedia_upd(if_t);
149 static void sis_init(void *);
150 static void sis_initl(struct sis_softc *);
151 static void sis_intr(void *);
152 static int sis_ioctl(if_t, u_long, caddr_t);
153 static uint32_t sis_mii_bitbang_read(device_t);
154 static void sis_mii_bitbang_write(device_t, uint32_t);
155 static int sis_newbuf(struct sis_softc *, struct sis_rxdesc *);
156 static int sis_resume(device_t);
157 static int sis_rxeof(struct sis_softc *);
158 static void sis_rxfilter(struct sis_softc *);
159 static void sis_rxfilter_ns(struct sis_softc *);
160 static void sis_rxfilter_sis(struct sis_softc *);
161 static void sis_start(if_t);
162 static void sis_startl(if_t);
163 static void sis_stop(struct sis_softc *);
164 static int sis_suspend(device_t);
165 static void sis_add_sysctls(struct sis_softc *);
166 static void sis_watchdog(struct sis_softc *);
167 static void sis_wol(struct sis_softc *);
168
169 /*
170 * MII bit-bang glue
171 */
172 static const struct mii_bitbang_ops sis_mii_bitbang_ops = {
173 sis_mii_bitbang_read,
174 sis_mii_bitbang_write,
175 {
176 SIS_MII_DATA, /* MII_BIT_MDO */
177 SIS_MII_DATA, /* MII_BIT_MDI */
178 SIS_MII_CLK, /* MII_BIT_MDC */
179 SIS_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
180 0, /* MII_BIT_DIR_PHY_HOST */
181 }
182 };
183
184 static struct resource_spec sis_res_spec[] = {
185 #ifdef SIS_USEIOSPACE
186 { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE},
187 #else
188 { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE},
189 #endif
190 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE},
191 { -1, 0 }
192 };
193
194 #define SIS_SETBIT(sc, reg, x) \
195 CSR_WRITE_4(sc, reg, \
196 CSR_READ_4(sc, reg) | (x))
197
198 #define SIS_CLRBIT(sc, reg, x) \
199 CSR_WRITE_4(sc, reg, \
200 CSR_READ_4(sc, reg) & ~(x))
201
202 #define SIO_SET(x) \
203 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
204
205 #define SIO_CLR(x) \
206 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
207
208 /*
209 * Routine to reverse the bits in a word. Stolen almost
210 * verbatim from /usr/games/fortune.
211 */
212 static uint16_t
sis_reverse(uint16_t n)213 sis_reverse(uint16_t n)
214 {
215 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
216 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
217 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
218 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
219
220 return (n);
221 }
222
223 static void
sis_delay(struct sis_softc * sc)224 sis_delay(struct sis_softc *sc)
225 {
226 int idx;
227
228 for (idx = (300 / 33) + 1; idx > 0; idx--)
229 CSR_READ_4(sc, SIS_CSR);
230 }
231
232 static void
sis_eeprom_idle(struct sis_softc * sc)233 sis_eeprom_idle(struct sis_softc *sc)
234 {
235 int i;
236
237 SIO_SET(SIS_EECTL_CSEL);
238 sis_delay(sc);
239 SIO_SET(SIS_EECTL_CLK);
240 sis_delay(sc);
241
242 for (i = 0; i < 25; i++) {
243 SIO_CLR(SIS_EECTL_CLK);
244 sis_delay(sc);
245 SIO_SET(SIS_EECTL_CLK);
246 sis_delay(sc);
247 }
248
249 SIO_CLR(SIS_EECTL_CLK);
250 sis_delay(sc);
251 SIO_CLR(SIS_EECTL_CSEL);
252 sis_delay(sc);
253 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
254 }
255
256 /*
257 * Send a read command and address to the EEPROM, check for ACK.
258 */
259 static void
sis_eeprom_putbyte(struct sis_softc * sc,int addr)260 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
261 {
262 int d, i;
263
264 d = addr | SIS_EECMD_READ;
265
266 /*
267 * Feed in each bit and stobe the clock.
268 */
269 for (i = 0x400; i; i >>= 1) {
270 if (d & i) {
271 SIO_SET(SIS_EECTL_DIN);
272 } else {
273 SIO_CLR(SIS_EECTL_DIN);
274 }
275 sis_delay(sc);
276 SIO_SET(SIS_EECTL_CLK);
277 sis_delay(sc);
278 SIO_CLR(SIS_EECTL_CLK);
279 sis_delay(sc);
280 }
281 }
282
283 /*
284 * Read a word of data stored in the EEPROM at address 'addr.'
285 */
286 static void
sis_eeprom_getword(struct sis_softc * sc,int addr,uint16_t * dest)287 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
288 {
289 int i;
290 uint16_t word = 0;
291
292 /* Force EEPROM to idle state. */
293 sis_eeprom_idle(sc);
294
295 /* Enter EEPROM access mode. */
296 sis_delay(sc);
297 SIO_CLR(SIS_EECTL_CLK);
298 sis_delay(sc);
299 SIO_SET(SIS_EECTL_CSEL);
300 sis_delay(sc);
301
302 /*
303 * Send address of word we want to read.
304 */
305 sis_eeprom_putbyte(sc, addr);
306
307 /*
308 * Start reading bits from EEPROM.
309 */
310 for (i = 0x8000; i; i >>= 1) {
311 SIO_SET(SIS_EECTL_CLK);
312 sis_delay(sc);
313 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
314 word |= i;
315 sis_delay(sc);
316 SIO_CLR(SIS_EECTL_CLK);
317 sis_delay(sc);
318 }
319
320 /* Turn off EEPROM access mode. */
321 sis_eeprom_idle(sc);
322
323 *dest = word;
324 }
325
326 /*
327 * Read a sequence of words from the EEPROM.
328 */
329 static void
sis_read_eeprom(struct sis_softc * sc,caddr_t dest,int off,int cnt,int swap)330 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
331 {
332 int i;
333 uint16_t word = 0, *ptr;
334
335 for (i = 0; i < cnt; i++) {
336 sis_eeprom_getword(sc, off + i, &word);
337 ptr = (uint16_t *)(dest + (i * 2));
338 if (swap)
339 *ptr = ntohs(word);
340 else
341 *ptr = word;
342 }
343 }
344
345 #if defined(__i386__) || defined(__amd64__)
346 static device_t
sis_find_bridge(device_t dev)347 sis_find_bridge(device_t dev)
348 {
349 devclass_t pci_devclass;
350 device_t *pci_devices;
351 int pci_count = 0;
352 device_t *pci_children;
353 int pci_childcount = 0;
354 device_t *busp, *childp;
355 device_t child = NULL;
356 int i, j;
357
358 if ((pci_devclass = devclass_find("pci")) == NULL)
359 return (NULL);
360
361 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
362
363 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
364 if (device_get_children(*busp, &pci_children, &pci_childcount))
365 continue;
366 for (j = 0, childp = pci_children;
367 j < pci_childcount; j++, childp++) {
368 if (pci_get_vendor(*childp) == SIS_VENDORID &&
369 pci_get_device(*childp) == 0x0008) {
370 child = *childp;
371 free(pci_children, M_TEMP);
372 goto done;
373 }
374 }
375 free(pci_children, M_TEMP);
376 }
377
378 done:
379 free(pci_devices, M_TEMP);
380 return (child);
381 }
382
383 static void
sis_read_cmos(struct sis_softc * sc,device_t dev,caddr_t dest,int off,int cnt)384 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt)
385 {
386 device_t bridge;
387 uint8_t reg;
388 int i;
389 bus_space_tag_t btag;
390
391 bridge = sis_find_bridge(dev);
392 if (bridge == NULL)
393 return;
394 reg = pci_read_config(bridge, 0x48, 1);
395 pci_write_config(bridge, 0x48, reg|0x40, 1);
396
397 /* XXX */
398 #if defined(__amd64__) || defined(__i386__)
399 btag = X86_BUS_SPACE_IO;
400 #endif
401
402 for (i = 0; i < cnt; i++) {
403 bus_space_write_1(btag, 0x0, 0x70, i + off);
404 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
405 }
406
407 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
408 }
409
410 static void
sis_read_mac(struct sis_softc * sc,device_t dev,caddr_t dest)411 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
412 {
413 uint32_t filtsave, csrsave;
414
415 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
416 csrsave = CSR_READ_4(sc, SIS_CSR);
417
418 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
419 CSR_WRITE_4(sc, SIS_CSR, 0);
420
421 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
422
423 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
424 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
425 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
426 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
427 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
428 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
429
430 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
431 CSR_WRITE_4(sc, SIS_CSR, csrsave);
432 }
433 #endif
434
435 /*
436 * Read the MII serial port for the MII bit-bang module.
437 */
438 static uint32_t
sis_mii_bitbang_read(device_t dev)439 sis_mii_bitbang_read(device_t dev)
440 {
441 struct sis_softc *sc;
442 uint32_t val;
443
444 sc = device_get_softc(dev);
445
446 val = CSR_READ_4(sc, SIS_EECTL);
447 CSR_BARRIER(sc, SIS_EECTL, 4,
448 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
449 return (val);
450 }
451
452 /*
453 * Write the MII serial port for the MII bit-bang module.
454 */
455 static void
sis_mii_bitbang_write(device_t dev,uint32_t val)456 sis_mii_bitbang_write(device_t dev, uint32_t val)
457 {
458 struct sis_softc *sc;
459
460 sc = device_get_softc(dev);
461
462 CSR_WRITE_4(sc, SIS_EECTL, val);
463 CSR_BARRIER(sc, SIS_EECTL, 4,
464 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
465 }
466
467 static int
sis_miibus_readreg(device_t dev,int phy,int reg)468 sis_miibus_readreg(device_t dev, int phy, int reg)
469 {
470 struct sis_softc *sc;
471
472 sc = device_get_softc(dev);
473
474 if (sc->sis_type == SIS_TYPE_83815) {
475 if (phy != 0)
476 return (0);
477 /*
478 * The NatSemi chip can take a while after
479 * a reset to come ready, during which the BMSR
480 * returns a value of 0. This is *never* supposed
481 * to happen: some of the BMSR bits are meant to
482 * be hardwired in the on position, and this can
483 * confuse the miibus code a bit during the probe
484 * and attach phase. So we make an effort to check
485 * for this condition and wait for it to clear.
486 */
487 if (!CSR_READ_4(sc, NS_BMSR))
488 DELAY(1000);
489 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
490 }
491
492 /*
493 * Chipsets < SIS_635 seem not to be able to read/write
494 * through mdio. Use the enhanced PHY access register
495 * again for them.
496 */
497 if (sc->sis_type == SIS_TYPE_900 &&
498 sc->sis_rev < SIS_REV_635) {
499 int i, val = 0;
500
501 if (phy != 0)
502 return (0);
503
504 CSR_WRITE_4(sc, SIS_PHYCTL,
505 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
506 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
507
508 for (i = 0; i < SIS_TIMEOUT; i++) {
509 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
510 break;
511 }
512
513 if (i == SIS_TIMEOUT) {
514 device_printf(sc->sis_dev,
515 "PHY failed to come ready\n");
516 return (0);
517 }
518
519 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
520
521 if (val == 0xFFFF)
522 return (0);
523
524 return (val);
525 } else
526 return (mii_bitbang_readreg(dev, &sis_mii_bitbang_ops, phy,
527 reg));
528 }
529
530 static int
sis_miibus_writereg(device_t dev,int phy,int reg,int data)531 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
532 {
533 struct sis_softc *sc;
534
535 sc = device_get_softc(dev);
536
537 if (sc->sis_type == SIS_TYPE_83815) {
538 if (phy != 0)
539 return (0);
540 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
541 return (0);
542 }
543
544 /*
545 * Chipsets < SIS_635 seem not to be able to read/write
546 * through mdio. Use the enhanced PHY access register
547 * again for them.
548 */
549 if (sc->sis_type == SIS_TYPE_900 &&
550 sc->sis_rev < SIS_REV_635) {
551 int i;
552
553 if (phy != 0)
554 return (0);
555
556 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
557 (reg << 6) | SIS_PHYOP_WRITE);
558 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
559
560 for (i = 0; i < SIS_TIMEOUT; i++) {
561 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
562 break;
563 }
564
565 if (i == SIS_TIMEOUT)
566 device_printf(sc->sis_dev,
567 "PHY failed to come ready\n");
568 } else
569 mii_bitbang_writereg(dev, &sis_mii_bitbang_ops, phy, reg,
570 data);
571 return (0);
572 }
573
574 static void
sis_miibus_statchg(device_t dev)575 sis_miibus_statchg(device_t dev)
576 {
577 struct sis_softc *sc;
578 struct mii_data *mii;
579 if_t ifp;
580 uint32_t reg;
581
582 sc = device_get_softc(dev);
583 SIS_LOCK_ASSERT(sc);
584
585 mii = device_get_softc(sc->sis_miibus);
586 ifp = sc->sis_ifp;
587 if (mii == NULL || ifp == NULL ||
588 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
589 return;
590
591 sc->sis_flags &= ~SIS_FLAG_LINK;
592 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
593 (IFM_ACTIVE | IFM_AVALID)) {
594 switch (IFM_SUBTYPE(mii->mii_media_active)) {
595 case IFM_10_T:
596 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
597 sc->sis_flags |= SIS_FLAG_LINK;
598 break;
599 case IFM_100_TX:
600 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
601 sc->sis_flags |= SIS_FLAG_LINK;
602 break;
603 default:
604 break;
605 }
606 }
607
608 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) {
609 /*
610 * Stopping MACs seem to reset SIS_TX_LISTPTR and
611 * SIS_RX_LISTPTR which in turn requires resetting
612 * TX/RX buffers. So just don't do anything for
613 * lost link.
614 */
615 return;
616 }
617
618 /* Set full/half duplex mode. */
619 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
620 SIS_SETBIT(sc, SIS_TX_CFG,
621 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
622 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
623 } else {
624 SIS_CLRBIT(sc, SIS_TX_CFG,
625 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
626 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
627 }
628
629 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
630 /*
631 * MPII03.D: Half Duplex Excessive Collisions.
632 * Also page 49 in 83816 manual
633 */
634 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D);
635 }
636
637 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A &&
638 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
639 /*
640 * Short Cable Receive Errors (MP21.E)
641 */
642 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
643 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;
644 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);
645 DELAY(100);
646 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
647 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {
648 device_printf(sc->sis_dev,
649 "Applying short cable fix (reg=%x)\n", reg);
650 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8);
651 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20);
652 }
653 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
654 }
655 /* Enable TX/RX MACs. */
656 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
657 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE | SIS_CSR_RX_ENABLE);
658 }
659
660 static uint32_t
sis_mchash(struct sis_softc * sc,const uint8_t * addr)661 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
662 {
663 uint32_t crc;
664
665 /* Compute CRC for the address value. */
666 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
667
668 /*
669 * return the filter bit position
670 *
671 * The NatSemi chip has a 512-bit filter, which is
672 * different than the SiS, so we special-case it.
673 */
674 if (sc->sis_type == SIS_TYPE_83815)
675 return (crc >> 23);
676 else if (sc->sis_rev >= SIS_REV_635 ||
677 sc->sis_rev == SIS_REV_900B)
678 return (crc >> 24);
679 else
680 return (crc >> 25);
681 }
682
683 static void
sis_rxfilter(struct sis_softc * sc)684 sis_rxfilter(struct sis_softc *sc)
685 {
686
687 SIS_LOCK_ASSERT(sc);
688
689 if (sc->sis_type == SIS_TYPE_83815)
690 sis_rxfilter_ns(sc);
691 else
692 sis_rxfilter_sis(sc);
693 }
694
695 static u_int
sis_write_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)696 sis_write_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
697 {
698 struct sis_softc *sc = arg;
699 uint32_t h;
700 int bit, index;
701
702 h = sis_mchash(sc, LLADDR(sdl));
703 index = h >> 3;
704 bit = h & 0x1F;
705 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
706 if (bit > 0xF)
707 bit -= 0x10;
708 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
709
710 return (1);
711 }
712
713 static void
sis_rxfilter_ns(struct sis_softc * sc)714 sis_rxfilter_ns(struct sis_softc *sc)
715 {
716 if_t ifp;
717 uint32_t i, filter;
718
719 ifp = sc->sis_ifp;
720 filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
721 if (filter & SIS_RXFILTCTL_ENABLE) {
722 /*
723 * Filter should be disabled to program other bits.
724 */
725 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE);
726 CSR_READ_4(sc, SIS_RXFILT_CTL);
727 }
728 filter &= ~(NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT |
729 NS_RXFILTCTL_MCHASH | SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
730 SIS_RXFILTCTL_ALLMULTI);
731
732 if (if_getflags(ifp) & IFF_BROADCAST)
733 filter |= SIS_RXFILTCTL_BROAD;
734 /*
735 * For the NatSemi chip, we have to explicitly enable the
736 * reception of ARP frames, as well as turn on the 'perfect
737 * match' filter where we store the station address, otherwise
738 * we won't receive unicasts meant for this host.
739 */
740 filter |= NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT;
741
742 if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) {
743 filter |= SIS_RXFILTCTL_ALLMULTI;
744 if (if_getflags(ifp) & IFF_PROMISC)
745 filter |= SIS_RXFILTCTL_ALLPHYS;
746 } else {
747 /*
748 * We have to explicitly enable the multicast hash table
749 * on the NatSemi chip if we want to use it, which we do.
750 */
751 filter |= NS_RXFILTCTL_MCHASH;
752
753 /* first, zot all the existing hash bits */
754 for (i = 0; i < 32; i++) {
755 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO +
756 (i * 2));
757 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
758 }
759
760 if_foreach_llmaddr(ifp, sis_write_maddr, sc);
761 }
762
763 /* Turn the receive filter on */
764 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter | SIS_RXFILTCTL_ENABLE);
765 CSR_READ_4(sc, SIS_RXFILT_CTL);
766 }
767
768 struct sis_hash_maddr_ctx {
769 struct sis_softc *sc;
770 uint16_t hashes[16];
771 };
772
773 static u_int
sis_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)774 sis_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
775 {
776 struct sis_hash_maddr_ctx *ctx = arg;
777 uint32_t h;
778
779 h = sis_mchash(ctx->sc, LLADDR(sdl));
780 ctx->hashes[h >> 4] |= 1 << (h & 0xf);
781
782 return (1);
783 }
784
785 static void
sis_rxfilter_sis(struct sis_softc * sc)786 sis_rxfilter_sis(struct sis_softc *sc)
787 {
788 if_t ifp;
789 struct sis_hash_maddr_ctx ctx;
790 uint32_t filter, i, n;
791
792 ifp = sc->sis_ifp;
793
794 /* hash table size */
795 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
796 n = 16;
797 else
798 n = 8;
799
800 filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
801 if (filter & SIS_RXFILTCTL_ENABLE) {
802 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE);
803 CSR_READ_4(sc, SIS_RXFILT_CTL);
804 }
805 filter &= ~(SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
806 SIS_RXFILTCTL_ALLMULTI);
807 if (if_getflags(ifp) & IFF_BROADCAST)
808 filter |= SIS_RXFILTCTL_BROAD;
809
810 if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) {
811 filter |= SIS_RXFILTCTL_ALLMULTI;
812 if (if_getflags(ifp) & IFF_PROMISC)
813 filter |= SIS_RXFILTCTL_ALLPHYS;
814 for (i = 0; i < n; i++)
815 ctx.hashes[i] = ~0;
816 } else {
817 for (i = 0; i < n; i++)
818 ctx.hashes[i] = 0;
819 ctx.sc = sc;
820 if (if_foreach_llmaddr(ifp, sis_hash_maddr, &ctx) > n) {
821 filter |= SIS_RXFILTCTL_ALLMULTI;
822 for (i = 0; i < n; i++)
823 ctx.hashes[i] = ~0;
824 }
825 }
826
827 for (i = 0; i < n; i++) {
828 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
829 CSR_WRITE_4(sc, SIS_RXFILT_DATA, ctx.hashes[i]);
830 }
831
832 /* Turn the receive filter on */
833 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter | SIS_RXFILTCTL_ENABLE);
834 CSR_READ_4(sc, SIS_RXFILT_CTL);
835 }
836
837 static void
sis_reset(struct sis_softc * sc)838 sis_reset(struct sis_softc *sc)
839 {
840 int i;
841
842 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
843
844 for (i = 0; i < SIS_TIMEOUT; i++) {
845 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
846 break;
847 }
848
849 if (i == SIS_TIMEOUT)
850 device_printf(sc->sis_dev, "reset never completed\n");
851
852 /* Wait a little while for the chip to get its brains in order. */
853 DELAY(1000);
854
855 /*
856 * If this is a NetSemi chip, make sure to clear
857 * PME mode.
858 */
859 if (sc->sis_type == SIS_TYPE_83815) {
860 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
861 CSR_WRITE_4(sc, NS_CLKRUN, 0);
862 } else {
863 /* Disable WOL functions. */
864 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, 0);
865 }
866 }
867
868 /*
869 * Probe for an SiS chip. Check the PCI vendor and device
870 * IDs against our list and return a device name if we find a match.
871 */
872 static int
sis_probe(device_t dev)873 sis_probe(device_t dev)
874 {
875 const struct sis_type *t;
876
877 t = sis_devs;
878
879 while (t->sis_name != NULL) {
880 if ((pci_get_vendor(dev) == t->sis_vid) &&
881 (pci_get_device(dev) == t->sis_did)) {
882 device_set_desc(dev, t->sis_name);
883 return (BUS_PROBE_DEFAULT);
884 }
885 t++;
886 }
887
888 return (ENXIO);
889 }
890
891 /*
892 * Attach the interface. Allocate softc structures, do ifmedia
893 * setup and ethernet/BPF attach.
894 */
895 static int
sis_attach(device_t dev)896 sis_attach(device_t dev)
897 {
898 u_char eaddr[ETHER_ADDR_LEN];
899 struct sis_softc *sc;
900 if_t ifp;
901 int error = 0, pmc;
902
903 sc = device_get_softc(dev);
904
905 sc->sis_dev = dev;
906
907 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
908 MTX_DEF);
909 callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0);
910
911 if (pci_get_device(dev) == SIS_DEVICEID_900)
912 sc->sis_type = SIS_TYPE_900;
913 if (pci_get_device(dev) == SIS_DEVICEID_7016)
914 sc->sis_type = SIS_TYPE_7016;
915 if (pci_get_vendor(dev) == NS_VENDORID)
916 sc->sis_type = SIS_TYPE_83815;
917
918 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
919 /*
920 * Map control/status registers.
921 */
922 pci_enable_busmaster(dev);
923
924 error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res);
925 if (error) {
926 device_printf(dev, "couldn't allocate resources\n");
927 goto fail;
928 }
929
930 /* Reset the adapter. */
931 sis_reset(sc);
932
933 if (sc->sis_type == SIS_TYPE_900 &&
934 (sc->sis_rev == SIS_REV_635 ||
935 sc->sis_rev == SIS_REV_900B)) {
936 SIO_SET(SIS_CFG_RND_CNT);
937 SIO_SET(SIS_CFG_PERR_DETECT);
938 }
939
940 /*
941 * Get station address from the EEPROM.
942 */
943 switch (pci_get_vendor(dev)) {
944 case NS_VENDORID:
945 sc->sis_srr = CSR_READ_4(sc, NS_SRR);
946
947 /* We can't update the device description, so spew */
948 if (sc->sis_srr == NS_SRR_15C)
949 device_printf(dev, "Silicon Revision: DP83815C\n");
950 else if (sc->sis_srr == NS_SRR_15D)
951 device_printf(dev, "Silicon Revision: DP83815D\n");
952 else if (sc->sis_srr == NS_SRR_16A)
953 device_printf(dev, "Silicon Revision: DP83816A\n");
954 else
955 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr);
956
957 /*
958 * Reading the MAC address out of the EEPROM on
959 * the NatSemi chip takes a bit more work than
960 * you'd expect. The address spans 4 16-bit words,
961 * with the first word containing only a single bit.
962 * You have to shift everything over one bit to
963 * get it aligned properly. Also, the bits are
964 * stored backwards (the LSB is really the MSB,
965 * and so on) so you have to reverse them in order
966 * to get the MAC address into the form we want.
967 * Why? Who the hell knows.
968 */
969 {
970 uint16_t tmp[4];
971
972 sis_read_eeprom(sc, (caddr_t)&tmp,
973 NS_EE_NODEADDR, 4, 0);
974
975 /* Shift everything over one bit. */
976 tmp[3] = tmp[3] >> 1;
977 tmp[3] |= tmp[2] << 15;
978 tmp[2] = tmp[2] >> 1;
979 tmp[2] |= tmp[1] << 15;
980 tmp[1] = tmp[1] >> 1;
981 tmp[1] |= tmp[0] << 15;
982
983 /* Now reverse all the bits. */
984 tmp[3] = sis_reverse(tmp[3]);
985 tmp[2] = sis_reverse(tmp[2]);
986 tmp[1] = sis_reverse(tmp[1]);
987
988 eaddr[0] = (tmp[1] >> 0) & 0xFF;
989 eaddr[1] = (tmp[1] >> 8) & 0xFF;
990 eaddr[2] = (tmp[2] >> 0) & 0xFF;
991 eaddr[3] = (tmp[2] >> 8) & 0xFF;
992 eaddr[4] = (tmp[3] >> 0) & 0xFF;
993 eaddr[5] = (tmp[3] >> 8) & 0xFF;
994 }
995 break;
996 case SIS_VENDORID:
997 default:
998 #if defined(__i386__) || defined(__amd64__)
999 /*
1000 * If this is a SiS 630E chipset with an embedded
1001 * SiS 900 controller, we have to read the MAC address
1002 * from the APC CMOS RAM. Our method for doing this
1003 * is very ugly since we have to reach out and grab
1004 * ahold of hardware for which we cannot properly
1005 * allocate resources. This code is only compiled on
1006 * the i386 architecture since the SiS 630E chipset
1007 * is for x86 motherboards only. Note that there are
1008 * a lot of magic numbers in this hack. These are
1009 * taken from SiS's Linux driver. I'd like to replace
1010 * them with proper symbolic definitions, but that
1011 * requires some datasheets that I don't have access
1012 * to at the moment.
1013 */
1014 if (sc->sis_rev == SIS_REV_630S ||
1015 sc->sis_rev == SIS_REV_630E ||
1016 sc->sis_rev == SIS_REV_630EA1)
1017 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1018
1019 else if (sc->sis_rev == SIS_REV_635 ||
1020 sc->sis_rev == SIS_REV_630ET)
1021 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1022 else if (sc->sis_rev == SIS_REV_96x) {
1023 /* Allow to read EEPROM from LAN. It is shared
1024 * between a 1394 controller and the NIC and each
1025 * time we access it, we need to set SIS_EECMD_REQ.
1026 */
1027 SIO_SET(SIS_EECMD_REQ);
1028 for (int waittime = 0; waittime < SIS_TIMEOUT;
1029 waittime++) {
1030 /* Force EEPROM to idle state. */
1031 sis_eeprom_idle(sc);
1032 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1033 sis_read_eeprom(sc, (caddr_t)&eaddr,
1034 SIS_EE_NODEADDR, 3, 0);
1035 break;
1036 }
1037 DELAY(1);
1038 }
1039 /*
1040 * Set SIS_EECTL_CLK to high, so a other master
1041 * can operate on the i2c bus.
1042 */
1043 SIO_SET(SIS_EECTL_CLK);
1044 /* Refuse EEPROM access by LAN */
1045 SIO_SET(SIS_EECMD_DONE);
1046 } else
1047 #endif
1048 sis_read_eeprom(sc, (caddr_t)&eaddr,
1049 SIS_EE_NODEADDR, 3, 0);
1050 break;
1051 }
1052
1053 sis_add_sysctls(sc);
1054
1055 /* Allocate DMA'able memory. */
1056 if ((error = sis_dma_alloc(sc)) != 0)
1057 goto fail;
1058
1059 ifp = sc->sis_ifp = if_alloc(IFT_ETHER);
1060 if_setsoftc(ifp, sc);
1061 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1062 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
1063 if_setioctlfn(ifp, sis_ioctl);
1064 if_setstartfn(ifp, sis_start);
1065 if_setinitfn(ifp, sis_init);
1066 if_setsendqlen(ifp, SIS_TX_LIST_CNT - 1);
1067 if_setsendqready(ifp);
1068
1069 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) == 0) {
1070 if (sc->sis_type == SIS_TYPE_83815)
1071 if_setcapabilitiesbit(ifp, IFCAP_WOL, 0);
1072 else
1073 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0);
1074 if_setcapenable(ifp, if_getcapabilities(ifp));
1075 }
1076
1077 /*
1078 * Do MII setup.
1079 */
1080 error = mii_attach(dev, &sc->sis_miibus, ifp, sis_ifmedia_upd,
1081 sis_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1082 if (error != 0) {
1083 device_printf(dev, "attaching PHYs failed\n");
1084 goto fail;
1085 }
1086
1087 /*
1088 * Call MI attach routine.
1089 */
1090 ether_ifattach(ifp, eaddr);
1091
1092 /*
1093 * Tell the upper layer(s) we support long frames.
1094 */
1095 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
1096 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
1097 if_setcapenable(ifp, if_getcapabilities(ifp));
1098 #ifdef DEVICE_POLLING
1099 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
1100 #endif
1101
1102 /* Hook interrupt last to avoid having to lock softc */
1103 error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE,
1104 NULL, sis_intr, sc, &sc->sis_intrhand);
1105
1106 if (error) {
1107 device_printf(dev, "couldn't set up irq\n");
1108 ether_ifdetach(ifp);
1109 goto fail;
1110 }
1111
1112 fail:
1113 if (error)
1114 sis_detach(dev);
1115
1116 return (error);
1117 }
1118
1119 /*
1120 * Shutdown hardware and free up resources. This can be called any
1121 * time after the mutex has been initialized. It is called in both
1122 * the error case in attach and the normal detach case so it needs
1123 * to be careful about only freeing resources that have actually been
1124 * allocated.
1125 */
1126 static int
sis_detach(device_t dev)1127 sis_detach(device_t dev)
1128 {
1129 struct sis_softc *sc;
1130 if_t ifp;
1131
1132 sc = device_get_softc(dev);
1133 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized"));
1134 ifp = sc->sis_ifp;
1135
1136 #ifdef DEVICE_POLLING
1137 if (if_getcapenable(ifp) & IFCAP_POLLING)
1138 ether_poll_deregister(ifp);
1139 #endif
1140
1141 /* These should only be active if attach succeeded. */
1142 if (device_is_attached(dev)) {
1143 SIS_LOCK(sc);
1144 sis_stop(sc);
1145 SIS_UNLOCK(sc);
1146 callout_drain(&sc->sis_stat_ch);
1147 ether_ifdetach(ifp);
1148 }
1149 if (sc->sis_miibus)
1150 device_delete_child(dev, sc->sis_miibus);
1151 bus_generic_detach(dev);
1152
1153 if (sc->sis_intrhand)
1154 bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand);
1155 bus_release_resources(dev, sis_res_spec, sc->sis_res);
1156
1157 if (ifp)
1158 if_free(ifp);
1159
1160 sis_dma_free(sc);
1161
1162 mtx_destroy(&sc->sis_mtx);
1163
1164 return (0);
1165 }
1166
1167 struct sis_dmamap_arg {
1168 bus_addr_t sis_busaddr;
1169 };
1170
1171 static void
sis_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int error)1172 sis_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1173 {
1174 struct sis_dmamap_arg *ctx;
1175
1176 if (error != 0)
1177 return;
1178
1179 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1180
1181 ctx = (struct sis_dmamap_arg *)arg;
1182 ctx->sis_busaddr = segs[0].ds_addr;
1183 }
1184
1185 static int
sis_dma_ring_alloc(struct sis_softc * sc,bus_size_t alignment,bus_size_t maxsize,bus_dma_tag_t * tag,uint8_t ** ring,bus_dmamap_t * map,bus_addr_t * paddr,const char * msg)1186 sis_dma_ring_alloc(struct sis_softc *sc, bus_size_t alignment,
1187 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
1188 bus_addr_t *paddr, const char *msg)
1189 {
1190 struct sis_dmamap_arg ctx;
1191 int error;
1192
1193 error = bus_dma_tag_create(sc->sis_parent_tag, alignment, 0,
1194 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1,
1195 maxsize, 0, NULL, NULL, tag);
1196 if (error != 0) {
1197 device_printf(sc->sis_dev,
1198 "could not create %s dma tag\n", msg);
1199 return (ENOMEM);
1200 }
1201 /* Allocate DMA'able memory for ring. */
1202 error = bus_dmamem_alloc(*tag, (void **)ring,
1203 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
1204 if (error != 0) {
1205 device_printf(sc->sis_dev,
1206 "could not allocate DMA'able memory for %s\n", msg);
1207 return (ENOMEM);
1208 }
1209 /* Load the address of the ring. */
1210 ctx.sis_busaddr = 0;
1211 error = bus_dmamap_load(*tag, *map, *ring, maxsize, sis_dmamap_cb,
1212 &ctx, BUS_DMA_NOWAIT);
1213 if (error != 0) {
1214 device_printf(sc->sis_dev,
1215 "could not load DMA'able memory for %s\n", msg);
1216 return (ENOMEM);
1217 }
1218 *paddr = ctx.sis_busaddr;
1219 return (0);
1220 }
1221
1222 static int
sis_dma_alloc(struct sis_softc * sc)1223 sis_dma_alloc(struct sis_softc *sc)
1224 {
1225 struct sis_rxdesc *rxd;
1226 struct sis_txdesc *txd;
1227 int error, i;
1228
1229 /* Allocate the parent bus DMA tag appropriate for PCI. */
1230 error = bus_dma_tag_create(bus_get_dma_tag(sc->sis_dev),
1231 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1232 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
1233 0, NULL, NULL, &sc->sis_parent_tag);
1234 if (error != 0) {
1235 device_printf(sc->sis_dev,
1236 "could not allocate parent dma tag\n");
1237 return (ENOMEM);
1238 }
1239
1240 /* Create RX ring. */
1241 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_RX_LIST_SZ,
1242 &sc->sis_rx_list_tag, (uint8_t **)&sc->sis_rx_list,
1243 &sc->sis_rx_list_map, &sc->sis_rx_paddr, "RX ring");
1244 if (error)
1245 return (error);
1246
1247 /* Create TX ring. */
1248 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_TX_LIST_SZ,
1249 &sc->sis_tx_list_tag, (uint8_t **)&sc->sis_tx_list,
1250 &sc->sis_tx_list_map, &sc->sis_tx_paddr, "TX ring");
1251 if (error)
1252 return (error);
1253
1254 /* Create tag for RX mbufs. */
1255 error = bus_dma_tag_create(sc->sis_parent_tag, SIS_RX_BUF_ALIGN, 0,
1256 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
1257 MCLBYTES, 0, NULL, NULL, &sc->sis_rx_tag);
1258 if (error) {
1259 device_printf(sc->sis_dev, "could not allocate RX dma tag\n");
1260 return (error);
1261 }
1262
1263 /* Create tag for TX mbufs. */
1264 error = bus_dma_tag_create(sc->sis_parent_tag, 1, 0,
1265 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1266 MCLBYTES * SIS_MAXTXSEGS, SIS_MAXTXSEGS, MCLBYTES, 0, NULL, NULL,
1267 &sc->sis_tx_tag);
1268 if (error) {
1269 device_printf(sc->sis_dev, "could not allocate TX dma tag\n");
1270 return (error);
1271 }
1272
1273 /* Create DMA maps for RX buffers. */
1274 error = bus_dmamap_create(sc->sis_rx_tag, 0, &sc->sis_rx_sparemap);
1275 if (error) {
1276 device_printf(sc->sis_dev,
1277 "can't create spare DMA map for RX\n");
1278 return (error);
1279 }
1280 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1281 rxd = &sc->sis_rxdesc[i];
1282 rxd->rx_m = NULL;
1283 error = bus_dmamap_create(sc->sis_rx_tag, 0, &rxd->rx_dmamap);
1284 if (error) {
1285 device_printf(sc->sis_dev,
1286 "can't create DMA map for RX\n");
1287 return (error);
1288 }
1289 }
1290
1291 /* Create DMA maps for TX buffers. */
1292 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1293 txd = &sc->sis_txdesc[i];
1294 txd->tx_m = NULL;
1295 error = bus_dmamap_create(sc->sis_tx_tag, 0, &txd->tx_dmamap);
1296 if (error) {
1297 device_printf(sc->sis_dev,
1298 "can't create DMA map for TX\n");
1299 return (error);
1300 }
1301 }
1302
1303 return (0);
1304 }
1305
1306 static void
sis_dma_free(struct sis_softc * sc)1307 sis_dma_free(struct sis_softc *sc)
1308 {
1309 struct sis_rxdesc *rxd;
1310 struct sis_txdesc *txd;
1311 int i;
1312
1313 /* Destroy DMA maps for RX buffers. */
1314 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1315 rxd = &sc->sis_rxdesc[i];
1316 if (rxd->rx_dmamap)
1317 bus_dmamap_destroy(sc->sis_rx_tag, rxd->rx_dmamap);
1318 }
1319 if (sc->sis_rx_sparemap)
1320 bus_dmamap_destroy(sc->sis_rx_tag, sc->sis_rx_sparemap);
1321
1322 /* Destroy DMA maps for TX buffers. */
1323 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1324 txd = &sc->sis_txdesc[i];
1325 if (txd->tx_dmamap)
1326 bus_dmamap_destroy(sc->sis_tx_tag, txd->tx_dmamap);
1327 }
1328
1329 if (sc->sis_rx_tag)
1330 bus_dma_tag_destroy(sc->sis_rx_tag);
1331 if (sc->sis_tx_tag)
1332 bus_dma_tag_destroy(sc->sis_tx_tag);
1333
1334 /* Destroy RX ring. */
1335 if (sc->sis_rx_paddr)
1336 bus_dmamap_unload(sc->sis_rx_list_tag, sc->sis_rx_list_map);
1337 if (sc->sis_rx_list)
1338 bus_dmamem_free(sc->sis_rx_list_tag, sc->sis_rx_list,
1339 sc->sis_rx_list_map);
1340
1341 if (sc->sis_rx_list_tag)
1342 bus_dma_tag_destroy(sc->sis_rx_list_tag);
1343
1344 /* Destroy TX ring. */
1345 if (sc->sis_tx_paddr)
1346 bus_dmamap_unload(sc->sis_tx_list_tag, sc->sis_tx_list_map);
1347
1348 if (sc->sis_tx_list)
1349 bus_dmamem_free(sc->sis_tx_list_tag, sc->sis_tx_list,
1350 sc->sis_tx_list_map);
1351
1352 if (sc->sis_tx_list_tag)
1353 bus_dma_tag_destroy(sc->sis_tx_list_tag);
1354
1355 /* Destroy the parent tag. */
1356 if (sc->sis_parent_tag)
1357 bus_dma_tag_destroy(sc->sis_parent_tag);
1358 }
1359
1360 /*
1361 * Initialize the TX and RX descriptors and allocate mbufs for them. Note that
1362 * we arrange the descriptors in a closed ring, so that the last descriptor
1363 * points back to the first.
1364 */
1365 static int
sis_ring_init(struct sis_softc * sc)1366 sis_ring_init(struct sis_softc *sc)
1367 {
1368 struct sis_rxdesc *rxd;
1369 struct sis_txdesc *txd;
1370 bus_addr_t next;
1371 int error, i;
1372
1373 bzero(&sc->sis_tx_list[0], SIS_TX_LIST_SZ);
1374 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1375 txd = &sc->sis_txdesc[i];
1376 txd->tx_m = NULL;
1377 if (i == SIS_TX_LIST_CNT - 1)
1378 next = SIS_TX_RING_ADDR(sc, 0);
1379 else
1380 next = SIS_TX_RING_ADDR(sc, i + 1);
1381 sc->sis_tx_list[i].sis_next = htole32(SIS_ADDR_LO(next));
1382 }
1383 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0;
1384 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1385 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1386
1387 sc->sis_rx_cons = 0;
1388 bzero(&sc->sis_rx_list[0], SIS_RX_LIST_SZ);
1389 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1390 rxd = &sc->sis_rxdesc[i];
1391 rxd->rx_desc = &sc->sis_rx_list[i];
1392 if (i == SIS_RX_LIST_CNT - 1)
1393 next = SIS_RX_RING_ADDR(sc, 0);
1394 else
1395 next = SIS_RX_RING_ADDR(sc, i + 1);
1396 rxd->rx_desc->sis_next = htole32(SIS_ADDR_LO(next));
1397 error = sis_newbuf(sc, rxd);
1398 if (error)
1399 return (error);
1400 }
1401 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1402 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1403
1404 return (0);
1405 }
1406
1407 /*
1408 * Initialize an RX descriptor and attach an MBUF cluster.
1409 */
1410 static int
sis_newbuf(struct sis_softc * sc,struct sis_rxdesc * rxd)1411 sis_newbuf(struct sis_softc *sc, struct sis_rxdesc *rxd)
1412 {
1413 struct mbuf *m;
1414 bus_dma_segment_t segs[1];
1415 bus_dmamap_t map;
1416 int nsegs;
1417
1418 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1419 if (m == NULL)
1420 return (ENOBUFS);
1421 m->m_len = m->m_pkthdr.len = SIS_RXLEN;
1422 #ifndef __NO_STRICT_ALIGNMENT
1423 m_adj(m, SIS_RX_BUF_ALIGN);
1424 #endif
1425
1426 if (bus_dmamap_load_mbuf_sg(sc->sis_rx_tag, sc->sis_rx_sparemap, m,
1427 segs, &nsegs, 0) != 0) {
1428 m_freem(m);
1429 return (ENOBUFS);
1430 }
1431 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1432
1433 if (rxd->rx_m != NULL) {
1434 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap,
1435 BUS_DMASYNC_POSTREAD);
1436 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap);
1437 }
1438 map = rxd->rx_dmamap;
1439 rxd->rx_dmamap = sc->sis_rx_sparemap;
1440 sc->sis_rx_sparemap = map;
1441 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD);
1442 rxd->rx_m = m;
1443 rxd->rx_desc->sis_ptr = htole32(SIS_ADDR_LO(segs[0].ds_addr));
1444 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN);
1445 return (0);
1446 }
1447
1448 static __inline void
sis_discard_rxbuf(struct sis_rxdesc * rxd)1449 sis_discard_rxbuf(struct sis_rxdesc *rxd)
1450 {
1451
1452 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN);
1453 }
1454
1455 #ifndef __NO_STRICT_ALIGNMENT
1456 static __inline void
sis_fixup_rx(struct mbuf * m)1457 sis_fixup_rx(struct mbuf *m)
1458 {
1459 uint16_t *src, *dst;
1460 int i;
1461
1462 src = mtod(m, uint16_t *);
1463 dst = src - (SIS_RX_BUF_ALIGN - ETHER_ALIGN) / sizeof(*src);
1464
1465 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1466 *dst++ = *src++;
1467
1468 m->m_data -= SIS_RX_BUF_ALIGN - ETHER_ALIGN;
1469 }
1470 #endif
1471
1472 /*
1473 * A frame has been uploaded: pass the resulting mbuf chain up to
1474 * the higher level protocols.
1475 */
1476 static int
sis_rxeof(struct sis_softc * sc)1477 sis_rxeof(struct sis_softc *sc)
1478 {
1479 struct mbuf *m;
1480 if_t ifp;
1481 struct sis_rxdesc *rxd;
1482 struct sis_desc *cur_rx;
1483 int prog, rx_cons, rx_npkts = 0, total_len;
1484 uint32_t rxstat;
1485
1486 SIS_LOCK_ASSERT(sc);
1487
1488 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1489 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1490
1491 rx_cons = sc->sis_rx_cons;
1492 ifp = sc->sis_ifp;
1493
1494 for (prog = 0; (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0;
1495 SIS_INC(rx_cons, SIS_RX_LIST_CNT), prog++) {
1496 #ifdef DEVICE_POLLING
1497 if (if_getcapenable(ifp) & IFCAP_POLLING) {
1498 if (sc->rxcycles <= 0)
1499 break;
1500 sc->rxcycles--;
1501 }
1502 #endif
1503 cur_rx = &sc->sis_rx_list[rx_cons];
1504 rxstat = le32toh(cur_rx->sis_cmdsts);
1505 if ((rxstat & SIS_CMDSTS_OWN) == 0)
1506 break;
1507 rxd = &sc->sis_rxdesc[rx_cons];
1508
1509 total_len = (rxstat & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN;
1510 if ((if_getcapenable(ifp) & IFCAP_VLAN_MTU) != 0 &&
1511 total_len <= (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN -
1512 ETHER_CRC_LEN))
1513 rxstat &= ~SIS_RXSTAT_GIANT;
1514 if (SIS_RXSTAT_ERROR(rxstat) != 0) {
1515 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1516 if (rxstat & SIS_RXSTAT_COLL)
1517 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1518 sis_discard_rxbuf(rxd);
1519 continue;
1520 }
1521
1522 /* Add a new receive buffer to the ring. */
1523 m = rxd->rx_m;
1524 if (sis_newbuf(sc, rxd) != 0) {
1525 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1526 sis_discard_rxbuf(rxd);
1527 continue;
1528 }
1529
1530 /* No errors; receive the packet. */
1531 m->m_pkthdr.len = m->m_len = total_len;
1532 #ifndef __NO_STRICT_ALIGNMENT
1533 /*
1534 * On architectures without alignment problems we try to
1535 * allocate a new buffer for the receive ring, and pass up
1536 * the one where the packet is already, saving the expensive
1537 * copy operation.
1538 */
1539 sis_fixup_rx(m);
1540 #endif
1541 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1542 m->m_pkthdr.rcvif = ifp;
1543
1544 SIS_UNLOCK(sc);
1545 if_input(ifp, m);
1546 SIS_LOCK(sc);
1547 rx_npkts++;
1548 }
1549
1550 if (prog > 0) {
1551 sc->sis_rx_cons = rx_cons;
1552 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1553 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1554 }
1555
1556 return (rx_npkts);
1557 }
1558
1559 /*
1560 * A frame was downloaded to the chip. It's safe for us to clean up
1561 * the list buffers.
1562 */
1563
1564 static void
sis_txeof(struct sis_softc * sc)1565 sis_txeof(struct sis_softc *sc)
1566 {
1567 if_t ifp;
1568 struct sis_desc *cur_tx;
1569 struct sis_txdesc *txd;
1570 uint32_t cons, txstat;
1571
1572 SIS_LOCK_ASSERT(sc);
1573
1574 cons = sc->sis_tx_cons;
1575 if (cons == sc->sis_tx_prod)
1576 return;
1577
1578 ifp = sc->sis_ifp;
1579 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1580 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1581
1582 /*
1583 * Go through our tx list and free mbufs for those
1584 * frames that have been transmitted.
1585 */
1586 for (; cons != sc->sis_tx_prod; SIS_INC(cons, SIS_TX_LIST_CNT)) {
1587 cur_tx = &sc->sis_tx_list[cons];
1588 txstat = le32toh(cur_tx->sis_cmdsts);
1589 if ((txstat & SIS_CMDSTS_OWN) != 0)
1590 break;
1591 txd = &sc->sis_txdesc[cons];
1592 if (txd->tx_m != NULL) {
1593 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap,
1594 BUS_DMASYNC_POSTWRITE);
1595 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
1596 m_freem(txd->tx_m);
1597 txd->tx_m = NULL;
1598 if ((txstat & SIS_CMDSTS_PKT_OK) != 0) {
1599 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1600 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
1601 (txstat & SIS_TXSTAT_COLLCNT) >> 16);
1602 } else {
1603 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1604 if (txstat & SIS_TXSTAT_EXCESSCOLLS)
1605 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1606 if (txstat & SIS_TXSTAT_OUTOFWINCOLL)
1607 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1608 }
1609 }
1610 sc->sis_tx_cnt--;
1611 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1612 }
1613 sc->sis_tx_cons = cons;
1614 if (sc->sis_tx_cnt == 0)
1615 sc->sis_watchdog_timer = 0;
1616 }
1617
1618 static void
sis_tick(void * xsc)1619 sis_tick(void *xsc)
1620 {
1621 struct sis_softc *sc;
1622 struct mii_data *mii;
1623
1624 sc = xsc;
1625 SIS_LOCK_ASSERT(sc);
1626
1627 mii = device_get_softc(sc->sis_miibus);
1628 mii_tick(mii);
1629 sis_watchdog(sc);
1630 if ((sc->sis_flags & SIS_FLAG_LINK) == 0)
1631 sis_miibus_statchg(sc->sis_dev);
1632 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
1633 }
1634
1635 #ifdef DEVICE_POLLING
1636 static poll_handler_t sis_poll;
1637
1638 static int
sis_poll(if_t ifp,enum poll_cmd cmd,int count)1639 sis_poll(if_t ifp, enum poll_cmd cmd, int count)
1640 {
1641 struct sis_softc *sc = if_getsoftc(ifp);
1642 int rx_npkts = 0;
1643
1644 SIS_LOCK(sc);
1645 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
1646 SIS_UNLOCK(sc);
1647 return (rx_npkts);
1648 }
1649
1650 /*
1651 * On the sis, reading the status register also clears it.
1652 * So before returning to intr mode we must make sure that all
1653 * possible pending sources of interrupts have been served.
1654 * In practice this means run to completion the *eof routines,
1655 * and then call the interrupt routine
1656 */
1657 sc->rxcycles = count;
1658 rx_npkts = sis_rxeof(sc);
1659 sis_txeof(sc);
1660 if (!if_sendq_empty(ifp))
1661 sis_startl(ifp);
1662
1663 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1664 uint32_t status;
1665
1666 /* Reading the ISR register clears all interrupts. */
1667 status = CSR_READ_4(sc, SIS_ISR);
1668
1669 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1670 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1671
1672 if (status & (SIS_ISR_RX_IDLE))
1673 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1674
1675 if (status & SIS_ISR_SYSERR) {
1676 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1677 sis_initl(sc);
1678 }
1679 }
1680
1681 SIS_UNLOCK(sc);
1682 return (rx_npkts);
1683 }
1684 #endif /* DEVICE_POLLING */
1685
1686 static void
sis_intr(void * arg)1687 sis_intr(void *arg)
1688 {
1689 struct sis_softc *sc;
1690 if_t ifp;
1691 uint32_t status;
1692
1693 sc = arg;
1694 ifp = sc->sis_ifp;
1695
1696 SIS_LOCK(sc);
1697 #ifdef DEVICE_POLLING
1698 if (if_getcapenable(ifp) & IFCAP_POLLING) {
1699 SIS_UNLOCK(sc);
1700 return;
1701 }
1702 #endif
1703
1704 /* Reading the ISR register clears all interrupts. */
1705 status = CSR_READ_4(sc, SIS_ISR);
1706 if ((status & SIS_INTRS) == 0) {
1707 /* Not ours. */
1708 SIS_UNLOCK(sc);
1709 return;
1710 }
1711
1712 /* Disable interrupts. */
1713 CSR_WRITE_4(sc, SIS_IER, 0);
1714
1715 for (;(status & SIS_INTRS) != 0;) {
1716 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
1717 break;
1718 if (status &
1719 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR |
1720 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) )
1721 sis_txeof(sc);
1722
1723 if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK |
1724 SIS_ISR_RX_ERR | SIS_ISR_RX_IDLE))
1725 sis_rxeof(sc);
1726
1727 if (status & SIS_ISR_RX_OFLOW)
1728 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1729
1730 if (status & (SIS_ISR_RX_IDLE))
1731 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1732
1733 if (status & SIS_ISR_SYSERR) {
1734 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1735 sis_initl(sc);
1736 SIS_UNLOCK(sc);
1737 return;
1738 }
1739 status = CSR_READ_4(sc, SIS_ISR);
1740 }
1741
1742 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1743 /* Re-enable interrupts. */
1744 CSR_WRITE_4(sc, SIS_IER, 1);
1745
1746 if (!if_sendq_empty(ifp))
1747 sis_startl(ifp);
1748 }
1749
1750 SIS_UNLOCK(sc);
1751 }
1752
1753 /*
1754 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1755 * pointers to the fragment pointers.
1756 */
1757 static int
sis_encap(struct sis_softc * sc,struct mbuf ** m_head)1758 sis_encap(struct sis_softc *sc, struct mbuf **m_head)
1759 {
1760 struct mbuf *m;
1761 struct sis_txdesc *txd;
1762 struct sis_desc *f;
1763 bus_dma_segment_t segs[SIS_MAXTXSEGS];
1764 bus_dmamap_t map;
1765 int error, i, frag, nsegs, prod;
1766 int padlen;
1767
1768 prod = sc->sis_tx_prod;
1769 txd = &sc->sis_txdesc[prod];
1770 if ((sc->sis_flags & SIS_FLAG_MANUAL_PAD) != 0 &&
1771 (*m_head)->m_pkthdr.len < SIS_MIN_FRAMELEN) {
1772 m = *m_head;
1773 padlen = SIS_MIN_FRAMELEN - m->m_pkthdr.len;
1774 if (M_WRITABLE(m) == 0) {
1775 /* Get a writable copy. */
1776 m = m_dup(*m_head, M_NOWAIT);
1777 m_freem(*m_head);
1778 if (m == NULL) {
1779 *m_head = NULL;
1780 return (ENOBUFS);
1781 }
1782 *m_head = m;
1783 }
1784 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) {
1785 m = m_defrag(m, M_NOWAIT);
1786 if (m == NULL) {
1787 m_freem(*m_head);
1788 *m_head = NULL;
1789 return (ENOBUFS);
1790 }
1791 }
1792 /*
1793 * Manually pad short frames, and zero the pad space
1794 * to avoid leaking data.
1795 */
1796 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1797 m->m_pkthdr.len += padlen;
1798 m->m_len = m->m_pkthdr.len;
1799 *m_head = m;
1800 }
1801 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap,
1802 *m_head, segs, &nsegs, 0);
1803 if (error == EFBIG) {
1804 m = m_collapse(*m_head, M_NOWAIT, SIS_MAXTXSEGS);
1805 if (m == NULL) {
1806 m_freem(*m_head);
1807 *m_head = NULL;
1808 return (ENOBUFS);
1809 }
1810 *m_head = m;
1811 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap,
1812 *m_head, segs, &nsegs, 0);
1813 if (error != 0) {
1814 m_freem(*m_head);
1815 *m_head = NULL;
1816 return (error);
1817 }
1818 } else if (error != 0)
1819 return (error);
1820
1821 /* Check for descriptor overruns. */
1822 if (sc->sis_tx_cnt + nsegs > SIS_TX_LIST_CNT - 1) {
1823 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
1824 return (ENOBUFS);
1825 }
1826
1827 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, BUS_DMASYNC_PREWRITE);
1828
1829 frag = prod;
1830 for (i = 0; i < nsegs; i++) {
1831 f = &sc->sis_tx_list[prod];
1832 if (i == 0)
1833 f->sis_cmdsts = htole32(segs[i].ds_len |
1834 SIS_CMDSTS_MORE);
1835 else
1836 f->sis_cmdsts = htole32(segs[i].ds_len |
1837 SIS_CMDSTS_OWN | SIS_CMDSTS_MORE);
1838 f->sis_ptr = htole32(SIS_ADDR_LO(segs[i].ds_addr));
1839 SIS_INC(prod, SIS_TX_LIST_CNT);
1840 sc->sis_tx_cnt++;
1841 }
1842
1843 /* Update producer index. */
1844 sc->sis_tx_prod = prod;
1845
1846 /* Remove MORE flag on the last descriptor. */
1847 prod = (prod - 1) & (SIS_TX_LIST_CNT - 1);
1848 f = &sc->sis_tx_list[prod];
1849 f->sis_cmdsts &= ~htole32(SIS_CMDSTS_MORE);
1850
1851 /* Lastly transfer ownership of packet to the controller. */
1852 f = &sc->sis_tx_list[frag];
1853 f->sis_cmdsts |= htole32(SIS_CMDSTS_OWN);
1854
1855 /* Swap the last and the first dmamaps. */
1856 map = txd->tx_dmamap;
1857 txd->tx_dmamap = sc->sis_txdesc[prod].tx_dmamap;
1858 sc->sis_txdesc[prod].tx_dmamap = map;
1859 sc->sis_txdesc[prod].tx_m = *m_head;
1860
1861 return (0);
1862 }
1863
1864 static void
sis_start(if_t ifp)1865 sis_start(if_t ifp)
1866 {
1867 struct sis_softc *sc;
1868
1869 sc = if_getsoftc(ifp);
1870 SIS_LOCK(sc);
1871 sis_startl(ifp);
1872 SIS_UNLOCK(sc);
1873 }
1874
1875 static void
sis_startl(if_t ifp)1876 sis_startl(if_t ifp)
1877 {
1878 struct sis_softc *sc;
1879 struct mbuf *m_head;
1880 int queued;
1881
1882 sc = if_getsoftc(ifp);
1883
1884 SIS_LOCK_ASSERT(sc);
1885
1886 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1887 IFF_DRV_RUNNING || (sc->sis_flags & SIS_FLAG_LINK) == 0)
1888 return;
1889
1890 for (queued = 0; !if_sendq_empty(ifp) &&
1891 sc->sis_tx_cnt < SIS_TX_LIST_CNT - 4;) {
1892 m_head = if_dequeue(ifp);
1893 if (m_head == NULL)
1894 break;
1895
1896 if (sis_encap(sc, &m_head) != 0) {
1897 if (m_head == NULL)
1898 break;
1899 if_sendq_prepend(ifp, m_head);
1900 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1901 break;
1902 }
1903
1904 queued++;
1905
1906 /*
1907 * If there's a BPF listener, bounce a copy of this frame
1908 * to him.
1909 */
1910 BPF_MTAP(ifp, m_head);
1911 }
1912
1913 if (queued) {
1914 /* Transmit */
1915 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1916 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1917 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1918
1919 /*
1920 * Set a timeout in case the chip goes out to lunch.
1921 */
1922 sc->sis_watchdog_timer = 5;
1923 }
1924 }
1925
1926 static void
sis_init(void * xsc)1927 sis_init(void *xsc)
1928 {
1929 struct sis_softc *sc = xsc;
1930
1931 SIS_LOCK(sc);
1932 sis_initl(sc);
1933 SIS_UNLOCK(sc);
1934 }
1935
1936 static void
sis_initl(struct sis_softc * sc)1937 sis_initl(struct sis_softc *sc)
1938 {
1939 if_t ifp = sc->sis_ifp;
1940 struct mii_data *mii;
1941 uint8_t *eaddr;
1942
1943 SIS_LOCK_ASSERT(sc);
1944
1945 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1946 return;
1947
1948 /*
1949 * Cancel pending I/O and free all RX/TX buffers.
1950 */
1951 sis_stop(sc);
1952 /*
1953 * Reset the chip to a known state.
1954 */
1955 sis_reset(sc);
1956 #ifdef notyet
1957 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
1958 /*
1959 * Configure 400usec of interrupt holdoff. This is based
1960 * on empirical tests on a Soekris 4801.
1961 */
1962 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4);
1963 }
1964 #endif
1965
1966 mii = device_get_softc(sc->sis_miibus);
1967
1968 /* Set MAC address */
1969 eaddr = if_getlladdr(sc->sis_ifp);
1970 if (sc->sis_type == SIS_TYPE_83815) {
1971 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1972 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8);
1973 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1974 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8);
1975 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1976 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8);
1977 } else {
1978 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1979 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8);
1980 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1981 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8);
1982 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1983 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8);
1984 }
1985
1986 /* Init circular TX/RX lists. */
1987 if (sis_ring_init(sc) != 0) {
1988 device_printf(sc->sis_dev,
1989 "initialization failed: no memory for rx buffers\n");
1990 sis_stop(sc);
1991 return;
1992 }
1993
1994 if (sc->sis_type == SIS_TYPE_83815) {
1995 if (sc->sis_manual_pad != 0)
1996 sc->sis_flags |= SIS_FLAG_MANUAL_PAD;
1997 else
1998 sc->sis_flags &= ~SIS_FLAG_MANUAL_PAD;
1999 }
2000
2001 /*
2002 * Short Cable Receive Errors (MP21.E)
2003 * also: Page 78 of the DP83815 data sheet (september 2002 version)
2004 * recommends the following register settings "for optimum
2005 * performance." for rev 15C. Set this also for 15D parts as
2006 * they require it in practice.
2007 */
2008 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) {
2009 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
2010 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
2011 /* set val for c2 */
2012 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
2013 /* load/kill c2 */
2014 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
2015 /* rais SD off, from 4 to c */
2016 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
2017 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
2018 }
2019
2020 sis_rxfilter(sc);
2021
2022 /*
2023 * Load the address of the RX and TX lists.
2024 */
2025 CSR_WRITE_4(sc, SIS_RX_LISTPTR, SIS_ADDR_LO(sc->sis_rx_paddr));
2026 CSR_WRITE_4(sc, SIS_TX_LISTPTR, SIS_ADDR_LO(sc->sis_tx_paddr));
2027
2028 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
2029 * the PCI bus. When this bit is set, the Max DMA Burst Size
2030 * for TX/RX DMA should be no larger than 16 double words.
2031 */
2032 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) {
2033 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
2034 } else {
2035 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
2036 }
2037
2038 /* Accept Long Packets for VLAN support */
2039 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
2040
2041 /*
2042 * Assume 100Mbps link, actual MAC configuration is done
2043 * after getting a valid link.
2044 */
2045 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
2046
2047 /*
2048 * Enable interrupts.
2049 */
2050 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
2051 #ifdef DEVICE_POLLING
2052 /*
2053 * ... only enable interrupts if we are not polling, make sure
2054 * they are off otherwise.
2055 */
2056 if (if_getcapenable(ifp) & IFCAP_POLLING)
2057 CSR_WRITE_4(sc, SIS_IER, 0);
2058 else
2059 #endif
2060 CSR_WRITE_4(sc, SIS_IER, 1);
2061
2062 /* Clear MAC disable. */
2063 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
2064
2065 sc->sis_flags &= ~SIS_FLAG_LINK;
2066 mii_mediachg(mii);
2067
2068 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
2069 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2070
2071 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
2072 }
2073
2074 /*
2075 * Set media options.
2076 */
2077 static int
sis_ifmedia_upd(if_t ifp)2078 sis_ifmedia_upd(if_t ifp)
2079 {
2080 struct sis_softc *sc;
2081 struct mii_data *mii;
2082 struct mii_softc *miisc;
2083 int error;
2084
2085 sc = if_getsoftc(ifp);
2086
2087 SIS_LOCK(sc);
2088 mii = device_get_softc(sc->sis_miibus);
2089 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2090 PHY_RESET(miisc);
2091 error = mii_mediachg(mii);
2092 SIS_UNLOCK(sc);
2093
2094 return (error);
2095 }
2096
2097 /*
2098 * Report current media status.
2099 */
2100 static void
sis_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)2101 sis_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
2102 {
2103 struct sis_softc *sc;
2104 struct mii_data *mii;
2105
2106 sc = if_getsoftc(ifp);
2107
2108 SIS_LOCK(sc);
2109 mii = device_get_softc(sc->sis_miibus);
2110 mii_pollstat(mii);
2111 ifmr->ifm_active = mii->mii_media_active;
2112 ifmr->ifm_status = mii->mii_media_status;
2113 SIS_UNLOCK(sc);
2114 }
2115
2116 static int
sis_ioctl(if_t ifp,u_long command,caddr_t data)2117 sis_ioctl(if_t ifp, u_long command, caddr_t data)
2118 {
2119 struct sis_softc *sc = if_getsoftc(ifp);
2120 struct ifreq *ifr = (struct ifreq *) data;
2121 struct mii_data *mii;
2122 int error = 0, mask;
2123
2124 switch (command) {
2125 case SIOCSIFFLAGS:
2126 SIS_LOCK(sc);
2127 if (if_getflags(ifp) & IFF_UP) {
2128 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 &&
2129 ((if_getflags(ifp) ^ sc->sis_if_flags) &
2130 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2131 sis_rxfilter(sc);
2132 else
2133 sis_initl(sc);
2134 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
2135 sis_stop(sc);
2136 sc->sis_if_flags = if_getflags(ifp);
2137 SIS_UNLOCK(sc);
2138 break;
2139 case SIOCADDMULTI:
2140 case SIOCDELMULTI:
2141 SIS_LOCK(sc);
2142 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2143 sis_rxfilter(sc);
2144 SIS_UNLOCK(sc);
2145 break;
2146 case SIOCGIFMEDIA:
2147 case SIOCSIFMEDIA:
2148 mii = device_get_softc(sc->sis_miibus);
2149 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2150 break;
2151 case SIOCSIFCAP:
2152 SIS_LOCK(sc);
2153 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
2154 #ifdef DEVICE_POLLING
2155 if ((mask & IFCAP_POLLING) != 0 &&
2156 (IFCAP_POLLING & if_getcapabilities(ifp)) != 0) {
2157 if_togglecapenable(ifp, IFCAP_POLLING);
2158 if ((IFCAP_POLLING & if_getcapenable(ifp)) != 0) {
2159 error = ether_poll_register(sis_poll, ifp);
2160 if (error != 0) {
2161 SIS_UNLOCK(sc);
2162 break;
2163 }
2164 /* Disable interrupts. */
2165 CSR_WRITE_4(sc, SIS_IER, 0);
2166 } else {
2167 error = ether_poll_deregister(ifp);
2168 /* Enable interrupts. */
2169 CSR_WRITE_4(sc, SIS_IER, 1);
2170 }
2171 }
2172 #endif /* DEVICE_POLLING */
2173 if ((mask & IFCAP_WOL) != 0 &&
2174 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) {
2175 if ((mask & IFCAP_WOL_UCAST) != 0)
2176 if_togglecapenable(ifp, IFCAP_WOL_UCAST);
2177 if ((mask & IFCAP_WOL_MCAST) != 0)
2178 if_togglecapenable(ifp, IFCAP_WOL_MCAST);
2179 if ((mask & IFCAP_WOL_MAGIC) != 0)
2180 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
2181 }
2182 SIS_UNLOCK(sc);
2183 break;
2184 default:
2185 error = ether_ioctl(ifp, command, data);
2186 break;
2187 }
2188
2189 return (error);
2190 }
2191
2192 static void
sis_watchdog(struct sis_softc * sc)2193 sis_watchdog(struct sis_softc *sc)
2194 {
2195
2196 SIS_LOCK_ASSERT(sc);
2197
2198 if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0)
2199 return;
2200
2201 device_printf(sc->sis_dev, "watchdog timeout\n");
2202 if_inc_counter(sc->sis_ifp, IFCOUNTER_OERRORS, 1);
2203
2204 if_setdrvflagbits(sc->sis_ifp, 0, IFF_DRV_RUNNING);
2205 sis_initl(sc);
2206
2207 if (!if_sendq_empty(sc->sis_ifp))
2208 sis_startl(sc->sis_ifp);
2209 }
2210
2211 /*
2212 * Stop the adapter and free any mbufs allocated to the
2213 * RX and TX lists.
2214 */
2215 static void
sis_stop(struct sis_softc * sc)2216 sis_stop(struct sis_softc *sc)
2217 {
2218 if_t ifp;
2219 struct sis_rxdesc *rxd;
2220 struct sis_txdesc *txd;
2221 int i;
2222
2223 SIS_LOCK_ASSERT(sc);
2224
2225 ifp = sc->sis_ifp;
2226 sc->sis_watchdog_timer = 0;
2227
2228 callout_stop(&sc->sis_stat_ch);
2229
2230 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2231 CSR_WRITE_4(sc, SIS_IER, 0);
2232 CSR_WRITE_4(sc, SIS_IMR, 0);
2233 CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */
2234 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2235 DELAY(1000);
2236 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2237 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2238
2239 sc->sis_flags &= ~SIS_FLAG_LINK;
2240
2241 /*
2242 * Free data in the RX lists.
2243 */
2244 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2245 rxd = &sc->sis_rxdesc[i];
2246 if (rxd->rx_m != NULL) {
2247 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap,
2248 BUS_DMASYNC_POSTREAD);
2249 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap);
2250 m_freem(rxd->rx_m);
2251 rxd->rx_m = NULL;
2252 }
2253 }
2254
2255 /*
2256 * Free the TX list buffers.
2257 */
2258 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2259 txd = &sc->sis_txdesc[i];
2260 if (txd->tx_m != NULL) {
2261 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap,
2262 BUS_DMASYNC_POSTWRITE);
2263 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
2264 m_freem(txd->tx_m);
2265 txd->tx_m = NULL;
2266 }
2267 }
2268 }
2269
2270 /*
2271 * Stop all chip I/O so that the kernel's probe routines don't
2272 * get confused by errant DMAs when rebooting.
2273 */
2274 static int
sis_shutdown(device_t dev)2275 sis_shutdown(device_t dev)
2276 {
2277
2278 return (sis_suspend(dev));
2279 }
2280
2281 static int
sis_suspend(device_t dev)2282 sis_suspend(device_t dev)
2283 {
2284 struct sis_softc *sc;
2285
2286 sc = device_get_softc(dev);
2287 SIS_LOCK(sc);
2288 sis_stop(sc);
2289 sis_wol(sc);
2290 SIS_UNLOCK(sc);
2291 return (0);
2292 }
2293
2294 static int
sis_resume(device_t dev)2295 sis_resume(device_t dev)
2296 {
2297 struct sis_softc *sc;
2298 if_t ifp;
2299
2300 sc = device_get_softc(dev);
2301 SIS_LOCK(sc);
2302 ifp = sc->sis_ifp;
2303 if ((if_getflags(ifp) & IFF_UP) != 0) {
2304 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2305 sis_initl(sc);
2306 }
2307 SIS_UNLOCK(sc);
2308 return (0);
2309 }
2310
2311 static void
sis_wol(struct sis_softc * sc)2312 sis_wol(struct sis_softc *sc)
2313 {
2314 if_t ifp;
2315 uint32_t val;
2316 uint16_t pmstat;
2317 int pmc;
2318
2319 ifp = sc->sis_ifp;
2320 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0)
2321 return;
2322
2323 if (sc->sis_type == SIS_TYPE_83815) {
2324 /* Reset RXDP. */
2325 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2326
2327 /* Configure WOL events. */
2328 CSR_READ_4(sc, NS_WCSR);
2329 val = 0;
2330 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) != 0)
2331 val |= NS_WCSR_WAKE_UCAST;
2332 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0)
2333 val |= NS_WCSR_WAKE_MCAST;
2334 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
2335 val |= NS_WCSR_WAKE_MAGIC;
2336 CSR_WRITE_4(sc, NS_WCSR, val);
2337 /* Enable PME and clear PMESTS. */
2338 val = CSR_READ_4(sc, NS_CLKRUN);
2339 val |= NS_CLKRUN_PMEENB | NS_CLKRUN_PMESTS;
2340 CSR_WRITE_4(sc, NS_CLKRUN, val);
2341 /* Enable silent RX mode. */
2342 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
2343 } else {
2344 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) != 0)
2345 return;
2346 val = 0;
2347 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
2348 val |= SIS_PWRMAN_WOL_MAGIC;
2349 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, val);
2350 /* Request PME. */
2351 pmstat = pci_read_config(sc->sis_dev,
2352 pmc + PCIR_POWER_STATUS, 2);
2353 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2354 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
2355 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2356 pci_write_config(sc->sis_dev,
2357 pmc + PCIR_POWER_STATUS, pmstat, 2);
2358 }
2359 }
2360
2361 static void
sis_add_sysctls(struct sis_softc * sc)2362 sis_add_sysctls(struct sis_softc *sc)
2363 {
2364 struct sysctl_ctx_list *ctx;
2365 struct sysctl_oid_list *children;
2366
2367 ctx = device_get_sysctl_ctx(sc->sis_dev);
2368 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sis_dev));
2369
2370 /*
2371 * Unlike most other controllers, NS DP83815/DP83816 controllers
2372 * seem to pad with 0xFF when it encounter short frames. According
2373 * to RFC 1042 the pad bytes should be 0x00. Turning this tunable
2374 * on will have driver pad manully but it's disabled by default
2375 * because it will consume extra CPU cycles for short frames.
2376 */
2377 sc->sis_manual_pad = 0;
2378 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "manual_pad",
2379 CTLFLAG_RWTUN, &sc->sis_manual_pad, 0, "Manually pad short frames");
2380 }
2381
2382 static device_method_t sis_methods[] = {
2383 /* Device interface */
2384 DEVMETHOD(device_probe, sis_probe),
2385 DEVMETHOD(device_attach, sis_attach),
2386 DEVMETHOD(device_detach, sis_detach),
2387 DEVMETHOD(device_shutdown, sis_shutdown),
2388 DEVMETHOD(device_suspend, sis_suspend),
2389 DEVMETHOD(device_resume, sis_resume),
2390
2391 /* MII interface */
2392 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
2393 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
2394 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
2395
2396 DEVMETHOD_END
2397 };
2398
2399 static driver_t sis_driver = {
2400 "sis",
2401 sis_methods,
2402 sizeof(struct sis_softc)
2403 };
2404
2405 DRIVER_MODULE(sis, pci, sis_driver, 0, 0);
2406 DRIVER_MODULE(miibus, sis, miibus_driver, 0, 0);
2407