1 /*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $
33 */
34
35 /*
36 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
37 * available from http://www.sis.com.tw.
38 *
39 * This driver also supports the NatSemi DP83815. Datasheets are
40 * available from http://www.national.com.
41 *
42 * Written by Bill Paul <wpaul@ee.columbia.edu>
43 * Electrical Engineering Department
44 * Columbia University, New York City
45 */
46
47 /*
48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
49 * simple TX and RX descriptors of 3 longwords in size. The receiver
50 * has a single perfect filter entry for the station address and a
51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
52 * transceiver while the 7016 requires an external transceiver chip.
53 * Both chips offer the standard bit-bang MII interface as well as
54 * an enchanced PHY interface which simplifies accessing MII registers.
55 *
56 * The only downside to this chipset is that RX descriptors must be
57 * longword aligned.
58 */
59
60 #include "opt_ifpoll.h"
61
62 #include <sys/param.h>
63 #include <sys/systm.h>
64 #include <sys/sockio.h>
65 #include <sys/mbuf.h>
66 #include <sys/malloc.h>
67 #include <sys/kernel.h>
68 #include <sys/socket.h>
69 #include <sys/sysctl.h>
70 #include <sys/serialize.h>
71 #include <sys/bus.h>
72 #include <sys/rman.h>
73 #include <sys/interrupt.h>
74
75 #include <net/if.h>
76 #include <net/ifq_var.h>
77 #include <net/if_arp.h>
78 #include <net/ethernet.h>
79 #include <net/if_dl.h>
80 #include <net/if_media.h>
81 #include <net/if_poll.h>
82 #include <net/if_types.h>
83 #include <net/vlan/if_vlan_var.h>
84
85 #include <net/bpf.h>
86
87 #include <dev/netif/mii_layer/mii.h>
88 #include <dev/netif/mii_layer/miivar.h>
89
90 #include "pcidevs.h"
91 #include <bus/pci/pcireg.h>
92 #include <bus/pci/pcivar.h>
93
94 #define SIS_USEIOSPACE
95
96 #include "if_sisreg.h"
97
98 /* "controller miibus0" required. See GENERIC if you get errors here. */
99 #include "miibus_if.h"
100
101 /*
102 * Various supported device vendors/types and their names.
103 */
104 static struct sis_type sis_devs[] = {
105 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, "SiS 900 10/100BaseTX" },
106 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, "SiS 7016 10/100BaseTX" },
107 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
108 { 0, 0, NULL }
109 };
110
111 static int sis_probe(device_t);
112 static int sis_attach(device_t);
113 static int sis_detach(device_t);
114
115 static int sis_newbuf(struct sis_softc *, int, int);
116 static void sis_setup_rxdesc(struct sis_softc *, int);
117 static int sis_encap(struct sis_softc *, struct mbuf **, uint32_t *);
118 static void sis_rxeof(struct sis_softc *);
119 static void sis_rxeoc(struct sis_softc *);
120 static void sis_txeof(struct sis_softc *);
121 static void sis_intr(void *);
122 static void sis_tick(void *);
123 static void sis_start(struct ifnet *, struct ifaltq_subque *);
124 static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
125 static void sis_init(void *);
126 static void sis_stop(struct sis_softc *);
127 static void sis_watchdog(struct ifnet *);
128 static void sis_shutdown(device_t);
129 static int sis_ifmedia_upd(struct ifnet *);
130 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
131
132 static uint16_t sis_reverse(uint16_t);
133 static void sis_delay(struct sis_softc *);
134 static void sis_eeprom_idle(struct sis_softc *);
135 static void sis_eeprom_putbyte(struct sis_softc *, int);
136 static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *);
137 static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int);
138 #ifdef __x86_64__
139 static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int);
140 static void sis_read_mac(struct sis_softc *, device_t, caddr_t);
141 static device_t sis_find_bridge(device_t);
142 #endif
143
144 static void sis_mii_sync(struct sis_softc *);
145 static void sis_mii_send(struct sis_softc *, uint32_t, int);
146 static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *);
147 static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *);
148 static int sis_miibus_readreg(device_t, int, int);
149 static int sis_miibus_writereg(device_t, int, int, int);
150 static void sis_miibus_statchg(device_t);
151
152 static void sis_setmulti_sis(struct sis_softc *);
153 static void sis_setmulti_ns(struct sis_softc *);
154 static uint32_t sis_mchash(struct sis_softc *, const uint8_t *);
155 static void sis_reset(struct sis_softc *);
156 static int sis_list_rx_init(struct sis_softc *);
157 static int sis_list_tx_init(struct sis_softc *);
158
159 static int sis_dma_alloc(device_t dev);
160 static void sis_dma_free(device_t dev);
161 #ifdef IFPOLL_ENABLE
162 static void sis_npoll(struct ifnet *, struct ifpoll_info *);
163 static void sis_npoll_compat(struct ifnet *, void *, int);
164 #endif
165 #ifdef SIS_USEIOSPACE
166 #define SIS_RES SYS_RES_IOPORT
167 #define SIS_RID SIS_PCI_LOIO
168 #else
169 #define SIS_RES SYS_RES_MEMORY
170 #define SIS_RID SIS_PCI_LOMEM
171 #endif
172
173 static device_method_t sis_methods[] = {
174 /* Device interface */
175 DEVMETHOD(device_probe, sis_probe),
176 DEVMETHOD(device_attach, sis_attach),
177 DEVMETHOD(device_detach, sis_detach),
178 DEVMETHOD(device_shutdown, sis_shutdown),
179
180 /* bus interface */
181 DEVMETHOD(bus_print_child, bus_generic_print_child),
182 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
183
184 /* MII interface */
185 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
186 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
187 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
188
189 DEVMETHOD_END
190 };
191
192 static driver_t sis_driver = {
193 "sis",
194 sis_methods,
195 sizeof(struct sis_softc)
196 };
197
198 static devclass_t sis_devclass;
199
200 DECLARE_DUMMY_MODULE(if_sis);
201 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, NULL, NULL);
202 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, NULL, NULL);
203
204 #define SIS_SETBIT(sc, reg, x) \
205 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
206
207 #define SIS_CLRBIT(sc, reg, x) \
208 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
209
210 #define SIO_SET(x) \
211 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
212
213 #define SIO_CLR(x) \
214 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
215
216 /*
217 * Routine to reverse the bits in a word. Stolen almost
218 * verbatim from /usr/games/fortune.
219 */
220 static uint16_t
sis_reverse(uint16_t n)221 sis_reverse(uint16_t n)
222 {
223 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
224 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
225 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
226 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
227
228 return(n);
229 }
230
231 static void
sis_delay(struct sis_softc * sc)232 sis_delay(struct sis_softc *sc)
233 {
234 int idx;
235
236 for (idx = (300 / 33) + 1; idx > 0; idx--)
237 CSR_READ_4(sc, SIS_CSR);
238 }
239
240 static void
sis_eeprom_idle(struct sis_softc * sc)241 sis_eeprom_idle(struct sis_softc *sc)
242 {
243 int i;
244
245 SIO_SET(SIS_EECTL_CSEL);
246 sis_delay(sc);
247 SIO_SET(SIS_EECTL_CLK);
248 sis_delay(sc);
249
250 for (i = 0; i < 25; i++) {
251 SIO_CLR(SIS_EECTL_CLK);
252 sis_delay(sc);
253 SIO_SET(SIS_EECTL_CLK);
254 sis_delay(sc);
255 }
256
257 SIO_CLR(SIS_EECTL_CLK);
258 sis_delay(sc);
259 SIO_CLR(SIS_EECTL_CSEL);
260 sis_delay(sc);
261 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
262 }
263
264 /*
265 * Send a read command and address to the EEPROM, check for ACK.
266 */
267 static void
sis_eeprom_putbyte(struct sis_softc * sc,int addr)268 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
269 {
270 int d, i;
271
272 d = addr | SIS_EECMD_READ;
273
274 /*
275 * Feed in each bit and stobe the clock.
276 */
277 for (i = 0x400; i; i >>= 1) {
278 if (d & i)
279 SIO_SET(SIS_EECTL_DIN);
280 else
281 SIO_CLR(SIS_EECTL_DIN);
282 sis_delay(sc);
283 SIO_SET(SIS_EECTL_CLK);
284 sis_delay(sc);
285 SIO_CLR(SIS_EECTL_CLK);
286 sis_delay(sc);
287 }
288 }
289
290 /*
291 * Read a word of data stored in the EEPROM at address 'addr.'
292 */
293 static void
sis_eeprom_getword(struct sis_softc * sc,int addr,uint16_t * dest)294 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
295 {
296 int i;
297 uint16_t word = 0;
298
299 /* Force EEPROM to idle state. */
300 sis_eeprom_idle(sc);
301
302 /* Enter EEPROM access mode. */
303 sis_delay(sc);
304 SIO_CLR(SIS_EECTL_CLK);
305 sis_delay(sc);
306 SIO_SET(SIS_EECTL_CSEL);
307 sis_delay(sc);
308
309 /*
310 * Send address of word we want to read.
311 */
312 sis_eeprom_putbyte(sc, addr);
313
314 /*
315 * Start reading bits from EEPROM.
316 */
317 for (i = 0x8000; i; i >>= 1) {
318 SIO_SET(SIS_EECTL_CLK);
319 sis_delay(sc);
320 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
321 word |= i;
322 sis_delay(sc);
323 SIO_CLR(SIS_EECTL_CLK);
324 sis_delay(sc);
325 }
326
327 /* Turn off EEPROM access mode. */
328 sis_eeprom_idle(sc);
329
330 *dest = word;
331 }
332
333 /*
334 * Read a sequence of words from the EEPROM.
335 */
336 static void
sis_read_eeprom(struct sis_softc * sc,caddr_t dest,int off,int cnt,int swap)337 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
338 {
339 int i;
340 uint16_t word = 0, *ptr;
341
342 for (i = 0; i < cnt; i++) {
343 sis_eeprom_getword(sc, off + i, &word);
344 ptr = (uint16_t *)(dest + (i * 2));
345 if (swap)
346 *ptr = ntohs(word);
347 else
348 *ptr = word;
349 }
350 }
351
352 #ifdef __x86_64__
353 static device_t
sis_find_bridge(device_t dev)354 sis_find_bridge(device_t dev)
355 {
356 devclass_t pci_devclass;
357 device_t *pci_devices;
358 int pci_count = 0;
359 device_t *pci_children;
360 int pci_childcount = 0;
361 device_t *busp, *childp;
362 device_t child = NULL;
363 int i, j;
364
365 if ((pci_devclass = devclass_find("pci")) == NULL)
366 return(NULL);
367
368 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
369
370 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
371 pci_childcount = 0;
372 device_get_children(*busp, &pci_children, &pci_childcount);
373 for (j = 0, childp = pci_children; j < pci_childcount;
374 j++, childp++) {
375 if (pci_get_vendor(*childp) == PCI_VENDOR_SIS &&
376 pci_get_device(*childp) == 0x0008) {
377 child = *childp;
378 goto done;
379 }
380 }
381 }
382
383 done:
384 kfree(pci_devices, M_TEMP);
385 kfree(pci_children, M_TEMP);
386 return(child);
387 }
388
389 static void
sis_read_cmos(struct sis_softc * sc,device_t dev,caddr_t dest,int off,int cnt)390 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off,
391 int cnt)
392 {
393 device_t bridge;
394 uint8_t reg;
395 int i;
396 bus_space_tag_t btag;
397
398 bridge = sis_find_bridge(dev);
399 if (bridge == NULL)
400 return;
401 reg = pci_read_config(bridge, 0x48, 1);
402 pci_write_config(bridge, 0x48, reg|0x40, 1);
403
404 /* XXX */
405 btag = X86_64_BUS_SPACE_IO;
406
407 for (i = 0; i < cnt; i++) {
408 bus_space_write_1(btag, 0x0, 0x70, i + off);
409 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
410 }
411
412 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
413 }
414
415 static void
sis_read_mac(struct sis_softc * sc,device_t dev,caddr_t dest)416 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
417 {
418 uint32_t filtsave, csrsave;
419
420 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
421 csrsave = CSR_READ_4(sc, SIS_CSR);
422
423 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
424 CSR_WRITE_4(sc, SIS_CSR, 0);
425
426 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
427
428 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
429 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
430 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
431 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
432 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
433 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
434
435 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
436 CSR_WRITE_4(sc, SIS_CSR, csrsave);
437 }
438 #endif
439
440 /*
441 * Sync the PHYs by setting data bit and strobing the clock 32 times.
442 */
443 static void
sis_mii_sync(struct sis_softc * sc)444 sis_mii_sync(struct sis_softc *sc)
445 {
446 int i;
447
448 SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
449
450 for (i = 0; i < 32; i++) {
451 SIO_SET(SIS_MII_CLK);
452 DELAY(1);
453 SIO_CLR(SIS_MII_CLK);
454 DELAY(1);
455 }
456 }
457
458 /*
459 * Clock a series of bits through the MII.
460 */
461 static void
sis_mii_send(struct sis_softc * sc,uint32_t bits,int cnt)462 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt)
463 {
464 int i;
465
466 SIO_CLR(SIS_MII_CLK);
467
468 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
469 if (bits & i)
470 SIO_SET(SIS_MII_DATA);
471 else
472 SIO_CLR(SIS_MII_DATA);
473 DELAY(1);
474 SIO_CLR(SIS_MII_CLK);
475 DELAY(1);
476 SIO_SET(SIS_MII_CLK);
477 }
478 }
479
480 /*
481 * Read an PHY register through the MII.
482 */
483 static int
sis_mii_readreg(struct sis_softc * sc,struct sis_mii_frame * frame)484 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame)
485 {
486 int i, ack;
487
488 /*
489 * Set up frame for RX.
490 */
491 frame->mii_stdelim = SIS_MII_STARTDELIM;
492 frame->mii_opcode = SIS_MII_READOP;
493 frame->mii_turnaround = 0;
494 frame->mii_data = 0;
495
496 /*
497 * Turn on data xmit.
498 */
499 SIO_SET(SIS_MII_DIR);
500
501 sis_mii_sync(sc);
502
503 /*
504 * Send command/address info.
505 */
506 sis_mii_send(sc, frame->mii_stdelim, 2);
507 sis_mii_send(sc, frame->mii_opcode, 2);
508 sis_mii_send(sc, frame->mii_phyaddr, 5);
509 sis_mii_send(sc, frame->mii_regaddr, 5);
510
511 /* Idle bit */
512 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
513 DELAY(1);
514 SIO_SET(SIS_MII_CLK);
515 DELAY(1);
516
517 /* Turn off xmit. */
518 SIO_CLR(SIS_MII_DIR);
519
520 /* Check for ack */
521 SIO_CLR(SIS_MII_CLK);
522 DELAY(1);
523 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
524 SIO_SET(SIS_MII_CLK);
525 DELAY(1);
526
527 /*
528 * Now try reading data bits. If the ack failed, we still
529 * need to clock through 16 cycles to keep the PHY(s) in sync.
530 */
531 if (ack) {
532 for(i = 0; i < 16; i++) {
533 SIO_CLR(SIS_MII_CLK);
534 DELAY(1);
535 SIO_SET(SIS_MII_CLK);
536 DELAY(1);
537 }
538 goto fail;
539 }
540
541 for (i = 0x8000; i; i >>= 1) {
542 SIO_CLR(SIS_MII_CLK);
543 DELAY(1);
544 if (!ack) {
545 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
546 frame->mii_data |= i;
547 DELAY(1);
548 }
549 SIO_SET(SIS_MII_CLK);
550 DELAY(1);
551 }
552
553 fail:
554
555 SIO_CLR(SIS_MII_CLK);
556 DELAY(1);
557 SIO_SET(SIS_MII_CLK);
558 DELAY(1);
559
560 if (ack)
561 return(1);
562 return(0);
563 }
564
565 /*
566 * Write to a PHY register through the MII.
567 */
568 static int
sis_mii_writereg(struct sis_softc * sc,struct sis_mii_frame * frame)569 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame)
570 {
571 /*
572 * Set up frame for TX.
573 */
574
575 frame->mii_stdelim = SIS_MII_STARTDELIM;
576 frame->mii_opcode = SIS_MII_WRITEOP;
577 frame->mii_turnaround = SIS_MII_TURNAROUND;
578
579 /*
580 * Turn on data output.
581 */
582 SIO_SET(SIS_MII_DIR);
583
584 sis_mii_sync(sc);
585
586 sis_mii_send(sc, frame->mii_stdelim, 2);
587 sis_mii_send(sc, frame->mii_opcode, 2);
588 sis_mii_send(sc, frame->mii_phyaddr, 5);
589 sis_mii_send(sc, frame->mii_regaddr, 5);
590 sis_mii_send(sc, frame->mii_turnaround, 2);
591 sis_mii_send(sc, frame->mii_data, 16);
592
593 /* Idle bit. */
594 SIO_SET(SIS_MII_CLK);
595 DELAY(1);
596 SIO_CLR(SIS_MII_CLK);
597 DELAY(1);
598
599 /*
600 * Turn off xmit.
601 */
602 SIO_CLR(SIS_MII_DIR);
603
604 return(0);
605 }
606
607 static int
sis_miibus_readreg(device_t dev,int phy,int reg)608 sis_miibus_readreg(device_t dev, int phy, int reg)
609 {
610 struct sis_softc *sc;
611 struct sis_mii_frame frame;
612
613 sc = device_get_softc(dev);
614
615 if (sc->sis_type == SIS_TYPE_83815) {
616 if (phy != 0)
617 return(0);
618 /*
619 * The NatSemi chip can take a while after
620 * a reset to come ready, during which the BMSR
621 * returns a value of 0. This is *never* supposed
622 * to happen: some of the BMSR bits are meant to
623 * be hardwired in the on position, and this can
624 * confuse the miibus code a bit during the probe
625 * and attach phase. So we make an effort to check
626 * for this condition and wait for it to clear.
627 */
628 if (!CSR_READ_4(sc, NS_BMSR))
629 DELAY(1000);
630 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
631 }
632 /*
633 * Chipsets < SIS_635 seem not to be able to read/write
634 * through mdio. Use the enhanced PHY access register
635 * again for them.
636 */
637 if (sc->sis_type == SIS_TYPE_900 &&
638 sc->sis_rev < SIS_REV_635) {
639 int i, val = 0;
640
641 if (phy != 0)
642 return(0);
643
644 CSR_WRITE_4(sc, SIS_PHYCTL,
645 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
646 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
647
648 for (i = 0; i < SIS_TIMEOUT; i++) {
649 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
650 break;
651 }
652
653 if (i == SIS_TIMEOUT) {
654 device_printf(dev, "PHY failed to come ready\n");
655 return(0);
656 }
657
658 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
659
660 if (val == 0xFFFF)
661 return(0);
662
663 return(val);
664 } else {
665 bzero((char *)&frame, sizeof(frame));
666
667 frame.mii_phyaddr = phy;
668 frame.mii_regaddr = reg;
669 sis_mii_readreg(sc, &frame);
670
671 return(frame.mii_data);
672 }
673 }
674
675 static int
sis_miibus_writereg(device_t dev,int phy,int reg,int data)676 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
677 {
678 struct sis_softc *sc;
679 struct sis_mii_frame frame;
680
681 sc = device_get_softc(dev);
682
683 if (sc->sis_type == SIS_TYPE_83815) {
684 if (phy != 0)
685 return(0);
686 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
687 return(0);
688 }
689
690 if (sc->sis_type == SIS_TYPE_900 &&
691 sc->sis_rev < SIS_REV_635) {
692 int i;
693
694 if (phy != 0)
695 return(0);
696
697 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
698 (reg << 6) | SIS_PHYOP_WRITE);
699 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
700
701 for (i = 0; i < SIS_TIMEOUT; i++) {
702 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
703 break;
704 }
705
706 if (i == SIS_TIMEOUT)
707 device_printf(dev, "PHY failed to come ready\n");
708 } else {
709 bzero((char *)&frame, sizeof(frame));
710
711 frame.mii_phyaddr = phy;
712 frame.mii_regaddr = reg;
713 frame.mii_data = data;
714 sis_mii_writereg(sc, &frame);
715 }
716 return(0);
717 }
718
719 static void
sis_miibus_statchg(device_t dev)720 sis_miibus_statchg(device_t dev)
721 {
722 struct sis_softc *sc;
723
724 sc = device_get_softc(dev);
725 sis_init(sc);
726 }
727
728 static uint32_t
sis_mchash(struct sis_softc * sc,const uint8_t * addr)729 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
730 {
731 uint32_t crc, carry;
732 int i, j;
733 uint8_t c;
734
735 /* Compute CRC for the address value. */
736 crc = 0xFFFFFFFF; /* initial value */
737
738 for (i = 0; i < 6; i++) {
739 c = *(addr + i);
740 for (j = 0; j < 8; j++) {
741 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
742 crc <<= 1;
743 c >>= 1;
744 if (carry)
745 crc = (crc ^ 0x04c11db6) | carry;
746 }
747 }
748
749 /*
750 * return the filter bit position
751 *
752 * The NatSemi chip has a 512-bit filter, which is
753 * different than the SiS, so we special-case it.
754 */
755 if (sc->sis_type == SIS_TYPE_83815)
756 return (crc >> 23);
757 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
758 return (crc >> 24);
759 else
760 return (crc >> 25);
761 }
762
763 static void
sis_setmulti_ns(struct sis_softc * sc)764 sis_setmulti_ns(struct sis_softc *sc)
765 {
766 struct ifnet *ifp;
767 struct ifmultiaddr *ifma;
768 uint32_t h = 0, i, filtsave;
769 int bit, index;
770
771 ifp = &sc->arpcom.ac_if;
772
773 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
774 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
775 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
776 return;
777 }
778
779 /*
780 * We have to explicitly enable the multicast hash table
781 * on the NatSemi chip if we want to use it, which we do.
782 */
783 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
784 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
785
786 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
787
788 /* first, zot all the existing hash bits */
789 for (i = 0; i < 32; i++) {
790 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
791 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
792 }
793
794 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
795 if (ifma->ifma_addr->sa_family != AF_LINK)
796 continue;
797 h = sis_mchash(sc,
798 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
799 index = h >> 3;
800 bit = h & 0x1F;
801 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
802 if (bit > 0xF)
803 bit -= 0x10;
804 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
805 }
806
807 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
808 }
809
810 static void
sis_setmulti_sis(struct sis_softc * sc)811 sis_setmulti_sis(struct sis_softc *sc)
812 {
813 struct ifnet *ifp;
814 struct ifmultiaddr *ifma;
815 uint32_t h, i, n, ctl;
816 uint16_t hashes[16];
817
818 ifp = &sc->arpcom.ac_if;
819
820 /* hash table size */
821 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
822 n = 16;
823 else
824 n = 8;
825
826 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
827
828 if (ifp->if_flags & IFF_BROADCAST)
829 ctl |= SIS_RXFILTCTL_BROAD;
830
831 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
832 ctl |= SIS_RXFILTCTL_ALLMULTI;
833 if (ifp->if_flags & IFF_PROMISC)
834 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
835 for (i = 0; i < n; i++)
836 hashes[i] = ~0;
837 } else {
838 for (i = 0; i < n; i++)
839 hashes[i] = 0;
840 i = 0;
841 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
842 if (ifma->ifma_addr->sa_family != AF_LINK)
843 continue;
844 h = sis_mchash(sc,
845 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
846 hashes[h >> 4] |= 1 << (h & 0xf);
847 i++;
848 }
849 if (i > n) {
850 ctl |= SIS_RXFILTCTL_ALLMULTI;
851 for (i = 0; i < n; i++)
852 hashes[i] = ~0;
853 }
854 }
855
856 for (i = 0; i < n; i++) {
857 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
858 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
859 }
860
861 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
862 }
863
864 static void
sis_reset(struct sis_softc * sc)865 sis_reset(struct sis_softc *sc)
866 {
867 struct ifnet *ifp = &sc->arpcom.ac_if;
868 int i;
869
870 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
871
872 for (i = 0; i < SIS_TIMEOUT; i++) {
873 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
874 break;
875 }
876
877 if (i == SIS_TIMEOUT)
878 if_printf(ifp, "reset never completed\n");
879
880 /* Wait a little while for the chip to get its brains in order. */
881 DELAY(1000);
882
883 /*
884 * If this is a NetSemi chip, make sure to clear
885 * PME mode.
886 */
887 if (sc->sis_type == SIS_TYPE_83815) {
888 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
889 CSR_WRITE_4(sc, NS_CLKRUN, 0);
890 }
891 }
892
893 /*
894 * Probe for an SiS chip. Check the PCI vendor and device
895 * IDs against our list and return a device name if we find a match.
896 */
897 static int
sis_probe(device_t dev)898 sis_probe(device_t dev)
899 {
900 struct sis_type *t;
901
902 t = sis_devs;
903
904 while(t->sis_name != NULL) {
905 if ((pci_get_vendor(dev) == t->sis_vid) &&
906 (pci_get_device(dev) == t->sis_did)) {
907 device_set_desc(dev, t->sis_name);
908 return(0);
909 }
910 t++;
911 }
912
913 return(ENXIO);
914 }
915
916 /*
917 * Attach the interface. Allocate softc structures, do ifmedia
918 * setup and ethernet/BPF attach.
919 */
920 static int
sis_attach(device_t dev)921 sis_attach(device_t dev)
922 {
923 uint8_t eaddr[ETHER_ADDR_LEN];
924 uint32_t command;
925 struct sis_softc *sc;
926 struct ifnet *ifp;
927 int error, rid, waittime;
928
929 error = waittime = 0;
930 sc = device_get_softc(dev);
931
932 if (pci_get_device(dev) == PCI_PRODUCT_SIS_900)
933 sc->sis_type = SIS_TYPE_900;
934 if (pci_get_device(dev) == PCI_PRODUCT_SIS_7016)
935 sc->sis_type = SIS_TYPE_7016;
936 if (pci_get_vendor(dev) == PCI_VENDOR_NS)
937 sc->sis_type = SIS_TYPE_83815;
938
939 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
940
941 /*
942 * Handle power management nonsense.
943 */
944
945 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF;
946 if (command == 0x01) {
947
948 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4);
949 if (command & SIS_PSTATE_MASK) {
950 uint32_t iobase, membase, irq;
951
952 /* Save important PCI config data. */
953 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4);
954 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4);
955 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4);
956
957 /* Reset the power state. */
958 device_printf(dev, "chip is in D%d power mode "
959 "-- setting to D0\n", command & SIS_PSTATE_MASK);
960 command &= 0xFFFFFFFC;
961 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4);
962
963 /* Restore PCI config data. */
964 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4);
965 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4);
966 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4);
967 }
968 }
969
970 /*
971 * Map control/status registers.
972 */
973 command = pci_read_config(dev, PCIR_COMMAND, 4);
974 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
975 pci_write_config(dev, PCIR_COMMAND, command, 4);
976 command = pci_read_config(dev, PCIR_COMMAND, 4);
977
978 #ifdef SIS_USEIOSPACE
979 if (!(command & PCIM_CMD_PORTEN)) {
980 device_printf(dev, "failed to enable I/O ports!\n");
981 error = ENXIO;
982 goto fail;
983 }
984 #else
985 if (!(command & PCIM_CMD_MEMEN)) {
986 device_printf(dev, "failed to enable memory mapping!\n");
987 error = ENXIO;
988 goto fail;
989 }
990 #endif
991
992 rid = SIS_RID;
993 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE);
994
995 if (sc->sis_res == NULL) {
996 device_printf(dev, "couldn't map ports/memory\n");
997 error = ENXIO;
998 goto fail;
999 }
1000
1001 sc->sis_btag = rman_get_bustag(sc->sis_res);
1002 sc->sis_bhandle = rman_get_bushandle(sc->sis_res);
1003
1004 /* Allocate interrupt */
1005 rid = 0;
1006 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1007 RF_SHAREABLE | RF_ACTIVE);
1008
1009 if (sc->sis_irq == NULL) {
1010 device_printf(dev, "couldn't map interrupt\n");
1011 error = ENXIO;
1012 goto fail;
1013 }
1014
1015 /* Reset the adapter. */
1016 sis_reset(sc);
1017
1018 if (sc->sis_type == SIS_TYPE_900 &&
1019 (sc->sis_rev == SIS_REV_635 ||
1020 sc->sis_rev == SIS_REV_900B)) {
1021 SIO_SET(SIS_CFG_RND_CNT);
1022 SIO_SET(SIS_CFG_PERR_DETECT);
1023 }
1024
1025 /*
1026 * Get station address from the EEPROM.
1027 */
1028 switch (pci_get_vendor(dev)) {
1029 case PCI_VENDOR_NS:
1030 /*
1031 * Reading the MAC address out of the EEPROM on
1032 * the NatSemi chip takes a bit more work than
1033 * you'd expect. The address spans 4 16-bit words,
1034 * with the first word containing only a single bit.
1035 * You have to shift everything over one bit to
1036 * get it aligned properly. Also, the bits are
1037 * stored backwards (the LSB is really the MSB,
1038 * and so on) so you have to reverse them in order
1039 * to get the MAC address into the form we want.
1040 * Why? Who the hell knows.
1041 */
1042 {
1043 uint16_t tmp[4];
1044
1045 sis_read_eeprom(sc, (caddr_t)&tmp,
1046 NS_EE_NODEADDR, 4, 0);
1047
1048 /* Shift everything over one bit. */
1049 tmp[3] = tmp[3] >> 1;
1050 tmp[3] |= tmp[2] << 15;
1051 tmp[2] = tmp[2] >> 1;
1052 tmp[2] |= tmp[1] << 15;
1053 tmp[1] = tmp[1] >> 1;
1054 tmp[1] |= tmp[0] << 15;
1055
1056 /* Now reverse all the bits. */
1057 tmp[3] = sis_reverse(tmp[3]);
1058 tmp[2] = sis_reverse(tmp[2]);
1059 tmp[1] = sis_reverse(tmp[1]);
1060
1061 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
1062 }
1063 break;
1064 case PCI_VENDOR_SIS:
1065 default:
1066 #ifdef __x86_64__
1067 /*
1068 * If this is a SiS 630E chipset with an embedded
1069 * SiS 900 controller, we have to read the MAC address
1070 * from the APC CMOS RAM. Our method for doing this
1071 * is very ugly since we have to reach out and grab
1072 * ahold of hardware for which we cannot properly
1073 * allocate resources. This code is only compiled on
1074 * the x86_64 architecture since the SiS 630E chipset
1075 * is for x86 motherboards only. Note that there are
1076 * a lot of magic numbers in this hack. These are
1077 * taken from SiS's Linux driver. I'd like to replace
1078 * them with proper symbolic definitions, but that
1079 * requires some datasheets that I don't have access
1080 * to at the moment.
1081 */
1082 if (sc->sis_rev == SIS_REV_630S ||
1083 sc->sis_rev == SIS_REV_630E ||
1084 sc->sis_rev == SIS_REV_630EA1)
1085 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1086
1087 else if (sc->sis_rev == SIS_REV_635 ||
1088 sc->sis_rev == SIS_REV_630ET)
1089 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1090 else if (sc->sis_rev == SIS_REV_96x) {
1091 /*
1092 * Allow to read EEPROM from LAN. It is shared
1093 * between a 1394 controller and the NIC and each
1094 * time we access it, we need to set SIS_EECMD_REQ.
1095 */
1096 SIO_SET(SIS_EECMD_REQ);
1097 for (waittime = 0; waittime < SIS_TIMEOUT;
1098 waittime++) {
1099 /* Force EEPROM to idle state. */
1100 sis_eeprom_idle(sc);
1101 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1102 sis_read_eeprom(sc, (caddr_t)&eaddr,
1103 SIS_EE_NODEADDR, 3, 0);
1104 break;
1105 }
1106 DELAY(1);
1107 }
1108 /*
1109 * Set SIS_EECTL_CLK to high, so a other master
1110 * can operate on the i2c bus.
1111 */
1112 SIO_SET(SIS_EECTL_CLK);
1113 /* Refuse EEPROM access by LAN */
1114 SIO_SET(SIS_EECMD_DONE);
1115 } else
1116 #endif
1117 sis_read_eeprom(sc, (caddr_t)&eaddr,
1118 SIS_EE_NODEADDR, 3, 0);
1119 break;
1120 }
1121
1122 callout_init(&sc->sis_timer);
1123
1124 error = sis_dma_alloc(dev);
1125 if (error)
1126 goto fail;
1127
1128 ifp = &sc->arpcom.ac_if;
1129 ifp->if_softc = sc;
1130 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1131 ifp->if_mtu = ETHERMTU;
1132 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1133 ifp->if_ioctl = sis_ioctl;
1134 ifp->if_start = sis_start;
1135 ifp->if_watchdog = sis_watchdog;
1136 ifp->if_init = sis_init;
1137 ifp->if_baudrate = 10000000;
1138 ifq_set_maxlen(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1139 ifq_set_ready(&ifp->if_snd);
1140 #ifdef IFPOLL_ENABLE
1141 ifp->if_npoll = sis_npoll;
1142 #endif
1143 ifp->if_capenable = ifp->if_capabilities;
1144
1145 /*
1146 * Do MII setup.
1147 */
1148 if (mii_phy_probe(dev, &sc->sis_miibus,
1149 sis_ifmedia_upd, sis_ifmedia_sts)) {
1150 device_printf(dev, "MII without any PHY!\n");
1151 error = ENXIO;
1152 goto fail;
1153 }
1154
1155 /*
1156 * Call MI attach routine.
1157 */
1158 ether_ifattach(ifp, eaddr, NULL);
1159
1160 #ifdef IFPOLL_ENABLE
1161 ifpoll_compat_setup(&sc->sis_npoll, NULL, NULL, device_get_unit(dev),
1162 ifp->if_serializer);
1163 #endif
1164
1165 /*
1166 * Tell the upper layer(s) we support long frames.
1167 */
1168 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1169
1170 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sis_irq));
1171
1172 error = bus_setup_intr(dev, sc->sis_irq, INTR_MPSAFE,
1173 sis_intr, sc,
1174 &sc->sis_intrhand,
1175 ifp->if_serializer);
1176
1177 if (error) {
1178 device_printf(dev, "couldn't set up irq\n");
1179 ether_ifdetach(ifp);
1180 goto fail;
1181 }
1182
1183 fail:
1184 if (error)
1185 sis_detach(dev);
1186
1187 return(error);
1188 }
1189
1190 /*
1191 * Shutdown hardware and free up resources. It is called in both the error case
1192 * and the normal detach case so it needs to be careful about only freeing
1193 * resources that have actually been allocated.
1194 */
1195 static int
sis_detach(device_t dev)1196 sis_detach(device_t dev)
1197 {
1198 struct sis_softc *sc = device_get_softc(dev);
1199 struct ifnet *ifp = &sc->arpcom.ac_if;
1200
1201
1202 if (device_is_attached(dev)) {
1203 lwkt_serialize_enter(ifp->if_serializer);
1204 sis_reset(sc);
1205 sis_stop(sc);
1206 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1207 lwkt_serialize_exit(ifp->if_serializer);
1208
1209 ether_ifdetach(ifp);
1210 }
1211 if (sc->sis_miibus)
1212 device_delete_child(dev, sc->sis_miibus);
1213 bus_generic_detach(dev);
1214
1215 if (sc->sis_irq)
1216 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1217 if (sc->sis_res)
1218 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1219
1220 sis_dma_free(dev);
1221
1222 return(0);
1223 }
1224
1225 /*
1226 * Initialize the transmit descriptors.
1227 */
1228 static int
sis_list_tx_init(struct sis_softc * sc)1229 sis_list_tx_init(struct sis_softc *sc)
1230 {
1231 struct sis_list_data *ld = &sc->sis_ldata;
1232 struct sis_chain_data *cd = &sc->sis_cdata;
1233 int i, nexti;
1234
1235 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1236 bus_addr_t paddr;
1237
1238 /*
1239 * Link the TX desc together
1240 */
1241 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1;
1242 paddr = ld->sis_tx_paddr + (nexti * sizeof(struct sis_desc));
1243 ld->sis_tx_list[i].sis_next = paddr;
1244 }
1245 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0;
1246
1247 return 0;
1248 }
1249
1250 /*
1251 * Initialize the RX descriptors and allocate mbufs for them. Note that
1252 * we arrange the descriptors in a closed ring, so that the last descriptor
1253 * points back to the first.
1254 */
1255 static int
sis_list_rx_init(struct sis_softc * sc)1256 sis_list_rx_init(struct sis_softc *sc)
1257 {
1258 struct sis_list_data *ld = &sc->sis_ldata;
1259 struct sis_chain_data *cd = &sc->sis_cdata;
1260 int i, error;
1261
1262 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1263 bus_addr_t paddr;
1264 int nexti;
1265
1266 error = sis_newbuf(sc, i, 1);
1267 if (error)
1268 return error;
1269
1270 /*
1271 * Link the RX desc together
1272 */
1273 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1;
1274 paddr = ld->sis_rx_paddr + (nexti * sizeof(struct sis_desc));
1275 ld->sis_rx_list[i].sis_next = paddr;
1276 }
1277 cd->sis_rx_prod = 0;
1278
1279 return 0;
1280 }
1281
1282 /*
1283 * Initialize an RX descriptor and attach an MBUF cluster.
1284 */
1285 static int
sis_newbuf(struct sis_softc * sc,int idx,int init)1286 sis_newbuf(struct sis_softc *sc, int idx, int init)
1287 {
1288 struct sis_chain_data *cd = &sc->sis_cdata;
1289 struct sis_rx_data *rd = &cd->sis_rx_data[idx];
1290 bus_dma_segment_t seg;
1291 bus_dmamap_t map;
1292 struct mbuf *m;
1293 int nseg, error;
1294
1295 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR);
1296 if (m == NULL) {
1297 if (init)
1298 if_printf(&sc->arpcom.ac_if, "can't alloc RX mbuf\n");
1299 return ENOBUFS;
1300 }
1301 m->m_len = m->m_pkthdr.len = MCLBYTES;
1302
1303 /* Try loading the mbuf into tmp DMA map */
1304 error = bus_dmamap_load_mbuf_segment(cd->sis_rxbuf_tag,
1305 cd->sis_rx_tmpmap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
1306 if (error) {
1307 m_freem(m);
1308 if (init)
1309 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
1310 return error;
1311 }
1312
1313 /* Unload the currently loaded mbuf */
1314 if (rd->sis_mbuf != NULL) {
1315 bus_dmamap_sync(cd->sis_rxbuf_tag, rd->sis_map,
1316 BUS_DMASYNC_POSTREAD);
1317 bus_dmamap_unload(cd->sis_rxbuf_tag, rd->sis_map);
1318 }
1319
1320 /* Swap DMA maps */
1321 map = cd->sis_rx_tmpmap;
1322 cd->sis_rx_tmpmap = rd->sis_map;
1323 rd->sis_map = map;
1324
1325 /* Save necessary information */
1326 rd->sis_mbuf = m;
1327 rd->sis_paddr = seg.ds_addr;
1328
1329 sis_setup_rxdesc(sc, idx);
1330 return 0;
1331 }
1332
1333 static void
sis_setup_rxdesc(struct sis_softc * sc,int idx)1334 sis_setup_rxdesc(struct sis_softc *sc, int idx)
1335 {
1336 struct sis_desc *c = &sc->sis_ldata.sis_rx_list[idx];
1337
1338 /* Setup the RX desc */
1339 c->sis_ctl = SIS_RXLEN;
1340 c->sis_ptr = sc->sis_cdata.sis_rx_data[idx].sis_paddr;
1341 }
1342
1343 /*
1344 * A frame has been uploaded: pass the resulting mbuf chain up to
1345 * the higher level protocols.
1346 */
1347 static void
sis_rxeof(struct sis_softc * sc)1348 sis_rxeof(struct sis_softc *sc)
1349 {
1350 struct ifnet *ifp = &sc->arpcom.ac_if;
1351 int i, total_len = 0;
1352 uint32_t rxstat;
1353
1354 i = sc->sis_cdata.sis_rx_prod;
1355 while (SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) {
1356 struct sis_desc *cur_rx;
1357 struct sis_rx_data *rd;
1358 struct mbuf *m;
1359 int idx = i;
1360
1361 #ifdef IFPOLL_ENABLE
1362 if (ifp->if_flags & IFF_NPOLLING) {
1363 if (sc->rxcycles <= 0)
1364 break;
1365 sc->rxcycles--;
1366 }
1367 #endif /* IFPOLL_ENABLE */
1368
1369 cur_rx = &sc->sis_ldata.sis_rx_list[idx];
1370 rd = &sc->sis_cdata.sis_rx_data[idx];
1371
1372 rxstat = cur_rx->sis_rxstat;
1373 total_len = SIS_RXBYTES(cur_rx);
1374
1375 m = rd->sis_mbuf;
1376
1377 SIS_INC(i, SIS_RX_LIST_CNT);
1378
1379 /*
1380 * If an error occurs, update stats, clear the
1381 * status word and leave the mbuf cluster in place:
1382 * it should simply get re-used next time this descriptor
1383 * comes up in the ring.
1384 */
1385 if (!(rxstat & SIS_CMDSTS_PKT_OK)) {
1386 IFNET_STAT_INC(ifp, ierrors, 1);
1387 if (rxstat & SIS_RXSTAT_COLL)
1388 IFNET_STAT_INC(ifp, collisions, 1);
1389 sis_setup_rxdesc(sc, idx);
1390 continue;
1391 }
1392
1393 /* No errors; receive the packet. */
1394 if (sis_newbuf(sc, idx, 0) == 0) {
1395 m->m_pkthdr.len = m->m_len = total_len;
1396 m->m_pkthdr.rcvif = ifp;
1397 } else {
1398 IFNET_STAT_INC(ifp, ierrors, 1);
1399 sis_setup_rxdesc(sc, idx);
1400 continue;
1401 }
1402
1403 IFNET_STAT_INC(ifp, ipackets, 1);
1404 ifp->if_input(ifp, m, NULL, -1);
1405 }
1406 sc->sis_cdata.sis_rx_prod = i;
1407 }
1408
1409 static void
sis_rxeoc(struct sis_softc * sc)1410 sis_rxeoc(struct sis_softc *sc)
1411 {
1412 sis_rxeof(sc);
1413 sis_init(sc);
1414 }
1415
1416 /*
1417 * A frame was downloaded to the chip. It's safe for us to clean up
1418 * the list buffers.
1419 */
1420
1421 static void
sis_txeof(struct sis_softc * sc)1422 sis_txeof(struct sis_softc *sc)
1423 {
1424 struct ifnet *ifp = &sc->arpcom.ac_if;
1425 struct sis_chain_data *cd = &sc->sis_cdata;
1426 uint32_t idx;
1427
1428 /*
1429 * Go through our tx list and free mbufs for those
1430 * frames that have been transmitted.
1431 */
1432 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0;
1433 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) {
1434 struct sis_desc *cur_tx;
1435 struct sis_tx_data *td;
1436
1437 cur_tx = &sc->sis_ldata.sis_tx_list[idx];
1438 td = &cd->sis_tx_data[idx];
1439
1440 if (SIS_OWNDESC(cur_tx))
1441 break;
1442
1443 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE)
1444 continue;
1445
1446 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
1447 IFNET_STAT_INC(ifp, oerrors, 1);
1448 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
1449 IFNET_STAT_INC(ifp, collisions, 1);
1450 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
1451 IFNET_STAT_INC(ifp, collisions, 1);
1452 }
1453
1454 IFNET_STAT_INC(ifp, collisions,
1455 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16);
1456
1457 IFNET_STAT_INC(ifp, opackets, 1);
1458 if (td->sis_mbuf != NULL) {
1459 bus_dmamap_unload(cd->sis_txbuf_tag, td->sis_map);
1460 m_freem(td->sis_mbuf);
1461 td->sis_mbuf = NULL;
1462 }
1463 }
1464
1465 if (idx != sc->sis_cdata.sis_tx_cons) {
1466 /* we freed up some buffers */
1467 sc->sis_cdata.sis_tx_cons = idx;
1468 }
1469
1470 if (cd->sis_tx_cnt == 0)
1471 ifp->if_timer = 0;
1472 if (!SIS_IS_OACTIVE(sc))
1473 ifq_clr_oactive(&ifp->if_snd);
1474 }
1475
1476 static void
sis_tick(void * xsc)1477 sis_tick(void *xsc)
1478 {
1479 struct sis_softc *sc = xsc;
1480 struct mii_data *mii;
1481 struct ifnet *ifp = &sc->arpcom.ac_if;
1482
1483 lwkt_serialize_enter(ifp->if_serializer);
1484
1485 mii = device_get_softc(sc->sis_miibus);
1486 mii_tick(mii);
1487
1488 if (!sc->sis_link) {
1489 mii_pollstat(mii);
1490 if (mii->mii_media_status & IFM_ACTIVE &&
1491 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1492 sc->sis_link++;
1493 if (!ifq_is_empty(&ifp->if_snd))
1494 if_devstart(ifp);
1495 }
1496
1497 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
1498 lwkt_serialize_exit(ifp->if_serializer);
1499 }
1500
1501 #ifdef IFPOLL_ENABLE
1502
1503 static void
sis_npoll_compat(struct ifnet * ifp,void * arg __unused,int count)1504 sis_npoll_compat(struct ifnet *ifp, void *arg __unused, int count)
1505 {
1506 struct sis_softc *sc = ifp->if_softc;
1507
1508 ASSERT_SERIALIZED(ifp->if_serializer);
1509
1510 /*
1511 * On the sis, reading the status register also clears it.
1512 * So before returning to intr mode we must make sure that all
1513 * possible pending sources of interrupts have been served.
1514 * In practice this means run to completion the *eof routines,
1515 * and then call the interrupt routine
1516 */
1517 sc->rxcycles = count;
1518 sis_rxeof(sc);
1519 sis_txeof(sc);
1520 if (!ifq_is_empty(&ifp->if_snd))
1521 if_devstart(ifp);
1522
1523 if (sc->sis_npoll.ifpc_stcount-- == 0) {
1524 uint32_t status;
1525
1526 sc->sis_npoll.ifpc_stcount = sc->sis_npoll.ifpc_stfrac;
1527
1528 /* Reading the ISR register clears all interrupts. */
1529 status = CSR_READ_4(sc, SIS_ISR);
1530
1531 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1532 sis_rxeoc(sc);
1533
1534 if (status & (SIS_ISR_RX_IDLE))
1535 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1536
1537 if (status & SIS_ISR_SYSERR) {
1538 sis_reset(sc);
1539 sis_init(sc);
1540 }
1541 }
1542 }
1543
1544 static void
sis_npoll(struct ifnet * ifp,struct ifpoll_info * info)1545 sis_npoll(struct ifnet *ifp, struct ifpoll_info *info)
1546 {
1547 struct sis_softc *sc = ifp->if_softc;
1548
1549 ASSERT_SERIALIZED(ifp->if_serializer);
1550
1551 if (info != NULL) {
1552 int cpuid = sc->sis_npoll.ifpc_cpuid;
1553
1554 info->ifpi_rx[cpuid].poll_func = sis_npoll_compat;
1555 info->ifpi_rx[cpuid].arg = NULL;
1556 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
1557
1558 if (ifp->if_flags & IFF_RUNNING) {
1559 /* disable interrupts */
1560 CSR_WRITE_4(sc, SIS_IER, 0);
1561 sc->sis_npoll.ifpc_stcount = 0;
1562 }
1563 ifq_set_cpuid(&ifp->if_snd, cpuid);
1564 } else {
1565 if (ifp->if_flags & IFF_RUNNING) {
1566 /* enable interrupts */
1567 CSR_WRITE_4(sc, SIS_IER, 1);
1568 }
1569 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sis_irq));
1570 }
1571 }
1572
1573 #endif /* IFPOLL_ENABLE */
1574
1575 static void
sis_intr(void * arg)1576 sis_intr(void *arg)
1577 {
1578 struct sis_softc *sc;
1579 struct ifnet *ifp;
1580 uint32_t status;
1581
1582 sc = arg;
1583 ifp = &sc->arpcom.ac_if;
1584
1585 /* Supress unwanted interrupts */
1586 if (!(ifp->if_flags & IFF_UP)) {
1587 sis_stop(sc);
1588 return;
1589 }
1590
1591 /* Disable interrupts. */
1592 CSR_WRITE_4(sc, SIS_IER, 0);
1593
1594 for (;;) {
1595 /* Reading the ISR register clears all interrupts. */
1596 status = CSR_READ_4(sc, SIS_ISR);
1597
1598 if ((status & SIS_INTRS) == 0)
1599 break;
1600
1601 if (status &
1602 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK |
1603 SIS_ISR_TX_IDLE) )
1604 sis_txeof(sc);
1605
1606 if (status &
1607 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE))
1608 sis_rxeof(sc);
1609
1610 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW))
1611 sis_rxeoc(sc);
1612
1613 if (status & (SIS_ISR_RX_IDLE))
1614 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1615
1616 if (status & SIS_ISR_SYSERR) {
1617 sis_reset(sc);
1618 sis_init(sc);
1619 }
1620 }
1621
1622 /* Re-enable interrupts. */
1623 CSR_WRITE_4(sc, SIS_IER, 1);
1624
1625 if (!ifq_is_empty(&ifp->if_snd))
1626 if_devstart(ifp);
1627 }
1628
1629 /*
1630 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1631 * pointers to the fragment pointers.
1632 */
1633 static int
sis_encap(struct sis_softc * sc,struct mbuf ** m_head,uint32_t * txidx)1634 sis_encap(struct sis_softc *sc, struct mbuf **m_head, uint32_t *txidx)
1635 {
1636 struct sis_chain_data *cd = &sc->sis_cdata;
1637 struct sis_list_data *ld = &sc->sis_ldata;
1638 bus_dma_segment_t segs[SIS_NSEGS];
1639 bus_dmamap_t map;
1640 int frag, cur, maxsegs, nsegs, error, i;
1641
1642 maxsegs = SIS_TX_LIST_CNT - SIS_NSEGS_RESERVED - cd->sis_tx_cnt;
1643 KASSERT(maxsegs >= 1, ("not enough TX descs"));
1644 if (maxsegs > SIS_NSEGS)
1645 maxsegs = SIS_NSEGS;
1646
1647 map = cd->sis_tx_data[*txidx].sis_map;
1648 error = bus_dmamap_load_mbuf_defrag(cd->sis_txbuf_tag, map, m_head,
1649 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1650 if (error) {
1651 m_freem(*m_head);
1652 *m_head = NULL;
1653 return error;
1654 }
1655 bus_dmamap_sync(cd->sis_txbuf_tag, map, BUS_DMASYNC_PREWRITE);
1656
1657 cur = frag = *txidx;
1658 for (i = 0; i < nsegs; ++i) {
1659 struct sis_desc *f = &ld->sis_tx_list[frag];
1660
1661 f->sis_ctl = SIS_CMDSTS_MORE | segs[i].ds_len;
1662 f->sis_ptr = segs[i].ds_addr;
1663 if (i != 0)
1664 f->sis_ctl |= SIS_CMDSTS_OWN;
1665
1666 cur = frag;
1667 SIS_INC(frag, SIS_TX_LIST_CNT);
1668 }
1669 ld->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
1670 ld->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
1671
1672 /* Swap DMA map */
1673 cd->sis_tx_data[*txidx].sis_map = cd->sis_tx_data[cur].sis_map;
1674 cd->sis_tx_data[cur].sis_map = map;
1675
1676 cd->sis_tx_data[cur].sis_mbuf = *m_head;
1677
1678 cd->sis_tx_cnt += nsegs;
1679 *txidx = frag;
1680
1681 return 0;
1682 }
1683
1684 /*
1685 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1686 * to the mbuf data regions directly in the transmit lists. We also save a
1687 * copy of the pointers since the transmit list fragment pointers are
1688 * physical addresses.
1689 */
1690
1691 static void
sis_start(struct ifnet * ifp,struct ifaltq_subque * ifsq)1692 sis_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1693 {
1694 struct sis_softc *sc = ifp->if_softc;
1695 int need_trans, error;
1696 uint32_t idx;
1697
1698 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1699
1700 if (!sc->sis_link) {
1701 ifq_purge(&ifp->if_snd);
1702 return;
1703 }
1704
1705 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1706 return;
1707
1708 idx = sc->sis_cdata.sis_tx_prod;
1709 need_trans = 0;
1710
1711 while (sc->sis_cdata.sis_tx_data[idx].sis_mbuf == NULL) {
1712 struct mbuf *m_head;
1713
1714 /*
1715 * If there's no way we can send any packets, return now.
1716 */
1717 if (SIS_IS_OACTIVE(sc)) {
1718 ifq_set_oactive(&ifp->if_snd);
1719 break;
1720 }
1721
1722 m_head = ifq_dequeue(&ifp->if_snd);
1723 if (m_head == NULL)
1724 break;
1725
1726 error = sis_encap(sc, &m_head, &idx);
1727 if (error) {
1728 IFNET_STAT_INC(ifp, oerrors, 1);
1729 if (sc->sis_cdata.sis_tx_cnt == 0) {
1730 continue;
1731 } else {
1732 ifq_set_oactive(&ifp->if_snd);
1733 break;
1734 }
1735 }
1736 need_trans = 1;
1737
1738 /*
1739 * If there's a BPF listener, bounce a copy of this frame
1740 * to him.
1741 */
1742 BPF_MTAP(ifp, m_head);
1743 }
1744
1745 if (!need_trans)
1746 return;
1747
1748 /* Transmit */
1749 sc->sis_cdata.sis_tx_prod = idx;
1750 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1751
1752 /*
1753 * Set a timeout in case the chip goes out to lunch.
1754 */
1755 ifp->if_timer = 5;
1756 }
1757
1758 static void
sis_init(void * xsc)1759 sis_init(void *xsc)
1760 {
1761 struct sis_softc *sc = xsc;
1762 struct ifnet *ifp = &sc->arpcom.ac_if;
1763 struct mii_data *mii;
1764
1765 /*
1766 * Cancel pending I/O and free all RX/TX buffers.
1767 */
1768 sis_stop(sc);
1769
1770 mii = device_get_softc(sc->sis_miibus);
1771
1772 /* Set MAC address */
1773 if (sc->sis_type == SIS_TYPE_83815) {
1774 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1775 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1776 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1777 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1778 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1779 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1780 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1781 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1782 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1783 } else {
1784 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1785 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1786 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1787 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1788 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1789 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1790 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1791 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1792 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1793 }
1794
1795 /* Init circular RX list. */
1796 if (sis_list_rx_init(sc)) {
1797 if_printf(ifp, "initialization failed: "
1798 "no memory for rx buffers\n");
1799 sis_stop(sc);
1800 return;
1801 }
1802
1803 /*
1804 * Init tx descriptors.
1805 */
1806 sis_list_tx_init(sc);
1807
1808 /*
1809 * For the NatSemi chip, we have to explicitly enable the
1810 * reception of ARP frames, as well as turn on the 'perfect
1811 * match' filter where we store the station address, otherwise
1812 * we won't receive unicasts meant for this host.
1813 */
1814 if (sc->sis_type == SIS_TYPE_83815) {
1815 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
1816 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
1817 }
1818
1819 /* If we want promiscuous mode, set the allframes bit. */
1820 if (ifp->if_flags & IFF_PROMISC)
1821 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1822 else
1823 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1824
1825 /*
1826 * Set the capture broadcast bit to capture broadcast frames.
1827 */
1828 if (ifp->if_flags & IFF_BROADCAST)
1829 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1830 else
1831 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1832
1833 /*
1834 * Load the multicast filter.
1835 */
1836 if (sc->sis_type == SIS_TYPE_83815)
1837 sis_setmulti_ns(sc);
1838 else
1839 sis_setmulti_sis(sc);
1840
1841 /* Turn the receive filter on */
1842 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
1843
1844 /*
1845 * Load the address of the RX and TX lists.
1846 */
1847 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_ldata.sis_rx_paddr);
1848 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_ldata.sis_tx_paddr);
1849
1850 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
1851 * the PCI bus. When this bit is set, the Max DMA Burst Size
1852 * for TX/RX DMA should be no larger than 16 double words.
1853 */
1854 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN)
1855 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
1856 else
1857 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
1858
1859 /* Accept Long Packets for VLAN support */
1860 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
1861
1862 /* Set TX configuration */
1863 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)
1864 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
1865 else
1866 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
1867
1868 /* Set full/half duplex mode. */
1869 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1870 SIS_SETBIT(sc, SIS_TX_CFG,
1871 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1872 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1873 } else {
1874 SIS_CLRBIT(sc, SIS_TX_CFG,
1875 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1876 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1877 }
1878
1879 /*
1880 * Enable interrupts.
1881 */
1882 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
1883 #ifdef IFPOLL_ENABLE
1884 /*
1885 * ... only enable interrupts if we are not polling, make sure
1886 * they are off otherwise.
1887 */
1888 if (ifp->if_flags & IFF_NPOLLING) {
1889 CSR_WRITE_4(sc, SIS_IER, 0);
1890 sc->sis_npoll.ifpc_stcount = 0;
1891 } else
1892 #endif /* IFPOLL_ENABLE */
1893 CSR_WRITE_4(sc, SIS_IER, 1);
1894
1895 /* Enable receiver and transmitter. */
1896 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
1897 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1898
1899 #ifdef notdef
1900 mii_mediachg(mii);
1901 #endif
1902
1903 /*
1904 * Page 75 of the DP83815 manual recommends the
1905 * following register settings "for optimum
1906 * performance." Note however that at least three
1907 * of the registers are listed as "reserved" in
1908 * the register map, so who knows what they do.
1909 */
1910 if (sc->sis_type == SIS_TYPE_83815) {
1911 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
1912 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
1913 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
1914 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
1915 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
1916 }
1917
1918 ifp->if_flags |= IFF_RUNNING;
1919 ifq_clr_oactive(&ifp->if_snd);
1920
1921 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
1922 }
1923
1924 /*
1925 * Set media options.
1926 */
1927 static int
sis_ifmedia_upd(struct ifnet * ifp)1928 sis_ifmedia_upd(struct ifnet *ifp)
1929 {
1930 struct sis_softc *sc;
1931 struct mii_data *mii;
1932
1933 sc = ifp->if_softc;
1934
1935 mii = device_get_softc(sc->sis_miibus);
1936 sc->sis_link = 0;
1937 if (mii->mii_instance) {
1938 struct mii_softc *miisc;
1939 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1940 mii_phy_reset(miisc);
1941 }
1942 mii_mediachg(mii);
1943
1944 return(0);
1945 }
1946
1947 /*
1948 * Report current media status.
1949 */
1950 static void
sis_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)1951 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1952 {
1953 struct sis_softc *sc;
1954 struct mii_data *mii;
1955
1956 sc = ifp->if_softc;
1957
1958 mii = device_get_softc(sc->sis_miibus);
1959 mii_pollstat(mii);
1960 ifmr->ifm_active = mii->mii_media_active;
1961 ifmr->ifm_status = mii->mii_media_status;
1962 }
1963
1964 static int
sis_ioctl(struct ifnet * ifp,u_long command,caddr_t data,struct ucred * cr)1965 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1966 {
1967 struct sis_softc *sc = ifp->if_softc;
1968 struct ifreq *ifr = (struct ifreq *) data;
1969 struct mii_data *mii;
1970 int error = 0;
1971
1972 switch(command) {
1973 case SIOCSIFFLAGS:
1974 if (ifp->if_flags & IFF_UP) {
1975 sis_init(sc);
1976 } else {
1977 if (ifp->if_flags & IFF_RUNNING)
1978 sis_stop(sc);
1979 }
1980 error = 0;
1981 break;
1982 case SIOCADDMULTI:
1983 case SIOCDELMULTI:
1984 if (sc->sis_type == SIS_TYPE_83815)
1985 sis_setmulti_ns(sc);
1986 else
1987 sis_setmulti_sis(sc);
1988 error = 0;
1989 break;
1990 case SIOCGIFMEDIA:
1991 case SIOCSIFMEDIA:
1992 mii = device_get_softc(sc->sis_miibus);
1993 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1994 break;
1995 default:
1996 error = ether_ioctl(ifp, command, data);
1997 break;
1998 }
1999 return(error);
2000 }
2001
2002 static void
sis_watchdog(struct ifnet * ifp)2003 sis_watchdog(struct ifnet *ifp)
2004 {
2005 struct sis_softc *sc;
2006
2007 sc = ifp->if_softc;
2008
2009 IFNET_STAT_INC(ifp, oerrors, 1);
2010 if_printf(ifp, "watchdog timeout\n");
2011
2012 sis_stop(sc);
2013 sis_reset(sc);
2014 sis_init(sc);
2015
2016 if (!ifq_is_empty(&ifp->if_snd))
2017 if_devstart(ifp);
2018 }
2019
2020 /*
2021 * Stop the adapter and free any mbufs allocated to the
2022 * RX and TX lists.
2023 */
2024 static void
sis_stop(struct sis_softc * sc)2025 sis_stop(struct sis_softc *sc)
2026 {
2027 struct ifnet *ifp = &sc->arpcom.ac_if;
2028 struct sis_list_data *ld = &sc->sis_ldata;
2029 struct sis_chain_data *cd = &sc->sis_cdata;
2030 int i;
2031
2032 callout_stop(&sc->sis_timer);
2033
2034 ifp->if_flags &= ~IFF_RUNNING;
2035 ifq_clr_oactive(&ifp->if_snd);
2036 ifp->if_timer = 0;
2037
2038 CSR_WRITE_4(sc, SIS_IER, 0);
2039 CSR_WRITE_4(sc, SIS_IMR, 0);
2040 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2041 DELAY(1000);
2042 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2043 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2044
2045 sc->sis_link = 0;
2046
2047 /*
2048 * Free data in the RX lists.
2049 */
2050 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2051 struct sis_rx_data *rd = &cd->sis_rx_data[i];
2052
2053 if (rd->sis_mbuf != NULL) {
2054 bus_dmamap_unload(cd->sis_rxbuf_tag, rd->sis_map);
2055 m_freem(rd->sis_mbuf);
2056 rd->sis_mbuf = NULL;
2057 }
2058 }
2059 bzero(ld->sis_rx_list, SIS_RX_LIST_SZ);
2060
2061 /*
2062 * Free the TX list buffers.
2063 */
2064 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2065 struct sis_tx_data *td = &cd->sis_tx_data[i];
2066
2067 if (td->sis_mbuf != NULL) {
2068 bus_dmamap_unload(cd->sis_txbuf_tag, td->sis_map);
2069 m_freem(td->sis_mbuf);
2070 td->sis_mbuf = NULL;
2071 }
2072 }
2073 bzero(ld->sis_tx_list, SIS_TX_LIST_SZ);
2074 }
2075
2076 /*
2077 * Stop all chip I/O so that the kernel's probe routines don't
2078 * get confused by errant DMAs when rebooting.
2079 */
2080 static void
sis_shutdown(device_t dev)2081 sis_shutdown(device_t dev)
2082 {
2083 struct sis_softc *sc;
2084 struct ifnet *ifp;
2085
2086 sc = device_get_softc(dev);
2087 ifp = &sc->arpcom.ac_if;
2088 lwkt_serialize_enter(ifp->if_serializer);
2089 sis_reset(sc);
2090 sis_stop(sc);
2091 lwkt_serialize_exit(ifp->if_serializer);
2092 }
2093
2094 static int
sis_dma_alloc(device_t dev)2095 sis_dma_alloc(device_t dev)
2096 {
2097 struct sis_softc *sc = device_get_softc(dev);
2098 struct sis_chain_data *cd = &sc->sis_cdata;
2099 struct sis_list_data *ld = &sc->sis_ldata;
2100 int i, error;
2101
2102 /* Create top level DMA tag */
2103 error = bus_dma_tag_create(NULL, /* parent */
2104 1, 0, /* alignment, boundary */
2105 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
2106 BUS_SPACE_MAXADDR, /* highaddr */
2107 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
2108 0, /* nsegments */
2109 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
2110 0, /* flags */
2111 &sc->sis_parent_tag);
2112 if (error) {
2113 device_printf(dev, "could not create parent DMA tag\n");
2114 return error;
2115 }
2116
2117 /* Allocate RX ring */
2118 ld->sis_rx_list = bus_dmamem_coherent_any(sc->sis_parent_tag,
2119 SIS_RING_ALIGN, SIS_RX_LIST_SZ,
2120 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2121 &ld->sis_rx_tag, &ld->sis_rx_dmamap,
2122 &ld->sis_rx_paddr);
2123 if (ld->sis_rx_list == NULL) {
2124 device_printf(dev, "could not allocate RX ring\n");
2125 return ENOMEM;
2126 }
2127
2128 /* Allocate TX ring */
2129 ld->sis_tx_list = bus_dmamem_coherent_any(sc->sis_parent_tag,
2130 SIS_RING_ALIGN, SIS_TX_LIST_SZ,
2131 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2132 &ld->sis_tx_tag, &ld->sis_tx_dmamap,
2133 &ld->sis_tx_paddr);
2134 if (ld->sis_tx_list == NULL) {
2135 device_printf(dev, "could not allocate TX ring\n");
2136 return ENOMEM;
2137 }
2138
2139 /* Create DMA tag for TX mbuf */
2140 error = bus_dma_tag_create(sc->sis_parent_tag,/* parent */
2141 1, 0, /* alignment, boundary */
2142 BUS_SPACE_MAXADDR, /* lowaddr */
2143 BUS_SPACE_MAXADDR, /* highaddr */
2144 MCLBYTES, /* maxsize */
2145 SIS_NSEGS, /* nsegments */
2146 MCLBYTES, /* maxsegsize */
2147 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,/* flags */
2148 &cd->sis_txbuf_tag);
2149 if (error) {
2150 device_printf(dev, "could not create TX buf DMA tag\n");
2151 return error;
2152 }
2153
2154 /* Create DMA maps for TX mbufs */
2155 for (i = 0; i < SIS_TX_LIST_CNT; ++i) {
2156 error = bus_dmamap_create(cd->sis_txbuf_tag, BUS_DMA_WAITOK,
2157 &cd->sis_tx_data[i].sis_map);
2158 if (error) {
2159 int j;
2160
2161 for (j = 0; j < i; ++j) {
2162 bus_dmamap_destroy(cd->sis_txbuf_tag,
2163 cd->sis_tx_data[j].sis_map);
2164 }
2165 bus_dma_tag_destroy(cd->sis_txbuf_tag);
2166 cd->sis_txbuf_tag = NULL;
2167
2168 device_printf(dev, "could not create %dth "
2169 "TX buf DMA map\n", i);
2170 return error;
2171 }
2172 }
2173
2174 /* Create DMA tag for RX mbuf */
2175 error = bus_dma_tag_create(sc->sis_parent_tag,/* parent */
2176 SIS_RXBUF_ALIGN, 0, /* alignment, boundary */
2177 BUS_SPACE_MAXADDR, /* lowaddr */
2178 BUS_SPACE_MAXADDR, /* highaddr */
2179 MCLBYTES, /* maxsize */
2180 1, /* nsegments */
2181 MCLBYTES, /* maxsegsize */
2182 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2183 BUS_DMA_ALIGNED, /* flags */
2184 &cd->sis_rxbuf_tag);
2185 if (error) {
2186 device_printf(dev, "could not create RX buf DMA tag\n");
2187 return error;
2188 }
2189
2190 /* Create tmp DMA map for loading RX mbuf */
2191 error = bus_dmamap_create(cd->sis_rxbuf_tag, BUS_DMA_WAITOK,
2192 &cd->sis_rx_tmpmap);
2193 if (error) {
2194 device_printf(dev, "could not create RX buf tmp DMA map\n");
2195 bus_dma_tag_destroy(cd->sis_rxbuf_tag);
2196 cd->sis_rxbuf_tag = NULL;
2197 return error;
2198 }
2199
2200 /* Create DMA maps for RX mbufs */
2201 for (i = 0; i < SIS_RX_LIST_CNT; ++i) {
2202 error = bus_dmamap_create(cd->sis_rxbuf_tag, BUS_DMA_WAITOK,
2203 &cd->sis_rx_data[i].sis_map);
2204 if (error) {
2205 int j;
2206
2207 for (j = 0; j < i; ++j) {
2208 bus_dmamap_destroy(cd->sis_rxbuf_tag,
2209 cd->sis_rx_data[j].sis_map);
2210 }
2211 bus_dmamap_destroy(cd->sis_rxbuf_tag,
2212 cd->sis_rx_tmpmap);
2213 bus_dma_tag_destroy(cd->sis_rxbuf_tag);
2214 cd->sis_rxbuf_tag = NULL;
2215
2216 device_printf(dev, "could not create %dth "
2217 "RX buf DMA map\n", i);
2218 return error;
2219 }
2220 }
2221 return 0;
2222 }
2223
2224 static void
sis_dma_free(device_t dev)2225 sis_dma_free(device_t dev)
2226 {
2227 struct sis_softc *sc = device_get_softc(dev);
2228 struct sis_list_data *ld = &sc->sis_ldata;
2229 struct sis_chain_data *cd = &sc->sis_cdata;
2230 int i;
2231
2232 /* Free TX ring */
2233 if (ld->sis_tx_list != NULL) {
2234 bus_dmamap_unload(ld->sis_tx_tag, ld->sis_tx_dmamap);
2235 bus_dmamem_free(ld->sis_tx_tag, ld->sis_tx_list,
2236 ld->sis_tx_dmamap);
2237 bus_dma_tag_destroy(ld->sis_tx_tag);
2238 }
2239
2240 /* Free RX ring */
2241 if (ld->sis_rx_list != NULL) {
2242 bus_dmamap_unload(ld->sis_rx_tag, ld->sis_rx_dmamap);
2243 bus_dmamem_free(ld->sis_rx_tag, ld->sis_rx_list,
2244 ld->sis_rx_dmamap);
2245 bus_dma_tag_destroy(ld->sis_rx_tag);
2246 }
2247
2248 /* Destroy DMA stuffs for TX mbufs */
2249 if (cd->sis_txbuf_tag != NULL) {
2250 for (i = 0; i < SIS_TX_LIST_CNT; ++i) {
2251 KKASSERT(cd->sis_tx_data[i].sis_mbuf == NULL);
2252 bus_dmamap_destroy(cd->sis_txbuf_tag,
2253 cd->sis_tx_data[i].sis_map);
2254 }
2255 bus_dma_tag_destroy(cd->sis_txbuf_tag);
2256 }
2257
2258 /* Destroy DMA stuffs for RX mbufs */
2259 if (cd->sis_rxbuf_tag != NULL) {
2260 for (i = 0; i < SIS_RX_LIST_CNT; ++i) {
2261 KKASSERT(cd->sis_rx_data[i].sis_mbuf == NULL);
2262 bus_dmamap_destroy(cd->sis_rxbuf_tag,
2263 cd->sis_rx_data[i].sis_map);
2264 }
2265 bus_dmamap_destroy(cd->sis_rxbuf_tag, cd->sis_rx_tmpmap);
2266 bus_dma_tag_destroy(cd->sis_rxbuf_tag);
2267 }
2268 }
2269