xref: /dragonfly/sys/dev/netif/sk/if_sk.c (revision 030b0c8c)
1 /*
2  * Copyright (c) 1997, 1998, 1999, 2000
3  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  * 3. All advertising materials mentioning features or use of this software
14  *    must display the following acknowledgement:
15  *	This product includes software developed by Bill Paul.
16  * 4. Neither the name of the author nor the names of any co-contributors
17  *    may be used to endorse or promote products derived from this software
18  *    without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30  * THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  * $OpenBSD: if_sk.c,v 1.129 2006/10/16 12:30:08 tom Exp $
33  * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $
34  */
35 
36 /*
37  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
38  *
39  * Permission to use, copy, modify, and distribute this software for any
40  * purpose with or without fee is hereby granted, provided that the above
41  * copyright notice and this permission notice appear in all copies.
42  *
43  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
44  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
45  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
46  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
47  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
48  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
49  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
50  */
51 
52 /*
53  * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
54  * the SK-984x series adapters, both single port and dual port.
55  * References:
56  * 	The XaQti XMAC II datasheet,
57  * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
58  *	The SysKonnect GEnesis manual, http://www.syskonnect.com
59  *
60  * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
61  * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
62  * convenience to others until Vitesse corrects this problem:
63  *
64  * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
65  *
66  * Written by Bill Paul <wpaul@ee.columbia.edu>
67  * Department of Electrical Engineering
68  * Columbia University, New York City
69  */
70 
71 /*
72  * The SysKonnect gigabit ethernet adapters consist of two main
73  * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
74  * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
75  * components and a PHY while the GEnesis controller provides a PCI
76  * interface with DMA support. Each card may have between 512K and
77  * 2MB of SRAM on board depending on the configuration.
78  *
79  * The SysKonnect GEnesis controller can have either one or two XMAC
80  * chips connected to it, allowing single or dual port NIC configurations.
81  * SysKonnect has the distinction of being the only vendor on the market
82  * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
83  * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
84  * XMAC registers. This driver takes advantage of these features to allow
85  * both XMACs to operate as independent interfaces.
86  */
87 
88 #include <sys/param.h>
89 #include <sys/bus.h>
90 #include <sys/endian.h>
91 #include <sys/in_cksum.h>
92 #include <sys/kernel.h>
93 #include <sys/interrupt.h>
94 #include <sys/mbuf.h>
95 #include <sys/malloc.h>
96 #include <sys/queue.h>
97 #include <sys/rman.h>
98 #include <sys/serialize.h>
99 #include <sys/socket.h>
100 #include <sys/sockio.h>
101 #include <sys/sysctl.h>
102 
103 #include <net/bpf.h>
104 #include <net/ethernet.h>
105 #include <net/if.h>
106 #include <net/if_arp.h>
107 #include <net/if_dl.h>
108 #include <net/if_media.h>
109 #include <net/ifq_var.h>
110 #include <net/vlan/if_vlan_var.h>
111 
112 #include <netinet/ip.h>
113 #include <netinet/udp.h>
114 
115 #include <dev/netif/mii_layer/mii.h>
116 #include <dev/netif/mii_layer/miivar.h>
117 #include <dev/netif/mii_layer/brgphyreg.h>
118 
119 #include <bus/pci/pcireg.h>
120 #include <bus/pci/pcivar.h>
121 #include "pcidevs.h"
122 
123 #include <dev/netif/sk/if_skreg.h>
124 #include <dev/netif/sk/yukonreg.h>
125 #include <dev/netif/sk/xmaciireg.h>
126 #include <dev/netif/sk/if_skvar.h>
127 
128 #include "miibus_if.h"
129 
130 #if 0
131 #define SK_DEBUG
132 #endif
133 
134 #if 0
135 #define SK_RXCSUM
136 #endif
137 
138 /* supported device vendors */
139 static const struct skc_type {
140 	uint16_t	skc_vid;
141 	uint16_t	skc_did;
142 	const char	*skc_name;
143 } skc_devs[] = {
144 	{ PCI_VENDOR_3COM,		PCI_PRODUCT_3COM_3C940,
145 	  "3Com 3C940" },
146 	{ PCI_VENDOR_3COM,		PCI_PRODUCT_3COM_3C940B,
147 	  "3Com 3C940B" },
148 
149 	{ PCI_VENDOR_CNET,		PCI_PRODUCT_CNET_GIGACARD,
150 	  "CNet GigaCard" },
151 
152 	{ PCI_VENDOR_DLINK,		PCI_PRODUCT_DLINK_DGE530T_A1,
153 	  "D-Link DGE-530T A1" },
154 	{ PCI_VENDOR_DLINK,		PCI_PRODUCT_DLINK_DGE530T_B1,
155 	  "D-Link DGE-530T B1" },
156 
157 	{ PCI_VENDOR_LINKSYS,		PCI_PRODUCT_LINKSYS_EG1032,
158 	  "Linksys EG1032 v2" },
159 	{ PCI_VENDOR_LINKSYS,		PCI_PRODUCT_LINKSYS_EG1064,
160 	  "Linksys EG1064" },
161 
162 	{ PCI_VENDOR_MARVELL,		PCI_PRODUCT_MARVELL_YUKON,
163 	  "Marvell Yukon 88E8001/8003/8010" },
164 	{ PCI_VENDOR_MARVELL,		PCI_PRODUCT_MARVELL_YUKON_BELKIN,
165 	  "Belkin F5D5005" },
166 
167 	{ PCI_VENDOR_SCHNEIDERKOCH,	PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE,
168 	  "SysKonnect SK-NET" },
169 	{ PCI_VENDOR_SCHNEIDERKOCH,	PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2,
170 	  "SysKonnect SK9821 v2" },
171 
172 	{ 0, 0, NULL }
173 };
174 
175 static int	skc_probe(device_t);
176 static int	skc_attach(device_t);
177 static int	skc_detach(device_t);
178 static void	skc_shutdown(device_t);
179 static int	skc_sysctl_imtime(SYSCTL_HANDLER_ARGS);
180 
181 static int	sk_probe(device_t);
182 static int	sk_attach(device_t);
183 static int	sk_detach(device_t);
184 static void	sk_tick(void *);
185 static void	sk_yukon_tick(void *);
186 static void	sk_intr(void *);
187 static void	sk_intr_bcom(struct sk_if_softc *);
188 static void	sk_intr_xmac(struct sk_if_softc *);
189 static void	sk_intr_yukon(struct sk_if_softc *);
190 static void	sk_rxeof(struct sk_if_softc *);
191 static void	sk_txeof(struct sk_if_softc *);
192 static int	sk_encap(struct sk_if_softc *, struct mbuf **, uint32_t *);
193 static void	sk_start(struct ifnet *, struct ifaltq_subque *);
194 static int	sk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
195 static void	sk_init(void *);
196 static void	sk_init_xmac(struct sk_if_softc *);
197 static void	sk_init_yukon(struct sk_if_softc *);
198 static void	sk_stop(struct sk_if_softc *);
199 static void	sk_watchdog(struct ifnet *);
200 static int	sk_ifmedia_upd(struct ifnet *);
201 static void	sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
202 static void	sk_reset(struct sk_softc *);
203 static int	sk_newbuf_jumbo(struct sk_if_softc *, int, int);
204 static int	sk_newbuf_std(struct sk_if_softc *, int, int);
205 static int	sk_jpool_alloc(device_t);
206 static void	sk_jpool_free(struct sk_if_softc *);
207 static struct sk_jpool_entry
208 		*sk_jalloc(struct sk_if_softc *);
209 static void	sk_jfree(void *);
210 static void	sk_jref(void *);
211 static int	sk_init_rx_ring(struct sk_if_softc *);
212 static int	sk_init_tx_ring(struct sk_if_softc *);
213 
214 static int	sk_miibus_readreg(device_t, int, int);
215 static int	sk_miibus_writereg(device_t, int, int, int);
216 static void	sk_miibus_statchg(device_t);
217 
218 static int	sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
219 static int	sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, int);
220 static void	sk_xmac_miibus_statchg(struct sk_if_softc *);
221 
222 static int	sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
223 static int	sk_marv_miibus_writereg(struct sk_if_softc *, int, int, int);
224 static void	sk_marv_miibus_statchg(struct sk_if_softc *);
225 
226 static void	sk_setfilt(struct sk_if_softc *, caddr_t, int);
227 static void	sk_setmulti(struct sk_if_softc *);
228 static void	sk_setpromisc(struct sk_if_softc *);
229 
230 #ifdef SK_RXCSUM
231 static void	sk_rxcsum(struct ifnet *, struct mbuf *, const uint16_t,
232 			  const uint16_t);
233 #endif
234 static int	sk_dma_alloc(device_t);
235 static void	sk_dma_free(device_t);
236 
237 #ifdef SK_DEBUG
238 #define DPRINTF(x)	if (skdebug) kprintf x
239 #define DPRINTFN(n,x)	if (skdebug >= (n)) kprintf x
240 static int	skdebug = 2;
241 
242 static void	sk_dump_txdesc(struct sk_tx_desc *, int);
243 static void	sk_dump_mbuf(struct mbuf *);
244 static void	sk_dump_bytes(const char *, int);
245 #else
246 #define DPRINTF(x)
247 #define DPRINTFN(n,x)
248 #endif
249 
250 /* Interrupt moderation time. */
251 static int	skc_imtime = SK_IMTIME_DEFAULT;
252 TUNABLE_INT("hw.skc.imtime", &skc_imtime);
253 
254 /*
255  * Note that we have newbus methods for both the GEnesis controller
256  * itself and the XMAC(s). The XMACs are children of the GEnesis, and
257  * the miibus code is a child of the XMACs. We need to do it this way
258  * so that the miibus drivers can access the PHY registers on the
259  * right PHY. It's not quite what I had in mind, but it's the only
260  * design that achieves the desired effect.
261  */
262 static device_method_t skc_methods[] = {
263 	/* Device interface */
264 	DEVMETHOD(device_probe,		skc_probe),
265 	DEVMETHOD(device_attach,	skc_attach),
266 	DEVMETHOD(device_detach,	skc_detach),
267 	DEVMETHOD(device_shutdown,	skc_shutdown),
268 
269 	/* bus interface */
270 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
271 	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
272 
273 	DEVMETHOD_END
274 };
275 
276 static DEFINE_CLASS_0(skc, skc_driver, skc_methods, sizeof(struct sk_softc));
277 static devclass_t skc_devclass;
278 
279 static device_method_t sk_methods[] = {
280 	/* Device interface */
281 	DEVMETHOD(device_probe,		sk_probe),
282 	DEVMETHOD(device_attach,	sk_attach),
283 	DEVMETHOD(device_detach,	sk_detach),
284 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
285 
286 	/* bus interface */
287 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
288 	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
289 
290 	/* MII interface */
291 	DEVMETHOD(miibus_readreg,	sk_miibus_readreg),
292 	DEVMETHOD(miibus_writereg,	sk_miibus_writereg),
293 	DEVMETHOD(miibus_statchg,	sk_miibus_statchg),
294 
295 	DEVMETHOD_END
296 };
297 
298 static DEFINE_CLASS_0(sk, sk_driver, sk_methods, sizeof(struct sk_if_softc));
299 static devclass_t sk_devclass;
300 
301 DECLARE_DUMMY_MODULE(if_sk);
302 DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, NULL, NULL);
303 DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, NULL, NULL);
304 DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, NULL, NULL);
305 
306 static __inline uint32_t
sk_win_read_4(struct sk_softc * sc,uint32_t reg)307 sk_win_read_4(struct sk_softc *sc, uint32_t reg)
308 {
309 	return CSR_READ_4(sc, reg);
310 }
311 
312 static __inline uint16_t
sk_win_read_2(struct sk_softc * sc,uint32_t reg)313 sk_win_read_2(struct sk_softc *sc, uint32_t reg)
314 {
315 	return CSR_READ_2(sc, reg);
316 }
317 
318 static __inline uint8_t
sk_win_read_1(struct sk_softc * sc,uint32_t reg)319 sk_win_read_1(struct sk_softc *sc, uint32_t reg)
320 {
321 	return CSR_READ_1(sc, reg);
322 }
323 
324 static __inline void
sk_win_write_4(struct sk_softc * sc,uint32_t reg,uint32_t x)325 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x)
326 {
327 	CSR_WRITE_4(sc, reg, x);
328 }
329 
330 static __inline void
sk_win_write_2(struct sk_softc * sc,uint32_t reg,uint16_t x)331 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x)
332 {
333 	CSR_WRITE_2(sc, reg, x);
334 }
335 
336 static __inline void
sk_win_write_1(struct sk_softc * sc,uint32_t reg,uint8_t x)337 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x)
338 {
339 	CSR_WRITE_1(sc, reg, x);
340 }
341 
342 static __inline int
sk_newbuf(struct sk_if_softc * sc_if,int idx,int wait)343 sk_newbuf(struct sk_if_softc *sc_if, int idx, int wait)
344 {
345 	int ret;
346 
347 	if (sc_if->sk_use_jumbo)
348 		ret = sk_newbuf_jumbo(sc_if, idx, wait);
349 	else
350 		ret = sk_newbuf_std(sc_if, idx, wait);
351 	return ret;
352 }
353 
354 static int
sk_miibus_readreg(device_t dev,int phy,int reg)355 sk_miibus_readreg(device_t dev, int phy, int reg)
356 {
357 	struct sk_if_softc *sc_if = device_get_softc(dev);
358 
359 	if (SK_IS_GENESIS(sc_if->sk_softc))
360 		return sk_xmac_miibus_readreg(sc_if, phy, reg);
361 	else
362 		return sk_marv_miibus_readreg(sc_if, phy, reg);
363 }
364 
365 static int
sk_miibus_writereg(device_t dev,int phy,int reg,int val)366 sk_miibus_writereg(device_t dev, int phy, int reg, int val)
367 {
368 	struct sk_if_softc *sc_if = device_get_softc(dev);
369 
370 	if (SK_IS_GENESIS(sc_if->sk_softc))
371 		return sk_xmac_miibus_writereg(sc_if, phy, reg, val);
372 	else
373 		return sk_marv_miibus_writereg(sc_if, phy, reg, val);
374 }
375 
376 static void
sk_miibus_statchg(device_t dev)377 sk_miibus_statchg(device_t dev)
378 {
379 	struct sk_if_softc *sc_if = device_get_softc(dev);
380 
381 	if (SK_IS_GENESIS(sc_if->sk_softc))
382 		sk_xmac_miibus_statchg(sc_if);
383 	else
384 		sk_marv_miibus_statchg(sc_if);
385 }
386 
387 static int
sk_xmac_miibus_readreg(struct sk_if_softc * sc_if,int phy,int reg)388 sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
389 {
390 	int i;
391 
392 	DPRINTFN(9, ("sk_xmac_miibus_readreg\n"));
393 
394 	if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
395 		return(0);
396 
397 	SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
398 	SK_XM_READ_2(sc_if, XM_PHY_DATA);
399 	if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
400 		for (i = 0; i < SK_TIMEOUT; i++) {
401 			DELAY(1);
402 			if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
403 			    XM_MMUCMD_PHYDATARDY)
404 				break;
405 		}
406 
407 		if (i == SK_TIMEOUT) {
408 			if_printf(&sc_if->arpcom.ac_if,
409 				  "phy failed to come ready\n");
410 			return(0);
411 		}
412 	}
413 	DELAY(1);
414 	return(SK_XM_READ_2(sc_if, XM_PHY_DATA));
415 }
416 
417 static int
sk_xmac_miibus_writereg(struct sk_if_softc * sc_if,int phy,int reg,int val)418 sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
419 {
420 	int i;
421 
422 	DPRINTFN(9, ("sk_xmac_miibus_writereg\n"));
423 
424 	SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
425 	for (i = 0; i < SK_TIMEOUT; i++) {
426 		if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
427 			break;
428 	}
429 
430 	if (i == SK_TIMEOUT) {
431 		if_printf(&sc_if->arpcom.ac_if, "phy failed to come ready\n");
432 		return(ETIMEDOUT);
433 	}
434 
435 	SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
436 	for (i = 0; i < SK_TIMEOUT; i++) {
437 		DELAY(1);
438 		if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
439 			break;
440 	}
441 
442 	if (i == SK_TIMEOUT)
443 		if_printf(&sc_if->arpcom.ac_if, "phy write timed out\n");
444 	return(0);
445 }
446 
447 static void
sk_xmac_miibus_statchg(struct sk_if_softc * sc_if)448 sk_xmac_miibus_statchg(struct sk_if_softc *sc_if)
449 {
450 	struct mii_data *mii;
451 
452 	mii = device_get_softc(sc_if->sk_miibus);
453 	DPRINTFN(9, ("sk_xmac_miibus_statchg\n"));
454 
455 	/*
456 	 * If this is a GMII PHY, manually set the XMAC's
457 	 * duplex mode accordingly.
458 	 */
459 	if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
460 		if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
461 			SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
462 		else
463 			SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
464 	}
465 }
466 
467 static int
sk_marv_miibus_readreg(struct sk_if_softc * sc_if,int phy,int reg)468 sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
469 {
470 	uint16_t val;
471 	int i;
472 
473 	if (phy != 0 ||
474 	    (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
475 	     sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
476 		DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n",
477 			     phy, reg));
478 		return(0);
479 	}
480 
481         SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
482 		      YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
483 
484 	for (i = 0; i < SK_TIMEOUT; i++) {
485 		DELAY(1);
486 		val = SK_YU_READ_2(sc_if, YUKON_SMICR);
487 		if (val & YU_SMICR_READ_VALID)
488 			break;
489 	}
490 
491 	if (i == SK_TIMEOUT) {
492 		if_printf(&sc_if->arpcom.ac_if, "phy failed to come ready\n");
493 		return(0);
494 	}
495 
496  	DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i,
497 		     SK_TIMEOUT));
498 
499 	val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
500 
501 	DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n",
502 		     phy, reg, val));
503 
504 	return(val);
505 }
506 
507 static int
sk_marv_miibus_writereg(struct sk_if_softc * sc_if,int phy,int reg,int val)508 sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
509 {
510 	int i;
511 
512 	DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n",
513 		     phy, reg, val));
514 
515 	SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
516 	SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
517 		      YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
518 
519 	for (i = 0; i < SK_TIMEOUT; i++) {
520 		DELAY(1);
521 		if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)
522 			break;
523 	}
524 
525 	if (i == SK_TIMEOUT)
526 		if_printf(&sc_if->arpcom.ac_if, "phy write timed out\n");
527 
528 	return(0);
529 }
530 
531 static void
sk_marv_miibus_statchg(struct sk_if_softc * sc_if)532 sk_marv_miibus_statchg(struct sk_if_softc *sc_if)
533 {
534 	DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n",
535 		     SK_YU_READ_2(sc_if, YUKON_GPCR)));
536 }
537 
538 #define HASH_BITS	6
539 
540 static uint32_t
sk_xmac_hash(caddr_t addr)541 sk_xmac_hash(caddr_t addr)
542 {
543 	uint32_t crc;
544 
545 	crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
546 	return (~crc & ((1 << HASH_BITS) - 1));
547 }
548 
549 static uint32_t
sk_yukon_hash(caddr_t addr)550 sk_yukon_hash(caddr_t addr)
551 {
552 	uint32_t crc;
553 
554 	crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
555 	return (crc & ((1 << HASH_BITS) - 1));
556 }
557 
558 static void
sk_setfilt(struct sk_if_softc * sc_if,caddr_t addr,int slot)559 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot)
560 {
561 	int base;
562 
563 	base = XM_RXFILT_ENTRY(slot);
564 
565 	SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0]));
566 	SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2]));
567 	SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4]));
568 }
569 
570 static void
sk_setmulti(struct sk_if_softc * sc_if)571 sk_setmulti(struct sk_if_softc *sc_if)
572 {
573 	struct sk_softc *sc = sc_if->sk_softc;
574 	struct ifnet *ifp = &sc_if->arpcom.ac_if;
575 	uint32_t hashes[2] = { 0, 0 };
576 	int h = 0, i;
577 	struct ifmultiaddr *ifma;
578 	uint8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
579 
580 	/* First, zot all the existing filters. */
581 	switch(sc->sk_type) {
582 	case SK_GENESIS:
583 		for (i = 1; i < XM_RXFILT_MAX; i++)
584 			sk_setfilt(sc_if, (caddr_t)&dummy, i);
585 
586 		SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
587 		SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
588 		break;
589 	case SK_YUKON:
590 	case SK_YUKON_LITE:
591 	case SK_YUKON_LP:
592 		SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
593 		SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
594 		SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
595 		SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
596 		break;
597 	}
598 
599 	/* Now program new ones. */
600 	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
601 		hashes[0] = 0xFFFFFFFF;
602 		hashes[1] = 0xFFFFFFFF;
603 	} else {
604 		i = 1;
605 		/* First find the tail of the list. */
606 		TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead,
607 		    ifma_link) {
608 			caddr_t maddr;
609 
610 			if (ifma->ifma_addr->sa_family != AF_LINK)
611 				continue;
612 
613 			maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
614 
615 			/*
616 			 * Program the first XM_RXFILT_MAX multicast groups
617 			 * into the perfect filter. For all others,
618 			 * use the hash table.
619 			 */
620 			if (SK_IS_GENESIS(sc) && i < XM_RXFILT_MAX) {
621 				sk_setfilt(sc_if, maddr, i);
622 				i++;
623 				continue;
624 			}
625 
626 			switch(sc->sk_type) {
627 			case SK_GENESIS:
628 				h = sk_xmac_hash(maddr);
629 				break;
630 
631 			case SK_YUKON:
632 			case SK_YUKON_LITE:
633 			case SK_YUKON_LP:
634 				h = sk_yukon_hash(maddr);
635 				break;
636 			}
637 			if (h < 32)
638 				hashes[0] |= (1 << h);
639 			else
640 				hashes[1] |= (1 << (h - 32));
641 		}
642 	}
643 
644 	switch(sc->sk_type) {
645 	case SK_GENESIS:
646 		SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
647 			       XM_MODE_RX_USE_PERFECT);
648 		SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
649 		SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
650 		break;
651 	case SK_YUKON:
652 	case SK_YUKON_LITE:
653 	case SK_YUKON_LP:
654 		SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
655 		SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
656 		SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
657 		SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
658 		break;
659 	}
660 }
661 
662 static void
sk_setpromisc(struct sk_if_softc * sc_if)663 sk_setpromisc(struct sk_if_softc *sc_if)
664 {
665 	struct sk_softc	*sc = sc_if->sk_softc;
666 	struct ifnet *ifp = &sc_if->arpcom.ac_if;
667 
668 	switch(sc->sk_type) {
669 	case SK_GENESIS:
670 		if (ifp->if_flags & IFF_PROMISC)
671 			SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
672 		else
673 			SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
674 		break;
675 	case SK_YUKON:
676 	case SK_YUKON_LITE:
677 	case SK_YUKON_LP:
678 		if (ifp->if_flags & IFF_PROMISC) {
679 			SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
680 			    YU_RCR_UFLEN | YU_RCR_MUFLEN);
681 		} else {
682 			SK_YU_SETBIT_2(sc_if, YUKON_RCR,
683 			    YU_RCR_UFLEN | YU_RCR_MUFLEN);
684 		}
685 		break;
686 	}
687 }
688 
689 static int
sk_init_rx_ring(struct sk_if_softc * sc_if)690 sk_init_rx_ring(struct sk_if_softc *sc_if)
691 {
692 	struct sk_chain_data *cd = &sc_if->sk_cdata;
693 	struct sk_ring_data *rd = &sc_if->sk_rdata;
694 	int i, nexti, error;
695 
696 	bzero(rd->sk_rx_ring, SK_RX_RING_SIZE);
697 
698 	for (i = 0; i < SK_RX_RING_CNT; i++) {
699 		bus_addr_t paddr;
700 
701 		if (i == (SK_RX_RING_CNT - 1))
702 			nexti = 0;
703 		else
704 			nexti = i + 1;
705 		paddr = rd->sk_rx_ring_paddr +
706 			(nexti * sizeof(struct sk_rx_desc));
707 
708 		rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(paddr));
709 		rd->sk_rx_ring[i].sk_csum1_start = htole16(ETHER_HDR_LEN);
710 		rd->sk_rx_ring[i].sk_csum2_start =
711 			htole16(ETHER_HDR_LEN + sizeof(struct ip));
712 
713 		error = sk_newbuf(sc_if, i, 1);
714 		if (error) {
715 			if_printf(&sc_if->arpcom.ac_if,
716 				  "failed alloc of %dth mbuf\n", i);
717 			return error;
718 		}
719 	}
720 
721 	cd->sk_rx_prod = 0;
722 	cd->sk_rx_cons = 0;
723 
724 	return (0);
725 }
726 
727 static int
sk_init_tx_ring(struct sk_if_softc * sc_if)728 sk_init_tx_ring(struct sk_if_softc *sc_if)
729 {
730 	struct sk_ring_data *rd = &sc_if->sk_rdata;
731 	int i, nexti;
732 
733 	bzero(rd->sk_tx_ring, SK_TX_RING_SIZE);
734 
735 	for (i = 0; i < SK_TX_RING_CNT; i++) {
736 		bus_addr_t paddr;
737 
738 		if (i == (SK_TX_RING_CNT - 1))
739 			nexti = 0;
740 		else
741 			nexti = i + 1;
742 		paddr = rd->sk_tx_ring_paddr +
743 			(nexti * sizeof(struct sk_tx_desc));
744 
745 		rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(paddr));
746 	}
747 
748 	sc_if->sk_cdata.sk_tx_prod = 0;
749 	sc_if->sk_cdata.sk_tx_cons = 0;
750 	sc_if->sk_cdata.sk_tx_cnt = 0;
751 
752 	return (0);
753 }
754 
755 static int
sk_newbuf_jumbo(struct sk_if_softc * sc_if,int idx,int wait)756 sk_newbuf_jumbo(struct sk_if_softc *sc_if, int idx, int wait)
757 {
758 	struct sk_jpool_entry *entry;
759 	struct mbuf *m_new = NULL;
760 	struct sk_rx_desc *r;
761 	bus_addr_t paddr;
762 
763 	KKASSERT(idx < SK_RX_RING_CNT && idx >= 0);
764 
765 	MGETHDR(m_new, wait ? M_WAITOK : M_NOWAIT, MT_DATA);
766 	if (m_new == NULL)
767 		return ENOBUFS;
768 
769 	/* Allocate the jumbo buffer */
770 	entry = sk_jalloc(sc_if);
771 	if (entry == NULL) {
772 		m_freem(m_new);
773 		DPRINTFN(1, ("%s jumbo allocation failed -- packet "
774 		    "dropped!\n", sc_if->arpcom.ac_if.if_xname));
775 		return ENOBUFS;
776 	}
777 
778 	m_new->m_ext.ext_arg = entry;
779 	m_new->m_ext.ext_buf = entry->buf;
780 	m_new->m_ext.ext_free = sk_jfree;
781 	m_new->m_ext.ext_ref = sk_jref;
782 	m_new->m_ext.ext_size = SK_JLEN;
783 
784 	m_new->m_flags |= M_EXT;
785 
786 	m_new->m_data = m_new->m_ext.ext_buf;
787 	m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
788 
789 	paddr = entry->paddr;
790 
791 	/*
792 	 * Adjust alignment so packet payload begins on a
793 	 * longword boundary. Mandatory for Alpha, useful on
794 	 * x86 too.
795 	 */
796 	m_adj(m_new, ETHER_ALIGN);
797 	paddr += ETHER_ALIGN;
798 
799 	sc_if->sk_cdata.sk_rx_mbuf[idx] = m_new;
800 
801 	r = &sc_if->sk_rdata.sk_rx_ring[idx];
802 	r->sk_data_lo = htole32(SK_ADDR_LO(paddr));
803 	r->sk_data_hi = htole32(SK_ADDR_HI(paddr));
804 	r->sk_ctl = htole32(m_new->m_pkthdr.len | SK_RXSTAT);
805 
806 	return 0;
807 }
808 
809 static int
sk_newbuf_std(struct sk_if_softc * sc_if,int idx,int wait)810 sk_newbuf_std(struct sk_if_softc *sc_if, int idx, int wait)
811 {
812 	struct mbuf *m_new = NULL;
813 	struct sk_chain_data *cd = &sc_if->sk_cdata;
814 	struct sk_rx_desc *r;
815 	bus_dma_segment_t seg;
816 	bus_dmamap_t map;
817 	int error, nseg;
818 
819 	KKASSERT(idx < SK_RX_RING_CNT && idx >= 0);
820 
821 	m_new = m_getcl(wait ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR);
822 	if (m_new == NULL)
823 		return ENOBUFS;
824 
825 	m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
826 
827 	/*
828 	 * Adjust alignment so packet payload begins on a
829 	 * longword boundary. Mandatory for Alpha, useful on
830 	 * x86 too.
831 	 */
832 	m_adj(m_new, ETHER_ALIGN);
833 
834 	error = bus_dmamap_load_mbuf_segment(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp,
835 			m_new, &seg, 1, &nseg, BUS_DMA_NOWAIT);
836 	if (error) {
837 		m_freem(m_new);
838 		if (wait) {
839 			if_printf(&sc_if->arpcom.ac_if,
840 				  "could not map RX mbuf\n");
841 		}
842 		return error;
843 	}
844 
845 	/* Unload originally mapped mbuf */
846 	if (cd->sk_rx_mbuf[idx] != NULL) {
847 		bus_dmamap_sync(cd->sk_rx_dtag, cd->sk_rx_dmap[idx],
848 				BUS_DMASYNC_POSTREAD);
849 		bus_dmamap_unload(cd->sk_rx_dtag, cd->sk_rx_dmap[idx]);
850 	}
851 
852 	/* Switch DMA map with tmp DMA map */
853 	map = cd->sk_rx_dmap_tmp;
854 	cd->sk_rx_dmap_tmp = cd->sk_rx_dmap[idx];
855 	cd->sk_rx_dmap[idx] = map;
856 
857 	cd->sk_rx_mbuf[idx] = m_new;
858 
859 	r = &sc_if->sk_rdata.sk_rx_ring[idx];
860 	r->sk_data_lo = htole32(SK_ADDR_LO(seg.ds_addr));
861 	r->sk_data_hi = htole32(SK_ADDR_HI(seg.ds_addr));
862 	r->sk_ctl = htole32(m_new->m_pkthdr.len | SK_RXSTAT);
863 
864 	return 0;
865 }
866 
867 /*
868  * Allocate a jumbo buffer.
869  */
870 static struct sk_jpool_entry *
sk_jalloc(struct sk_if_softc * sc_if)871 sk_jalloc(struct sk_if_softc *sc_if)
872 {
873 	struct sk_chain_data *cd = &sc_if->sk_cdata;
874 	struct sk_jpool_entry *entry;
875 
876 	lwkt_serialize_enter(&cd->sk_jpool_serializer);
877 
878 	entry = SLIST_FIRST(&cd->sk_jpool_free_ent);
879 	if (entry != NULL) {
880 		SLIST_REMOVE_HEAD(&cd->sk_jpool_free_ent, entry_next);
881 		entry->inuse = 1;
882 	} else {
883 		DPRINTF(("no free jumbo buffer\n"));
884 	}
885 
886 	lwkt_serialize_exit(&cd->sk_jpool_serializer);
887 	return entry;
888 }
889 
890 /*
891  * Release a jumbo buffer.
892  */
893 static void
sk_jfree(void * arg)894 sk_jfree(void *arg)
895 {
896 	struct sk_jpool_entry *entry = arg;
897 	struct sk_chain_data *cd = &entry->sc_if->sk_cdata;
898 
899 	if (&cd->sk_jpool_ent[entry->slot] != entry)
900 		panic("%s: free wrong jumbo buffer", __func__);
901 	else if (entry->inuse == 0)
902 		panic("%s: jumbo buffer already freed", __func__);
903 
904 	lwkt_serialize_enter(&cd->sk_jpool_serializer);
905 
906 	atomic_subtract_int(&entry->inuse, 1);
907 	if (entry->inuse == 0)
908 		SLIST_INSERT_HEAD(&cd->sk_jpool_free_ent, entry, entry_next);
909 
910 	lwkt_serialize_exit(&cd->sk_jpool_serializer);
911 }
912 
913 static void
sk_jref(void * arg)914 sk_jref(void *arg)
915 {
916 	struct sk_jpool_entry *entry = arg;
917 	struct sk_chain_data *cd = &entry->sc_if->sk_cdata;
918 
919 	if (&cd->sk_jpool_ent[entry->slot] != entry)
920 		panic("%s: free wrong jumbo buffer", __func__);
921 	else if (entry->inuse == 0)
922 		panic("%s: jumbo buffer already freed", __func__);
923 
924 	atomic_add_int(&entry->inuse, 1);
925 }
926 
927 /*
928  * Set media options.
929  */
930 static int
sk_ifmedia_upd(struct ifnet * ifp)931 sk_ifmedia_upd(struct ifnet *ifp)
932 {
933 	struct sk_if_softc *sc_if = ifp->if_softc;
934 	struct mii_data *mii;
935 
936 	mii = device_get_softc(sc_if->sk_miibus);
937 	sk_init(sc_if);
938 	mii_mediachg(mii);
939 
940 	return(0);
941 }
942 
943 /*
944  * Report current media status.
945  */
946 static void
sk_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)947 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
948 {
949 	struct sk_if_softc *sc_if;
950 	struct mii_data *mii;
951 
952 	sc_if = ifp->if_softc;
953 	mii = device_get_softc(sc_if->sk_miibus);
954 
955 	mii_pollstat(mii);
956 	ifmr->ifm_active = mii->mii_media_active;
957 	ifmr->ifm_status = mii->mii_media_status;
958 }
959 
960 static int
sk_ioctl(struct ifnet * ifp,u_long command,caddr_t data,struct ucred * cr)961 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
962 {
963 	struct sk_if_softc *sc_if = ifp->if_softc;
964 	struct ifreq *ifr = (struct ifreq *)data;
965 	struct mii_data *mii;
966 	int error = 0;
967 
968 	ASSERT_SERIALIZED(ifp->if_serializer);
969 
970 	switch(command) {
971 	case SIOCSIFMTU:
972 		if (ifr->ifr_mtu > SK_JUMBO_MTU)
973 			error = EINVAL;
974 		else {
975 			ifp->if_mtu = ifr->ifr_mtu;
976 			ifp->if_flags &= ~IFF_RUNNING;
977 			sk_init(sc_if);
978 		}
979 		break;
980 	case SIOCSIFFLAGS:
981 		if (ifp->if_flags & IFF_UP) {
982 			if (ifp->if_flags & IFF_RUNNING) {
983 				if ((ifp->if_flags ^ sc_if->sk_if_flags)
984 				    & IFF_PROMISC) {
985 					sk_setpromisc(sc_if);
986 					sk_setmulti(sc_if);
987 				}
988 			} else
989 				sk_init(sc_if);
990 		} else {
991 			if (ifp->if_flags & IFF_RUNNING)
992 				sk_stop(sc_if);
993 		}
994 		sc_if->sk_if_flags = ifp->if_flags;
995 		break;
996 	case SIOCADDMULTI:
997 	case SIOCDELMULTI:
998 		sk_setmulti(sc_if);
999 		break;
1000 	case SIOCGIFMEDIA:
1001 	case SIOCSIFMEDIA:
1002 		mii = device_get_softc(sc_if->sk_miibus);
1003 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1004 		break;
1005 	default:
1006 		error = ether_ioctl(ifp, command, data);
1007 		break;
1008 	}
1009 
1010 	return(error);
1011 }
1012 
1013 /*
1014  * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1015  * IDs against our list and return a device name if we find a match.
1016  */
1017 static int
skc_probe(device_t dev)1018 skc_probe(device_t dev)
1019 {
1020 	const struct skc_type *t;
1021 	uint16_t vid, did;
1022 
1023 	vid = pci_get_vendor(dev);
1024 	did = pci_get_device(dev);
1025 
1026 	/*
1027 	 * Only attach to rev.2 of the Linksys EG1032 adapter.
1028 	 * Rev.3 is supported by re(4).
1029 	 */
1030 	if (vid == PCI_VENDOR_LINKSYS &&
1031 	    did == PCI_PRODUCT_LINKSYS_EG1032 &&
1032 	    pci_get_subdevice(dev) != SUBDEVICEID_LINKSYS_EG1032_REV2)
1033 		return ENXIO;
1034 
1035 	for (t = skc_devs; t->skc_name != NULL; t++) {
1036 		if (vid == t->skc_vid && did == t->skc_did) {
1037 			device_set_desc(dev, t->skc_name);
1038 			return 0;
1039 		}
1040 	}
1041 	return ENXIO;
1042 }
1043 
1044 /*
1045  * Force the GEnesis into reset, then bring it out of reset.
1046  */
1047 static void
sk_reset(struct sk_softc * sc)1048 sk_reset(struct sk_softc *sc)
1049 {
1050 	DPRINTFN(2, ("sk_reset\n"));
1051 
1052 	CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1053 	CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1054 	if (SK_IS_YUKON(sc))
1055 		CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1056 
1057 	DELAY(1000);
1058 	CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1059 	DELAY(2);
1060 	CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1061 	if (SK_IS_YUKON(sc))
1062 		CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1063 
1064 	DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR)));
1065 	DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n",
1066 		     CSR_READ_2(sc, SK_LINK_CTRL)));
1067 
1068 	if (SK_IS_GENESIS(sc)) {
1069 		/* Configure packet arbiter */
1070 		sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1071 		sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1072 		sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1073 		sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1074 		sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1075 	}
1076 
1077 	/* Enable RAM interface */
1078 	sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1079 
1080 	/*
1081 	 * Configure interrupt moderation. The moderation timer
1082 	 * defers interrupts specified in the interrupt moderation
1083 	 * timer mask based on the timeout specified in the interrupt
1084 	 * moderation timer init register. Each bit in the timer
1085 	 * register represents one tick, so to specify a timeout in
1086 	 * microseconds, we have to multiply by the correct number of
1087 	 * ticks-per-microsecond.
1088 	 */
1089 	KKASSERT(sc->sk_imtimer_ticks != 0 && sc->sk_imtime != 0);
1090 	sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc, sc->sk_imtime));
1091 	sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
1092 	    SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
1093 	sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1094 }
1095 
1096 static int
sk_probe(device_t dev)1097 sk_probe(device_t dev)
1098 {
1099 	struct sk_softc *sc = device_get_softc(device_get_parent(dev));
1100 	const char *revstr = "", *name = NULL;
1101 	char devname[80];
1102 
1103 	switch (sc->sk_type) {
1104 	case SK_GENESIS:
1105 		name = "SysKonnect GEnesis";
1106 		break;
1107 	case SK_YUKON:
1108 		name = "Marvell Yukon";
1109 		break;
1110 	case SK_YUKON_LITE:
1111 		name = "Marvell Yukon Lite";
1112 		switch (sc->sk_rev) {
1113 		case SK_YUKON_LITE_REV_A0:
1114 			revstr = " rev.A0";
1115 			break;
1116 		case SK_YUKON_LITE_REV_A1:
1117 			revstr = " rev.A1";
1118 			break;
1119 		case SK_YUKON_LITE_REV_A3:
1120 			revstr = " rev.A3";
1121 			break;
1122 		}
1123 		break;
1124 	case SK_YUKON_LP:
1125 		name = "Marvell Yukon LP";
1126 		break;
1127 	default:
1128 		return ENXIO;
1129 	}
1130 
1131 	ksnprintf(devname, sizeof(devname), "%s%s (0x%x)",
1132 		 name, revstr, sc->sk_rev);
1133 	device_set_desc_copy(dev, devname);
1134 	return 0;
1135 }
1136 
1137 /*
1138  * Each XMAC chip is attached as a separate logical IP interface.
1139  * Single port cards will have only one logical interface of course.
1140  */
1141 static int
sk_attach(device_t dev)1142 sk_attach(device_t dev)
1143 {
1144 	struct sk_softc *sc = device_get_softc(device_get_parent(dev));
1145 	struct sk_if_softc *sc_if = device_get_softc(dev);
1146 	struct ifnet *ifp = &sc_if->arpcom.ac_if;
1147 	int i, error, if_attached = 0;
1148 
1149 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1150 
1151 	sc_if->sk_port = *(int *)device_get_ivars(dev);
1152 	KKASSERT(sc_if->sk_port == SK_PORT_A || sc_if->sk_port == SK_PORT_B);
1153 
1154 	sc_if->sk_softc = sc;
1155 	sc->sk_if[sc_if->sk_port] = sc_if;
1156 
1157 	kfree(device_get_ivars(dev), M_DEVBUF);
1158 	device_set_ivars(dev, NULL);
1159 
1160 	if (sc_if->sk_port == SK_PORT_A)
1161 		sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1162 	if (sc_if->sk_port == SK_PORT_B)
1163 		sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1164 
1165 	DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port));
1166 
1167 	/*
1168 	 * Get station address for this interface. Note that
1169 	 * dual port cards actually come with three station
1170 	 * addresses: one for each port, plus an extra. The
1171 	 * extra one is used by the SysKonnect driver software
1172 	 * as a 'virtual' station address for when both ports
1173 	 * are operating in failover mode. Currently we don't
1174 	 * use this extra address.
1175 	 */
1176 	for (i = 0; i < ETHER_ADDR_LEN; i++) {
1177 		/* XXX */
1178 		sc_if->arpcom.ac_enaddr[i] =
1179 		    sk_win_read_1(sc, SK_MAC0_0 + (sc_if->sk_port * 8) + i);
1180 	}
1181 
1182 	/*
1183 	 * Set up RAM buffer addresses. The NIC will have a certain
1184 	 * amount of SRAM on it, somewhere between 512K and 2MB. We
1185 	 * need to divide this up a) between the transmitter and
1186  	 * receiver and b) between the two XMACs, if this is a
1187 	 * dual port NIC. Our algorithm is to divide up the memory
1188 	 * evenly so that everyone gets a fair share.
1189 	 */
1190 	if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1191 		uint32_t chunk, val;
1192 
1193 		chunk = sc->sk_ramsize / 2;
1194 		val = sc->sk_rboff / sizeof(uint64_t);
1195 		sc_if->sk_rx_ramstart = val;
1196 		val += (chunk / sizeof(uint64_t));
1197 		sc_if->sk_rx_ramend = val - 1;
1198 		sc_if->sk_tx_ramstart = val;
1199 		val += (chunk / sizeof(uint64_t));
1200 		sc_if->sk_tx_ramend = val - 1;
1201 	} else {
1202 		uint32_t chunk, val;
1203 
1204 		chunk = sc->sk_ramsize / 4;
1205 		val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1206 		    sizeof(uint64_t);
1207 		sc_if->sk_rx_ramstart = val;
1208 		val += (chunk / sizeof(uint64_t));
1209 		sc_if->sk_rx_ramend = val - 1;
1210 		sc_if->sk_tx_ramstart = val;
1211 		val += (chunk / sizeof(uint64_t));
1212 		sc_if->sk_tx_ramend = val - 1;
1213 	}
1214 
1215 	DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n"
1216 		     "           tx_ramstart=%#x tx_ramend=%#x\n",
1217 		     sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend,
1218 		     sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend));
1219 
1220 	/* Read and save PHY type */
1221 	sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1222 
1223 	/* Set PHY address */
1224 	if (SK_IS_GENESIS(sc)) {
1225 		switch (sc_if->sk_phytype) {
1226 		case SK_PHYTYPE_XMAC:
1227 			sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1228 			break;
1229 		case SK_PHYTYPE_BCOM:
1230 			sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1231 			break;
1232 		default:
1233 			device_printf(dev, "unsupported PHY type: %d\n",
1234 			    sc_if->sk_phytype);
1235 			error = ENXIO;
1236 			goto fail;
1237 		}
1238 	}
1239 
1240 	if (SK_IS_YUKON(sc)) {
1241 		if ((sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1242 		    sc->sk_pmd != 'L' && sc->sk_pmd != 'S')) {
1243 			/* not initialized, punt */
1244 			sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1245 			sc->sk_coppertype = 1;
1246 		}
1247 
1248 		sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1249 
1250 		if (!(sc->sk_coppertype))
1251 			sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
1252 	}
1253 
1254 	error = sk_dma_alloc(dev);
1255 	if (error)
1256 		goto fail;
1257 
1258 	ifp->if_softc = sc_if;
1259 	ifp->if_mtu = ETHERMTU;
1260 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1261 	ifp->if_ioctl = sk_ioctl;
1262 	ifp->if_start = sk_start;
1263 	ifp->if_watchdog = sk_watchdog;
1264 	ifp->if_init = sk_init;
1265 	ifp->if_baudrate = 1000000000;
1266 	ifq_set_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1);
1267 	ifq_set_ready(&ifp->if_snd);
1268 
1269 	ifp->if_capabilities = IFCAP_VLAN_MTU;
1270 
1271 	/* Don't use jumbo buffers by default */
1272 	sc_if->sk_use_jumbo = 0;
1273 
1274 	/*
1275 	 * Call MI attach routines.
1276 	 *
1277 	 * NOTE:
1278 	 * This must be done before following sk_init_xxx(), in which
1279 	 * if_multiaddrs will be used.
1280 	 */
1281 	ether_ifattach(ifp, sc_if->arpcom.ac_enaddr, &sc->sk_serializer);
1282 	if_attached = 1;
1283 
1284 	/*
1285 	 * Do miibus setup.
1286 	 */
1287 	switch (sc->sk_type) {
1288 	case SK_GENESIS:
1289 		sk_init_xmac(sc_if);
1290 		break;
1291 	case SK_YUKON:
1292 	case SK_YUKON_LITE:
1293 	case SK_YUKON_LP:
1294 		sk_init_yukon(sc_if);
1295 		break;
1296 	default:
1297 		device_printf(dev, "unknown device type %d\n", sc->sk_type);
1298 		error = ENXIO;
1299 		goto fail;
1300 	}
1301 
1302  	DPRINTFN(2, ("sk_attach: 1\n"));
1303 
1304 	error = mii_phy_probe(dev, &sc_if->sk_miibus,
1305 			      sk_ifmedia_upd, sk_ifmedia_sts);
1306 	if (error) {
1307 		device_printf(dev, "no PHY found!\n");
1308 		goto fail;
1309 	}
1310 
1311 	callout_init(&sc_if->sk_tick_timer);
1312 
1313 	DPRINTFN(2, ("sk_attach: end\n"));
1314 	return 0;
1315 fail:
1316 	if (if_attached)
1317 		ether_ifdetach(ifp);
1318 	sk_detach(dev);
1319 	sc->sk_if[sc_if->sk_port] = NULL;
1320 	return error;
1321 }
1322 
1323 /*
1324  * Attach the interface. Allocate softc structures, do ifmedia
1325  * setup and ethernet/BPF attach.
1326  */
1327 static int
skc_attach(device_t dev)1328 skc_attach(device_t dev)
1329 {
1330 	struct sk_softc *sc = device_get_softc(dev);
1331 	uint8_t skrs;
1332 	int *port;
1333 	int error, cpuid;
1334 
1335 	DPRINTFN(2, ("begin skc_attach\n"));
1336 
1337 	sc->sk_dev = dev;
1338 	lwkt_serialize_init(&sc->sk_serializer);
1339 
1340 #ifndef BURN_BRIDGES
1341 	/*
1342 	 * Handle power management nonsense.
1343 	 */
1344 	if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1345 		uint32_t iobase, membase, irq;
1346 
1347 		/* Save important PCI config data. */
1348 		iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
1349 		membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
1350 		irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
1351 
1352 		/* Reset the power state. */
1353 		device_printf(dev, "chip is in D%d power mode "
1354 			      "-- setting to D0\n", pci_get_powerstate(dev));
1355 
1356 		pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1357 
1358 		/* Restore PCI config data. */
1359 		pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
1360 		pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
1361 		pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
1362 	}
1363 #endif	/* BURN_BRIDGES */
1364 
1365 	/*
1366 	 * Map control/status registers.
1367 	 */
1368 	pci_enable_busmaster(dev);
1369 
1370 	sc->sk_res_rid = SK_PCI_LOMEM;
1371 	sc->sk_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1372 					    &sc->sk_res_rid, RF_ACTIVE);
1373 	if (sc->sk_res == NULL) {
1374 		device_printf(dev, "couldn't map memory\n");
1375 		error = ENXIO;
1376 		goto fail;
1377 	}
1378 	sc->sk_btag = rman_get_bustag(sc->sk_res);
1379 	sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
1380 
1381 	sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1382 	sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4);
1383 
1384 	/* Bail out here if chip is not recognized */
1385 	if (!SK_IS_GENESIS(sc) && !SK_IS_YUKON(sc)) {
1386 		device_printf(dev, "unknown chip type: %d\n", sc->sk_type);
1387 		error = ENXIO;
1388 		goto fail;
1389 	}
1390 
1391 	DPRINTFN(2, ("skc_attach: allocate interrupt\n"));
1392 
1393 	/* Allocate interrupt */
1394 	sc->sk_irq_rid = 0;
1395 	sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sk_irq_rid,
1396 					    RF_SHAREABLE | RF_ACTIVE);
1397 	if (sc->sk_irq == NULL) {
1398 		device_printf(dev, "couldn't map interrupt\n");
1399 		error = ENXIO;
1400 		goto fail;
1401 	}
1402 
1403 	switch (sc->sk_type) {
1404 	case SK_GENESIS:
1405 		sc->sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS;
1406 		break;
1407 	default:
1408 		sc->sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
1409 		break;
1410 	}
1411 	sc->sk_imtime = skc_imtime;
1412 
1413 	/* Reset the adapter. */
1414 	sk_reset(sc);
1415 
1416 	skrs = sk_win_read_1(sc, SK_EPROM0);
1417 	if (SK_IS_GENESIS(sc)) {
1418 		/* Read and save RAM size and RAMbuffer offset */
1419 		switch(skrs) {
1420 		case SK_RAMSIZE_512K_64:
1421 			sc->sk_ramsize = 0x80000;
1422 			sc->sk_rboff = SK_RBOFF_0;
1423 			break;
1424 		case SK_RAMSIZE_1024K_64:
1425 			sc->sk_ramsize = 0x100000;
1426 			sc->sk_rboff = SK_RBOFF_80000;
1427 			break;
1428 		case SK_RAMSIZE_1024K_128:
1429 			sc->sk_ramsize = 0x100000;
1430 			sc->sk_rboff = SK_RBOFF_0;
1431 			break;
1432 		case SK_RAMSIZE_2048K_128:
1433 			sc->sk_ramsize = 0x200000;
1434 			sc->sk_rboff = SK_RBOFF_0;
1435 			break;
1436 		default:
1437 			device_printf(dev, "unknown ram size: %d\n", skrs);
1438 			error = ENXIO;
1439 			goto fail;
1440 		}
1441 	} else {
1442 		if (skrs == 0x00)
1443 			sc->sk_ramsize = 0x20000;
1444 		else
1445 			sc->sk_ramsize = skrs * (1<<12);
1446 		sc->sk_rboff = SK_RBOFF_0;
1447 	}
1448 
1449 	DPRINTFN(2, ("skc_attach: ramsize=%d (%dk), rboff=%d\n",
1450 		     sc->sk_ramsize, sc->sk_ramsize / 1024,
1451 		     sc->sk_rboff));
1452 
1453 	/* Read and save physical media type */
1454 	sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1455 
1456 	if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1457 		sc->sk_coppertype = 1;
1458 	else
1459 		sc->sk_coppertype = 0;
1460 
1461 	/* Yukon Lite Rev A0 needs special test, from sk98lin driver */
1462 	if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1463 		uint32_t flashaddr;
1464 		uint8_t testbyte;
1465 
1466 		flashaddr = sk_win_read_4(sc, SK_EP_ADDR);
1467 
1468 		/* Test Flash-Address Register */
1469 		sk_win_write_1(sc, SK_EP_ADDR+3, 0xff);
1470 		testbyte = sk_win_read_1(sc, SK_EP_ADDR+3);
1471 
1472 		if (testbyte != 0) {
1473 			/* This is a Yukon Lite Rev A0 */
1474 			sc->sk_type = SK_YUKON_LITE;
1475 			sc->sk_rev = SK_YUKON_LITE_REV_A0;
1476 			/* Restore Flash-Address Register */
1477 			sk_win_write_4(sc, SK_EP_ADDR, flashaddr);
1478 		}
1479 	}
1480 
1481 	/*
1482 	 * Create sysctl nodes.
1483 	 */
1484 	SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1485 			SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1486 			OID_AUTO, "imtime", CTLTYPE_INT | CTLFLAG_RW,
1487 			sc, 0, skc_sysctl_imtime, "I",
1488 			"Interrupt moderation time (usec).");
1489 
1490 	sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
1491 	port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK);
1492 	*port = SK_PORT_A;
1493 	device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1494 
1495 	if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1496 		sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
1497 		port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK);
1498 		*port = SK_PORT_B;
1499 		device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1500 	}
1501 
1502 	/* Turn on the 'driver is loaded' LED. */
1503 	CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1504 
1505 	bus_generic_attach(dev);
1506 
1507 	cpuid = rman_get_cpuid(sc->sk_irq);
1508 	if (sc->sk_if[0] != NULL)
1509 		ifq_set_cpuid(&sc->sk_if[0]->arpcom.ac_if.if_snd, cpuid);
1510 	if (sc->sk_if[1] != NULL)
1511 		ifq_set_cpuid(&sc->sk_if[1]->arpcom.ac_if.if_snd, cpuid);
1512 
1513 	error = bus_setup_intr(dev, sc->sk_irq, INTR_MPSAFE, sk_intr, sc,
1514 			       &sc->sk_intrhand, &sc->sk_serializer);
1515 	if (error) {
1516 		device_printf(dev, "couldn't set up irq\n");
1517 		goto fail;
1518 	}
1519 
1520 	return 0;
1521 fail:
1522 	skc_detach(dev);
1523 	return error;
1524 }
1525 
1526 static int
sk_detach(device_t dev)1527 sk_detach(device_t dev)
1528 {
1529 	struct sk_if_softc *sc_if = device_get_softc(dev);
1530 
1531 	if (device_is_attached(dev)) {
1532 		struct sk_softc *sc = sc_if->sk_softc;
1533 		struct ifnet *ifp = &sc_if->arpcom.ac_if;
1534 
1535 		lwkt_serialize_enter(ifp->if_serializer);
1536 
1537 		if (sc->sk_intrhand != NULL) {
1538 			if (sc->sk_if[SK_PORT_A] != NULL)
1539 				sk_stop(sc->sk_if[SK_PORT_A]);
1540 			if (sc->sk_if[SK_PORT_B] != NULL)
1541 				sk_stop(sc->sk_if[SK_PORT_B]);
1542 
1543 			bus_teardown_intr(sc->sk_dev, sc->sk_irq,
1544 					  sc->sk_intrhand);
1545 			sc->sk_intrhand = NULL;
1546 		}
1547 
1548 		lwkt_serialize_exit(ifp->if_serializer);
1549 
1550 		ether_ifdetach(ifp);
1551 	}
1552 
1553 	if (sc_if->sk_miibus != NULL)
1554 		device_delete_child(dev, sc_if->sk_miibus);
1555 
1556 	sk_dma_free(dev);
1557 	return 0;
1558 }
1559 
1560 static int
skc_detach(device_t dev)1561 skc_detach(device_t dev)
1562 {
1563 	struct sk_softc *sc = device_get_softc(dev);
1564 	int *port;
1565 
1566 #ifdef INVARIANTS
1567 	if (device_is_attached(dev)) {
1568 		KASSERT(sc->sk_intrhand == NULL,
1569 			("intr has not been torn down yet"));
1570 	}
1571 #endif
1572 
1573 	if (sc->sk_devs[SK_PORT_A] != NULL) {
1574 		port = device_get_ivars(sc->sk_devs[SK_PORT_A]);
1575 		if (port != NULL) {
1576 			kfree(port, M_DEVBUF);
1577 			device_set_ivars(sc->sk_devs[SK_PORT_A], NULL);
1578 		}
1579 		device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
1580 	}
1581 	if (sc->sk_devs[SK_PORT_B] != NULL) {
1582 		port = device_get_ivars(sc->sk_devs[SK_PORT_B]);
1583 		if (port != NULL) {
1584 			kfree(port, M_DEVBUF);
1585 			device_set_ivars(sc->sk_devs[SK_PORT_B], NULL);
1586 		}
1587 		device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
1588 	}
1589 
1590 	if (sc->sk_irq != NULL) {
1591 		bus_release_resource(dev, SYS_RES_IRQ, sc->sk_irq_rid,
1592 				     sc->sk_irq);
1593 	}
1594 	if (sc->sk_res != NULL) {
1595 		bus_release_resource(dev, SYS_RES_MEMORY, sc->sk_res_rid,
1596 				     sc->sk_res);
1597 	}
1598 
1599 	return 0;
1600 }
1601 
1602 static int
sk_encap(struct sk_if_softc * sc_if,struct mbuf ** m_head0,uint32_t * txidx)1603 sk_encap(struct sk_if_softc *sc_if, struct mbuf **m_head0, uint32_t *txidx)
1604 {
1605 	struct sk_chain_data *cd = &sc_if->sk_cdata;
1606 	struct sk_ring_data *rd = &sc_if->sk_rdata;
1607 	struct sk_tx_desc *f = NULL;
1608 	uint32_t frag, cur, sk_ctl;
1609 	bus_dma_segment_t segs[SK_NTXSEG];
1610 	bus_dmamap_t map;
1611 	int i, error, maxsegs, nsegs;
1612 
1613 	DPRINTFN(2, ("sk_encap\n"));
1614 
1615 	maxsegs = SK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - SK_NDESC_RESERVE;
1616 	KASSERT(maxsegs >= SK_NDESC_SPARE, ("not enough spare TX desc"));
1617 	if (maxsegs > SK_NTXSEG)
1618 		maxsegs = SK_NTXSEG;
1619 
1620 	cur = frag = *txidx;
1621 
1622 #ifdef SK_DEBUG
1623 	if (skdebug >= 2)
1624 		sk_dump_mbuf(*m_head0);
1625 #endif
1626 
1627 	map = cd->sk_tx_dmap[*txidx];
1628 
1629 	error = bus_dmamap_load_mbuf_defrag(cd->sk_tx_dtag, map, m_head0,
1630 			segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1631 	if (error) {
1632 		m_freem(*m_head0);
1633 		*m_head0 = NULL;
1634 		return error;
1635 	}
1636 
1637 	DPRINTFN(2, ("sk_encap: nsegs=%d\n", nsegs));
1638 
1639 	/* Sync the DMA map. */
1640 	bus_dmamap_sync(cd->sk_tx_dtag, map, BUS_DMASYNC_PREWRITE);
1641 
1642 	for (i = 0; i < nsegs; i++) {
1643 		f = &rd->sk_tx_ring[frag];
1644 		f->sk_data_lo = htole32(SK_ADDR_LO(segs[i].ds_addr));
1645 		f->sk_data_hi = htole32(SK_ADDR_HI(segs[i].ds_addr));
1646 		sk_ctl = segs[i].ds_len | SK_OPCODE_DEFAULT;
1647 		if (i == 0)
1648 			sk_ctl |= SK_TXCTL_FIRSTFRAG;
1649 		else
1650 			sk_ctl |= SK_TXCTL_OWN;
1651 		f->sk_ctl = htole32(sk_ctl);
1652 		cur = frag;
1653 		SK_INC(frag, SK_TX_RING_CNT);
1654 	}
1655 
1656 	cd->sk_tx_mbuf[cur] = *m_head0;
1657 	/* Switch DMA map */
1658 	cd->sk_tx_dmap[*txidx] = cd->sk_tx_dmap[cur];
1659 	cd->sk_tx_dmap[cur] = map;
1660 
1661 	rd->sk_tx_ring[cur].sk_ctl |=
1662 		htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR);
1663 	rd->sk_tx_ring[*txidx].sk_ctl |= htole32(SK_TXCTL_OWN);
1664 
1665 	sc_if->sk_cdata.sk_tx_cnt += nsegs;
1666 
1667 #ifdef SK_DEBUG
1668 	if (skdebug >= 2) {
1669 		struct sk_tx_desc *desc;
1670 		uint32_t idx;
1671 
1672 		for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) {
1673 			desc = &sc_if->sk_rdata->sk_tx_ring[idx];
1674 			sk_dump_txdesc(desc, idx);
1675 		}
1676 	}
1677 #endif
1678 
1679 	*txidx = frag;
1680 
1681 	DPRINTFN(2, ("sk_encap: completed successfully\n"));
1682 
1683 	return (0);
1684 }
1685 
1686 static void
sk_start(struct ifnet * ifp,struct ifaltq_subque * ifsq)1687 sk_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1688 {
1689 	struct sk_if_softc *sc_if = ifp->if_softc;
1690 	struct sk_softc *sc = sc_if->sk_softc;
1691 	uint32_t idx = sc_if->sk_cdata.sk_tx_prod;
1692 	int trans = 0;
1693 
1694 	ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1695 	DPRINTFN(2, ("sk_start\n"));
1696 
1697 	if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1698 		return;
1699 
1700 	while (sc_if->sk_cdata.sk_tx_mbuf[idx] == NULL) {
1701 		struct mbuf *m_head;
1702 
1703 		if (SK_IS_OACTIVE(sc_if)) {
1704 			ifq_set_oactive(&ifp->if_snd);
1705 			break;
1706 		}
1707 
1708 		m_head = ifq_dequeue(&ifp->if_snd);
1709 		if (m_head == NULL)
1710 			break;
1711 
1712 		/*
1713 		 * Pack the data into the transmit ring. If we
1714 		 * don't have room, set the OACTIVE flag and wait
1715 		 * for the NIC to drain the ring.
1716 		 */
1717 		if (sk_encap(sc_if, &m_head, &idx)) {
1718 			if (sc_if->sk_cdata.sk_tx_cnt == 0) {
1719 				continue;
1720 			} else {
1721 				ifq_set_oactive(&ifp->if_snd);
1722 				break;
1723 			}
1724 		}
1725 
1726 		trans = 1;
1727 		BPF_MTAP(ifp, m_head);
1728 	}
1729 	if (!trans)
1730 		return;
1731 
1732 	/* Transmit */
1733 	if (idx != sc_if->sk_cdata.sk_tx_prod) {
1734 		sc_if->sk_cdata.sk_tx_prod = idx;
1735 		CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1736 
1737 		/* Set a timeout in case the chip goes out to lunch. */
1738 		ifp->if_timer = 5;
1739 	}
1740 }
1741 
1742 static void
sk_watchdog(struct ifnet * ifp)1743 sk_watchdog(struct ifnet *ifp)
1744 {
1745 	struct sk_if_softc *sc_if = ifp->if_softc;
1746 
1747 	ASSERT_SERIALIZED(ifp->if_serializer);
1748 	/*
1749 	 * Reclaim first as there is a possibility of losing Tx completion
1750 	 * interrupts.
1751 	 */
1752 	sk_txeof(sc_if);
1753 	if (sc_if->sk_cdata.sk_tx_cnt != 0) {
1754 		if_printf(&sc_if->arpcom.ac_if, "watchdog timeout\n");
1755 		IFNET_STAT_INC(ifp, oerrors, 1);
1756 		ifp->if_flags &= ~IFF_RUNNING;
1757 		sk_init(sc_if);
1758 	}
1759 }
1760 
1761 static void
skc_shutdown(device_t dev)1762 skc_shutdown(device_t dev)
1763 {
1764 	struct sk_softc *sc = device_get_softc(dev);
1765 
1766 	DPRINTFN(2, ("sk_shutdown\n"));
1767 
1768 	lwkt_serialize_enter(&sc->sk_serializer);
1769 
1770 	/* Turn off the 'driver is loaded' LED. */
1771 	CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1772 
1773 	/*
1774 	 * Reset the GEnesis controller. Doing this should also
1775 	 * assert the resets on the attached XMAC(s).
1776 	 */
1777 	sk_reset(sc);
1778 
1779 	lwkt_serialize_exit(&sc->sk_serializer);
1780 }
1781 
1782 static __inline int
sk_rxvalid(struct sk_softc * sc,uint32_t stat,uint32_t len)1783 sk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len)
1784 {
1785 	if (sc->sk_type == SK_GENESIS) {
1786 		if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
1787 		    XM_RXSTAT_BYTES(stat) != len)
1788 			return (0);
1789 	} else {
1790 		if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
1791 		    YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
1792 		    YU_RXSTAT_JABBER)) != 0 ||
1793 		    (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
1794 		    YU_RXSTAT_BYTES(stat) != len)
1795 			return (0);
1796 	}
1797 
1798 	return (1);
1799 }
1800 
1801 static void
sk_rxeof(struct sk_if_softc * sc_if)1802 sk_rxeof(struct sk_if_softc *sc_if)
1803 {
1804 	struct sk_softc *sc = sc_if->sk_softc;
1805 	struct ifnet *ifp = &sc_if->arpcom.ac_if;
1806 	struct sk_chain_data *cd = &sc_if->sk_cdata;
1807 	struct sk_ring_data *rd = &sc_if->sk_rdata;
1808 	int i, max_frmlen;
1809 
1810 	DPRINTFN(2, ("sk_rxeof\n"));
1811 
1812 	i = cd->sk_rx_prod;
1813 
1814 	if (sc_if->sk_use_jumbo)
1815 		max_frmlen = SK_JUMBO_FRAMELEN;
1816 	else
1817 		max_frmlen = ETHER_MAX_LEN;
1818 
1819 	for (;;) {
1820 		struct sk_rx_desc *cur_desc;
1821 		uint32_t rxstat, sk_ctl;
1822 #ifdef SK_RXCSUM
1823 		uint16_t csum1, csum2;
1824 #endif
1825 		int cur, total_len;
1826 		struct mbuf *m;
1827 
1828 		cur = i;
1829 		cur_desc = &rd->sk_rx_ring[cur];
1830 
1831 		sk_ctl = le32toh(cur_desc->sk_ctl);
1832 		if (sk_ctl & SK_RXCTL_OWN) {
1833 			/* Invalidate the descriptor -- it's not ready yet */
1834 			cd->sk_rx_prod = cur;
1835 			break;
1836 		}
1837 
1838 		rxstat = le32toh(cur_desc->sk_xmac_rxstat);
1839 		total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl));
1840 
1841 #ifdef SK_RXCSUM
1842 		csum1 = le16toh(cur_desc->sk_csum1);
1843 		csum2 = le16toh(cur_desc->sk_csum2);
1844 #endif
1845 
1846 		m = cd->sk_rx_mbuf[cur];
1847 
1848 		/*
1849 		 * Bump 'i' here, so we can keep going, even if the current
1850 		 * RX descriptor reaping fails later.  'i' shoult NOT be used
1851 		 * in the following processing any more.
1852 		 */
1853 		SK_INC(i, SK_RX_RING_CNT);
1854 
1855 		if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
1856 		    SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
1857 		    SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
1858 		    total_len < SK_MIN_FRAMELEN || total_len > max_frmlen ||
1859 		    sk_rxvalid(sc, rxstat, total_len) == 0) {
1860 			IFNET_STAT_INC(ifp, ierrors, 1);
1861 			cur_desc->sk_ctl = htole32(m->m_pkthdr.len | SK_RXSTAT);
1862 			continue;
1863 		}
1864 
1865 		/*
1866 		 * Try to allocate a new RX buffer. If that fails,
1867 		 * copy the packet to mbufs and put the RX buffer
1868 		 * back in the ring so it can be re-used. If
1869 		 * allocating mbufs fails, then we have to drop
1870 		 * the packet.
1871 		 */
1872 		if (sk_newbuf(sc_if, cur, 0)) {
1873 			IFNET_STAT_INC(ifp, ierrors, 1);
1874 			cur_desc->sk_ctl = htole32(m->m_pkthdr.len | SK_RXSTAT);
1875 			continue;
1876 		} else {
1877 			m->m_pkthdr.rcvif = ifp;
1878 			m->m_pkthdr.len = m->m_len = total_len;
1879 		}
1880 
1881 #ifdef SK_RXCSUM
1882 		sk_rxcsum(ifp, m, csum1, csum2);
1883 #endif
1884 
1885 		IFNET_STAT_INC(ifp, ipackets, 1);
1886 		ifp->if_input(ifp, m, NULL, -1);
1887 	}
1888 }
1889 
1890 #ifdef SK_RXCSUM
1891 static void
sk_rxcsum(struct ifnet * ifp,struct mbuf * m,const uint16_t csum1,const uint16_t csum2)1892 sk_rxcsum(struct ifnet *ifp, struct mbuf *m,
1893 	  const uint16_t csum1, const uint16_t csum2)
1894 {
1895 	struct ether_header *eh;
1896 	struct ip *ip;
1897 	uint8_t *pp;
1898 	int hlen, len, plen;
1899 	uint16_t iph_csum, ipo_csum, ipd_csum, csum;
1900 
1901 	pp = mtod(m, uint8_t *);
1902 	plen = m->m_pkthdr.len;
1903 	if (plen < sizeof(*eh))
1904 		return;
1905 	eh = (struct ether_header *)pp;
1906 	iph_csum = in_addword(csum1, (~csum2 & 0xffff));
1907 
1908 	if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1909 		uint16_t *xp = (uint16_t *)pp;
1910 
1911 		xp = (uint16_t *)pp;
1912 		if (xp[1] != htons(ETHERTYPE_IP))
1913 			return;
1914 		iph_csum = in_addword(iph_csum, (~xp[0] & 0xffff));
1915 		iph_csum = in_addword(iph_csum, (~xp[1] & 0xffff));
1916 		xp = (uint16_t *)(pp + sizeof(struct ip));
1917 		iph_csum = in_addword(iph_csum, xp[0]);
1918 		iph_csum = in_addword(iph_csum, xp[1]);
1919 		pp += EVL_ENCAPLEN;
1920 	} else if (eh->ether_type != htons(ETHERTYPE_IP)) {
1921 		return;
1922 	}
1923 
1924 	pp += sizeof(*eh);
1925 	plen -= sizeof(*eh);
1926 
1927 	ip = (struct ip *)pp;
1928 
1929 	if (ip->ip_v != IPVERSION)
1930 		return;
1931 
1932 	hlen = ip->ip_hl << 2;
1933 	if (hlen < sizeof(struct ip))
1934 		return;
1935 	if (hlen > ntohs(ip->ip_len))
1936 		return;
1937 
1938 	/* Don't deal with truncated or padded packets. */
1939 	if (plen != ntohs(ip->ip_len))
1940 		return;
1941 
1942 	len = hlen - sizeof(struct ip);
1943 	if (len > 0) {
1944 		uint16_t *p;
1945 
1946 		p = (uint16_t *)(ip + 1);
1947 		ipo_csum = 0;
1948 		for (ipo_csum = 0; len > 0; len -= sizeof(*p), p++)
1949 			ipo_csum = in_addword(ipo_csum, *p);
1950 		iph_csum = in_addword(iph_csum, ipo_csum);
1951 		ipd_csum = in_addword(csum2, (~ipo_csum & 0xffff));
1952 	} else {
1953 		ipd_csum = csum2;
1954 	}
1955 
1956 	if (iph_csum != 0xffff)
1957 		return;
1958 	m->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID;
1959 
1960 	if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
1961 		return;                 /* ip frag, we're done for now */
1962 
1963 	pp += hlen;
1964 
1965 	/* Only know checksum protocol for udp/tcp */
1966 	if (ip->ip_p == IPPROTO_UDP) {
1967 		struct udphdr *uh = (struct udphdr *)pp;
1968 
1969 		if (uh->uh_sum == 0)    /* udp with no checksum */
1970 			return;
1971 	} else if (ip->ip_p != IPPROTO_TCP) {
1972 		return;
1973 	}
1974 
1975 	csum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1976 	    htonl(ntohs(ip->ip_len) - hlen + ip->ip_p) + ipd_csum);
1977 	if (csum == 0xffff) {
1978 		m->m_pkthdr.csum_data = csum;
1979 		m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1980 	}
1981 }
1982 #endif
1983 
1984 static void
sk_txeof(struct sk_if_softc * sc_if)1985 sk_txeof(struct sk_if_softc *sc_if)
1986 {
1987 	struct sk_chain_data *cd = &sc_if->sk_cdata;
1988 	struct ifnet *ifp = &sc_if->arpcom.ac_if;
1989 	uint32_t idx;
1990 
1991 	DPRINTFN(2, ("sk_txeof\n"));
1992 
1993 	/*
1994 	 * Go through our tx ring and free mbufs for those
1995 	 * frames that have been sent.
1996 	 */
1997 	idx = cd->sk_tx_cons;
1998 	while (idx != cd->sk_tx_prod) {
1999 		struct sk_tx_desc *cur_tx;
2000 		uint32_t sk_ctl;
2001 
2002 		cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx];
2003 		sk_ctl = le32toh(cur_tx->sk_ctl);
2004 #ifdef SK_DEBUG
2005 		if (skdebug >= 2)
2006 			sk_dump_txdesc(cur_tx, idx);
2007 #endif
2008 		if (sk_ctl & SK_TXCTL_OWN)
2009 			break;
2010 		if (sk_ctl & SK_TXCTL_LASTFRAG)
2011 			IFNET_STAT_INC(ifp, opackets, 1);
2012 		if (cd->sk_tx_mbuf[idx] != NULL) {
2013 			bus_dmamap_unload(cd->sk_tx_dtag, cd->sk_tx_dmap[idx]);
2014 			m_freem(cd->sk_tx_mbuf[idx]);
2015 			cd->sk_tx_mbuf[idx] = NULL;
2016 		}
2017 		sc_if->sk_cdata.sk_tx_cnt--;
2018 		SK_INC(idx, SK_TX_RING_CNT);
2019 	}
2020 
2021 	if (!SK_IS_OACTIVE(sc_if))
2022 		ifq_clr_oactive(&ifp->if_snd);
2023 
2024 	if (sc_if->sk_cdata.sk_tx_cnt == 0)
2025 		ifp->if_timer = 0;
2026 
2027 	sc_if->sk_cdata.sk_tx_cons = idx;
2028 }
2029 
2030 static void
sk_tick(void * xsc_if)2031 sk_tick(void *xsc_if)
2032 {
2033 	struct sk_if_softc *sc_if = xsc_if;
2034 	struct ifnet *ifp = &sc_if->arpcom.ac_if;
2035 	struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2036 	int i;
2037 
2038 	DPRINTFN(2, ("sk_tick\n"));
2039 
2040 	lwkt_serialize_enter(ifp->if_serializer);
2041 
2042 	if ((ifp->if_flags & IFF_UP) == 0) {
2043 		lwkt_serialize_exit(ifp->if_serializer);
2044 		return;
2045 	}
2046 
2047 	if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2048 		sk_intr_bcom(sc_if);
2049 		lwkt_serialize_exit(ifp->if_serializer);
2050 		return;
2051 	}
2052 
2053 	/*
2054 	 * According to SysKonnect, the correct way to verify that
2055 	 * the link has come back up is to poll bit 0 of the GPIO
2056 	 * register three times. This pin has the signal from the
2057 	 * link sync pin connected to it; if we read the same link
2058 	 * state 3 times in a row, we know the link is up.
2059 	 */
2060 	for (i = 0; i < 3; i++) {
2061 		if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2062 			break;
2063 	}
2064 
2065 	if (i != 3) {
2066 		callout_reset(&sc_if->sk_tick_timer, hz, sk_tick, sc_if);
2067 		lwkt_serialize_exit(ifp->if_serializer);
2068 		return;
2069 	}
2070 
2071 	/* Turn the GP0 interrupt back on. */
2072 	SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2073 	SK_XM_READ_2(sc_if, XM_ISR);
2074 	mii_tick(mii);
2075 	callout_stop(&sc_if->sk_tick_timer);
2076 	lwkt_serialize_exit(ifp->if_serializer);
2077 }
2078 
2079 static void
sk_yukon_tick(void * xsc_if)2080 sk_yukon_tick(void *xsc_if)
2081 {
2082 	struct sk_if_softc *sc_if = xsc_if;
2083 	struct ifnet *ifp = &sc_if->arpcom.ac_if;
2084 	struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2085 
2086 	lwkt_serialize_enter(ifp->if_serializer);
2087 	mii_tick(mii);
2088 	callout_reset(&sc_if->sk_tick_timer, hz, sk_yukon_tick, sc_if);
2089 	lwkt_serialize_exit(ifp->if_serializer);
2090 }
2091 
2092 static void
sk_intr_bcom(struct sk_if_softc * sc_if)2093 sk_intr_bcom(struct sk_if_softc *sc_if)
2094 {
2095 	struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2096 	struct ifnet *ifp = &sc_if->arpcom.ac_if;
2097 	int status;
2098 
2099 	DPRINTFN(2, ("sk_intr_bcom\n"));
2100 
2101 	SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2102 
2103 	/*
2104 	 * Read the PHY interrupt register to make sure
2105 	 * we clear any pending interrupts.
2106 	 */
2107 	status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
2108 
2109 	if ((ifp->if_flags & IFF_RUNNING) == 0) {
2110 		sk_init_xmac(sc_if);
2111 		return;
2112 	}
2113 
2114 	if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
2115 		int lstat;
2116 
2117 		lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
2118 		    BRGPHY_MII_AUXSTS);
2119 
2120 		if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
2121 			mii_mediachg(mii);
2122 			/* Turn off the link LED. */
2123 			SK_IF_WRITE_1(sc_if, 0,
2124 			    SK_LINKLED1_CTL, SK_LINKLED_OFF);
2125 			sc_if->sk_link = 0;
2126 		} else if (status & BRGPHY_ISR_LNK_CHG) {
2127 			sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2128 			    BRGPHY_MII_IMR, 0xFF00);
2129 			mii_tick(mii);
2130 			sc_if->sk_link = 1;
2131 			/* Turn on the link LED. */
2132 			SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2133 			    SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
2134 			    SK_LINKLED_BLINK_OFF);
2135 		} else {
2136 			mii_tick(mii);
2137 			callout_reset(&sc_if->sk_tick_timer, hz,
2138 				      sk_tick, sc_if);
2139 		}
2140 	}
2141 
2142 	SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2143 }
2144 
2145 static void
sk_intr_xmac(struct sk_if_softc * sc_if)2146 sk_intr_xmac(struct sk_if_softc *sc_if)
2147 {
2148 	uint16_t status;
2149 
2150 	status = SK_XM_READ_2(sc_if, XM_ISR);
2151 	DPRINTFN(2, ("sk_intr_xmac\n"));
2152 
2153 	if (sc_if->sk_phytype == SK_PHYTYPE_XMAC &&
2154 	    (status & (XM_ISR_GP0_SET | XM_ISR_AUTONEG_DONE))) {
2155 		if (status & XM_ISR_GP0_SET)
2156 			SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2157 
2158 		callout_reset(&sc_if->sk_tick_timer, hz,
2159 			      sk_tick, sc_if);
2160 	}
2161 
2162 	if (status & XM_IMR_TX_UNDERRUN)
2163 		SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
2164 
2165 	if (status & XM_IMR_RX_OVERRUN)
2166 		SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
2167 }
2168 
2169 static void
sk_intr_yukon(struct sk_if_softc * sc_if)2170 sk_intr_yukon(struct sk_if_softc *sc_if)
2171 {
2172 	uint8_t status;
2173 
2174 	status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
2175 	/* RX overrun */
2176 	if ((status & SK_GMAC_INT_RX_OVER) != 0) {
2177 		SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
2178 		    SK_RFCTL_RX_FIFO_OVER);
2179 	}
2180 	/* TX underrun */
2181 	if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
2182 		SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
2183 		    SK_TFCTL_TX_FIFO_UNDER);
2184 	}
2185 
2186 	DPRINTFN(2, ("sk_intr_yukon status=%#x\n", status));
2187 }
2188 
2189 static void
sk_intr(void * xsc)2190 sk_intr(void *xsc)
2191 {
2192 	struct sk_softc *sc = xsc;
2193 	struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A];
2194 	struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B];
2195 	struct ifnet *ifp0 = NULL, *ifp1 = NULL;
2196 	uint32_t status;
2197 
2198 	ASSERT_SERIALIZED(&sc->sk_serializer);
2199 
2200 	status = CSR_READ_4(sc, SK_ISSR);
2201 	if (status == 0 || status == 0xffffffff)
2202 		return;
2203 
2204 	if (sc_if0 != NULL)
2205 		ifp0 = &sc_if0->arpcom.ac_if;
2206 	if (sc_if1 != NULL)
2207 		ifp1 = &sc_if1->arpcom.ac_if;
2208 
2209 	for (; (status &= sc->sk_intrmask) != 0;) {
2210 		/* Handle receive interrupts first. */
2211 		if (sc_if0 && (status & SK_ISR_RX1_EOF)) {
2212 			sk_rxeof(sc_if0);
2213 			CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
2214 			    SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2215 		}
2216 		if (sc_if1 && (status & SK_ISR_RX2_EOF)) {
2217 			sk_rxeof(sc_if1);
2218 			CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
2219 			    SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2220 		}
2221 
2222 		/* Then transmit interrupts. */
2223 		if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) {
2224 			sk_txeof(sc_if0);
2225 			CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
2226 			    SK_TXBMU_CLR_IRQ_EOF);
2227 		}
2228 		if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) {
2229 			sk_txeof(sc_if1);
2230 			CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
2231 			    SK_TXBMU_CLR_IRQ_EOF);
2232 		}
2233 
2234 		/* Then MAC interrupts. */
2235 		if (sc_if0 && (status & SK_ISR_MAC1) &&
2236 		    (ifp0->if_flags & IFF_RUNNING)) {
2237 			if (SK_IS_GENESIS(sc))
2238 				sk_intr_xmac(sc_if0);
2239 			else
2240 				sk_intr_yukon(sc_if0);
2241 		}
2242 
2243 		if (sc_if1 && (status & SK_ISR_MAC2) &&
2244 		    (ifp1->if_flags & IFF_RUNNING)) {
2245 			if (SK_IS_GENESIS(sc))
2246 				sk_intr_xmac(sc_if1);
2247 			else
2248 				sk_intr_yukon(sc_if1);
2249 		}
2250 
2251 		if (status & SK_ISR_EXTERNAL_REG) {
2252 			if (sc_if0 != NULL &&
2253 			    sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
2254 				sk_intr_bcom(sc_if0);
2255 
2256 			if (sc_if1 != NULL &&
2257 			    sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
2258 				sk_intr_bcom(sc_if1);
2259 		}
2260 		status = CSR_READ_4(sc, SK_ISSR);
2261 	}
2262 
2263 	CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2264 
2265 	if (ifp0 != NULL && !ifq_is_empty(&ifp0->if_snd))
2266 		if_devstart(ifp0);
2267 	if (ifp1 != NULL && !ifq_is_empty(&ifp1->if_snd))
2268 		if_devstart(ifp1);
2269 }
2270 
2271 static void
sk_init_xmac(struct sk_if_softc * sc_if)2272 sk_init_xmac(struct sk_if_softc	*sc_if)
2273 {
2274 	struct sk_softc *sc = sc_if->sk_softc;
2275 	struct ifnet *ifp = &sc_if->arpcom.ac_if;
2276 	static const struct sk_bcom_hack bhack[] = {
2277 	{ 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
2278 	{ 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
2279 	{ 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
2280 	{ 0, 0 } };
2281 
2282 	DPRINTFN(2, ("sk_init_xmac\n"));
2283 
2284 	/* Unreset the XMAC. */
2285 	SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
2286 	DELAY(1000);
2287 
2288 	/* Reset the XMAC's internal state. */
2289 	SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2290 
2291 	/* Save the XMAC II revision */
2292 	sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
2293 
2294 	/*
2295 	 * Perform additional initialization for external PHYs,
2296 	 * namely for the 1000baseT cards that use the XMAC's
2297 	 * GMII mode.
2298 	 */
2299 	if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2300 		int i = 0;
2301 		uint32_t val;
2302 
2303 		/* Take PHY out of reset. */
2304 		val = sk_win_read_4(sc, SK_GPIO);
2305 		if (sc_if->sk_port == SK_PORT_A)
2306 			val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
2307 		else
2308 			val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
2309 		sk_win_write_4(sc, SK_GPIO, val);
2310 
2311 		/* Enable GMII mode on the XMAC. */
2312 		SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
2313 
2314 		sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2315 		    BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
2316 		DELAY(10000);
2317 		sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2318 		    BRGPHY_MII_IMR, 0xFFF0);
2319 
2320 		/*
2321 		 * Early versions of the BCM5400 apparently have
2322 		 * a bug that requires them to have their reserved
2323 		 * registers initialized to some magic values. I don't
2324 		 * know what the numbers do, I'm just the messenger.
2325 		 */
2326 		if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
2327 		    == 0x6041) {
2328 			while(bhack[i].reg) {
2329 				sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2330 				    bhack[i].reg, bhack[i].val);
2331 				i++;
2332 			}
2333 		}
2334 	}
2335 
2336 	/* Set station address */
2337 	SK_XM_WRITE_2(sc_if, XM_PAR0,
2338 	    *(uint16_t *)(&sc_if->arpcom.ac_enaddr[0]));
2339 	SK_XM_WRITE_2(sc_if, XM_PAR1,
2340 	    *(uint16_t *)(&sc_if->arpcom.ac_enaddr[2]));
2341 	SK_XM_WRITE_2(sc_if, XM_PAR2,
2342 	    *(uint16_t *)(&sc_if->arpcom.ac_enaddr[4]));
2343 	SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
2344 
2345 	if (ifp->if_flags & IFF_BROADCAST)
2346 		SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2347 	else
2348 		SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2349 
2350 	/* We don't need the FCS appended to the packet. */
2351 	SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
2352 
2353 	/* We want short frames padded to 60 bytes. */
2354 	SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
2355 
2356 	/*
2357 	 * Enable the reception of all error frames. This is
2358 	 * a necessary evil due to the design of the XMAC. The
2359 	 * XMAC's receive FIFO is only 8K in size, however jumbo
2360 	 * frames can be up to 9000 bytes in length. When bad
2361 	 * frame filtering is enabled, the XMAC's RX FIFO operates
2362 	 * in 'store and forward' mode. For this to work, the
2363 	 * entire frame has to fit into the FIFO, but that means
2364 	 * that jumbo frames larger than 8192 bytes will be
2365 	 * truncated. Disabling all bad frame filtering causes
2366 	 * the RX FIFO to operate in streaming mode, in which
2367 	 * case the XMAC will start transfering frames out of the
2368 	 * RX FIFO as soon as the FIFO threshold is reached.
2369 	 */
2370 	if (sc_if->sk_use_jumbo) {
2371 		SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
2372 		    XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
2373 		    XM_MODE_RX_INRANGELEN);
2374 	}
2375 
2376 	SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2377 
2378 	/*
2379 	 * Bump up the transmit threshold. This helps hold off transmit
2380 	 * underruns when we're blasting traffic from both ports at once.
2381 	 */
2382 	SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2383 
2384 	/* Set promiscuous mode */
2385 	sk_setpromisc(sc_if);
2386 
2387 	/* Set multicast filter */
2388 	sk_setmulti(sc_if);
2389 
2390 	/* Clear and enable interrupts */
2391 	SK_XM_READ_2(sc_if, XM_ISR);
2392 	if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2393 		SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2394 	else
2395 		SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2396 
2397 	/* Configure MAC arbiter */
2398 	switch(sc_if->sk_xmac_rev) {
2399 	case XM_XMAC_REV_B2:
2400 		sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2401 		sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2402 		sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2403 		sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2404 		sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2405 		sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2406 		sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2407 		sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2408 		sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2409 		break;
2410 	case XM_XMAC_REV_C1:
2411 		sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2412 		sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2413 		sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2414 		sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2415 		sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2416 		sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2417 		sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2418 		sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2419 		sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2420 		break;
2421 	default:
2422 		break;
2423 	}
2424 	sk_win_write_2(sc, SK_MACARB_CTL,
2425 	    SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
2426 
2427 	sc_if->sk_link = 1;
2428 }
2429 
2430 static void
sk_init_yukon(struct sk_if_softc * sc_if)2431 sk_init_yukon(struct sk_if_softc *sc_if)
2432 {
2433 	uint32_t phy, v;
2434 	uint16_t reg;
2435 	struct sk_softc *sc;
2436 	int i;
2437 
2438 	sc = sc_if->sk_softc;
2439 
2440 	DPRINTFN(2, ("sk_init_yukon: start: sk_csr=%#x\n",
2441 		     CSR_READ_4(sc_if->sk_softc, SK_CSR)));
2442 
2443 	if (sc->sk_type == SK_YUKON_LITE &&
2444 	    sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
2445 		/*
2446 		 * Workaround code for COMA mode, set PHY reset.
2447 		 * Otherwise it will not correctly take chip out of
2448 		 * powerdown (coma)
2449 		 */
2450 		v = sk_win_read_4(sc, SK_GPIO);
2451 		v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
2452 		sk_win_write_4(sc, SK_GPIO, v);
2453 	}
2454 
2455 	DPRINTFN(6, ("sk_init_yukon: 1\n"));
2456 
2457 	/* GMAC and GPHY Reset */
2458 	SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
2459 	SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2460 	DELAY(1000);
2461 
2462 	DPRINTFN(6, ("sk_init_yukon: 2\n"));
2463 
2464 	if (sc->sk_type == SK_YUKON_LITE &&
2465 	    sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
2466 		/*
2467 		 * Workaround code for COMA mode, clear PHY reset
2468 		 */
2469 		v = sk_win_read_4(sc, SK_GPIO);
2470 		v |= SK_GPIO_DIR9;
2471 		v &= ~SK_GPIO_DAT9;
2472 		sk_win_write_4(sc, SK_GPIO, v);
2473 	}
2474 
2475 	phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
2476 		SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
2477 
2478 	if (sc->sk_coppertype)
2479 		phy |= SK_GPHY_COPPER;
2480 	else
2481 		phy |= SK_GPHY_FIBER;
2482 
2483 	DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy));
2484 
2485 	SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
2486 	DELAY(1000);
2487 	SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
2488 	SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
2489 		      SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
2490 
2491 	DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n",
2492 		     SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL)));
2493 
2494 	DPRINTFN(6, ("sk_init_yukon: 3\n"));
2495 
2496 	/* unused read of the interrupt source register */
2497 	DPRINTFN(6, ("sk_init_yukon: 4\n"));
2498 	SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2499 
2500 	DPRINTFN(6, ("sk_init_yukon: 4a\n"));
2501 	reg = SK_YU_READ_2(sc_if, YUKON_PAR);
2502 	DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
2503 
2504 	/* MIB Counter Clear Mode set */
2505 	reg |= YU_PAR_MIB_CLR;
2506 	DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
2507 	DPRINTFN(6, ("sk_init_yukon: 4b\n"));
2508 	SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2509 
2510 	/* MIB Counter Clear Mode clear */
2511 	DPRINTFN(6, ("sk_init_yukon: 5\n"));
2512 	reg &= ~YU_PAR_MIB_CLR;
2513 	SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2514 
2515 	/* receive control reg */
2516 	DPRINTFN(6, ("sk_init_yukon: 7\n"));
2517 	SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
2518 
2519 	/* transmit parameter register */
2520 	DPRINTFN(6, ("sk_init_yukon: 8\n"));
2521 	SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2522 		      YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
2523 
2524 	/* serial mode register */
2525 	DPRINTFN(6, ("sk_init_yukon: 9\n"));
2526 	reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
2527 	if (sc_if->sk_use_jumbo)
2528 		reg |= YU_SMR_MFL_JUMBO;
2529 	SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
2530 
2531 	DPRINTFN(6, ("sk_init_yukon: 10\n"));
2532 	/* Setup Yukon's address */
2533 	for (i = 0; i < 3; i++) {
2534 		/* Write Source Address 1 (unicast filter) */
2535 		SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2536 			      sc_if->arpcom.ac_enaddr[i * 2] |
2537 			      sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8);
2538 	}
2539 
2540 	for (i = 0; i < 3; i++) {
2541 		reg = sk_win_read_2(sc_if->sk_softc,
2542 				    SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2543 		SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2544 	}
2545 
2546 	/* Set promiscuous mode */
2547 	sk_setpromisc(sc_if);
2548 
2549 	/* Set multicast filter */
2550 	DPRINTFN(6, ("sk_init_yukon: 11\n"));
2551 	sk_setmulti(sc_if);
2552 
2553 	/* enable interrupt mask for counter overflows */
2554 	DPRINTFN(6, ("sk_init_yukon: 12\n"));
2555 	SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2556 	SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2557 	SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2558 
2559 	/* Configure RX MAC FIFO Flush Mask */
2560 	v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
2561 	    YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
2562 	    YU_RXSTAT_JABBER;
2563 	SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
2564 
2565 	/* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
2566 	if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
2567 		v = SK_TFCTL_OPERATION_ON;
2568 	else
2569 		v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
2570 	/* Configure RX MAC FIFO */
2571 	SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2572 	SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
2573 
2574 	/* Increase flush threshould to 64 bytes */
2575 	SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
2576 	    SK_RFCTL_FIFO_THRESHOLD + 1);
2577 
2578 	/* Configure TX MAC FIFO */
2579 	SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2580 	SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2581 
2582 	DPRINTFN(6, ("sk_init_yukon: end\n"));
2583 }
2584 
2585 /*
2586  * Note that to properly initialize any part of the GEnesis chip,
2587  * you first have to take it out of reset mode.
2588  */
2589 static void
sk_init(void * xsc_if)2590 sk_init(void *xsc_if)
2591 {
2592 	struct sk_if_softc *sc_if = xsc_if;
2593 	struct sk_softc *sc = sc_if->sk_softc;
2594 	struct ifnet *ifp = &sc_if->arpcom.ac_if;
2595 	struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2596 
2597 	DPRINTFN(2, ("sk_init\n"));
2598 
2599 	ASSERT_SERIALIZED(ifp->if_serializer);
2600 
2601 	if (ifp->if_flags & IFF_RUNNING)
2602 		return;
2603 
2604 	/* Cancel pending I/O and free all RX/TX buffers. */
2605 	sk_stop(sc_if);
2606 
2607 	/*
2608 	 * NOTE: Change sk_use_jumbo after sk_stop(),
2609 	 *       but before real initialization.
2610 	 */
2611 	if (ifp->if_mtu > ETHER_MAX_LEN)
2612 		sc_if->sk_use_jumbo = 1;
2613 	else
2614 		sc_if->sk_use_jumbo = 0;
2615 	DPRINTF(("use jumbo buffer: %s\n", sc_if->sk_use_jumbo ? "YES" : "NO"));
2616 
2617 	if (SK_IS_GENESIS(sc)) {
2618 		/* Configure LINK_SYNC LED */
2619 		SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2620 		SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2621 			SK_LINKLED_LINKSYNC_ON);
2622 
2623 		/* Configure RX LED */
2624 		SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
2625 			SK_RXLEDCTL_COUNTER_START);
2626 
2627 		/* Configure TX LED */
2628 		SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
2629 			SK_TXLEDCTL_COUNTER_START);
2630 	}
2631 
2632 	/*
2633 	 * Configure descriptor poll timer
2634 	 *
2635 	 * SK-NET GENESIS data sheet says that possibility of losing Start
2636 	 * transmit command due to CPU/cache related interim storage problems
2637 	 * under certain conditions. The document recommends a polling
2638 	 * mechanism to send a Start transmit command to initiate transfer
2639 	 * of ready descriptors regulary. To cope with this issue sk(4) now
2640 	 * enables descriptor poll timer to initiate descriptor processing
2641 	 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
2642 	 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
2643 	 * command instead of waiting for next descriptor polling time.
2644 	 * The same rule may apply to Rx side too but it seems that is not
2645 	 * needed at the moment.
2646 	 * Since sk(4) uses descriptor polling as a last resort there is no
2647 	 * need to set smaller polling time than maximum allowable one.
2648 	 */
2649 	SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
2650 
2651 	/* Configure I2C registers */
2652 
2653 	/* Configure XMAC(s) */
2654 	switch (sc->sk_type) {
2655 	case SK_GENESIS:
2656 		sk_init_xmac(sc_if);
2657 		break;
2658 	case SK_YUKON:
2659 	case SK_YUKON_LITE:
2660 	case SK_YUKON_LP:
2661 		sk_init_yukon(sc_if);
2662 		break;
2663 	}
2664 	mii_mediachg(mii);
2665 
2666 	if (SK_IS_GENESIS(sc)) {
2667 		/* Configure MAC FIFOs */
2668 		SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2669 		SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2670 		SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2671 
2672 		SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2673 		SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2674 		SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2675 	}
2676 
2677 	/* Configure transmit arbiter(s) */
2678 	SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2679 	    SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON);
2680 
2681 	/* Configure RAMbuffers */
2682 	SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2683 	SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2684 	SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2685 	SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2686 	SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2687 	SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2688 
2689 	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2690 	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2691 	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2692 	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2693 	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2694 	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2695 	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2696 
2697 	/* Configure BMUs */
2698 	SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2699 	SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2700 		      SK_ADDR_LO(sc_if->sk_rdata.sk_rx_ring_paddr));
2701 	SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
2702 		      SK_ADDR_HI(sc_if->sk_rdata.sk_rx_ring_paddr));
2703 
2704 	SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2705 	SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2706 		      SK_ADDR_LO(sc_if->sk_rdata.sk_tx_ring_paddr));
2707 	SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI,
2708 		      SK_ADDR_HI(sc_if->sk_rdata.sk_tx_ring_paddr));
2709 
2710 	/* Init descriptors */
2711 	if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2712 		if_printf(ifp, "initialization failed: "
2713 			  "no memory for rx buffers\n");
2714 		sk_stop(sc_if);
2715 		return;
2716 	}
2717 
2718 	if (sk_init_tx_ring(sc_if) == ENOBUFS) {
2719 		if_printf(ifp, "initialization failed: "
2720 			  "no memory for tx buffers\n");
2721 		sk_stop(sc_if);
2722 		return;
2723 	}
2724 
2725 	/* Configure interrupt handling */
2726 	CSR_READ_4(sc, SK_ISSR);
2727 	if (sc_if->sk_port == SK_PORT_A)
2728 		sc->sk_intrmask |= SK_INTRS1;
2729 	else
2730 		sc->sk_intrmask |= SK_INTRS2;
2731 
2732 	sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2733 
2734 	CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2735 
2736 	/* Start BMUs. */
2737 	SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2738 
2739 	if (SK_IS_GENESIS(sc)) {
2740 		/* Enable XMACs TX and RX state machines */
2741 		SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2742 		SK_XM_SETBIT_2(sc_if, XM_MMUCMD,
2743 			       XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2744 	}
2745 
2746 	if (SK_IS_YUKON(sc)) {
2747 		uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
2748 		reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
2749 #if 0
2750 		/* XXX disable 100Mbps and full duplex mode? */
2751 		reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
2752 #endif
2753 		SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
2754 	}
2755 
2756 	/* Activate descriptor polling timer */
2757 	SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
2758 	/* Start transfer of Tx descriptors */
2759 	CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2760 
2761 	ifp->if_flags |= IFF_RUNNING;
2762 	ifq_clr_oactive(&ifp->if_snd);
2763 
2764 	if (SK_IS_YUKON(sc))
2765 		callout_reset(&sc_if->sk_tick_timer, hz, sk_yukon_tick, sc_if);
2766 }
2767 
2768 static void
sk_stop(struct sk_if_softc * sc_if)2769 sk_stop(struct sk_if_softc *sc_if)
2770 {
2771 	struct sk_softc *sc = sc_if->sk_softc;
2772 	struct ifnet *ifp = &sc_if->arpcom.ac_if;
2773 	struct sk_chain_data *cd = &sc_if->sk_cdata;
2774 	uint32_t val;
2775 	int i;
2776 
2777 	ASSERT_SERIALIZED(ifp->if_serializer);
2778 
2779 	DPRINTFN(2, ("sk_stop\n"));
2780 
2781 	callout_stop(&sc_if->sk_tick_timer);
2782 
2783 	ifp->if_flags &= ~IFF_RUNNING;
2784 	ifq_clr_oactive(&ifp->if_snd);
2785 
2786 	/* Stop Tx descriptor polling timer */
2787 	SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
2788 
2789 	/* Stop transfer of Tx descriptors */
2790 	CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
2791 	for (i = 0; i < SK_TIMEOUT; i++) {
2792 		val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
2793 		if (!(val & SK_TXBMU_TX_STOP))
2794 			break;
2795 		DELAY(1);
2796 	}
2797 	if (i == SK_TIMEOUT)
2798 		if_printf(ifp, "cannot stop transfer of Tx descriptors\n");
2799 
2800 	/* Stop transfer of Rx descriptors */
2801 	SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
2802 	for (i = 0; i < SK_TIMEOUT; i++) {
2803 		val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
2804 		if (!(val & SK_RXBMU_RX_STOP))
2805 			break;
2806 		DELAY(1);
2807 	}
2808 	if (i == SK_TIMEOUT)
2809 		if_printf(ifp, "cannot stop transfer of Rx descriptors\n");
2810 
2811 	if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2812 		/* Put PHY back into reset. */
2813 		val = sk_win_read_4(sc, SK_GPIO);
2814 		if (sc_if->sk_port == SK_PORT_A) {
2815 			val |= SK_GPIO_DIR0;
2816 			val &= ~SK_GPIO_DAT0;
2817 		} else {
2818 			val |= SK_GPIO_DIR2;
2819 			val &= ~SK_GPIO_DAT2;
2820 		}
2821 		sk_win_write_4(sc, SK_GPIO, val);
2822 	}
2823 
2824 	/* Turn off various components of this interface. */
2825 	SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2826 	switch (sc->sk_type) {
2827 	case SK_GENESIS:
2828 		SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
2829 		SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2830 		break;
2831 	case SK_YUKON:
2832 	case SK_YUKON_LITE:
2833 	case SK_YUKON_LP:
2834 		SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2835 		SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2836 		break;
2837 	}
2838 	SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2839 	SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF);
2840 	SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2841 	SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST,
2842 	    SK_RBCTL_RESET | SK_RBCTL_OFF);
2843 	SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2844 	SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2845 	SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2846 	SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2847 	SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2848 
2849 	/* Disable interrupts */
2850 	if (sc_if->sk_port == SK_PORT_A)
2851 		sc->sk_intrmask &= ~SK_INTRS1;
2852 	else
2853 		sc->sk_intrmask &= ~SK_INTRS2;
2854 	CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2855 
2856 	SK_XM_READ_2(sc_if, XM_ISR);
2857 	SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2858 
2859 	/* Free RX and TX mbufs still in the queues. */
2860 	for (i = 0; i < SK_RX_RING_CNT; i++) {
2861 		if (cd->sk_rx_mbuf[i] != NULL) {
2862 			if (!sc_if->sk_use_jumbo) {
2863 				bus_dmamap_unload(cd->sk_rx_dtag,
2864 						  cd->sk_rx_dmap[i]);
2865 			}
2866 			m_freem(cd->sk_rx_mbuf[i]);
2867 			cd->sk_rx_mbuf[i] = NULL;
2868 		}
2869 	}
2870 	for (i = 0; i < SK_TX_RING_CNT; i++) {
2871 		if (cd->sk_tx_mbuf[i] != NULL) {
2872 			bus_dmamap_unload(cd->sk_tx_dtag, cd->sk_tx_dmap[i]);
2873 			m_freem(cd->sk_tx_mbuf[i]);
2874 			cd->sk_tx_mbuf[i] = NULL;
2875 		}
2876 	}
2877 }
2878 
2879 #ifdef SK_DEBUG
2880 static void
sk_dump_txdesc(struct sk_tx_desc * desc,int idx)2881 sk_dump_txdesc(struct sk_tx_desc *desc, int idx)
2882 {
2883 #define DESC_PRINT(X)					\
2884 	if (X)					\
2885 		kprintf("txdesc[%d]." #X "=%#x\n",	\
2886 		       idx, X);
2887 
2888 	DESC_PRINT(le32toh(desc->sk_ctl));
2889 	DESC_PRINT(le32toh(desc->sk_next));
2890 	DESC_PRINT(le32toh(desc->sk_data_lo));
2891 	DESC_PRINT(le32toh(desc->sk_data_hi));
2892 	DESC_PRINT(le32toh(desc->sk_xmac_txstat));
2893 	DESC_PRINT(le16toh(desc->sk_rsvd0));
2894 	DESC_PRINT(le16toh(desc->sk_csum_startval));
2895 	DESC_PRINT(le16toh(desc->sk_csum_startpos));
2896 	DESC_PRINT(le16toh(desc->sk_csum_writepos));
2897 	DESC_PRINT(le16toh(desc->sk_rsvd1));
2898 #undef PRINT
2899 }
2900 
2901 static void
sk_dump_bytes(const char * data,int len)2902 sk_dump_bytes(const char *data, int len)
2903 {
2904 	int c, i, j;
2905 
2906 	for (i = 0; i < len; i += 16) {
2907 		kprintf("%08x  ", i);
2908 		c = len - i;
2909 		if (c > 16) c = 16;
2910 
2911 		for (j = 0; j < c; j++) {
2912 			kprintf("%02x ", data[i + j] & 0xff);
2913 			if ((j & 0xf) == 7 && j > 0)
2914 				kprintf(" ");
2915 		}
2916 
2917 		for (; j < 16; j++)
2918 			kprintf("   ");
2919 		kprintf("  ");
2920 
2921 		for (j = 0; j < c; j++) {
2922 			int ch = data[i + j] & 0xff;
2923 			kprintf("%c", ' ' <= ch && ch <= '~' ? ch : ' ');
2924 		}
2925 
2926 		kprintf("\n");
2927 
2928 		if (c < 16)
2929 			break;
2930 	}
2931 }
2932 
2933 static void
sk_dump_mbuf(struct mbuf * m)2934 sk_dump_mbuf(struct mbuf *m)
2935 {
2936 	int count = m->m_pkthdr.len;
2937 
2938 	kprintf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len);
2939 
2940 	while (count > 0 && m) {
2941 		kprintf("m=%p, m->m_data=%p, m->m_len=%d\n",
2942 		       m, m->m_data, m->m_len);
2943 		sk_dump_bytes(mtod(m, char *), m->m_len);
2944 
2945 		count -= m->m_len;
2946 		m = m->m_next;
2947 	}
2948 }
2949 #endif
2950 
2951 /*
2952  * Allocate jumbo buffer storage. The SysKonnect adapters support
2953  * "jumbograms" (9K frames), although SysKonnect doesn't currently
2954  * use them in their drivers. In order for us to use them, we need
2955  * large 9K receive buffers, however standard mbuf clusters are only
2956  * 2048 bytes in size. Consequently, we need to allocate and manage
2957  * our own jumbo buffer pool. Fortunately, this does not require an
2958  * excessive amount of additional code.
2959  */
2960 static int
sk_jpool_alloc(device_t dev)2961 sk_jpool_alloc(device_t dev)
2962 {
2963 	struct sk_if_softc *sc_if = device_get_softc(dev);
2964 	struct sk_chain_data *cd = &sc_if->sk_cdata;
2965 	bus_dmamem_t dmem;
2966 	bus_addr_t paddr;
2967 	caddr_t buf;
2968 	int error, i;
2969 
2970 	lwkt_serialize_init(&cd->sk_jpool_serializer);
2971 
2972 	error = bus_dmamem_coherent(cd->sk_buf_dtag, PAGE_SIZE /* XXX */, 0,
2973 				    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2974 				    SK_JMEM, BUS_DMA_WAITOK, &dmem);
2975 	if (error) {
2976 		device_printf(dev, "can't allocate jumbo frame pool\n");
2977 		return error;
2978 	}
2979 	cd->sk_jpool_dtag = dmem.dmem_tag;
2980 	cd->sk_jpool_dmap = dmem.dmem_map;
2981 	cd->sk_jpool = dmem.dmem_addr;
2982 	paddr = dmem.dmem_busaddr;
2983 
2984 	SLIST_INIT(&cd->sk_jpool_free_ent);
2985 	buf = cd->sk_jpool;
2986 
2987 	/*
2988 	 * Now divide it up into SK_JLEN pieces.
2989 	 */
2990 	for (i = 0; i < SK_JSLOTS; i++) {
2991 		struct sk_jpool_entry *entry = &cd->sk_jpool_ent[i];
2992 
2993 		entry->sc_if = sc_if;
2994 		entry->inuse = 0;
2995 		entry->slot = i;
2996 		entry->buf = buf;
2997 		entry->paddr = paddr;
2998 
2999 		SLIST_INSERT_HEAD(&cd->sk_jpool_free_ent, entry, entry_next);
3000 
3001 		buf += SK_JLEN;
3002 		paddr += SK_JLEN;
3003 	}
3004 	return 0;
3005 }
3006 
3007 static void
sk_jpool_free(struct sk_if_softc * sc_if)3008 sk_jpool_free(struct sk_if_softc *sc_if)
3009 {
3010 	struct sk_chain_data *cd = &sc_if->sk_cdata;
3011 
3012 	if (cd->sk_jpool_dtag != NULL) {
3013 		bus_dmamap_unload(cd->sk_jpool_dtag, cd->sk_jpool_dmap);
3014 		bus_dmamem_free(cd->sk_jpool_dtag, cd->sk_jpool,
3015 				cd->sk_jpool_dmap);
3016 		bus_dma_tag_destroy(cd->sk_jpool_dtag);
3017 		cd->sk_jpool_dtag = NULL;
3018 	}
3019 }
3020 
3021 static int
sk_dma_alloc(device_t dev)3022 sk_dma_alloc(device_t dev)
3023 {
3024 	struct sk_if_softc *sc_if = device_get_softc(dev);
3025 	struct sk_chain_data *cd = &sc_if->sk_cdata;
3026 	struct sk_ring_data *rd = &sc_if->sk_rdata;
3027 	bus_dmamem_t dmem;
3028 	int i, j, error;
3029 
3030 	/* Create parent DMA tag */
3031 	error = bus_dma_tag_create(NULL, 1, 0,
3032 				   BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3033 				   BUS_SPACE_MAXSIZE_32BIT, 0,
3034 				   BUS_SPACE_MAXSIZE_32BIT,
3035 				   0, &sc_if->sk_parent_dtag);
3036 	if (error) {
3037 		device_printf(dev, "can't create parent DMA tag\n");
3038 		return error;
3039 	}
3040 
3041 	/* Create top level ring DMA tag */
3042 	error = bus_dma_tag_create(sc_if->sk_parent_dtag,
3043 				   1, SK_RING_BOUNDARY,
3044 				   BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3045 				   BUS_SPACE_MAXSIZE_32BIT, 0,
3046 				   BUS_SPACE_MAXSIZE_32BIT,
3047 				   0, &rd->sk_ring_dtag);
3048 	if (error) {
3049 		device_printf(dev, "can't create ring DMA tag\n");
3050 		return error;
3051 	}
3052 
3053 	/* Create top level buffer DMA tag */
3054 	error = bus_dma_tag_create(sc_if->sk_parent_dtag, 1, 0,
3055 				   BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3056 				   BUS_SPACE_MAXSIZE_32BIT, 0,
3057 				   BUS_SPACE_MAXSIZE_32BIT,
3058 				   0, &cd->sk_buf_dtag);
3059 	if (error) {
3060 		device_printf(dev, "can't create buf DMA tag\n");
3061 		return error;
3062 	}
3063 
3064 	/* Allocate the TX descriptor queue. */
3065 	error = bus_dmamem_coherent(rd->sk_ring_dtag, SK_RING_ALIGN, 0,
3066 				    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3067 				    SK_TX_RING_SIZE,
3068 				    BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3069 	if (error) {
3070 		device_printf(dev, "can't allocate TX ring\n");
3071 		return error;
3072 	}
3073 	rd->sk_tx_ring_dtag = dmem.dmem_tag;
3074 	rd->sk_tx_ring_dmap = dmem.dmem_map;
3075 	rd->sk_tx_ring = dmem.dmem_addr;
3076 	rd->sk_tx_ring_paddr = dmem.dmem_busaddr;
3077 
3078 	/* Allocate the RX descriptor queue. */
3079 	error = bus_dmamem_coherent(rd->sk_ring_dtag, SK_RING_ALIGN, 0,
3080 				    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3081 				    SK_RX_RING_SIZE,
3082 				    BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3083 	if (error) {
3084 		device_printf(dev, "can't allocate TX ring\n");
3085 		return error;
3086 	}
3087 	rd->sk_rx_ring_dtag = dmem.dmem_tag;
3088 	rd->sk_rx_ring_dmap = dmem.dmem_map;
3089 	rd->sk_rx_ring = dmem.dmem_addr;
3090 	rd->sk_rx_ring_paddr = dmem.dmem_busaddr;
3091 
3092 	/* Try to allocate memory for jumbo buffers. */
3093 	error = sk_jpool_alloc(dev);
3094 	if (error) {
3095 		device_printf(dev, "jumbo buffer allocation failed\n");
3096 		return error;
3097 	}
3098 
3099 	/* Create DMA tag for TX. */
3100 	error = bus_dma_tag_create(cd->sk_buf_dtag, 1, 0,
3101 				   BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3102 				   SK_JLEN, SK_NTXSEG, SK_JLEN,
3103 				   BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3104 				   BUS_DMA_ONEBPAGE,
3105 				   &cd->sk_tx_dtag);
3106 	if (error) {
3107 		device_printf(dev, "can't create TX DMA tag\n");
3108 		return error;
3109 	}
3110 
3111 	/* Create DMA maps for TX. */
3112 	for (i = 0; i < SK_TX_RING_CNT; i++) {
3113 		error = bus_dmamap_create(cd->sk_tx_dtag,
3114 					  BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3115 					  &cd->sk_tx_dmap[i]);
3116 		if (error) {
3117 			device_printf(dev, "can't create %dth TX DMA map\n", i);
3118 
3119 			for (j = 0; j < i; ++j) {
3120 				bus_dmamap_destroy(cd->sk_tx_dtag,
3121 						   cd->sk_tx_dmap[i]);
3122 			}
3123 			bus_dma_tag_destroy(cd->sk_tx_dtag);
3124 			cd->sk_tx_dtag = NULL;
3125 			return error;
3126 		}
3127 	}
3128 
3129 	/* Create DMA tag for RX. */
3130 	error = bus_dma_tag_create(cd->sk_buf_dtag, 1, 0,
3131 				   BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3132 				   MCLBYTES, 1, MCLBYTES,
3133 				   BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3134 				   &cd->sk_rx_dtag);
3135 	if (error) {
3136 		device_printf(dev, "can't create RX DMA tag\n");
3137 		return error;
3138 	}
3139 
3140 	/* Create a spare RX DMA map. */
3141 	error = bus_dmamap_create(cd->sk_rx_dtag, BUS_DMA_WAITOK,
3142 				  &cd->sk_rx_dmap_tmp);
3143 	if (error) {
3144 		device_printf(dev, "can't create spare RX DMA map\n");
3145 		bus_dma_tag_destroy(cd->sk_rx_dtag);
3146 		cd->sk_rx_dtag = NULL;
3147 		return error;
3148 	}
3149 
3150 	/* Create DMA maps for RX. */
3151 	for (i = 0; i < SK_RX_RING_CNT; ++i) {
3152 		error = bus_dmamap_create(cd->sk_rx_dtag, BUS_DMA_WAITOK,
3153 					  &cd->sk_rx_dmap[i]);
3154 		if (error) {
3155 			device_printf(dev, "can't create %dth RX DMA map\n", i);
3156 
3157 			for (j = 0; j < i; ++j) {
3158 				bus_dmamap_destroy(cd->sk_rx_dtag,
3159 						   cd->sk_rx_dmap[i]);
3160 			}
3161 			bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp);
3162 			bus_dma_tag_destroy(cd->sk_rx_dtag);
3163 			cd->sk_rx_dtag = NULL;
3164 			return error;
3165 		}
3166 	}
3167 	return 0;
3168 }
3169 
3170 static void
sk_dma_free(device_t dev)3171 sk_dma_free(device_t dev)
3172 {
3173 	struct sk_if_softc *sc_if = device_get_softc(dev);
3174 	struct sk_chain_data *cd = &sc_if->sk_cdata;
3175 	struct sk_ring_data *rd = &sc_if->sk_rdata;
3176 	int i;
3177 
3178 	if (cd->sk_tx_dtag != NULL) {
3179 		for (i = 0; i < SK_TX_RING_CNT; ++i) {
3180 			KASSERT(cd->sk_tx_mbuf[i] == NULL,
3181 				("sk_stop() is not called before %s()",
3182 				 __func__));
3183 			bus_dmamap_destroy(cd->sk_tx_dtag, cd->sk_tx_dmap[i]);
3184 		}
3185 		bus_dma_tag_destroy(cd->sk_tx_dtag);
3186 	}
3187 
3188 	if (cd->sk_rx_dtag != NULL) {
3189 		for (i = 0; i < SK_RX_RING_CNT; ++i) {
3190 			KASSERT(cd->sk_rx_mbuf[i] == NULL,
3191 				("sk_stop() is not called before %s()",
3192 				 __func__));
3193 			bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap[i]);
3194 		}
3195 		bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp);
3196 		bus_dma_tag_destroy(cd->sk_rx_dtag);
3197 	}
3198 
3199 	sk_jpool_free(sc_if);
3200 
3201 	if (rd->sk_rx_ring_dtag != NULL) {
3202 		bus_dmamap_unload(rd->sk_rx_ring_dtag, rd->sk_rx_ring_dmap);
3203 		bus_dmamem_free(rd->sk_rx_ring_dtag, rd->sk_rx_ring,
3204 				rd->sk_rx_ring_dmap);
3205 		bus_dma_tag_destroy(rd->sk_rx_ring_dtag);
3206 	}
3207 
3208 	if (rd->sk_tx_ring_dtag != NULL) {
3209 		bus_dmamap_unload(rd->sk_tx_ring_dtag, rd->sk_tx_ring_dmap);
3210 		bus_dmamem_free(rd->sk_tx_ring_dtag, rd->sk_tx_ring,
3211 				rd->sk_tx_ring_dmap);
3212 		bus_dma_tag_destroy(rd->sk_tx_ring_dtag);
3213 	}
3214 
3215 	if (rd->sk_ring_dtag != NULL)
3216 		bus_dma_tag_destroy(rd->sk_ring_dtag);
3217 	if (cd->sk_buf_dtag != NULL)
3218 		bus_dma_tag_destroy(cd->sk_buf_dtag);
3219 	if (sc_if->sk_parent_dtag != NULL)
3220 		bus_dma_tag_destroy(sc_if->sk_parent_dtag);
3221 }
3222 
3223 static int
skc_sysctl_imtime(SYSCTL_HANDLER_ARGS)3224 skc_sysctl_imtime(SYSCTL_HANDLER_ARGS)
3225 {
3226 	struct sk_softc *sc = arg1;
3227 	struct lwkt_serialize *slize = &sc->sk_serializer;
3228 	int error = 0, v;
3229 
3230 	lwkt_serialize_enter(slize);
3231 
3232 	v = sc->sk_imtime;
3233 	error = sysctl_handle_int(oidp, &v, 0, req);
3234 	if (error || req->newptr == NULL)
3235 		goto back;
3236 	if (v <= 0) {
3237 		error = EINVAL;
3238 		goto back;
3239 	}
3240 
3241 	if (sc->sk_imtime != v) {
3242 		sc->sk_imtime = v;
3243 		sk_win_write_4(sc, SK_IMTIMERINIT,
3244 			       SK_IM_USECS(sc, sc->sk_imtime));
3245 
3246 		/*
3247 		 * Force interrupt moderation timer to
3248 		 * reload new value.
3249 		 */
3250 		sk_win_write_4(sc, SK_IMTIMER, 0);
3251 	}
3252 back:
3253 	lwkt_serialize_exit(slize);
3254 	return error;
3255 }
3256