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Searched defs:smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL_DEFAULT (Results 1 – 2 of 2) sorted by last modified time

/dragonfly/sys/dev/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_default.h4985 #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 macro
H A Dnbio_6_1_default.h3460 #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 macro