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Searched defs:smnPCIE_PERF_CNTL_EVENT0_PORT_SEL_DEFAULT (Results 1 – 2 of 2) sorted by last modified time

/dragonfly/sys/dev/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_default.h9039 #define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL_DEFAULT 0x00000000 macro
H A Dnbio_6_1_default.h5192 #define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL_DEFAULT 0x00000000 macro