1 /*
2 * SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3 * SPDX-License-Identifier: MIT
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "common_nvswitch.h"
25 #include "soe/haldefs_soe_nvswitch.h"
26 #include "soe/soe_nvswitch.h"
27 #include "soe/soe_priv_nvswitch.h"
28
29 #include "export_nvswitch.h"
30
31 NV_STATUS
soeProcessMessages(nvswitch_device * device,PSOE pSoe)32 soeProcessMessages
33 (
34 nvswitch_device *device,
35 PSOE pSoe
36 )
37 {
38 if (pSoe->base.pHal->processMessages == NULL)
39 {
40 NVSWITCH_ASSERT(0);
41 return NV_ERR_INVALID_ARGUMENT;
42 }
43
44 return pSoe->base.pHal->processMessages(device, pSoe);
45 }
46
47 NV_STATUS
soeWaitForInitAck(nvswitch_device * device,PSOE pSoe)48 soeWaitForInitAck
49 (
50 nvswitch_device *device,
51 PSOE pSoe
52 )
53 {
54 if (pSoe->base.pHal->waitForInitAck == NULL)
55 {
56 NVSWITCH_ASSERT(0);
57 return NV_ERR_INVALID_ARGUMENT;
58 }
59
60 return pSoe->base.pHal->waitForInitAck(device, pSoe);
61 }
62
63
64
65 NvU32
soeService_HAL(nvswitch_device * device,PSOE pSoe)66 soeService_HAL
67 (
68 nvswitch_device *device,
69 PSOE pSoe
70 )
71 {
72 if (pSoe->base.pHal->service == NULL)
73 {
74 NVSWITCH_ASSERT(0);
75 return 0;
76 }
77
78 return pSoe->base.pHal->service(device, pSoe);
79 }
80
81 void
soeServiceHalt_HAL(nvswitch_device * device,PSOE pSoe)82 soeServiceHalt_HAL
83 (
84 nvswitch_device *device,
85 PSOE pSoe
86 )
87 {
88 if (pSoe->base.pHal->serviceHalt == NULL)
89 {
90 NVSWITCH_ASSERT(0);
91 return;
92 }
93
94 pSoe->base.pHal->serviceHalt(device, pSoe);
95 }
96
97 void
soeEmemTransfer_HAL(nvswitch_device * device,PSOE pSoe,NvU32 dmemAddr,NvU8 * pBuf,NvU32 sizeBytes,NvU8 port,NvBool bCopyFrom)98 soeEmemTransfer_HAL
99 (
100 nvswitch_device *device,
101 PSOE pSoe,
102 NvU32 dmemAddr,
103 NvU8 *pBuf,
104 NvU32 sizeBytes,
105 NvU8 port,
106 NvBool bCopyFrom
107 )
108 {
109 if (pSoe->base.pHal->ememTransfer == NULL)
110 {
111 NVSWITCH_ASSERT(0);
112 return;
113 }
114
115 pSoe->base.pHal->ememTransfer(device, pSoe, dmemAddr, pBuf, sizeBytes, port, bCopyFrom);
116 }
117
118 NvU32
soeGetEmemSize_HAL(nvswitch_device * device,PSOE pSoe)119 soeGetEmemSize_HAL
120 (
121 nvswitch_device *device,
122 PSOE pSoe
123 )
124 {
125 if (pSoe->base.pHal->getEmemSize == NULL)
126 {
127 NVSWITCH_ASSERT(0);
128 return 0;
129 }
130
131 return pSoe->base.pHal->getEmemSize(device, pSoe);
132 }
133
134 NvU32
soeGetEmemStartOffset_HAL(nvswitch_device * device,PSOE pSoe)135 soeGetEmemStartOffset_HAL
136 (
137 nvswitch_device *device,
138 PSOE pSoe
139 )
140 {
141 if (pSoe->base.pHal->getEmemStartOffset == NULL)
142 {
143 NVSWITCH_ASSERT(0);
144 return 0;
145 }
146
147 return pSoe->base.pHal->getEmemStartOffset(device, pSoe);
148 }
149
150 NV_STATUS
soeEmemPortToRegAddr_HAL(nvswitch_device * device,PSOE pSoe,NvU32 port,NvU32 * pEmemCAddr,NvU32 * pEmemDAddr)151 soeEmemPortToRegAddr_HAL
152 (
153 nvswitch_device *device,
154 PSOE pSoe,
155 NvU32 port,
156 NvU32 *pEmemCAddr,
157 NvU32 *pEmemDAddr
158 )
159 {
160 if (pSoe->base.pHal->ememPortToRegAddr == NULL)
161 {
162 NVSWITCH_ASSERT(0);
163 return NV_ERR_INVALID_ARGUMENT;
164 }
165
166 return pSoe->base.pHal->ememPortToRegAddr(device, pSoe, port, pEmemCAddr, pEmemDAddr);
167 }
168
169 void
soeServiceExterr_HAL(nvswitch_device * device,PSOE pSoe)170 soeServiceExterr_HAL
171 (
172 nvswitch_device *device,
173 PSOE pSoe
174 )
175 {
176 if (pSoe->base.pHal->serviceExterr == NULL)
177 {
178 NVSWITCH_ASSERT(0);
179 return;
180 }
181
182 pSoe->base.pHal->serviceExterr(device, pSoe);
183 }
184
185 NV_STATUS
soeGetExtErrRegAddrs_HAL(nvswitch_device * device,PSOE pSoe,NvU32 * pExtErrAddr,NvU32 * pExtErrStat)186 soeGetExtErrRegAddrs_HAL
187 (
188 nvswitch_device *device,
189 PSOE pSoe,
190 NvU32 *pExtErrAddr,
191 NvU32 *pExtErrStat
192 )
193 {
194 if (pSoe->base.pHal->getExtErrRegAddrs == NULL)
195 {
196 NVSWITCH_ASSERT(0);
197 return NV_ERR_INVALID_ARGUMENT;
198 }
199
200 return pSoe->base.pHal->getExtErrRegAddrs(device, pSoe, pExtErrAddr, pExtErrStat);
201 }
202
203 NvU32
soeEmemPortSizeGet_HAL(nvswitch_device * device,PSOE pSoe)204 soeEmemPortSizeGet_HAL
205 (
206 nvswitch_device *device,
207 PSOE pSoe
208 )
209 {
210 if (pSoe->base.pHal->ememPortSizeGet == NULL)
211 {
212 NVSWITCH_ASSERT(0);
213 return 0;
214 }
215
216 return pSoe->base.pHal->ememPortSizeGet(device, pSoe);
217 }
218
219 NvBool
soeIsCpuHalted_HAL(nvswitch_device * device,PSOE pSoe)220 soeIsCpuHalted_HAL
221 (
222 nvswitch_device *device,
223 PSOE pSoe
224 )
225 {
226 if (pSoe->base.pHal->isCpuHalted == NULL)
227 {
228 NVSWITCH_ASSERT(0);
229 return NV_FALSE;
230 }
231
232 return pSoe->base.pHal->isCpuHalted(device, pSoe);
233 }
234
235 NvlStatus
soeTestDma_HAL(nvswitch_device * device,PSOE pSoe)236 soeTestDma_HAL
237 (
238 nvswitch_device *device,
239 PSOE pSoe
240 )
241 {
242 if (pSoe->base.pHal->testDma == NULL)
243 {
244 NVSWITCH_ASSERT(0);
245 return -NVL_BAD_ARGS;
246 }
247
248 return pSoe->base.pHal->testDma(device);
249 }
250
251 NvlStatus
soeSetPexEOM_HAL(nvswitch_device * device,NvU8 mode,NvU8 nblks,NvU8 nerrs,NvU8 berEyeSel)252 soeSetPexEOM_HAL
253 (
254 nvswitch_device *device,
255 NvU8 mode,
256 NvU8 nblks,
257 NvU8 nerrs,
258 NvU8 berEyeSel
259 )
260 {
261 PSOE pSoe = (PSOE)device->pSoe;
262 if (pSoe->base.pHal->setPexEOM == NULL)
263 {
264 NVSWITCH_ASSERT(0);
265 return -NVL_BAD_ARGS;
266 }
267
268 return pSoe->base.pHal->setPexEOM(device, mode, nblks, nerrs, berEyeSel);
269 }
270
271 NvlStatus
soeGetPexEomStatus_HAL(nvswitch_device * device,NvU8 mode,NvU8 nblks,NvU8 nerrs,NvU8 berEyeSel,NvU32 laneMask,NvU16 * pEomStatus)272 soeGetPexEomStatus_HAL
273 (
274 nvswitch_device *device,
275 NvU8 mode,
276 NvU8 nblks,
277 NvU8 nerrs,
278 NvU8 berEyeSel,
279 NvU32 laneMask,
280 NvU16 *pEomStatus
281 )
282 {
283 PSOE pSoe = (PSOE)device->pSoe;
284 if (pSoe->base.pHal->getPexEomStatus == NULL)
285 {
286 NVSWITCH_ASSERT(0);
287 return -NVL_BAD_ARGS;
288 }
289
290 return pSoe->base.pHal->getPexEomStatus(device, mode, nblks, nerrs, berEyeSel, laneMask, pEomStatus);
291 }
292
293 NvlStatus
soeGetUphyDlnCfgSpace_HAL(nvswitch_device * device,NvU32 regAddress,NvU32 laneSelectMask,NvU16 * pRegValue)294 soeGetUphyDlnCfgSpace_HAL
295 (
296 nvswitch_device *device,
297 NvU32 regAddress,
298 NvU32 laneSelectMask,
299 NvU16 *pRegValue
300 )
301 {
302 PSOE pSoe = (PSOE)device->pSoe;
303 if (pSoe->base.pHal->getUphyDlnCfgSpace == NULL)
304 {
305 NVSWITCH_ASSERT(0);
306 return -NVL_BAD_ARGS;
307 }
308
309 return pSoe->base.pHal->getUphyDlnCfgSpace(device, regAddress, laneSelectMask, pRegValue);
310 }
311
312 NvlStatus
soeForceThermalSlowdown_HAL(nvswitch_device * device,NvBool slowdown,NvU32 periodUs)313 soeForceThermalSlowdown_HAL
314 (
315 nvswitch_device *device,
316 NvBool slowdown,
317 NvU32 periodUs
318 )
319 {
320 PSOE pSoe = (PSOE)device->pSoe;
321 if (pSoe->base.pHal->forceThermalSlowdown == NULL)
322 {
323 NVSWITCH_ASSERT(0);
324 return -NVL_BAD_ARGS;
325 }
326
327 return pSoe->base.pHal->forceThermalSlowdown(device, slowdown, periodUs);
328 }
329
330 NvlStatus
soeSetPcieLinkSpeed_HAL(nvswitch_device * device,NvU32 linkSpeed)331 soeSetPcieLinkSpeed_HAL
332 (
333 nvswitch_device *device,
334 NvU32 linkSpeed
335 )
336 {
337 PSOE pSoe = (PSOE)device->pSoe;
338 if (pSoe->base.pHal->setPcieLinkSpeed == NULL)
339 {
340 NVSWITCH_ASSERT(0);
341 return -NVL_BAD_ARGS;
342 }
343
344 return pSoe->base.pHal->setPcieLinkSpeed(device, linkSpeed);
345 }
346
347 NV_STATUS
soeProcessMessages_HAL(nvswitch_device * device,PSOE pSoe)348 soeProcessMessages_HAL
349 (
350 nvswitch_device *device,
351 PSOE pSoe
352 )
353 {
354 if (pSoe->base.pHal->processMessages == NULL)
355 {
356 NVSWITCH_ASSERT(0);
357 return 0;
358 }
359
360 return pSoe->base.pHal->processMessages(device, pSoe);
361 }
362
363 NV_STATUS
soeWaitForInitAck_HAL(nvswitch_device * device,PSOE pSoe)364 soeWaitForInitAck_HAL
365 (
366 nvswitch_device *device,
367 PSOE pSoe
368 )
369 {
370 if (pSoe->base.pHal->waitForInitAck == NULL)
371 {
372 NVSWITCH_ASSERT(0);
373 return 0;
374 }
375
376 return pSoe->base.pHal->waitForInitAck(device, pSoe);
377 }
378
379 NvlStatus
soeI2CAccess_HAL(nvswitch_device * device,NVSWITCH_CTRL_I2C_INDEXED_PARAMS * pParams)380 soeI2CAccess_HAL
381 (
382 nvswitch_device *device,
383 NVSWITCH_CTRL_I2C_INDEXED_PARAMS *pParams
384 )
385 {
386 PSOE pSoe = (PSOE)device->pSoe;
387 if (pSoe->base.pHal->i2cAccess == NULL)
388 {
389 NVSWITCH_ASSERT(0);
390 return 0;
391 }
392
393 return pSoe->base.pHal->i2cAccess(device, pParams);
394 }
395