xref: /original-bsd/sys/vax/uba/qdreg.h (revision a05d0f95)
1 /*-
2  * Copyright (c) 1982, 1986 The Regents of the University of California.
3  * All rights reserved.
4  *
5  * %sccs.include.redist.c%
6  *
7  *	@(#)qdreg.h	7.1 (Berkeley) 05/09/91
8  */
9 
10 /************************************************************************
11  *									*
12  *			Copyright (c) 1985, 1986 by			*
13  *		Digital Equipment Corporation, Maynard, MA		*
14  *			All rights reserved.				*
15  *									*
16  *   This software is furnished under a license and may be used and	*
17  *   copied  only  in accordance with the terms of such license and	*
18  *   with the  inclusion  of  the  above  copyright  notice.   This	*
19  *   software  or  any	other copies thereof may not be provided or	*
20  *   otherwise made available to any other person.  No title to and	*
21  *   ownership of the software is hereby transferred.			*
22  *									*
23  *   The information in this software is subject to change  without	*
24  *   notice  and should not be construed as a commitment by Digital	*
25  *   Equipment Corporation.						*
26  *									*
27  *   Digital assumes no responsibility for the use  or	reliability	*
28  *   of its software on equipment which is not supplied by Digital.	*
29  *									*
30  ************************************************************************/
31 
32 /* Dragon ADDER reg map */
33 /* ADDER register bit definitions */
34 /* Y_SCROLL_CONSTANT */
35 
36 #define SCROLL_ERASE		0x2000
37 #define ADDER_SCROLL_DOWN	0x1000
38 
39 /* ADDER status and interrupt enable registers [1], [2], [3] */
40 
41 #define DISABLE 		0x0000
42 #define PAUSE_COMPLETE		0x0001
43 #define FRAME_SYNC		0x0002
44 #define INIT_COMPLETE		0x0004
45 #define RASTEROP_COMPLETE	0x0008
46 
47 #define ADDRESS_COMPLETE	0x0010
48 #define RX_READY		0x0020
49 #define TX_READY		0x0040
50 #define ID_SCROLL_READY 	0x0080
51 
52 #define TOP_CLIP		0x0100
53 #define BOTTOM_CLIP		0x0200
54 #define LEFT_CLIP		0x0400
55 #define RIGHT_CLIP		0x0800
56 #define NO_CLIP 		0x1000
57 #define VSYNC			0x2000
58 
59 /* ADDER command register [8], [10] */
60 
61 #define OCR_zero		0x0000
62 #define Z_BLOCK0		0x0000
63 #define OCRA			0x0000
64 #define OCRB			0x0004
65 #define RASTEROP		0x02c0
66 #define PBT			0x03c0
67 #define BTPZ			0x0bb0
68 #define PTBZ			0x07a0
69 #define DTE			0x0400
70 #define S1E			0x0800
71 #define S2E			0x1000
72 #define VIPER_Z_LOAD		0x01A0
73 #define ID_LOAD 		0x0100
74 #define CANCEL			0x0000
75 #define LF_R1			0x0000
76 #define LF_R2			0x0010
77 #define LF_R3			0x0020
78 #define LF_R4			0x0030
79 
80 /* ADDER rasterop mode register [9] */
81 
82 #define NORMAL			0x0000
83 #define LINEAR_PATTERN		0x0002
84 #define X_FILL			0x0003
85 #define Y_FILL			0x0007
86 #define BASELINE		0x0008
87 #define HOLE_ENABLE		0x0010
88 #define SRC_1_INDEX_ENABLE	0x0020
89 #define DST_INDEX_ENABLE	0x0040
90 #define DST_WRITE_ENABLE	0x0080
91 
92 /* ADDER source 2 size register */
93 
94 #define NO_TILE 		0x0080
95 
96 /* External registers base addresses */
97 
98 #define CS_UPDATE_MASK		0x0060
99 #define CS_SCROLL_MASK		0x0040
100 
101 /* VIPER registers */
102 
103 #define RESOLUTION_MODE 	0x0080
104 #define MEMORY_BUS_WIDTH	0x0081
105 #define PLANE_ADDRESS		0x0083
106 #define LU_FUNCTION_R1		0x0084
107 #define LU_FUNCTION_R2		0x0085
108 #define LU_FUNCTION_R3		0x0086
109 #define LU_FUNCTION_R4		0x0087
110 #define MASK_1			0x0088
111 #define MASK_2			0x0089
112 #define SOURCE			0x008a
113 #define SOURCE_Z		0x0000
114 #define BACKGROUND_COLOR	0x008e
115 #define BACKGROUND_COLOR_Z	0x000C
116 #define FOREGROUND_COLOR	0x008f
117 #define FOREGROUND_COLOR_Z	0x0004
118 #define SRC1_OCR_A		0x0090
119 #define SRC2_OCR_A		0x0091
120 #define DST_OCR_A		0x0092
121 #define SRC1_OCR_B		0x0094
122 #define SRC2_OCR_B		0x0095
123 #define DST_OCR_B		0x0096
124 
125 /* VIPER scroll registers */
126 
127 #define SCROLL_CONSTANT 	0x0082
128 #define SCROLL_FILL		0x008b
129 #define SCROLL_FILL_Z		0x0008
130 #define LEFT_SCROLL_MASK	0x008c
131 #define RIGHT_SCROLL_MASK	0x008d
132 
133 /* VIPER register bit definitions */
134 
135 #define EXT_NONE		0x0000
136 #define EXT_SOURCE		0x0001
137 #define EXT_M1_M2		0x0002
138 #define INT_NONE		0x0000
139 #define INT_SOURCE		0x0004
140 #define INT_M1_M2		0x0008
141 #define ID			0x0010
142 #define NO_ID			0x0000
143 #define WAIT			0x0020
144 #define NO_WAIT 		0x0000
145 #define BAR_SHIFT_DELAY 	WAIT
146 #define NO_BAR_SHIFT_DELAY	NO_WAIT
147 
148 
149 /* VIPER logical function unit codes */
150 
151 #define LF_ZEROS		0x0000
152 #define LF_D_XOR_S		0x0006
153 #define LF_SOURCE		0x000A
154 #define LF_D_OR_S		0x000E
155 #define LF_ONES 		0x000F
156 #define INV_M1_M2		0x0030
157 #define FULL_SRC_RESOLUTION	0X00C0 /* makes second pass like first pass */
158 
159 /* VIPER scroll register [2] */
160 
161 #define SCROLL_DISABLE		0x0040
162 #define SCROLL_ENABLE		0x0020
163 #define VIPER_LEFT		0x0000
164 #define VIPER_RIGHT		0x0010
165 #define VIPER_UP		0x0040
166 #define VIPER_DOWN		0x0000
167 
168 /* Adder scroll register */
169 
170 #define ADDER_UP		0x0000
171 #define ADDER_DOWN		0x1000
172 
173 /* Misc scroll definitions */
174 
175 #define UP		0
176 #define DOWN		1
177 #define LEFT		2
178 #define RIGHT		3
179 #define NODIR		4
180 #define SCROLL_VMAX	31
181 #define SCROLL_HMAX	15
182 #define NEW		2
183 #define OLD		1
184 #define BUSY		1
185 #define DRAG		1
186 #define SCROLL		0
187 
188 /* miscellaneous defines */
189 
190 #define ALL_PLANES	0xffffffff
191 #define UNITY		0x1fff		 /* Adder scale factor */
192 #define MAX_SCREEN_X	1024
193 #define MAX_SCREEN_Y	864
194 #define FONT_HEIGHT	32
195 
196 	struct adder {
197 
198 	    /* adder control registers */
199 
200 	    u_short register_address;	/* ADDER reg pntr for use by DGA */
201 	    u_short request_enable;	/* DMA request enables */
202 	    u_short interrupt_enable;	/* interrupt enables */
203 	    u_short status;		/* ADDER status bits */
204 	    u_short reserved1;		/* test function only */
205 	    u_short spare1;		/* spare address (what else?) */
206 
207 	    u_short reserved2;		/* test function only */
208 	    u_short id_data;		/* data path to I/D bus */
209 	    u_short command;		/* ADDER chip command register */
210 	    u_short rasterop_mode;	/* sets rasterop execution modes */
211 	    u_short cmd;		/* duplicate path to above cmd reg */
212 	    u_short reserved3;		/* test function only */
213 
214 	    /* scroll registers */
215 
216 	    u_short ID_scroll_data;	/* I/D bus scroll data */
217 	    u_short ID_scroll_command;	/* I/D bus scroll command */
218 	    u_short scroll_x_min;	/* X scroll min - left boundary */
219 	    u_short scroll_x_max;	/* X scroll max - right boundary */
220 	    u_short scroll_y_min;	/* Y scroll min - upper boundary */
221 	    u_short scroll_y_max;	/* Y scroll max - lower boundary */
222 	    u_short pause;		/* Y coord to set stat when scanned */
223 	    u_short y_offset_pending;	/* vertical scroll control */
224 	    u_short y_scroll_constant;
225 
226 	    /* update control registers */
227 
228 	    u_short x_index_pending;	/* x pending index */
229 	    u_short y_index_pending;	/* y pending index */
230 	    u_short x_index_new;	/* new x index */
231 	    u_short y_index_new;		/* new y index */
232 	    u_short x_index_old;		/* old x index */
233 	    u_short y_index_old;		/* old y index */
234 	    u_short x_clip_min; 	/* left clipping boundary */
235 	    u_short x_clip_max; 	/* right clipping boundary */
236 	    u_short y_clip_min; 	/* upper clipping boundary */
237 	    u_short y_clip_max; 	/* lower clipping boundary */
238 	    u_short spare2;		/* spare address (another!) */
239 
240 	    /* rasterop control registers */
241 
242 	    u_short source_1_dx;	/* source #1 x vector */
243 	    u_short source_1_dy;	/* source #1 y vector*/
244 	    u_short source_1_x; 	/* source #1 x origin */
245 	    u_short source_1_y; 	/* source #1 y origin */
246 	    u_short destination_x;	/* destination x origin */
247 	    u_short destination_y;	/* destination y origin */
248 	    u_short fast_dest_dx;	/* destination x fast vector */
249 	    u_short fast_dest_dy;	/* destination y fast vector */
250 	    u_short slow_dest_dx;	/* destination x slow vector */
251 	    u_short slow_dest_dy;	/* destination y slow vector */
252 	    u_short fast_scale; 	/* scale factor for fast vector */
253 	    u_short slow_scale; 	/* scale factor for slow vector */
254 	    u_short source_2_x; 	/* source #2 x origin */
255 	    u_short source_2_y; 	/* source #2 y origin */
256 	    u_short source_2_size;	/* source #2 height & width */
257 	    u_short error_1;		/* error regs (?) */
258 	    u_short error_2;
259 
260 	    /* screen format control registers */
261 
262 	    u_short y_scan_count_0;	/* y scan counts for vert timing */
263 	    u_short y_scan_count_1;
264 	    u_short y_scan_count_2;
265 	    u_short y_scan_count_3;
266 	    u_short x_scan_conf;	/* x scan configuration */
267 	    u_short x_limit;
268 	    u_short y_limit;
269 	    u_short x_scan_count_0;	/* x scan count for horiz timing */
270 	    u_short x_scan_count_1;
271 	    u_short x_scan_count_2;
272 	    u_short x_scan_count_3;
273 	    u_short x_scan_count_4;
274 	    u_short x_scan_count_5;
275 	    u_short x_scan_count_6;
276 	    u_short sync_phase_adj;	/* sync phase (horiz sync count) */
277 	};
278 
279 /*---------------------
280 * DUART definitions */
281 
282 	/* command definitions */
283 
284 #define EN_RCV		0x01
285 #define DIS_RCV 	0x02
286 #define EN_XMT		0x04
287 #define DIS_XMT 	0x08
288 #define RESET_M 	0x10
289 #define RESET_RCV	0x20
290 #define RESET_XMT	0x30
291 #define RESET_ERR	0x40
292 #define RESET_BD	0x50
293 #define START_BREAK	0x60
294 #define STOP_BREAK	0x70
295 
296 	/* interupt bit definitions */
297 
298 #define EI_XMT_A	0x01
299 #define EI_RCV_A	0x02
300 #define EI_XMT_B	0x10
301 #define EI_RCV_B	0x20
302 
303 #define XMT_RDY_A	0x01
304 #define RCV_RDY_A	0x02
305 #define XMT_RDY_B	0x10
306 #define RCV_RDY_B	0x20
307 
308 	/* status register bit defintions */
309 
310 #define RCV_RDY 	0x01
311 #define FIFO_FULL	0x02
312 #define XMT_RDY 	0x04
313 #define XMT_EMT 	0x08
314 #define OVER_ERR	0x10
315 #define ERR_PARITY	0x20
316 #define FRAME_ERR	0x40
317 #define RCVD_BREAK	0x80
318 
319 
320 	struct duart {
321 
322 	    /* channel A - LK201 */
323 
324 	    short modeA;		/* ch.A mode reg (read/write) */
325 	    short statusA;		/* ch.A status reg (read) */
326 #define clkselA statusA 		/* ch.A clock slect reg (write) */
327 	    short cmdA; 		/* ch.A command reg (write) */
328 	    short dataA;		/* rcv/xmt data ch.A (read/write) */
329 	    short inchng;		/* input change state reg (read) */
330 #define auxctl inchng			/* auxiliary control reg (write) */
331 	    short istatus;		/* interrupt status reg (read) */
332 #define imask istatus			/* interrupt mask reg (write) */
333 	    short CThi; 		/* counter/timer hi byte (read) */
334 #define CTRhi CThi			/* counter/timer hi reg (write) */
335 	    short CTlo; 		/* counter/timer lo byte (read) */
336 #define CTRlo CTlo			/* counter/timer lo reg (write) */
337 
338 	    /* channel B - pointing device */
339 
340 	    short modeB;		/* ch.B mode reg (read/write) */
341 	    short statusB;		/* ch.B status reg (read) */
342 #define clkselB statusB 		/* ch.B clock select reg (write) */
343 	    short cmdB; 		/* ch.B command reg (write) */
344 	    short dataB;		/* ch.B rcv/xmt data (read/write) */
345 	    short rsrvd;
346 	    short inport;		/* input port (read) */
347 #define outconf inport			/* output port config reg (write) */
348 	    short strctr;		/* start counter command (read) */
349 #define setbits setctr			/* output bits set command (write) */
350 	    short stpctr;		/* stop counter command (read) */
351 #define resetbits stpctr		/* output bits reset cmd (write) */
352 
353 };
354