1 /* $OpenBSD: mb89352.c,v 1.35 2024/11/04 18:27:14 miod Exp $ */
2 /* $NetBSD: mb89352.c,v 1.5 2000/03/23 07:01:31 thorpej Exp $ */
3 /* NecBSD: mb89352.c,v 1.4 1998/03/14 07:31:20 kmatsuda Exp */
4
5 #ifdef DDB
6 #define integrate
7 #else
8 #define integrate static __inline
9 #endif
10
11 /*-
12 * Copyright (c) 1996,97,98,99 The NetBSD Foundation, Inc.
13 * All rights reserved.
14 *
15 * This code is derived from software contributed to The NetBSD Foundation
16 * by Charles M. Hannum, Masaru Oki and Kouichi Matsuda.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions
20 * are met:
21 * 1. Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 * 3. All advertising materials mentioning features or use of this software
27 * must display the following acknowledgement:
28 * This product includes software developed by Charles M. Hannum.
29 * 4. The name of the author may not be used to endorse or promote products
30 * derived from this software without specific prior written permission.
31 *
32 * Copyright (c) 1994 Jarle Greipsland
33 * All rights reserved.
34 *
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
37 * are met:
38 * 1. Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * 2. Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in the
42 * documentation and/or other materials provided with the distribution.
43 * 3. The name of the author may not be used to endorse or promote products
44 * derived from this software without specific prior written permission.
45 *
46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
48 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
49 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
50 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
51 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
52 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
54 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
55 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
56 * POSSIBILITY OF SUCH DAMAGE.
57 */
58 /*
59 * [NetBSD for NEC PC-98 series]
60 * Copyright (c) 1996, 1997, 1998
61 * NetBSD/pc98 porting staff. All rights reserved.
62 * Copyright (c) 1996, 1997, 1998
63 * Kouichi Matsuda. All rights reserved.
64 */
65
66 /*
67 * Acknowledgements: Many of the algorithms used in this driver are
68 * inspired by the work of Julian Elischer (julian@tfs.com) and
69 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million!
70 */
71
72 /* TODO list:
73 * 1) Get the DMA stuff working.
74 * 2) Get the iov/uio stuff working. Is this a good thing ???
75 * 3) Get the synch stuff working.
76 * 4) Rewrite it to use malloc for the acb structs instead of static alloc.?
77 */
78
79 /*
80 * A few customizable items:
81 */
82
83 /* Synchronous data transfers? */
84 #define SPC_USE_SYNCHRONOUS 0
85 #define SPC_SYNC_REQ_ACK_OFS 8
86
87 /* Wide data transfers? */
88 #define SPC_USE_WIDE 0
89 #define SPC_MAX_WIDTH 0
90
91 /* Max attempts made to transmit a message */
92 #define SPC_MSG_MAX_ATTEMPT 3 /* Not used now XXX */
93
94 /*
95 * Some spin loop parameters (essentially how long to wait some places)
96 * The problem(?) is that sometimes we expect either to be able to transmit a
97 * byte or to get a new one from the SCSI bus pretty soon. In order to avoid
98 * returning from the interrupt just to get yanked back for the next byte we
99 * may spin in the interrupt routine waiting for this byte to come. How long?
100 * This is really (SCSI) device and processor dependent. Tuneable, I guess.
101 */
102 #define SPC_MSGIN_SPIN 1 /* Will spinwait upto ?ms for a new msg byte */
103 #define SPC_MSGOUT_SPIN 1
104
105 /*
106 * Include debug functions? At the end of this file there are a bunch of
107 * functions that will print out various information regarding queued SCSI
108 * commands, driver state and chip contents. You can call them from the
109 * kernel debugger. If you set SPC_DEBUG to 0 they are not included (the
110 * kernel uses less memory) but you lose the debugging facilities.
111 */
112 /* #define SPC_DEBUG */
113
114 #define SPC_ABORT_TIMEOUT 2000 /* time to wait for abort */
115
116 /* End of customizable parameters */
117
118 /*
119 * MB89352 SCSI Protocol Controller (SPC) routines.
120 */
121
122 #include <sys/param.h>
123 #include <sys/systm.h>
124 #include <sys/kernel.h>
125 #include <sys/errno.h>
126 #include <sys/ioctl.h>
127 #include <sys/device.h>
128 #include <sys/buf.h>
129 #include <sys/proc.h>
130 #include <sys/queue.h>
131
132 #include <machine/intr.h>
133 #include <machine/bus.h>
134
135 #include <scsi/scsi_all.h>
136 #include <scsi/scsi_message.h>
137 #include <scsi/scsiconf.h>
138
139 #include <luna88k/dev/mb89352reg.h>
140 #include <luna88k/dev/mb89352var.h>
141
142 #ifndef DDB
143 #define db_enter() panic("should call debugger here (mb89352.c)")
144 #endif /* ! DDB */
145
146 #ifdef SPC_DEBUG
147 int spc_debug = 0x00; /* SPC_SHOWSTART|SPC_SHOWMISC|SPC_SHOWTRACE; */
148 #endif
149
150 void spc_done (struct spc_softc *, struct spc_acb *);
151 void spc_dequeue (struct spc_softc *, struct spc_acb *);
152 void spc_scsi_cmd (struct scsi_xfer *);
153 int spc_poll (struct spc_softc *, struct scsi_xfer *, int);
154 integrate void spc_sched_msgout(struct spc_softc *, u_char);
155 integrate void spc_setsync(struct spc_softc *, struct spc_tinfo *);
156 void spc_select (struct spc_softc *, struct spc_acb *);
157 void spc_timeout (void *);
158 void spc_scsi_reset (struct spc_softc *);
159 void spc_reset (struct spc_softc *);
160 void spc_acb_free (void *, void *);
161 void *spc_acb_alloc (void *);
162 int spc_reselect (struct spc_softc *, int);
163 void spc_sense (struct spc_softc *, struct spc_acb *);
164 void spc_msgin (struct spc_softc *);
165 void spc_abort (struct spc_softc *, struct spc_acb *);
166 void spc_msgout (struct spc_softc *);
167 int spc_dataout_pio (struct spc_softc *, u_char *, int);
168 int spc_datain_pio (struct spc_softc *, u_char *, int);
169 #ifdef SPC_DEBUG
170 void spc_print_acb (struct spc_acb *);
171 void spc_dump_driver (struct spc_softc *);
172 void spc_dump89352 (struct spc_softc *);
173 void spc_show_scsi_cmd(struct spc_acb *);
174 void spc_print_active_acb(void);
175 #endif
176
177 extern struct cfdriver spc_cd;
178
179 #define breathe() \
180 do { \
181 asm volatile ("or %r0, %r0, %r0"); \
182 asm volatile ("or %r0, %r0, %r0"); \
183 asm volatile ("or %r0, %r0, %r0"); \
184 asm volatile ("or %r0, %r0, %r0"); \
185 } while (0)
186
187 /*
188 * INITIALIZATION ROUTINES (probe, attach ++)
189 */
190
191 void
192 /* spc_attach(sc) */
spc_attach(struct spc_softc * sc,const struct scsi_adapter * adapter)193 spc_attach(struct spc_softc *sc, const struct scsi_adapter *adapter)
194 {
195 struct scsibus_attach_args saa;
196 SPC_TRACE(("spc_attach "));
197 sc->sc_state = SPC_INIT;
198
199 sc->sc_freq = 20; /* XXXX Assume 20 MHz. */
200
201 #if SPC_USE_SYNCHRONOUS
202 /*
203 * These are the bounds of the sync period, based on the frequency of
204 * the chip's clock input and the size and offset of the sync period
205 * register.
206 *
207 * For a 20MHz clock, this gives us 25, or 100nS, or 10MB/s, as a
208 * maximum transfer rate, and 112.5, or 450nS, or 2.22MB/s, as a
209 * minimum transfer rate.
210 */
211 sc->sc_minsync = (2 * 250) / sc->sc_freq;
212 sc->sc_maxsync = (9 * 250) / sc->sc_freq;
213 #endif
214
215 spc_init(sc); /* Init chip and driver */
216
217 saa.saa_adapter_softc = sc;
218 saa.saa_adapter_target = sc->sc_initiator;
219 saa.saa_adapter = adapter;
220 saa.saa_luns = saa.saa_adapter_buswidth = 8;
221 saa.saa_openings = 2;
222 saa.saa_pool = &sc->sc_iopool;
223 saa.saa_flags = saa.saa_quirks = 0;
224 saa.saa_wwpn = saa.saa_wwnn = 0;
225
226 config_found(&sc->sc_dev, &saa, scsiprint);
227 }
228
229 /*
230 * Initialize MB89352 chip itself
231 * The following conditions should hold:
232 * spc_isa_probe should have succeeded, i.e. the iobase address in spc_softc
233 * must be valid.
234 */
235 void
spc_reset(struct spc_softc * sc)236 spc_reset(struct spc_softc *sc)
237 {
238 bus_space_tag_t iot = sc->sc_iot;
239 bus_space_handle_t ioh = sc->sc_ioh;
240
241 SPC_TRACE(("spc_reset "));
242 /*
243 * Disable interrupts then reset the FUJITSU chip.
244 */
245 bus_space_write_1(iot, ioh, SCTL, SCTL_DISABLE | SCTL_CTRLRST);
246 bus_space_write_1(iot, ioh, SCMD, 0);
247 bus_space_write_1(iot, ioh, TMOD, 0);
248 bus_space_write_1(iot, ioh, PCTL, 0);
249 bus_space_write_1(iot, ioh, TEMP, 0);
250 bus_space_write_1(iot, ioh, TCH, 0);
251 bus_space_write_1(iot, ioh, TCM, 0);
252 bus_space_write_1(iot, ioh, TCL, 0);
253 bus_space_write_1(iot, ioh, INTS, 0);
254 bus_space_write_1(iot, ioh, SCTL,
255 SCTL_DISABLE | SCTL_ABRT_ENAB | SCTL_PARITY_ENAB | SCTL_RESEL_ENAB);
256 bus_space_write_1(iot, ioh, BDID, sc->sc_initiator);
257 delay(400);
258 bus_space_write_1(iot, ioh, SCTL,
259 bus_space_read_1(iot, ioh, SCTL) & ~SCTL_DISABLE);
260 }
261
262
263 /*
264 * Pull the SCSI RST line for 500us.
265 */
266 void
spc_scsi_reset(struct spc_softc * sc)267 spc_scsi_reset(struct spc_softc *sc)
268 {
269 bus_space_tag_t iot = sc->sc_iot;
270 bus_space_handle_t ioh = sc->sc_ioh;
271
272 SPC_TRACE(("spc_scsi_reset "));
273 bus_space_write_1(iot, ioh, SCMD, bus_space_read_1(iot, ioh, SCMD) | SCMD_RST);
274 delay(500);
275 bus_space_write_1(iot, ioh, SCMD, bus_space_read_1(iot, ioh, SCMD) & ~SCMD_RST);
276 delay(50);
277 }
278
279 /*
280 * Initialize spc SCSI driver.
281 */
282 void
spc_init(struct spc_softc * sc)283 spc_init(struct spc_softc *sc)
284 {
285 struct spc_acb *acb;
286 int r;
287
288 SPC_TRACE(("spc_init "));
289 spc_reset(sc);
290 spc_scsi_reset(sc);
291 spc_reset(sc);
292
293 if (sc->sc_state == SPC_INIT) {
294 /* First time through; initialize. */
295 TAILQ_INIT(&sc->ready_list);
296 TAILQ_INIT(&sc->nexus_list);
297 TAILQ_INIT(&sc->free_list);
298 mtx_init(&sc->sc_acb_mtx, IPL_BIO);
299 scsi_iopool_init(&sc->sc_iopool, sc, spc_acb_alloc, spc_acb_free);
300 sc->sc_nexus = NULL;
301 acb = sc->sc_acb;
302 bzero(acb, sizeof(sc->sc_acb));
303 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) {
304 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain);
305 acb++;
306 }
307 bzero(&sc->sc_tinfo, sizeof(sc->sc_tinfo));
308 } else {
309 /* Cancel any active commands. */
310 sc->sc_state = SPC_CLEANING;
311 if ((acb = sc->sc_nexus) != NULL) {
312 acb->xs->error = XS_DRIVER_STUFFUP;
313 timeout_del(&acb->xs->stimeout);
314 spc_done(sc, acb);
315 }
316 while ((acb = TAILQ_FIRST(&sc->nexus_list)) != NULL) {
317 acb->xs->error = XS_DRIVER_STUFFUP;
318 timeout_del(&acb->xs->stimeout);
319 spc_done(sc, acb);
320 }
321 }
322
323 sc->sc_prevphase = PH_INVALID;
324 for (r = 0; r < 8; r++) {
325 struct spc_tinfo *ti = &sc->sc_tinfo[r];
326
327 ti->flags = 0;
328 #if SPC_USE_SYNCHRONOUS
329 ti->flags |= DO_SYNC;
330 ti->period = sc->sc_minsync;
331 ti->offset = SPC_SYNC_REQ_ACK_OFS;
332 #else
333 ti->period = ti->offset = 0;
334 #endif
335 #if SPC_USE_WIDE
336 ti->flags |= DO_WIDE;
337 ti->width = SPC_MAX_WIDTH;
338 #else
339 ti->width = 0;
340 #endif
341 }
342
343 sc->sc_state = SPC_IDLE;
344 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SCTL,
345 bus_space_read_1(sc->sc_iot, sc->sc_ioh, SCTL) | SCTL_INTR_ENAB);
346 }
347
348 void
spc_acb_free(void * xsc,void * xacb)349 spc_acb_free(void *xsc, void *xacb)
350 {
351 struct spc_softc *sc = xsc;
352 struct spc_acb *acb = xacb;
353
354 SPC_TRACE(("spc_acb_free "));
355
356 acb->flags = 0;
357 mtx_enter(&sc->sc_acb_mtx);
358 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain);
359 mtx_leave(&sc->sc_acb_mtx);
360 }
361
362 void *
spc_acb_alloc(void * xsc)363 spc_acb_alloc(void *xsc)
364 {
365 struct spc_softc *sc = xsc;
366 struct spc_acb *acb;
367
368 SPC_TRACE(("spc_acb_alloc "));
369
370 mtx_enter(&sc->sc_acb_mtx);
371 acb = TAILQ_FIRST(&sc->free_list);
372 if (acb)
373 TAILQ_REMOVE(&sc->free_list, acb, chain);
374 mtx_leave(&sc->sc_acb_mtx);
375
376 return acb;
377 }
378
379 /*
380 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS
381 */
382
383 /*
384 * Expected sequence:
385 * 1) Command inserted into ready list
386 * 2) Command selected for execution
387 * 3) Command won arbitration and has selected target device
388 * 4) Send message out (identify message, eventually also sync.negotiations)
389 * 5) Send command
390 * 5a) Receive disconnect message, disconnect.
391 * 5b) Reselected by target
392 * 5c) Receive identify message from target.
393 * 6) Send or receive data
394 * 7) Receive status
395 * 8) Receive message (command complete etc.)
396 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd.
397 * Repeat 2-8 (no disconnects please...)
398 */
399
400 /*
401 * Start a SCSI-command
402 * This function is called by the higher level SCSI-driver to queue/run
403 * SCSI-commands.
404 */
405 void
spc_scsi_cmd(struct scsi_xfer * xs)406 spc_scsi_cmd(struct scsi_xfer *xs)
407 {
408 struct scsi_link *sc_link = xs->sc_link;
409 struct spc_softc *sc = sc_link->bus->sb_adapter_softc;
410 struct spc_acb *acb;
411 int s, flags;
412
413 SPC_TRACE(("spc_scsi_cmd "));
414 SPC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd.opcode, xs->cmdlen,
415 sc_link->target));
416
417 flags = xs->flags;
418 acb = xs->io;
419
420 /* Initialize acb */
421 acb->xs = xs;
422 timeout_set(&xs->stimeout, spc_timeout, acb);
423
424 if (xs->flags & SCSI_RESET) {
425 acb->flags |= ACB_RESET;
426 acb->scsi_cmd_length = 0;
427 acb->data_length = 0;
428 } else {
429 bcopy(&xs->cmd, &acb->scsi_cmd, xs->cmdlen);
430 acb->scsi_cmd_length = xs->cmdlen;
431 acb->data_addr = xs->data;
432 acb->data_length = xs->datalen;
433 }
434 acb->target_stat = 0;
435
436 s = splbio();
437
438 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain);
439 /*
440 * Start scheduling unless a queue process is in progress.
441 */
442 if (sc->sc_state == SPC_IDLE)
443 spc_sched(sc);
444 /*
445 * After successful sending, check if we should return just now.
446 */
447
448 splx(s);
449
450 if ((flags & SCSI_POLL) == 0)
451 return;
452
453 /* Not allowed to use interrupts, use polling instead */
454 s = splbio();
455 if (spc_poll(sc, xs, xs->timeout)) {
456 spc_timeout(acb);
457 if (spc_poll(sc, xs, xs->timeout))
458 spc_timeout(acb);
459 }
460 splx(s);
461 }
462
463 /*
464 * Used when interrupt driven I/O isn't allowed, e.g. during boot.
465 */
466 int
spc_poll(struct spc_softc * sc,struct scsi_xfer * xs,int count)467 spc_poll(struct spc_softc *sc, struct scsi_xfer *xs, int count)
468 {
469 bus_space_tag_t iot = sc->sc_iot;
470 bus_space_handle_t ioh = sc->sc_ioh;
471
472 SPC_TRACE(("spc_poll "));
473 while (count) {
474 /*
475 * If we had interrupts enabled, would we
476 * have got an interrupt?
477 */
478 if (bus_space_read_1(iot, ioh, INTS) != 0)
479 spc_intr(sc);
480 if ((xs->flags & ITSDONE) != 0)
481 return 0;
482 delay(1000);
483 count--;
484 }
485 return 1;
486 }
487
488 /*
489 * LOW LEVEL SCSI UTILITIES
490 */
491
492 integrate void
spc_sched_msgout(struct spc_softc * sc,u_char m)493 spc_sched_msgout(struct spc_softc *sc, u_char m)
494 {
495 bus_space_tag_t iot = sc->sc_iot;
496 bus_space_handle_t ioh = sc->sc_ioh;
497
498 SPC_TRACE(("spc_sched_msgout "));
499 if (sc->sc_msgpriq == 0)
500 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ATN);
501 sc->sc_msgpriq |= m;
502 }
503
504 /*
505 * Set synchronous transfer offset and period.
506 */
507 integrate void
spc_setsync(struct spc_softc * sc,struct spc_tinfo * ti)508 spc_setsync(struct spc_softc *sc, struct spc_tinfo *ti)
509 {
510 #if SPC_USE_SYNCHRONOUS
511 bus_space_tag_t iot = sc->sc_iot;
512 bus_space_handle_t ioh = sc->sc_ioh;
513
514 SPC_TRACE(("spc_setsync "));
515 if (ti->offset != 0)
516 bus_space_write_1(iot, ioh, TMOD,
517 ((ti->period * sc->sc_freq) / 250 - 2) << 4 | ti->offset);
518 else
519 bus_space_write_1(iot, ioh, TMOD, 0);
520 #endif
521 }
522
523 /*
524 * Start a selection. This is used by spc_sched() to select an idle target,
525 * and by spc_done() to immediately reselect a target to get sense information.
526 */
527 void
spc_select(struct spc_softc * sc,struct spc_acb * acb)528 spc_select(struct spc_softc *sc, struct spc_acb *acb)
529 {
530 struct scsi_link *sc_link = acb->xs->sc_link;
531 int target = sc_link->target;
532 struct spc_tinfo *ti = &sc->sc_tinfo[target];
533 bus_space_tag_t iot = sc->sc_iot;
534 bus_space_handle_t ioh = sc->sc_ioh;
535
536 SPC_TRACE(("spc_select "));
537 spc_setsync(sc, ti);
538
539 #if 0
540 bus_space_write_1(iot, ioh, SCMD, SCMD_SET_ATN);
541 #endif
542
543 bus_space_write_1(iot, ioh, PCTL, 0);
544 bus_space_write_1(iot, ioh, TEMP,
545 (1 << sc->sc_initiator) | (1 << target));
546 /*
547 * Setup BSY timeout (selection timeout).
548 * 250ms according to the SCSI specification.
549 * T = (X * 256 + 15) * Tclf * 2 (Tclf = 200ns on x68k)
550 * To setup 256ms timeout,
551 * 128000ns/200ns = X * 256 + 15
552 * 640 - 15 = X * 256
553 * X = 625 / 256
554 * X = 2 + 113 / 256
555 * ==> tch = 2, tcm = 113 (correct?)
556 */
557 /* Time to the information transfer phase start. */
558 /* XXX These values should be calculated from sc_freq */
559 bus_space_write_1(iot, ioh, TCH, 2);
560 bus_space_write_1(iot, ioh, TCM, 113);
561 bus_space_write_1(iot, ioh, TCL, 3);
562 bus_space_write_1(iot, ioh, SCMD, SCMD_SELECT);
563
564 sc->sc_state = SPC_SELECTING;
565 }
566
567 int
spc_reselect(struct spc_softc * sc,int message)568 spc_reselect(struct spc_softc *sc, int message)
569 {
570 u_char selid, target, lun;
571 struct spc_acb *acb;
572 struct scsi_link *sc_link;
573 struct spc_tinfo *ti;
574
575 SPC_TRACE(("spc_reselect "));
576 /*
577 * The SCSI chip made a snapshot of the data bus while the reselection
578 * was being negotiated. This enables us to determine which target did
579 * the reselect.
580 */
581 selid = sc->sc_selid & ~(1 << sc->sc_initiator);
582 if (selid & (selid - 1)) {
583 printf("%s: reselect with invalid selid %02x; "
584 "sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid);
585 SPC_BREAK();
586 goto reset;
587 }
588
589 /*
590 * Search wait queue for disconnected cmd
591 * The list should be short, so I haven't bothered with
592 * any more sophisticated structures than a simple
593 * singly linked list.
594 */
595 target = ffs(selid) - 1;
596 lun = message & 0x07;
597 TAILQ_FOREACH(acb, &sc->nexus_list, chain) {
598 sc_link = acb->xs->sc_link;
599 if (sc_link->target == target &&
600 sc_link->lun == lun)
601 break;
602 }
603 if (acb == NULL) {
604 printf("%s: reselect from target %d lun %d with no nexus; "
605 "sending ABORT\n", sc->sc_dev.dv_xname, target, lun);
606 SPC_BREAK();
607 goto abort;
608 }
609
610 /* Make this nexus active again. */
611 TAILQ_REMOVE(&sc->nexus_list, acb, chain);
612 sc->sc_state = SPC_CONNECTED;
613 sc->sc_nexus = acb;
614 ti = &sc->sc_tinfo[target];
615 ti->lubusy |= (1 << lun);
616 spc_setsync(sc, ti);
617
618 if (acb->flags & ACB_RESET)
619 spc_sched_msgout(sc, SEND_DEV_RESET);
620 else if (acb->flags & ACB_ABORT)
621 spc_sched_msgout(sc, SEND_ABORT);
622
623 /* Do an implicit RESTORE POINTERS. */
624 sc->sc_dp = acb->data_addr;
625 sc->sc_dleft = acb->data_length;
626 sc->sc_cp = (u_char *)&acb->scsi_cmd;
627 sc->sc_cleft = acb->scsi_cmd_length;
628
629 return (0);
630
631 reset:
632 spc_sched_msgout(sc, SEND_DEV_RESET);
633 return (1);
634
635 abort:
636 spc_sched_msgout(sc, SEND_ABORT);
637 return (1);
638 }
639
640 /*
641 * Schedule a SCSI operation. This has now been pulled out of the interrupt
642 * handler so that we may call it from spc_scsi_cmd and spc_done. This may
643 * save us an unnecessary interrupt just to get things going. Should only be
644 * called when state == SPC_IDLE and at bio pl.
645 */
646 void
spc_sched(struct spc_softc * sc)647 spc_sched(struct spc_softc *sc)
648 {
649 struct spc_acb *acb;
650 struct scsi_link *sc_link;
651 struct spc_tinfo *ti;
652
653 /* missing the hw, just return and wait for our hw */
654 if (sc->sc_flags & SPC_INACTIVE)
655 return;
656 SPC_TRACE(("spc_sched "));
657 /*
658 * Find first acb in ready queue that is for a target/lunit pair that
659 * is not busy.
660 */
661 TAILQ_FOREACH(acb, &sc->ready_list, chain) {
662 sc_link = acb->xs->sc_link;
663 ti = &sc->sc_tinfo[sc_link->target];
664 if ((ti->lubusy & (1 << sc_link->lun)) == 0) {
665 SPC_MISC(("selecting %d:%d ",
666 sc_link->target, sc_link->lun));
667 TAILQ_REMOVE(&sc->ready_list, acb, chain);
668 sc->sc_nexus = acb;
669 spc_select(sc, acb);
670 return;
671 } else
672 SPC_MISC(("%d:%d busy\n",
673 sc_link->target, sc_link->lun));
674 }
675 SPC_MISC(("idle "));
676 /* Nothing to start; just enable reselections and wait. */
677 }
678
679 void
spc_sense(struct spc_softc * sc,struct spc_acb * acb)680 spc_sense(struct spc_softc *sc, struct spc_acb *acb)
681 {
682 struct scsi_xfer *xs = acb->xs;
683 struct scsi_link *sc_link = xs->sc_link;
684 struct spc_tinfo *ti = &sc->sc_tinfo[sc_link->target];
685 struct scsi_sense *ss = (void *)&acb->scsi_cmd;
686
687 SPC_MISC(("requesting sense "));
688 /* Next, setup a request sense command block */
689 bzero(ss, sizeof(*ss));
690 ss->opcode = REQUEST_SENSE;
691 ss->byte2 = sc_link->lun << 5;
692 ss->length = sizeof(struct scsi_sense_data);
693 acb->scsi_cmd_length = sizeof(*ss);
694 acb->data_addr = (char *)&xs->sense;
695 acb->data_length = sizeof(struct scsi_sense_data);
696 acb->flags |= ACB_SENSE;
697 ti->senses++;
698 if (acb->flags & ACB_NEXUS)
699 ti->lubusy &= ~(1 << sc_link->lun);
700 if (acb == sc->sc_nexus) {
701 spc_select(sc, acb);
702 } else {
703 spc_dequeue(sc, acb);
704 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain);
705 if (sc->sc_state == SPC_IDLE)
706 spc_sched(sc);
707 }
708 }
709
710 /*
711 * POST PROCESSING OF SCSI_CMD (usually current)
712 */
713 void
spc_done(struct spc_softc * sc,struct spc_acb * acb)714 spc_done(struct spc_softc *sc, struct spc_acb *acb)
715 {
716 struct scsi_xfer *xs = acb->xs;
717 struct scsi_link *sc_link = xs->sc_link;
718 struct spc_tinfo *ti = &sc->sc_tinfo[sc_link->target];
719
720 SPC_TRACE(("spc_done "));
721
722 /*
723 * Now, if we've come here with no error code, i.e. we've kept the
724 * initial XS_NOERROR, and the status code signals that we should
725 * check sense, we'll need to set up a request sense cmd block and
726 * push the command back into the ready queue *before* any other
727 * commands for this target/lunit, else we lose the sense info.
728 * We don't support chk sense conditions for the request sense cmd.
729 */
730 if (xs->error == XS_NOERROR) {
731 if (acb->flags & ACB_ABORT) {
732 xs->error = XS_DRIVER_STUFFUP;
733 } else if (acb->flags & ACB_SENSE) {
734 xs->error = XS_SENSE;
735 } else {
736 switch (acb->target_stat) {
737 case SCSI_CHECK:
738 /* First, save the return values */
739 xs->resid = acb->data_length;
740 xs->status = acb->target_stat;
741 spc_sense(sc, acb);
742 return;
743 case SCSI_BUSY:
744 xs->error = XS_BUSY;
745 break;
746 case SCSI_OK:
747 xs->resid = acb->data_length;
748 break;
749 default:
750 xs->error = XS_DRIVER_STUFFUP;
751 #ifdef SPC_DEBUG
752 printf("%s: spc_done: bad stat 0x%x\n",
753 sc->sc_dev.dv_xname, acb->target_stat);
754 #endif
755 break;
756 }
757 }
758 }
759
760 #ifdef SPC_DEBUG
761 if ((spc_debug & SPC_SHOWMISC) != 0) {
762 if (xs->resid != 0)
763 printf("resid=%d ", xs->resid);
764 if (xs->error == XS_SENSE)
765 printf("sense=0x%02x\n", xs->sense.error_code);
766 else
767 printf("error=%d\n", xs->error);
768 }
769 #endif
770
771 /*
772 * Remove the ACB from whatever queue it happens to be on.
773 */
774 if (acb->flags & ACB_NEXUS)
775 ti->lubusy &= ~(1 << sc_link->lun);
776 if (acb == sc->sc_nexus) {
777 sc->sc_nexus = NULL;
778 sc->sc_state = SPC_IDLE;
779 spc_sched(sc);
780 } else
781 spc_dequeue(sc, acb);
782
783 ti->cmds++;
784 scsi_done(xs);
785 }
786
787 void
spc_dequeue(struct spc_softc * sc,struct spc_acb * acb)788 spc_dequeue(struct spc_softc *sc, struct spc_acb *acb)
789 {
790
791 SPC_TRACE(("spc_dequeue "));
792 if (acb->flags & ACB_NEXUS)
793 TAILQ_REMOVE(&sc->nexus_list, acb, chain);
794 else
795 TAILQ_REMOVE(&sc->ready_list, acb, chain);
796 }
797
798 /*
799 * INTERRUPT/PROTOCOL ENGINE
800 */
801
802 /*
803 * Precondition:
804 * The SCSI bus is already in the MSGI phase and there is a message byte
805 * on the bus, along with an asserted REQ signal.
806 */
807 void
spc_msgin(struct spc_softc * sc)808 spc_msgin(struct spc_softc *sc)
809 {
810 bus_space_tag_t iot = sc->sc_iot;
811 bus_space_handle_t ioh = sc->sc_ioh;
812 int n;
813
814 SPC_TRACE(("spc_msgin "));
815
816 if (sc->sc_prevphase == PH_MSGIN) {
817 /* This is a continuation of the previous message. */
818 n = sc->sc_imp - sc->sc_imess;
819 goto nextbyte;
820 }
821
822 /* This is a new MESSAGE IN phase. Clean up our state. */
823 sc->sc_flags &= ~SPC_DROP_MSGIN;
824
825 nextmsg:
826 n = 0;
827 sc->sc_imp = &sc->sc_imess[n];
828
829 nextbyte:
830 /*
831 * Read a whole message, but don't ack the last byte. If we reject the
832 * message, we have to assert ATN during the message transfer phase
833 * itself.
834 */
835 for (;;) {
836 u_int8_t intstat;
837 #if 0
838 for (;;) {
839 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) != 0)
840 break;
841 /* Wait for REQINIT. XXX Need timeout. */
842 }
843 #endif
844 if (bus_space_read_1(iot, ioh, INTS) != 0) {
845 /*
846 * Target left MESSAGE IN, probably because it
847 * a) noticed our ATN signal, or
848 * b) ran out of messages.
849 */
850 goto out;
851 }
852
853 /* If parity error, just dump everything on the floor. */
854 if ((bus_space_read_1(iot, ioh, SERR) &
855 (SERR_SCSI_PAR|SERR_SPC_PAR)) != 0) {
856 sc->sc_flags |= SPC_DROP_MSGIN;
857 spc_sched_msgout(sc, SEND_PARITY_ERROR);
858 }
859
860 /* send TRANSFER command. */
861 bus_space_write_1(iot, ioh, TCH, 0);
862 bus_space_write_1(iot, ioh, TCM, 0);
863 bus_space_write_1(iot, ioh, TCL, 1);
864 bus_space_write_1(iot, ioh, PCTL,
865 sc->sc_phase | PCTL_BFINT_ENAB);
866 #ifdef x68k
867 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* | SCMD_PROG_XFR */
868 #else
869 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR | SCMD_PROG_XFR); /* XXX */
870 #endif
871 intstat = 0;
872 for (;;) {
873 /*if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0
874 && (bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_EMPTY) != 0)*/
875 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_EMPTY) == 0)
876 break;
877 /*
878 * We have to read INTS before checking SSTS to avoid
879 * race between SSTS_DREG_EMPTY and INTS_CMD_DONE.
880 */
881 if (intstat != 0)
882 goto out;
883 intstat = bus_space_read_1(iot, ioh, INTS);
884 }
885
886 /* Gather incoming message bytes if needed. */
887 if ((sc->sc_flags & SPC_DROP_MSGIN) == 0) {
888 if (n >= SPC_MAX_MSG_LEN) {
889 (void) bus_space_read_1(iot, ioh, DREG);
890 sc->sc_flags |= SPC_DROP_MSGIN;
891 spc_sched_msgout(sc, SEND_REJECT);
892 } else {
893 *sc->sc_imp++ = bus_space_read_1(iot, ioh, DREG);
894 n++;
895 /*
896 * This testing is suboptimal, but most
897 * messages will be of the one byte variety, so
898 * it should not affect performance
899 * significantly.
900 */
901 if (n == 1 && IS1BYTEMSG(sc->sc_imess[0]))
902 break;
903 if (n == 2 && IS2BYTEMSG(sc->sc_imess[0]))
904 break;
905 if (n >= 3 && ISEXTMSG(sc->sc_imess[0]) &&
906 n == sc->sc_imess[1] + 2)
907 break;
908 }
909 } else
910 (void) bus_space_read_1(iot, ioh, DREG);
911
912 /*
913 * If we reach this spot we're either:
914 * a) in the middle of a multi-byte message, or
915 * b) dropping bytes.
916 */
917 #if 0
918 /* Ack the last byte read. */
919 /*(void) bus_space_read_1(iot, ioh, DREG);*/
920 while ((bus_space_read_1(iot, ioh, PSNS) & ACKI) != 0)
921 ;
922 #endif
923 }
924
925 SPC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0]));
926
927 /* We now have a complete message. Parse it. */
928 switch (sc->sc_state) {
929 struct spc_acb *acb;
930 struct scsi_link *sc_link;
931 struct spc_tinfo *ti;
932
933 case SPC_CONNECTED:
934 SPC_ASSERT(sc->sc_nexus != NULL);
935 acb = sc->sc_nexus;
936 ti = &sc->sc_tinfo[acb->xs->sc_link->target];
937
938 switch (sc->sc_imess[0]) {
939 case MSG_CMDCOMPLETE:
940 if (sc->sc_dleft < 0) {
941 sc_link = acb->xs->sc_link;
942 printf("%s: %ld extra bytes from %d:%d\n",
943 sc->sc_dev.dv_xname, -sc->sc_dleft,
944 sc_link->target, sc_link->lun);
945 acb->data_length = 0;
946 }
947 acb->xs->resid = acb->data_length = sc->sc_dleft;
948 sc->sc_state = SPC_CMDCOMPLETE;
949 break;
950
951 case MSG_PARITY_ERROR:
952 /* Resend the last message. */
953 spc_sched_msgout(sc, sc->sc_lastmsg);
954 break;
955
956 case MSG_MESSAGE_REJECT:
957 SPC_MISC(("message rejected %02x ", sc->sc_lastmsg));
958 switch (sc->sc_lastmsg) {
959 #if SPC_USE_SYNCHRONOUS + SPC_USE_WIDE
960 case SEND_IDENTIFY:
961 ti->flags &= ~(DO_SYNC | DO_WIDE);
962 ti->period = ti->offset = 0;
963 spc_setsync(sc, ti);
964 ti->width = 0;
965 break;
966 #endif
967 #if SPC_USE_SYNCHRONOUS
968 case SEND_SDTR:
969 ti->flags &= ~DO_SYNC;
970 ti->period = ti->offset = 0;
971 spc_setsync(sc, ti);
972 break;
973 #endif
974 #if SPC_USE_WIDE
975 case SEND_WDTR:
976 ti->flags &= ~DO_WIDE;
977 ti->width = 0;
978 break;
979 #endif
980 case SEND_INIT_DET_ERR:
981 spc_sched_msgout(sc, SEND_ABORT);
982 break;
983 }
984 break;
985
986 case MSG_NOOP:
987 break;
988
989 case MSG_DISCONNECT:
990 ti->dconns++;
991 sc->sc_state = SPC_DISCONNECT;
992 break;
993
994 case MSG_SAVEDATAPOINTER:
995 acb->data_addr = sc->sc_dp;
996 acb->data_length = sc->sc_dleft;
997 break;
998
999 case MSG_RESTOREPOINTERS:
1000 sc->sc_dp = acb->data_addr;
1001 sc->sc_dleft = acb->data_length;
1002 sc->sc_cp = (u_char *)&acb->scsi_cmd;
1003 sc->sc_cleft = acb->scsi_cmd_length;
1004 break;
1005
1006 case MSG_EXTENDED:
1007 switch (sc->sc_imess[2]) {
1008 #if SPC_USE_SYNCHRONOUS
1009 case MSG_EXT_SDTR:
1010 if (sc->sc_imess[1] != 3)
1011 goto reject;
1012 ti->period = sc->sc_imess[3];
1013 ti->offset = sc->sc_imess[4];
1014 ti->flags &= ~DO_SYNC;
1015 if (ti->offset == 0) {
1016 } else if (ti->period < sc->sc_minsync ||
1017 ti->period > sc->sc_maxsync ||
1018 ti->offset > 8) {
1019 ti->period = ti->offset = 0;
1020 spc_sched_msgout(sc, SEND_SDTR);
1021 } else {
1022 sc_print_addr(acb->xs->sc_link);
1023 printf("sync, offset %d, "
1024 "period %dnsec\n",
1025 ti->offset, ti->period * 4);
1026 }
1027 spc_setsync(sc, ti);
1028 break;
1029 #endif
1030
1031 #if SPC_USE_WIDE
1032 case MSG_EXT_WDTR:
1033 if (sc->sc_imess[1] != 2)
1034 goto reject;
1035 ti->width = sc->sc_imess[3];
1036 ti->flags &= ~DO_WIDE;
1037 if (ti->width == 0) {
1038 } else if (ti->width > SPC_MAX_WIDTH) {
1039 ti->width = 0;
1040 spc_sched_msgout(sc, SEND_WDTR);
1041 } else {
1042 sc_print_addr(acb->xs->sc_link);
1043 printf("wide, width %d\n",
1044 1 << (3 + ti->width));
1045 }
1046 break;
1047 #endif
1048
1049 default:
1050 printf("%s: unrecognized MESSAGE EXTENDED; "
1051 "sending REJECT\n", sc->sc_dev.dv_xname);
1052 SPC_BREAK();
1053 goto reject;
1054 }
1055 break;
1056
1057 default:
1058 printf("%s: unrecognized MESSAGE; sending REJECT\n",
1059 sc->sc_dev.dv_xname);
1060 SPC_BREAK();
1061 reject:
1062 spc_sched_msgout(sc, SEND_REJECT);
1063 break;
1064 }
1065 break;
1066
1067 case SPC_RESELECTED:
1068 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) {
1069 printf("%s: reselect without IDENTIFY; "
1070 "sending DEVICE RESET\n", sc->sc_dev.dv_xname);
1071 SPC_BREAK();
1072 goto reset;
1073 }
1074
1075 (void) spc_reselect(sc, sc->sc_imess[0]);
1076 break;
1077
1078 default:
1079 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n",
1080 sc->sc_dev.dv_xname);
1081 SPC_BREAK();
1082 reset:
1083 spc_sched_msgout(sc, SEND_DEV_RESET);
1084 break;
1085
1086 #ifdef notdef
1087 abort:
1088 spc_sched_msgout(sc, SEND_ABORT);
1089 break;
1090 #endif
1091 }
1092
1093 /* Ack the last message byte. */
1094 #if 0 /* XXX? */
1095 (void) bus_space_read_1(iot, ioh, DREG);
1096 while ((bus_space_read_1(iot, ioh, PSNS) & ACKI) != 0)
1097 ;
1098 #endif
1099
1100 /* Go get the next message, if any. */
1101 goto nextmsg;
1102
1103 out:
1104 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ACK);
1105 SPC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0]));
1106 }
1107
1108 /*
1109 * Send the highest priority, scheduled message.
1110 */
1111 void
spc_msgout(struct spc_softc * sc)1112 spc_msgout(struct spc_softc *sc)
1113 {
1114 bus_space_tag_t iot = sc->sc_iot;
1115 bus_space_handle_t ioh = sc->sc_ioh;
1116 #if SPC_USE_SYNCHRONOUS
1117 struct spc_tinfo *ti;
1118 #endif
1119 int n;
1120
1121 SPC_TRACE(("spc_msgout "));
1122
1123 if (sc->sc_prevphase == PH_MSGOUT) {
1124 if (sc->sc_omp == sc->sc_omess) {
1125 /*
1126 * This is a retransmission.
1127 *
1128 * We get here if the target stayed in MESSAGE OUT
1129 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates
1130 * that all of the previously transmitted messages must
1131 * be sent again, in the same order. Therefore, we
1132 * requeue all the previously transmitted messages, and
1133 * start again from the top. Our simple priority
1134 * scheme keeps the messages in the right order.
1135 */
1136 SPC_MISC(("retransmitting "));
1137 sc->sc_msgpriq |= sc->sc_msgoutq;
1138 /*
1139 * Set ATN. If we're just sending a trivial 1-byte
1140 * message, we'll clear ATN later on anyway.
1141 */
1142 bus_space_write_1(iot, ioh, SCMD,
1143 SCMD_SET_ATN); /* XXX? */
1144 } else {
1145 /* This is a continuation of the previous message. */
1146 n = sc->sc_omp - sc->sc_omess;
1147 goto nextbyte;
1148 }
1149 }
1150
1151 /* No messages transmitted so far. */
1152 sc->sc_msgoutq = 0;
1153 sc->sc_lastmsg = 0;
1154
1155 nextmsg:
1156 /* Pick up highest priority message. */
1157 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq;
1158 sc->sc_msgpriq &= ~sc->sc_currmsg;
1159 sc->sc_msgoutq |= sc->sc_currmsg;
1160
1161 /* Build the outgoing message data. */
1162 switch (sc->sc_currmsg) {
1163 case SEND_IDENTIFY:
1164 SPC_ASSERT(sc->sc_nexus != NULL);
1165 sc->sc_omess[0] =
1166 MSG_IDENTIFY(sc->sc_nexus->xs->sc_link->lun, 1);
1167 n = 1;
1168 break;
1169
1170 #if SPC_USE_SYNCHRONOUS
1171 case SEND_SDTR:
1172 SPC_ASSERT(sc->sc_nexus != NULL);
1173 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->target];
1174 sc->sc_omess[4] = MSG_EXTENDED;
1175 sc->sc_omess[3] = MSG_EXT_SDTR_LEN;
1176 sc->sc_omess[2] = MSG_EXT_SDTR;
1177 sc->sc_omess[1] = ti->period >> 2;
1178 sc->sc_omess[0] = ti->offset;
1179 n = 5;
1180 break;
1181 #endif
1182
1183 #if SPC_USE_WIDE
1184 case SEND_WDTR:
1185 SPC_ASSERT(sc->sc_nexus != NULL);
1186 ti = &sc->sc_tinfo[sc->sc_nexus->xs->sc_link->target];
1187 sc->sc_omess[3] = MSG_EXTENDED;
1188 sc->sc_omess[2] = MSG_EXT_WDTR_LEN;
1189 sc->sc_omess[1] = MSG_EXT_WDTR;
1190 sc->sc_omess[0] = ti->width;
1191 n = 4;
1192 break;
1193 #endif
1194
1195 case SEND_DEV_RESET:
1196 sc->sc_flags |= SPC_ABORTING;
1197 sc->sc_omess[0] = MSG_BUS_DEV_RESET;
1198 n = 1;
1199 break;
1200
1201 case SEND_REJECT:
1202 sc->sc_omess[0] = MSG_MESSAGE_REJECT;
1203 n = 1;
1204 break;
1205
1206 case SEND_PARITY_ERROR:
1207 sc->sc_omess[0] = MSG_PARITY_ERROR;
1208 n = 1;
1209 break;
1210
1211 case SEND_INIT_DET_ERR:
1212 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR;
1213 n = 1;
1214 break;
1215
1216 case SEND_ABORT:
1217 sc->sc_flags |= SPC_ABORTING;
1218 sc->sc_omess[0] = MSG_ABORT;
1219 n = 1;
1220 break;
1221
1222 default:
1223 printf("%s: unexpected MESSAGE OUT; sending NOOP\n",
1224 sc->sc_dev.dv_xname);
1225 SPC_BREAK();
1226 sc->sc_omess[0] = MSG_NOOP;
1227 n = 1;
1228 break;
1229 }
1230 sc->sc_omp = &sc->sc_omess[n];
1231
1232 nextbyte:
1233 /* Send message bytes. */
1234 /* send TRANSFER command. */
1235 bus_space_write_1(iot, ioh, TCH, n >> 16);
1236 bus_space_write_1(iot, ioh, TCM, n >> 8);
1237 bus_space_write_1(iot, ioh, TCL, n);
1238 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB);
1239 #ifdef x68k
1240 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */
1241 #else
1242 bus_space_write_1(iot, ioh, SCMD,
1243 SCMD_XFR | SCMD_PROG_XFR | SCMD_ICPT_XFR);
1244 #endif
1245 for (;;) {
1246 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0)
1247 break;
1248 if (bus_space_read_1(iot, ioh, INTS) != 0)
1249 goto out;
1250 }
1251 for (;;) {
1252 #if 0
1253 for (;;) {
1254 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) != 0)
1255 break;
1256 /* Wait for REQINIT. XXX Need timeout. */
1257 }
1258 #endif
1259 if (bus_space_read_1(iot, ioh, INTS) != 0) {
1260 /*
1261 * Target left MESSAGE OUT, possibly to reject
1262 * our message.
1263 *
1264 * If this is the last message being sent, then we
1265 * deassert ATN, since either the target is going to
1266 * ignore this message, or it's going to ask for a
1267 * retransmission via MESSAGE PARITY ERROR (in which
1268 * case we reassert ATN anyway).
1269 */
1270 #if 0
1271 if (sc->sc_msgpriq == 0)
1272 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN);
1273 #endif
1274 goto out;
1275 }
1276
1277 #if 0
1278 /* Clear ATN before last byte if this is the last message. */
1279 if (n == 1 && sc->sc_msgpriq == 0)
1280 bus_space_write_1(iot, ioh, SCMD, SCMD_RST_ATN);
1281 #endif
1282
1283 while ((bus_space_read_1(iot, ioh, SSTS) & SSTS_DREG_FULL) != 0)
1284 ;
1285 /* Send message byte. */
1286 bus_space_write_1(iot, ioh, DREG, *--sc->sc_omp);
1287 --n;
1288 /* Keep track of the last message we've sent any bytes of. */
1289 sc->sc_lastmsg = sc->sc_currmsg;
1290 #if 0
1291 /* Wait for ACK to be negated. XXX Need timeout. */
1292 while ((bus_space_read_1(iot, ioh, PSNS) & ACKI) != 0)
1293 ;
1294 #endif
1295
1296 if (n == 0)
1297 break;
1298 }
1299
1300 /* We get here only if the entire message has been transmitted. */
1301 if (sc->sc_msgpriq != 0) {
1302 /* There are more outgoing messages. */
1303 goto nextmsg;
1304 }
1305
1306 /*
1307 * The last message has been transmitted. We need to remember the last
1308 * message transmitted (in case the target switches to MESSAGE IN phase
1309 * and sends a MESSAGE REJECT), and the list of messages transmitted
1310 * this time around (in case the target stays in MESSAGE OUT phase to
1311 * request a retransmit).
1312 */
1313
1314 out:
1315 /* Disable REQ/ACK protocol. */
1316 return;
1317 }
1318
1319 /*
1320 * spc_dataout_pio: perform a data transfer using the FIFO datapath in the spc
1321 * Precondition: The SCSI bus should be in the DOUT phase, with REQ asserted
1322 * and ACK deasserted (i.e. waiting for a data byte).
1323 *
1324 * This new revision has been optimized (I tried) to make the common case fast,
1325 * and the rarer cases (as a result) somewhat more complex.
1326 */
1327 int
spc_dataout_pio(struct spc_softc * sc,u_char * p,int n)1328 spc_dataout_pio(struct spc_softc *sc, u_char *p, int n)
1329 {
1330 bus_space_tag_t iot = sc->sc_iot;
1331 bus_space_handle_t ioh = sc->sc_ioh;
1332 u_char intstat = 0;
1333 int out = 0;
1334 #define DOUTAMOUNT 8 /* Full FIFO */
1335
1336 SPC_TRACE(("spc_dataout_pio "));
1337 /* send TRANSFER command. */
1338 bus_space_write_1(iot, ioh, TCH, n >> 16);
1339 bus_space_write_1(iot, ioh, TCM, n >> 8);
1340 bus_space_write_1(iot, ioh, TCL, n);
1341 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB);
1342 #ifdef x68k
1343 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */
1344 #else
1345 bus_space_write_1(iot, ioh, SCMD,
1346 SCMD_XFR | SCMD_PROG_XFR | SCMD_ICPT_XFR); /* XXX */
1347 #endif
1348 for (;;) {
1349 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0)
1350 break;
1351 if (bus_space_read_1(iot, ioh, INTS) != 0)
1352 break;
1353 }
1354
1355 /*
1356 * I have tried to make the main loop as tight as possible. This
1357 * means that some of the code following the loop is a bit more
1358 * complex than otherwise.
1359 */
1360 while (n > 0) {
1361 int xfer;
1362
1363 for (;;) {
1364 intstat = bus_space_read_1(iot, ioh, INTS);
1365 /* Wait till buffer is empty. */
1366 if ((bus_space_read_1(iot, ioh, SSTS) &
1367 SSTS_DREG_EMPTY) != 0)
1368 break;
1369 /* Break on interrupt. */
1370 if (intstat != 0)
1371 goto phasechange;
1372 }
1373
1374 xfer = min(DOUTAMOUNT, n);
1375
1376 SPC_MISC(("%d> ", xfer));
1377
1378 n -= xfer;
1379 out += xfer;
1380 #if 0
1381 bus_space_write_multi_1(iot, ioh, DREG, p, xfer);
1382 p += xfer;
1383 #else
1384 switch (xfer) {
1385 case 8:
1386 bus_space_write_1(iot, ioh, DREG, *p++);
1387 case 7:
1388 bus_space_write_1(iot, ioh, DREG, *p++);
1389 case 6:
1390 bus_space_write_1(iot, ioh, DREG, *p++);
1391 case 5:
1392 bus_space_write_1(iot, ioh, DREG, *p++);
1393 case 4:
1394 bus_space_write_1(iot, ioh, DREG, *p++);
1395 case 3:
1396 bus_space_write_1(iot, ioh, DREG, *p++);
1397 case 2:
1398 bus_space_write_1(iot, ioh, DREG, *p++);
1399 case 1:
1400 bus_space_write_1(iot, ioh, DREG, *p++);
1401 }
1402 #endif
1403 }
1404
1405 if (out == 0) {
1406 for (;;) {
1407 if (bus_space_read_1(iot, ioh, INTS) != 0)
1408 break;
1409 }
1410 SPC_MISC(("extra data "));
1411 } else {
1412 /* See the bytes off chip */
1413 for (;;) {
1414 /* Wait till buffer is empty. */
1415 if ((bus_space_read_1(iot, ioh, SSTS) &
1416 SSTS_DREG_EMPTY) != 0)
1417 break;
1418 intstat = bus_space_read_1(iot, ioh, INTS);
1419 /* Break on interrupt. */
1420 if (intstat != 0)
1421 goto phasechange;
1422 }
1423 }
1424
1425 phasechange:
1426 /* Stop the FIFO data path. */
1427
1428 if (intstat != 0) {
1429 /* Some sort of phase change. */
1430 int amount;
1431
1432 amount = ((bus_space_read_1(iot, ioh, TCH) << 16) |
1433 (bus_space_read_1(iot, ioh, TCM) << 8) |
1434 bus_space_read_1(iot, ioh, TCL));
1435 if (amount > 0) {
1436 out -= amount;
1437 SPC_MISC(("+%d ", amount));
1438 }
1439 }
1440
1441 return out;
1442 }
1443
1444 /*
1445 * spc_datain_pio: perform data transfers using the FIFO datapath in the spc
1446 * Precondition: The SCSI bus should be in the DIN phase, with REQ asserted
1447 * and ACK deasserted (i.e. at least one byte is ready).
1448 *
1449 * For now, uses a pretty dumb algorithm, hangs around until all data has been
1450 * transferred. This, is OK for fast targets, but not so smart for slow
1451 * targets which don't disconnect or for huge transfers.
1452 */
1453 int
spc_datain_pio(struct spc_softc * sc,u_char * p,int n)1454 spc_datain_pio(struct spc_softc *sc, u_char *p, int n)
1455 {
1456 bus_space_tag_t iot = sc->sc_iot;
1457 bus_space_handle_t ioh = sc->sc_ioh;
1458 u_int8_t intstat, sstat;
1459 int in = 0;
1460 #define DINAMOUNT 8 /* Full FIFO */
1461
1462 SPC_TRACE(("spc_datain_pio "));
1463 /* send TRANSFER command. */
1464 bus_space_write_1(iot, ioh, TCH, n >> 16);
1465 bus_space_write_1(iot, ioh, TCM, n >> 8);
1466 bus_space_write_1(iot, ioh, TCL, n);
1467 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase | PCTL_BFINT_ENAB);
1468 #ifdef x68k
1469 bus_space_write_1(iot, ioh, SCMD, SCMD_XFR); /* XXX */
1470 #else
1471 bus_space_write_1(iot, ioh, SCMD,
1472 SCMD_XFR | SCMD_PROG_XFR); /* XXX */
1473 #endif
1474 for (;;) {
1475 if ((bus_space_read_1(iot, ioh, SSTS) & SSTS_BUSY) != 0)
1476 break;
1477 if (bus_space_read_1(iot, ioh, INTS) != 0)
1478 goto phasechange;
1479 }
1480
1481 /*
1482 * We leave this loop if one or more of the following is true:
1483 * a) phase != PH_DATAIN && FIFOs are empty
1484 * b) reset has occurred or busfree is detected.
1485 */
1486 while (n > 0) {
1487 int xfer;
1488
1489 /* Wait for fifo half full or phase mismatch */
1490 for (;;) {
1491 intstat = bus_space_read_1(iot, ioh, INTS);
1492 sstat = bus_space_read_1(iot, ioh, SSTS);
1493 if (intstat != 0 ||
1494 (sstat & SSTS_DREG_FULL) != 0 ||
1495 (sstat & SSTS_DREG_EMPTY) == 0)
1496 break;
1497 }
1498
1499 #if 1
1500 if (intstat != 0)
1501 goto phasechange;
1502 #else
1503 if (intstat != 0 &&
1504 (sstat & SSTS_DREG_EMPTY) != 0)
1505 goto phasechange;
1506 #endif
1507 if ((sstat & SSTS_DREG_FULL) != 0)
1508 xfer = min(DINAMOUNT, n);
1509 else
1510 xfer = 1;
1511
1512 SPC_MISC((">%d ", xfer));
1513
1514 n -= xfer;
1515 in += xfer;
1516 #if 0
1517 bus_space_read_multi_1(iot, ioh, DREG, p, xfer);
1518 p += xfer;
1519 #else
1520 switch (xfer) {
1521 case 8:
1522 *p++ = bus_space_read_1(iot, ioh, DREG);
1523 case 7:
1524 *p++ = bus_space_read_1(iot, ioh, DREG);
1525 case 6:
1526 *p++ = bus_space_read_1(iot, ioh, DREG);
1527 case 5:
1528 *p++ = bus_space_read_1(iot, ioh, DREG);
1529 case 4:
1530 *p++ = bus_space_read_1(iot, ioh, DREG);
1531 case 3:
1532 *p++ = bus_space_read_1(iot, ioh, DREG);
1533 case 2:
1534 *p++ = bus_space_read_1(iot, ioh, DREG);
1535 case 1:
1536 *p++ = bus_space_read_1(iot, ioh, DREG);
1537 }
1538 #endif
1539
1540 if (intstat != 0)
1541 goto phasechange;
1542 }
1543
1544 /*
1545 * Some SCSI-devices are rude enough to transfer more data than what
1546 * was requested, e.g. 2048 bytes from a CD-ROM instead of the
1547 * requested 512. Test for progress, i.e. real transfers. If no real
1548 * transfers have been performed (n is probably already zero) and the
1549 * FIFO is not empty, waste some bytes....
1550 */
1551 if (in == 0) {
1552 for (;;) {
1553 /* XXX needs timeout */
1554 if (bus_space_read_1(iot, ioh, INTS) != 0)
1555 break;
1556 }
1557 SPC_MISC(("extra data "));
1558 }
1559
1560 phasechange:
1561 /* Stop the FIFO data path. */
1562
1563 return in;
1564 }
1565
1566 /*
1567 * Catch an interrupt from the adaptor
1568 */
1569 /*
1570 * This is the workhorse routine of the driver.
1571 * Deficiencies (for now):
1572 * 1) always uses programmed I/O
1573 */
1574 int
spc_intr(void * arg)1575 spc_intr(void *arg)
1576 {
1577 struct spc_softc *sc = arg;
1578 bus_space_tag_t iot = sc->sc_iot;
1579 bus_space_handle_t ioh = sc->sc_ioh;
1580 u_char ints;
1581 struct spc_acb *acb;
1582 struct scsi_link *sc_link;
1583 struct spc_tinfo *ti;
1584 int n;
1585
1586 /*
1587 * On LUNA-88K2, 2 spc(4)'s share the level 3 interrupt.
1588 * So, first, check if this device needs to process this interrupt.
1589 */
1590 ints = bus_space_read_1(iot, ioh, INTS);
1591 if (ints == 0) /* No interrupt event on this device */
1592 return 0;
1593
1594 /*
1595 * Disable interrupt.
1596 */
1597 bus_space_write_1(iot, ioh, SCTL,
1598 bus_space_read_1(iot, ioh, SCTL) & ~SCTL_INTR_ENAB);
1599
1600 SPC_TRACE(("spc_intr "));
1601
1602 loop:
1603 /*
1604 * Loop until transfer completion.
1605 */
1606 /*
1607 * First check for abnormal conditions, such as reset.
1608 */
1609 #ifdef x68k /* XXX? */
1610 while ((ints = bus_space_read_1(iot, ioh, INTS)) == 0)
1611 delay(1);
1612 SPC_MISC(("ints = 0x%x ", ints));
1613 #else
1614 ints = bus_space_read_1(iot, ioh, INTS);
1615 SPC_MISC(("ints = 0x%x ", ints));
1616 #endif
1617
1618 if ((ints & INTS_RST) != 0) {
1619 printf("%s: SCSI bus reset\n", sc->sc_dev.dv_xname);
1620 goto reset;
1621 }
1622
1623 /*
1624 * Check for less serious errors.
1625 */
1626 if ((bus_space_read_1(iot, ioh, SERR) & (SERR_SCSI_PAR|SERR_SPC_PAR))
1627 != 0) {
1628 printf("%s: SCSI bus parity error\n", sc->sc_dev.dv_xname);
1629 if (sc->sc_prevphase == PH_MSGIN) {
1630 sc->sc_flags |= SPC_DROP_MSGIN;
1631 spc_sched_msgout(sc, SEND_PARITY_ERROR);
1632 } else
1633 spc_sched_msgout(sc, SEND_INIT_DET_ERR);
1634 }
1635
1636 /*
1637 * If we're not already busy doing something test for the following
1638 * conditions:
1639 * 1) We have been reselected by something
1640 * 2) We have selected something successfully
1641 * 3) Our selection process has timed out
1642 * 4) This is really a bus free interrupt just to get a new command
1643 * going?
1644 * 5) Spurious interrupt?
1645 */
1646 switch (sc->sc_state) {
1647 case SPC_IDLE:
1648 case SPC_SELECTING:
1649 SPC_MISC(("ints:0x%02x ", ints));
1650
1651 if ((ints & INTS_SEL) != 0) {
1652 /*
1653 * We don't currently support target mode.
1654 */
1655 printf("%s: target mode selected; going to BUS FREE\n",
1656 sc->sc_dev.dv_xname);
1657
1658 goto sched;
1659 } else if ((ints & INTS_RESEL) != 0) {
1660 SPC_MISC(("reselected "));
1661
1662 /*
1663 * If we're trying to select a target ourselves,
1664 * push our command back into the ready list.
1665 */
1666 if (sc->sc_state == SPC_SELECTING) {
1667 SPC_MISC(("backoff selector "));
1668 SPC_ASSERT(sc->sc_nexus != NULL);
1669 acb = sc->sc_nexus;
1670 sc->sc_nexus = NULL;
1671 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain);
1672 }
1673
1674 /* Save reselection ID. */
1675 sc->sc_selid = bus_space_read_1(iot, ioh, TEMP);
1676
1677 sc->sc_state = SPC_RESELECTED;
1678 } else if ((ints & INTS_CMD_DONE) != 0) {
1679 SPC_MISC(("selected "));
1680
1681 /*
1682 * We have selected a target. Things to do:
1683 * a) Determine what message(s) to send.
1684 * b) Verify that we're still selecting the target.
1685 * c) Mark device as busy.
1686 */
1687 if (sc->sc_state != SPC_SELECTING) {
1688 printf("%s: selection out while idle; "
1689 "resetting\n", sc->sc_dev.dv_xname);
1690 SPC_BREAK();
1691 goto reset;
1692 }
1693 SPC_ASSERT(sc->sc_nexus != NULL);
1694 acb = sc->sc_nexus;
1695 sc_link = acb->xs->sc_link;
1696 ti = &sc->sc_tinfo[sc_link->target];
1697
1698 sc->sc_msgpriq = SEND_IDENTIFY;
1699 if (acb->flags & ACB_RESET)
1700 sc->sc_msgpriq |= SEND_DEV_RESET;
1701 else if (acb->flags & ACB_ABORT)
1702 sc->sc_msgpriq |= SEND_ABORT;
1703 else {
1704 #if SPC_USE_SYNCHRONOUS
1705 if ((ti->flags & DO_SYNC) != 0)
1706 sc->sc_msgpriq |= SEND_SDTR;
1707 #endif
1708 #if SPC_USE_WIDE
1709 if ((ti->flags & DO_WIDE) != 0)
1710 sc->sc_msgpriq |= SEND_WDTR;
1711 #endif
1712 }
1713
1714 acb->flags |= ACB_NEXUS;
1715 ti->lubusy |= (1 << sc_link->lun);
1716
1717 /* Do an implicit RESTORE POINTERS. */
1718 sc->sc_dp = acb->data_addr;
1719 sc->sc_dleft = acb->data_length;
1720 sc->sc_cp = (u_char *)&acb->scsi_cmd;
1721 sc->sc_cleft = acb->scsi_cmd_length;
1722
1723 /* On our first connection, schedule a timeout. */
1724 if ((acb->xs->flags & SCSI_POLL) == 0)
1725 timeout_add_msec(&acb->xs->stimeout,
1726 acb->xs->timeout);
1727 sc->sc_state = SPC_CONNECTED;
1728 } else if ((ints & INTS_TIMEOUT) != 0) {
1729 SPC_MISC(("selection timeout "));
1730
1731 if (sc->sc_state != SPC_SELECTING) {
1732 printf("%s: selection timeout while idle; "
1733 "resetting\n", sc->sc_dev.dv_xname);
1734 SPC_BREAK();
1735 goto reset;
1736 }
1737 SPC_ASSERT(sc->sc_nexus != NULL);
1738 acb = sc->sc_nexus;
1739
1740 delay(250);
1741
1742 acb->xs->error = XS_SELTIMEOUT;
1743 goto finish;
1744 } else {
1745 if (sc->sc_state != SPC_IDLE) {
1746 printf("%s: BUS FREE while not idle; "
1747 "state=%d\n",
1748 sc->sc_dev.dv_xname, sc->sc_state);
1749 SPC_BREAK();
1750 goto out;
1751 }
1752
1753 goto sched;
1754 }
1755
1756 /*
1757 * Turn off selection stuff, and prepare to catch bus free
1758 * interrupts, parity errors, and phase changes.
1759 */
1760
1761 sc->sc_flags = 0;
1762 sc->sc_prevphase = PH_INVALID;
1763 goto dophase;
1764 }
1765
1766 if ((ints & INTS_DISCON) != 0) {
1767 /* disable disconnect interrupt */
1768 bus_space_write_1(iot, ioh, PCTL,
1769 bus_space_read_1(iot, ioh, PCTL) & ~PCTL_BFINT_ENAB);
1770 /* XXX reset interrupt */
1771 bus_space_write_1(iot, ioh, INTS, ints);
1772
1773 switch (sc->sc_state) {
1774 case SPC_RESELECTED:
1775 goto sched;
1776
1777 case SPC_CONNECTED:
1778 SPC_ASSERT(sc->sc_nexus != NULL);
1779 acb = sc->sc_nexus;
1780
1781 #if SPC_USE_SYNCHRONOUS + SPC_USE_WIDE
1782 if (sc->sc_prevphase == PH_MSGOUT) {
1783 /*
1784 * If the target went to BUS FREE phase during
1785 * or immediately after sending a SDTR or WDTR
1786 * message, disable negotiation.
1787 */
1788 sc_link = acb->xs->sc_link;
1789 ti = &sc->sc_tinfo[sc_link->target];
1790 switch (sc->sc_lastmsg) {
1791 #if SPC_USE_SYNCHRONOUS
1792 case SEND_SDTR:
1793 ti->flags &= ~DO_SYNC;
1794 ti->period = ti->offset = 0;
1795 break;
1796 #endif
1797 #if SPC_USE_WIDE
1798 case SEND_WDTR:
1799 ti->flags &= ~DO_WIDE;
1800 ti->width = 0;
1801 break;
1802 #endif
1803 }
1804 }
1805 #endif
1806
1807 if ((sc->sc_flags & SPC_ABORTING) == 0) {
1808 /*
1809 * Section 5.1.1 of the SCSI 2 spec suggests
1810 * issuing a REQUEST SENSE following an
1811 * unexpected disconnect. Some devices go into
1812 * a contingent allegiance condition when
1813 * disconnecting, and this is necessary to
1814 * clean up their state.
1815 */
1816 printf("%s: unexpected disconnect; "
1817 "sending REQUEST SENSE\n",
1818 sc->sc_dev.dv_xname);
1819 SPC_BREAK();
1820 spc_sense(sc, acb);
1821 goto out;
1822 }
1823
1824 acb->xs->error = XS_DRIVER_STUFFUP;
1825 goto finish;
1826
1827 case SPC_DISCONNECT:
1828 SPC_ASSERT(sc->sc_nexus != NULL);
1829 acb = sc->sc_nexus;
1830 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain);
1831 sc->sc_nexus = NULL;
1832 goto sched;
1833
1834 case SPC_CMDCOMPLETE:
1835 SPC_ASSERT(sc->sc_nexus != NULL);
1836 acb = sc->sc_nexus;
1837 goto finish;
1838 }
1839 }
1840 else if ((ints & INTS_CMD_DONE) != 0 &&
1841 sc->sc_prevphase == PH_MSGIN && sc->sc_state != SPC_CONNECTED)
1842 goto out;
1843
1844 dophase:
1845 #if 0
1846 if ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0) {
1847 /* Wait for REQINIT. */
1848 goto out;
1849 }
1850 #else
1851 bus_space_write_1(iot, ioh, INTS, ints);
1852 ints = 0;
1853 while ((bus_space_read_1(iot, ioh, PSNS) & PSNS_REQ) == 0)
1854 breathe(); /* need timeout XXX */
1855 #endif
1856
1857 /*
1858 * State transition.
1859 */
1860 sc->sc_phase = bus_space_read_1(iot, ioh, PSNS) & PH_MASK;
1861 #if 0
1862 bus_space_write_1(iot, ioh, PCTL, sc->sc_phase);
1863 #endif
1864
1865 SPC_MISC(("phase=%d\n", sc->sc_phase));
1866 switch (sc->sc_phase) {
1867 case PH_MSGOUT:
1868 if (sc->sc_state != SPC_CONNECTED &&
1869 sc->sc_state != SPC_RESELECTED)
1870 break;
1871 spc_msgout(sc);
1872 sc->sc_prevphase = PH_MSGOUT;
1873 goto loop;
1874
1875 case PH_MSGIN:
1876 if (sc->sc_state != SPC_CONNECTED &&
1877 sc->sc_state != SPC_RESELECTED)
1878 break;
1879 spc_msgin(sc);
1880 sc->sc_prevphase = PH_MSGIN;
1881 goto loop;
1882
1883 case PH_CMD:
1884 if (sc->sc_state != SPC_CONNECTED)
1885 break;
1886 #ifdef SPC_DEBUG
1887 if ((spc_debug & SPC_SHOWMISC) != 0) {
1888 SPC_ASSERT(sc->sc_nexus != NULL);
1889 acb = sc->sc_nexus;
1890 printf("cmd=0x%02x+%d ",
1891 acb->scsi_cmd.opcode, acb->scsi_cmd_length - 1);
1892 }
1893 #endif
1894 n = spc_dataout_pio(sc, sc->sc_cp, sc->sc_cleft);
1895 sc->sc_cp += n;
1896 sc->sc_cleft -= n;
1897 sc->sc_prevphase = PH_CMD;
1898 goto loop;
1899
1900 case PH_DATAOUT:
1901 if (sc->sc_state != SPC_CONNECTED)
1902 break;
1903 SPC_MISC(("dataout dleft=%d ", sc->sc_dleft));
1904 n = spc_dataout_pio(sc, sc->sc_dp, sc->sc_dleft);
1905 sc->sc_dp += n;
1906 sc->sc_dleft -= n;
1907 sc->sc_prevphase = PH_DATAOUT;
1908 goto loop;
1909
1910 case PH_DATAIN:
1911 if (sc->sc_state != SPC_CONNECTED)
1912 break;
1913 SPC_MISC(("datain "));
1914 n = spc_datain_pio(sc, sc->sc_dp, sc->sc_dleft);
1915 sc->sc_dp += n;
1916 sc->sc_dleft -= n;
1917 sc->sc_prevphase = PH_DATAIN;
1918 goto loop;
1919
1920 case PH_STAT:
1921 if (sc->sc_state != SPC_CONNECTED)
1922 break;
1923 SPC_ASSERT(sc->sc_nexus != NULL);
1924 acb = sc->sc_nexus;
1925 /*acb->target_stat = bus_space_read_1(iot, ioh, DREG);*/
1926 spc_datain_pio(sc, &acb->target_stat, 1);
1927 SPC_MISC(("target_stat=0x%02x ", acb->target_stat));
1928 sc->sc_prevphase = PH_STAT;
1929 goto loop;
1930 }
1931
1932 printf("%s: unexpected bus phase; resetting\n", sc->sc_dev.dv_xname);
1933 SPC_BREAK();
1934 reset:
1935 spc_init(sc);
1936 return 1;
1937
1938 finish:
1939 timeout_del(&acb->xs->stimeout);
1940 bus_space_write_1(iot, ioh, INTS, ints);
1941 ints = 0;
1942 spc_done(sc, acb);
1943 goto out;
1944
1945 sched:
1946 sc->sc_state = SPC_IDLE;
1947 spc_sched(sc);
1948 goto out;
1949
1950 out:
1951 if (ints)
1952 bus_space_write_1(iot, ioh, INTS, ints);
1953 bus_space_write_1(iot, ioh, SCTL,
1954 bus_space_read_1(iot, ioh, SCTL) | SCTL_INTR_ENAB);
1955 return 1;
1956 }
1957
1958 void
spc_abort(struct spc_softc * sc,struct spc_acb * acb)1959 spc_abort(struct spc_softc *sc, struct spc_acb *acb)
1960 {
1961
1962 /* 2 secs for the abort */
1963 acb->xs->timeout = SPC_ABORT_TIMEOUT;
1964 acb->flags |= ACB_ABORT;
1965
1966 if (acb == sc->sc_nexus) {
1967 /*
1968 * If we're still selecting, the message will be scheduled
1969 * after selection is complete.
1970 */
1971 if (sc->sc_state == SPC_CONNECTED)
1972 spc_sched_msgout(sc, SEND_ABORT);
1973 } else {
1974 spc_dequeue(sc, acb);
1975 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain);
1976 if (sc->sc_state == SPC_IDLE)
1977 spc_sched(sc);
1978 }
1979 }
1980
1981 void
spc_timeout(void * arg)1982 spc_timeout(void *arg)
1983 {
1984 struct spc_acb *acb = arg;
1985 struct scsi_xfer *xs = acb->xs;
1986 struct scsi_link *sc_link = xs->sc_link;
1987 struct spc_softc *sc = sc_link->bus->sb_adapter_softc;
1988 int s;
1989
1990 sc_print_addr(sc_link);
1991 printf("timed out");
1992
1993 s = splbio();
1994
1995 if (acb->flags & ACB_ABORT) {
1996 /* abort timed out */
1997 printf(" AGAIN\n");
1998 /* XXX Must reset! */
1999 } else {
2000 /* abort the operation that has timed out */
2001 printf("\n");
2002 acb->xs->error = XS_TIMEOUT;
2003 spc_abort(sc, acb);
2004 }
2005
2006 splx(s);
2007 }
2008
2009 #ifdef SPC_DEBUG
2010 /*
2011 * The following functions are mostly used for debugging purposes, either
2012 * directly called from the driver or from the kernel debugger.
2013 */
2014
2015 void
spc_show_scsi_cmd(spc_acb * acb)2016 spc_show_scsi_cmd(spc_acb *acb)
2017 {
2018 u_char *b = (u_char *)&acb->scsi_cmd;
2019 struct scsi_link *sc_link = acb->xs->sc_link;
2020 int i;
2021
2022 sc_print_addr(sc_link);
2023 if ((acb->xs->flags & SCSI_RESET) == 0) {
2024 for (i = 0; i < acb->scsi_cmd_length; i++) {
2025 if (i)
2026 printf(",");
2027 printf("%x", b[i]);
2028 }
2029 printf("\n");
2030 } else
2031 printf("RESET\n");
2032 }
2033
2034 void
spc_print_acb(spc_acb * acb)2035 spc_print_acb(spc_acb *acb)
2036 {
2037
2038 printf("acb@%p xs=%p flags=%x", acb, acb->xs, acb->flags);
2039 printf(" dp=%p dleft=%d target_stat=%x\n",
2040 acb->data_addr, acb->data_length, acb->target_stat);
2041 spc_show_scsi_cmd(acb);
2042 }
2043
2044 void
spc_print_active_acb()2045 spc_print_active_acb()
2046 {
2047 struct spc_acb *acb;
2048 struct spc_softc *sc = spc_cd.cd_devs[0]; /* XXX */
2049
2050 printf("ready list:\n");
2051 TAILQ_FOREACH(acb, &sc->ready_list, chain)
2052 spc_print_acb(acb);
2053 printf("nexus:\n");
2054 if (sc->sc_nexus != NULL)
2055 spc_print_acb(sc->sc_nexus);
2056 printf("nexus list:\n");
2057 TAILQ_FOREACH(acb, &sc->nexus_list, chain)
2058 spc_print_acb(acb);
2059 }
2060
2061 void
spc_dump89352(struct spc_softc * sc)2062 spc_dump89352(struct spc_softc *sc)
2063 {
2064 bus_space_tag_t iot = sc->sc_iot;
2065 bus_space_handle_t ioh = sc->sc_ioh;
2066
2067 printf("mb89352: BDID=%x SCTL=%x SCMD=%x TMOD=%x\n",
2068 bus_space_read_1(iot, ioh, BDID),
2069 bus_space_read_1(iot, ioh, SCTL),
2070 bus_space_read_1(iot, ioh, SCMD),
2071 bus_space_read_1(iot, ioh, TMOD));
2072 printf(" INTS=%x PSNS=%x SSTS=%x SERR=%x PCTL=%x\n",
2073 bus_space_read_1(iot, ioh, INTS),
2074 bus_space_read_1(iot, ioh, PSNS),
2075 bus_space_read_1(iot, ioh, SSTS),
2076 bus_space_read_1(iot, ioh, SERR),
2077 bus_space_read_1(iot, ioh, PCTL));
2078 printf(" MBC=%x DREG=%x TEMP=%x TCH=%x TCM=%x\n",
2079 bus_space_read_1(iot, ioh, MBC),
2080 #if 0
2081 bus_space_read_1(iot, ioh, DREG),
2082 #else
2083 0,
2084 #endif
2085 bus_space_read_1(iot, ioh, TEMP),
2086 bus_space_read_1(iot, ioh, TCH),
2087 bus_space_read_1(iot, ioh, TCM));
2088 printf(" TCL=%x EXBF=%x\n",
2089 bus_space_read_1(iot, ioh, TCL),
2090 bus_space_read_1(iot, ioh, EXBF));
2091 }
2092
2093 void
spc_dump_driver(struct spc_softc * sc)2094 spc_dump_driver(struct spc_softc *sc)
2095 {
2096 struct spc_tinfo *ti;
2097 int i;
2098
2099 printf("nexus=%p prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase);
2100 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x "
2101 "currmsg=%x\n", sc->sc_state, sc->sc_imess[0],
2102 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg);
2103 for (i = 0; i < 7; i++) {
2104 ti = &sc->sc_tinfo[i];
2105 printf("tinfo%d: %d cmds %d disconnects %d timeouts",
2106 i, ti->cmds, ti->dconns, ti->touts);
2107 printf(" %d senses flags=%x\n", ti->senses, ti->flags);
2108 }
2109 }
2110 #endif
2111