1 #ifndef IVL_Module_H 2 #define IVL_Module_H 3 /* 4 * Copyright (c) 1998-2019 Stephen Williams (steve@icarus.com) 5 * 6 * This source code is free software; you can redistribute it 7 * and/or modify it in source code form under the terms of the GNU 8 * General Public License as published by the Free Software 9 * Foundation; either version 2 of the License, or (at your option) 10 * any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 20 */ 21 22 23 # include <list> 24 # include <map> 25 # include <vector> 26 # include <utility> 27 # include "StringHeap.h" 28 # include "HName.h" 29 # include "named.h" 30 # include "PScope.h" 31 # include "PNamedItem.h" 32 # include "netlist.h" 33 # include "pform_types.h" 34 class PExpr; 35 class PEIdent; 36 class PGate; 37 class PGenerate; 38 class PModport; 39 class PSpecPath; 40 class PTask; 41 class PFunction; 42 class PWire; 43 class PProcess; 44 class Design; 45 class NetScope; 46 47 /* 48 * A module is a named container and scope. A module holds a bunch of 49 * semantic quantities such as wires and gates. The module is 50 * therefore the handle for grasping the described circuit. 51 * 52 * SystemVerilog introduces program blocks and interfaces. These have 53 * much in common with modules, so the Module class is used to represent 54 * these containers as well. 55 */ 56 57 class Module : public PScopeExtra, public PNamedItem { 58 59 /* The module ports are in general a vector of port_t 60 objects. Each port has a name and an ordered list of 61 wires. The name is the means that the outside uses to 62 access the port, the wires are the internal connections to 63 the port. */ 64 public: 65 struct port_t { 66 perm_string name; 67 vector<PEIdent*> expr; 68 }; 69 70 public: 71 /* The name passed here is the module name, not the instance 72 name. This name must be a permallocated string. */ 73 explicit Module(LexicalScope*parent, perm_string name); 74 ~Module(); 75 76 /* Initially false. This is set to true if the module has been 77 declared as a library module. This makes the module 78 ineligible for being chosen as an implicit root. It has no 79 other effect. */ 80 bool library_flag; 81 82 bool is_cell; 83 84 /* This is true if the module represents a program block 85 instead of a module/cell. Program blocks have content 86 restrictions and slightly modify scheduling semantics. */ 87 bool program_block; 88 89 /* This is true if the module represents a interface 90 instead of a module/cell. Interfaces have different 91 content restrictions and some extra allowed items. */ 92 bool is_interface; 93 94 enum UCDriveType { UCD_NONE, UCD_PULL0, UCD_PULL1 }; 95 UCDriveType uc_drive; 96 97 /* specparams are simpler than other parameters, in that they 98 can have a range, but not an explicit type. The restrictions 99 are enforced by the parser. */ 100 map<perm_string,param_expr_t*>specparams; 101 102 /* The module also has defparam assignments which don't create 103 new parameters within the module, but may be used to set 104 values within this module (when instantiated) or in other 105 instantiated modules. */ 106 typedef pair<pform_name_t,PExpr*> named_expr_t; 107 list<named_expr_t>defparms; 108 static list<named_expr_t>user_defparms; 109 110 /* Parameters may be overridden at instantiation time; 111 the overrides do not contain explicit parameter names, 112 but rather refer to parameters in the order they 113 appear in the instantiated module. Therefore a 114 list of names in module-order is needed to pass from 115 a parameter-index to its name. */ 116 list<perm_string> param_names; 117 118 /* This is an array of port descriptors, which is in turn a 119 named array of PEident pointers. */ 120 vector<port_t*> ports; 121 122 map<perm_string,PExpr*> attributes; 123 124 /* The module has a list of generate schemes that appear in 125 the module definition. These are used at elaboration time. */ 126 list<PGenerate*> generate_schemes; 127 128 /* Nested modules are placed here, and are not elaborated 129 unless they are instantiated, implicitly or explicitly. */ 130 std::map<perm_string,Module*> nested_modules; 131 132 /* An interface can contain one or more named modport lists. 133 The parser will ensure these don't appear in modules or 134 program blocks. */ 135 map<perm_string,PModport*> modports; 136 137 list<PSpecPath*> specify_paths; 138 139 // The mod_name() is the name of the module type. mod_name()140 perm_string mod_name() const { return pscope_name(); } 141 142 void add_gate(PGate*gate); 143 144 unsigned port_count() const; 145 const vector<PEIdent*>& get_port(unsigned idx) const; 146 unsigned find_port(const char*name) const; 147 148 // Return port name ("" for undeclared port) 149 perm_string get_port_name(unsigned idx) const; 150 151 PGate* get_gate(perm_string name); 152 153 const list<PGate*>& get_gates() const; 154 155 void dump(ostream&out) const; 156 bool elaborate(Design*, NetScope*scope) const; 157 158 typedef map<perm_string,PExpr*> replace_t; 159 bool elaborate_scope(Design*, NetScope*scope, const replace_t&rep); 160 161 bool elaborate_sig(Design*, NetScope*scope) const; 162 163 SymbolType symbol_type() const; 164 165 private: 166 void dump_specparams_(ostream&out, unsigned indent) const; 167 list<PGate*> gates_; 168 169 private: // Not implemented 170 Module(const Module&); 171 Module& operator= (const Module&); 172 }; 173 174 #endif /* IVL_Module_H */ 175