| /dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-pinebook/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-orangepi-pc2/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-orangepi-pc/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-orangepi-one/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-orangepi-pc-plus/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-bananapim2/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-rockpro64/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-rpi4/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-sifive-fu540/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-rpi3-32/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|
| /dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/drivers/phy/marvell/ |
| H A D | comphy_cp110.c | 32 #define COMPHY_FW_FORMAT(mode, idx, speeds) \ argument
35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds) \ argument
|