xref: /netbsd/sys/arch/mips/mips/spl_stubs.c (revision b6907d66)
1 /*	$NetBSD: spl_stubs.c,v 1.3 2011/02/20 16:38:13 rmind Exp $	*/
2 
3 /*-
4  * Copyright (c) 2010 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Matt Thomas <matt@3am-software.com>.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: spl_stubs.c,v 1.3 2011/02/20 16:38:13 rmind Exp $");
34 
35 #define __INTR_PRIVATE
36 
37 #include <sys/param.h>
38 
39 #include <mips/cache.h>
40 #include <mips/intr.h>
41 #include <mips/locore.h>
42 
43 int	splhigh(void)		__section(".stub");
44 int	splhigh_noprof(void)	__section(".stub");
45 int	splsched(void)		__section(".stub");
46 int	splvm(void)		__section(".stub");
47 int	splsoftserial(void)	__section(".stub");
48 int	splsoftnet(void)	__section(".stub");
49 int	splsoftbio(void)	__section(".stub");
50 int	splsoftclock(void)	__section(".stub");
51 int	splraise(int)		__section(".stub");
52 void	splx(int)		__section(".stub");
53 void	splx_noprof(int)	__section(".stub");
54 void	spl0(void)		__section(".stub");
55 int	splintr(uint32_t *)	__section(".stub");
56 void	_setsoftintr(uint32_t)	__section(".stub");
57 void	_clrsoftintr(uint32_t)	__section(".stub");
58 void	splcheck(void)		__section(".stub");
59 
60 int
splhigh(void)61 splhigh(void)
62 {
63 	return (*mips_splsw.splsw_splhigh)();
64 }
65 
66 int
splhigh_noprof(void)67 splhigh_noprof(void)
68 {
69 	return (*mips_splsw.splsw_splhigh_noprof)();
70 }
71 
72 int
splsched(void)73 splsched(void)
74 {
75 	return (*mips_splsw.splsw_splsched)();
76 }
77 
78 int
splvm(void)79 splvm(void)
80 {
81 	return (*mips_splsw.splsw_splvm)();
82 }
83 
84 int
splsoftserial(void)85 splsoftserial(void)
86 {
87 	return (*mips_splsw.splsw_splsoftserial)();
88 }
89 
90 int
splsoftnet(void)91 splsoftnet(void)
92 {
93 	return (*mips_splsw.splsw_splsoftnet)();
94 }
95 
96 int
splsoftbio(void)97 splsoftbio(void)
98 {
99 	return (*mips_splsw.splsw_splsoftbio)();
100 }
101 
102 int
splsoftclock(void)103 splsoftclock(void)
104 {
105 	return (*mips_splsw.splsw_splsoftclock)();
106 }
107 
108 void
spl0(void)109 spl0(void)
110 {
111 	(*mips_splsw.splsw_spl0)();
112 }
113 
114 void
splx(int s)115 splx(int s)
116 {
117 	(*mips_splsw.splsw_splx)(s);
118 }
119 
120 void
splx_noprof(int s)121 splx_noprof(int s)
122 {
123 	(*mips_splsw.splsw_splx_noprof)(s);
124 }
125 
126 int
splraise(int s)127 splraise(int s)
128 {
129         return (*mips_splsw.splsw_splraise)(s);
130 }
131 
132 int
splintr(uint32_t * p)133 splintr(uint32_t *p)
134 {
135 	return (*mips_splsw.splsw_splintr)(p);
136 }
137 
138 void
_setsoftintr(uint32_t m)139 _setsoftintr(uint32_t m)
140 {
141 	(*mips_splsw.splsw__setsoftintr)(m);
142 }
143 
144 void
_clrsoftintr(uint32_t m)145 _clrsoftintr(uint32_t m)
146 {
147 	(*mips_splsw.splsw__clrsoftintr)(m);
148 }
149 
150 void
splcheck(void)151 splcheck(void)
152 {
153 	(*mips_splsw.splsw_splcheck)();
154 }
155