1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #pragma once 25 26 #include <nvtypes.h> 27 28 // 29 // This file was generated with FINN, an NVIDIA coding tool. 30 // Source file: ctrl/ctrl30f1.finn 31 // 32 33 #include "ctrl/ctrlxxxx.h" 34 /* NV30_GSYNC_CTRL control commands and parameters */ 35 36 #define NV30F1_CTRL_CMD(cat,idx) NVXXXX_CTRL_CMD(0x30F1, NV30F1_CTRL_##cat, idx) 37 38 /* Command categories (6bits) */ 39 #define NV30F1_CTRL_RESERVED (0x00) 40 #define NV30F1_CTRL_GSYNC (0x01) 41 42 /* 43 * NV30F1_CTRL_CMD_NULL 44 * 45 * This command does nothing. 46 * This command does not take any parameters. 47 * 48 * Possible status values returned are: 49 * NV_OK 50 */ 51 #define NV30F1_CTRL_CMD_NULL (0x30f10000) /* finn: Evaluated from "(FINN_NV30_GSYNC_RESERVED_INTERFACE_ID << 8) | 0x0" */ 52 53 54 55 56 57 /* NV30F1_CTRL_GSYNC 58 * 59 * Gsync board access/control functionality. 60 * 61 */ 62 63 /* 64 * NV30F1_CTRL_CMD_GSYNC_GET_VERSION 65 * 66 * This command will get the current gsync api version info. 67 * 68 * version 69 * The api's major version. Does not change often. 70 * 71 * revision 72 * The api's minor version. 73 * Bumped with each change, no matter how minor. 74 * 75 * Possible status values returned are: 76 * NV_OK 77 * 78 */ 79 #define NV30F1_CTRL_CMD_GSYNC_GET_VERSION (0x30f10101) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS_MESSAGE_ID" */ 80 81 #define NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS_MESSAGE_ID (0x1U) 82 83 typedef struct NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS { 84 NvU32 version; 85 NvU32 revision; 86 } NV30F1_CTRL_GSYNC_GET_VERSION_PARAMS; 87 88 #define NV30F1_CTRL_GSYNC_API_VER 1 89 #define NV30F1_CTRL_GSYNC_API_REV 0 90 91 /* 92 * NV30F1_CTRL_GSYNC api 93 * 94 * The gsync interface provides access to gsync devices in the system. 95 * 96 * There are commands: 97 * NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SIGNALS 98 * Status on input sync signals. 99 * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_PARAMS 100 * Get gsync parameters. 101 * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS 102 * Get gsync parameters. 103 * NV30F1_CTRL_CMD_GSYNC_GET_INFO_CAPS 104 * Get basic info about the device and its connected displays 105 * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SYNC 106 * Enable frame sync. 107 * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_UNSYNC 108 * Disable frame sync. 109 * NV30F1_CTRL_CMD_GSYNC_GET_STATUS 110 * Get status info relevant for the control panel 111 * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_TESTING 112 * Test signal enabling/disabling 113 * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_WATCHDOG 114 * Control the gsync watchdog 115 * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_INTERLACE_MODE 116 * Set the interlace mode 117 * 118 */ 119 120 121 /* 122 * NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SIGNALS 123 * 124 * This command returns information associated with incoming signals to the 125 * gsync device. 126 * 127 * RJ45 128 * This parameter contains the signal information for each of the two RJ45 129 * ports on the gsync device. A value of ~0 indicates that a signal is 130 * detected, but no rate information is available. Anything else is a rate 131 * in units of 10e-4 Hz. 132 * house 133 * This parameter contains the signal information for the house sync signal 134 * (i.e. the bnc port). A value of 0 means that no signal is present. A value 135 * of ~0 indicates that a signal is detected, but no rate information is 136 * available. Anything else is a rate in units of 10e-4 Hz. 137 * rate 138 * A mask representing signals for which we would like rate information (if 139 * available). 140 * 141 * Possible status values returned are 142 * NV_OK 143 * NV_ERR_INVALID_ARGUMENT 144 * NV_ERR_INVALID_PARAM_STRUCT 145 * 146 */ 147 148 #define NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SIGNALS (0x30f10102) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS_MESSAGE_ID" */ 149 150 #define NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS_MESSAGE_ID (0x2U) 151 152 typedef struct NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS { 153 NvU32 RJ45[2]; 154 NvU32 house; 155 NvU32 rate; 156 } NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_PARAMS; 157 158 /* 159 * rate values 160 * 161 */ 162 163 #define NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_RJ45_0 (0x00000001) 164 #define NV30F1_CTRL_GSYNC_GET_STATUS_SIGNALS_RJ45_1 (0x00000002) 165 #define NV30F1_CTRL_GSYNC_GET_SIGNALS_HOUSE (0x00000004) 166 167 168 /* 169 * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_PARAMS 170 * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS 171 * 172 * These commands respectively return and set state related to the operation 173 * of the gsync device. 174 * 175 * which 176 * This value is a mask set by the client representing which parameters are 177 * to be updated. In the case of a GET command, these parameters will 178 * be used to change the state of the hardware. For both a GET 179 * command and a SET command, the hardware state will be returned by 180 * the RM in the respective parameter. All other parameters are untouched. 181 * syncPolarity 182 * This parameter specifies which edge of the house sync signal to sync with. 183 * videoMode 184 * This parameter specifies which video mode to use to decode the house sync 185 * signal. 186 * nSync 187 * This parameter specifies the number of pulses to wait between frame lock 188 * signal generation. 0 indicates that every incomming pulse should result in 189 * a frame lock sync pulse being generated (i.e. the input and output rate 190 * matches). 191 * syncSkew 192 * This parameter specifies the time delay between the frame sync signal and 193 * the GPUs signal in units of 0.977 us. Maximum value for SyncSkew is defined 194 * in respective header files of gsync boards. e.g. For P2060 board value 195 * is defined in drivers/resman/kernel/inc/dacp2060.h 196 * syncStartDelay 197 * In master mode, the amount of time to wait before generating the first 198 * sync pulse in units of 7.81 us, max 512 ms (i.e 65535 units). 199 * useHouseSync 200 * When a house sync signal is detected, this parameter indicates that it 201 * should be used as the reference to generate the frame sync signal. 202 * syncMulDiv 203 * Enables multiply/divide of the frequency of the house sync signal by an 204 * integer. Only supported if the 205 * NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_MULTIPLY_DIVIDE_SYNC bit is set. The 206 * maximum value of multiplyDivideValue is given by 207 * NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS.maxMulDivValue. 208 * 209 * Possible status values returned are: 210 * NV_OK 211 * NV_ERR_INVALID_ARGUMENT 212 * NV_ERR_GENERIC 213 */ 214 215 #define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_PARAMS (0x30f10103) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS_MESSAGE_ID" */ 216 217 #define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_PARAMS (0x30f10104) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS_MESSAGE_ID" */ 218 219 typedef struct NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS { 220 NvU8 multiplyDivideValue; 221 NvU8 multiplyDivideMode; 222 NvU16 rsvd; 223 } NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS; 224 225 typedef struct NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS { 226 NvU32 which; 227 NvU32 syncPolarity; 228 NvU32 syncVideoMode; 229 NvU32 nSync; 230 NvU32 syncSkew; 231 NvU32 syncStartDelay; 232 NvU32 useHouseSync; 233 NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS syncMulDiv; 234 } NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS; 235 236 #define NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS_MESSAGE_ID (0x3U) 237 238 typedef NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_PARAMS_PARAMS; 239 240 #define NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS_MESSAGE_ID (0x4U) 241 242 typedef NV30F1_CTRL_GSYNC_CONTROL_PARAMS_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_PARAMS_PARAMS; 243 244 /* 245 * which values 246 * 247 */ 248 249 #define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY 0x0001 250 #define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE 0x0002 251 #define NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC 0x0004 252 #define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW 0x0008 253 #define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY 0x0010 254 #define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE 0x0020 255 #define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE 0x0040 256 257 #define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_POLARITY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY 258 #define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE 259 #define NV30F1_CTRL_GSYNC_GET_CONTROL_NSYNC NV30F1_CTRL_GSYNC_SET_CONTROL_NSYNC 260 #define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_SKEW NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_SKEW 261 #define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_START_DELAY NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_START_DELAY 262 #define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_USE_HOUSE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_USE_HOUSE 263 #define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_MULTIPLY_DIVIDE NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_MULTIPLY_DIVIDE 264 265 /* 266 * syncPolarity values 267 * 268 */ 269 270 #define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_RISING_EDGE 0 271 #define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_FALLING_EDGE 1 272 #define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_POLARITY_BOTH_EDGES 2 273 274 /* 275 * syncVideoMode values 276 * Video_Mode_Composite is valid for P2060 only. 277 * 278 */ 279 280 #define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE 0 281 #define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL 1 282 #define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM 2 283 #define NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV 3 284 285 #define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NONE NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NONE 286 #define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_TTL NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_TTL 287 #define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_NTSCPALSECAM NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_NTSCPALSECAM 288 #define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_HDTV NV30F1_CTRL_GSYNC_SET_CONTROL_VIDEO_MODE_HDTV 289 #define NV30F1_CTRL_GSYNC_GET_CONTROL_VIDEO_MODE_COMPOSITE 4 290 291 /* 292 * multiplyDivide values 293 * 294 */ 295 #define NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_MULTIPLY 0 296 #define NV30F1_CTRL_GSYNC_SET_CONTROL_MULTIPLY_DIVIDE_MODE_DIVIDE 1 297 298 /* 299 * NV30F1_CTRL_CMD_GSYNC_GET_CAPS 300 * 301 * This command returns the capabilities of this gsync device. 302 * 303 * revId 304 * This parameter is set by the RM to indicate the combined 305 * FPGA revision (low 4 bits) and board ID (high 4 bits). 306 * 307 * boardId 308 * This parameter is set by the RM to indicate the board ID, 309 * allowing disambiguation of P2060 and so forth. 310 * 311 * minRevRequired 312 * This parameter is set by the RM to indicate the minimum 313 * Qsync FPGA revision required for a specific CHIP Familiy 314 * 315 * isFirmwareRevMismatch 316 * This parameter is set to TRUE by RM when the Qsync Firmware 317 * Revision is incompatibled with the connected GPU chip family. 318 * 319 * revision 320 * This parameter is set by the RM to indicate the device revision, 321 * also known as major version. 322 * 323 * extendedRevision 324 * This parameter is set by the RM to indicate the device extended 325 * revision, also known as minor version. 326 * 327 * capFlags 328 * This parameter is set by the RM to indicate capabilities of 329 * the board, preventing the client from needing to keep track 330 * of the feature lists supported by each revision of each board. 331 * 332 * maxSyncSkew 333 * This parameter returns that maximum units of sync skew the 334 * board supports. The value prgrammed into the board has to be 335 * between 0 and maxSyncSkew, inclusive. The value of each unit 336 * can be learned from the syncSkewResolution parameter. 337 * 338 * syncSkewResolution 339 * This parameter returns the number of nanoseconds that one unit 340 * of sync skew corresponds to. 341 * 342 * maxStartDelay 343 * This parameter returns that maximum units of sync start delay 344 * the board supports. The value prgrammed into the board has to be 345 * between 0 and maxStartDelay, inclusive. The value of each unit 346 * can be learned from the startDelayResolution parameter. 347 * 348 * startDelayResolution 349 * This parameter returns the number of nanoseconds that one unit 350 * of sync start delay corresponds to. 351 * 352 * maxSyncInterval 353 * This parameter returns the maximum duration of house sync interval 354 * between frame lock sync cycle that the board supports. The value 355 * programmed into the board has to be between 0 and maxSyncInterval, 356 * inclusive. 357 * 358 * maxMulDivValue 359 * This parameter returns the maximum possible value that can be 360 * programmed for multiplying / dividing house sync. Only valid if 361 * NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_MULTIPLY_DIVIDE_SYNC is set. 362 * 363 * Possible status values returned are: 364 * NV_OK 365 * NV_ERR_GENERIC 366 * NV_ERR_INVALID_ARGUMENT 367 */ 368 369 #define NV30F1_CTRL_CMD_GSYNC_GET_CAPS (0x30f10105) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID" */ 370 371 #define NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS_MESSAGE_ID (0x5U) 372 373 typedef struct NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS { 374 NvU32 revId; 375 NvU32 boardId; 376 NvU32 minRevRequired; 377 NvBool isFirmwareRevMismatch; 378 NvU32 revision; 379 NvU32 extendedRevision; 380 NvU32 capFlags; 381 NvU32 maxSyncSkew; 382 NvU32 syncSkewResolution; 383 NvU32 maxStartDelay; 384 NvU32 startDelayResolution; 385 NvU32 maxSyncInterval; 386 NvU32 maxMulDivValue; 387 } NV30F1_CTRL_GSYNC_GET_CAPS_PARAMS; 388 389 #define NV30F1_CTRL_GSYNC_GET_CAPS_BOARD_ID_P2060 (0x00002060) 390 #define NV30F1_CTRL_GSYNC_GET_CAPS_BOARD_ID_P2061 (0x00002061) 391 392 #define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FREQ_ACCURACY_2DPS (0x00000001) 393 #define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FREQ_ACCURACY_3DPS (0x00000002) 394 #define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FREQ_ACCURACY_4DPS (0x00000004) 395 396 #define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_NEED_MASTER_BARRIER_WAR (0x00000010) 397 #define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_MULTIPLY_DIVIDE_SYNC (0x00000020) 398 399 #define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_SYNC_LOCK_EVENT (0x10000000) 400 #define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_HOUSE_SYNC_EVENT (0x20000000) 401 #define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_FRAME_COUNT_EVENT (0x40000000) 402 403 #define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_ONLY_PRIMARY_CONNECTOR_EVENT (0x01000000) 404 #define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_ALL_CONNECTOR_EVENT (0x02000000) 405 406 // For P2060, clients can only request for video modes at BNC connector 407 // e.g. NO HS, TTL and Composite etc. 408 #define NV30F1_CTRL_GSYNC_GET_CAPS_CAP_FLAGS_ONLY_GET_VIDEO_MODE (0x00100000) 409 410 /* 411 * NV30F1_CTRL_CMD_GET_GSYNC_GPU_TOPOLOGY 412 * 413 * This command returns the list of GPU IDs connected with the associated 414 * gsync device. 415 * 416 * gpus 417 * This array is set by RM to contain the gpu connection information 418 * for gpus attached to the gsync device. Valid entries are contiguous, 419 * beginning with the first entry in the list. The elements of this array contain 420 * the following fields: 421 * gpuId 422 * This field contains the ID of the connected GPU. If the entry in the 423 * table is invalid, this fields contains NV30F1_CTRL_GPU_INVALID_ID. 424 * connector 425 * This field indicates which connector on the device the GPU is connected 426 * to (i.e. the primary or secondary connector), if any. 427 * proxyGpuId 428 * If the 'connector' field indicates that the GPU is not connected to 429 * a G-Sync device directly, then this field contains the ID of the 430 * GPU that acts as a proxy, i.e. the GPU to which this GPU should be 431 * a RasterLock slave. 432 * connectorCount 433 * This parameter indicates the number of GPU connectors available on 434 * the gsync device. The connector count of the gsync device may be 435 * less than NV30F1_CTRL_MAX_GPUS_PER_GSYNC. 436 * 437 * Possible status values returned are: 438 * NV_OK 439 * NV_ERR_INVALID_PARAM_STRUCT 440 */ 441 #define NV30F1_CTRL_CMD_GET_GSYNC_GPU_TOPOLOGY (0x30f10106) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS_MESSAGE_ID" */ 442 443 #define NV30F1_CTRL_MAX_GPUS_PER_GSYNC 4 444 #define NV30F1_CTRL_GPU_INVALID_ID (0xffffffff) 445 446 #define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS_MESSAGE_ID (0x6U) 447 448 typedef struct NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS { 449 struct { 450 NvU32 gpuId; 451 NvU32 connector; 452 NvU32 proxyGpuId; 453 } gpus[NV30F1_CTRL_MAX_GPUS_PER_GSYNC]; 454 NvU32 connectorCount; 455 } NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PARAMS; 456 457 /* 458 * connector values 459 * 460 */ 461 #define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_ONE 1 462 #define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_TWO 2 463 #define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_THREE 3 464 #define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_FOUR 4 465 466 #define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_NONE 0 467 #define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_PRIMARY NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_ONE 468 #define NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_SECONDARY NV30F1_CTRL_GET_GSYNC_GPU_TOPOLOGY_TWO 469 470 471 472 473 /* 474 * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SYNC 475 * 476 * This command enables frame sync on displays. 477 * 478 * gpuId 479 * The parameter is set by the client to indicate the gpuId on which 480 * frame lock will be enabled. 481 * master 482 * This parameter is set by the client to specify whether this/these 483 * displays should be set as the master or as slaves. If this is a GET 484 * and displays is not 0, this will be set by the RM to indicate if 485 * the display can be the master. 486 * displays 487 * This is a device mask set by the client to indicate which display(s) 488 * are to be synched. Note that only one display may be set as master. 489 * If this is a GET, this set by the client to indicate which display 490 * is to be queried. If the display cannot be synched to this device, 491 * the RM will overwrite the mask with a 0. 492 * validateExternal 493 * This parameter is set by the client to tell the RM to validate the 494 * presence of an external sync source when enabling a master. 495 * refresh 496 * This parameter is set by the client to indicate the desired refresh rate 497 * The value is in 0.0001 Hertz (i.e. it has been multiplied by 10000). 498 * configFlags 499 * contains flags for specific options. So far only 500 * NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_CONFIG_FLAGS_KEEP_MASTER_SWAPBARRIER_DISABLED 501 * is supported which allows the caller to prevent the rm code to automatically 502 * enable the swapbarrier on framelock masters on fpga revisions <= 5. 503 * 504 * Possible status values returned are: 505 * NV_OK 506 * NV_ERR_GENERIC 507 * NV_ERR_INVALID_ARGUMENT 508 * 509 */ 510 #define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SYNC (0x30f10110) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS_MESSAGE_ID" */ 511 512 #define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SYNC (0x30f10111) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS_MESSAGE_ID" */ 513 514 // If set the swapbarrier is not enable automatically when enablign a framelock master on fpga revs <= 5. 515 #define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_CONFIG_FLAGS_KEEP_MASTER_SWAPBARRIER_DISABLED (0x00000001) 516 517 typedef struct NV30F1_CTRL_GSYNC_CONTROL_SYNC_PARAMS { 518 NvU32 gpuId; 519 NvU32 master; 520 NvU32 displays; 521 NvU32 validateExternal; 522 NvU32 refresh; 523 NvU32 configFlags; 524 } NV30F1_CTRL_GSYNC_CONTROL_SYNC_PARAMS; 525 526 #define NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS_MESSAGE_ID (0x10U) 527 528 typedef NV30F1_CTRL_GSYNC_CONTROL_SYNC_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_SYNC_PARAMS; 529 530 #define NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS_MESSAGE_ID (0x11U) 531 532 typedef NV30F1_CTRL_GSYNC_CONTROL_SYNC_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_SYNC_PARAMS; 533 534 /* 535 * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_UNSYNC 536 * 537 * This command disables frame sync on displays 538 * 539 * gpuId 540 * The parameter is set by the client to indicate the gpuId on which 541 * frame lock will be disabled. 542 * master 543 * This parameter is set by the client to specify whether this/these 544 * display(s) to be unset is a master/are slaves. 545 * displays 546 * This is a device mask set by the client to indicate which display(s) 547 * are to be unsynched. 548 * retainMaster 549 * Retain the designation as master, but unsync the displays. 550 * 551 * Possible status values returned are: 552 * NV_OK 553 * NV_ERR_GENERIC 554 * NV_ERR_INVALID_ARGUMENT 555 */ 556 #define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_UNSYNC (0x30f10112) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS_MESSAGE_ID" */ 557 558 #define NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS_MESSAGE_ID (0x12U) 559 560 typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS { 561 NvU32 gpuId; 562 NvU32 master; 563 NvU32 displays; 564 NvU32 retainMaster; 565 } NV30F1_CTRL_GSYNC_SET_CONTROL_UNSYNC_PARAMS; 566 567 /* 568 * NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SYNC 569 * 570 * This command gets the sync state for the gpus attached to the 571 * framelock device. Note that the frame lock device only has 572 * knowledge of sync status at the gpu level, not the display 573 * device level. 574 * 575 * gpuId 576 * The parameter is set by the client to indicate which gpuId is to be 577 * queried. 578 * bTiming 579 * This parameter is set by the RM to indicate that timing on the GPU is 580 * in sync with the master sync signal. 581 * bStereoSync 582 * This parameter is set by the RM to indicate whether the phase of the 583 * timing signal coming from the GPU is the same as the phase of the 584 * master sync signal. 585 * bSyncReady 586 * This parameter is set by the RM to indicate if a sync signal has 587 * been detected. 588 * 589 * 590 * Possible status values returned are: 591 * NV_OK 592 * NV_ERR_GENERIC 593 * NV_ERR_INVALID_ARGUMENT 594 * 595 */ 596 597 #define NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SYNC (0x30f10113) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS_MESSAGE_ID" */ 598 599 #define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS_MESSAGE_ID (0x13U) 600 601 typedef struct NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS { 602 NvU32 gpuId; 603 NvU32 bTiming; 604 NvU32 bStereoSync; 605 NvU32 bSyncReady; 606 } NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_PARAMS; 607 608 609 /* 610 * NV30F1_CTRL_CMD_GSYNC_GET_STATUS 611 * 612 * This command gets status information for the frame lock device 613 * relevant to a control panel. 614 * 615 * which 616 * This is a mask set by the client describing which of the other 617 * parameters we should collect status information for. 618 * bLeadingEdge 619 * This parameter is set by the RM to indicate that the gsync device is 620 * set to sync to the leading edge of a house sync signal. Note that 621 * this does not mean that house sync is the signal source. 622 * bFallingEdge 623 * This parameter is set by the RM to indicate that the gsync device is 624 * set to sync to the falling edge of a house sync signal. Note that 625 * this does not mean that house sync is the signal source. 626 * syncDelay 627 * This parameter is set by the RM to indicate the sync delay in 628 * microseconds, 629 * refresh 630 * This parameter is set by the RM to indicate the rate of frame sync pulse in 631 * 0.0001 Hertz (i.e. it has been multiplied by 10000). This is not the refresh 632 * rate of display device. This is same as incoming house sync rate if 633 * framelocked to an external house sync signal. Otherwise, this is same 634 * as the refresh rate of the master display device. 635 * houseSyncIncomming 636 * This parameter is set by the RM to indicate the rate of an incomming 637 * house sync signal in 0.0001 Hertz (i.e. it has been multiplied by 10000). 638 * syncInterval 639 * This parameter is set by the RM to indicate the number of incoming 640 * sync pulses to wait before the generation of the frame sync pulse. 641 * bSyncReady 642 * This paramater is set by the RM to indicate if a sync signal has 643 * been detected (this parameter is also available from the 644 * NV30F1_CTRL_CMD_GSYNC_GET_STATUS_SYNC method). 645 * bSwapReady 646 * This paramater is set by the RM to indicate if the hardware is 647 * ready to swap. 648 * bHouseSync 649 * This parameter is set by the RM to indicate that a house sync signal 650 * should be used as the source signal if it is available. 651 * bPort0Input 652 * This parameter is set by the RM to indicate that RJ45 port 0 is 653 * configured as an input. 654 * bPort1Input 655 * This parameter is set by the RM to indicate that RJ45 port 1 is 656 * configured as an input 657 * bPort0Ehternet 658 * This parameter is set by the RM to indicate that RJ45 port 0 has 659 * been connected to an ethernet hub (this is not the right thing to do). 660 * bPort1Ehternet 661 * This parameter is set by the RM to indicate that RJ45 port 1 has 662 * been connected to an ethernet hub (this is not the right thing to do). 663 * universalFrameCount 664 * This parameter is set by the RM to indicate the value of the 665 * Universal frame counter. 666 * bInternalSlave 667 * This parameter is set by the RM to indicate that a p2061 has been 668 * configured as internal slave. 669 * 670 * Possible status values returned are: 671 * NV_OK 672 * NV_ERR_GENERIC 673 * NV_ERR_INVALID_ARGUMENT 674 * 675 */ 676 #define NV30F1_CTRL_CMD_GSYNC_GET_STATUS (0x30f10114) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS_MESSAGE_ID" */ 677 678 #define NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS_MESSAGE_ID (0x14U) 679 680 typedef struct NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS { 681 NvU32 which; 682 NvU32 bLeadingEdge; 683 NvU32 bFallingEdge; 684 NvU32 syncDelay; 685 NvU32 refresh; 686 NvU32 houseSyncIncoming; 687 NvU32 syncInterval; 688 NvU32 bSyncReady; 689 NvU32 bSwapReady; 690 NvU32 bHouseSync; 691 NvU32 bPort0Input; 692 NvU32 bPort1Input; 693 NvU32 bPort0Ethernet; 694 NvU32 bPort1Ethernet; 695 NvU32 universalFrameCount; 696 NvU32 bInternalSlave; 697 } NV30F1_CTRL_GSYNC_GET_STATUS_PARAMS; 698 699 /* 700 * which values 701 * 702 */ 703 704 #define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_POLARITY (0x00000001) 705 #define NV30F1_CTRL_GSYNC_GET_STATUS_LEADING_EDGE (0x00000001) 706 #define NV30F1_CTRL_GSYNC_GET_STATUS_FALLING_EDGE (0x00000001) 707 #define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_DELAY (0x00000002) 708 #define NV30F1_CTRL_GSYNC_GET_STATUS_REFRESH (0x00000004) 709 #define NV30F1_CTRL_GSYNC_GET_STATUS_HOUSE_SYNC_INCOMING (0x00000008) 710 #define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_INTERVAL (0x00000010) 711 #define NV30F1_CTRL_GSYNC_GET_STATUS_SYNC_READY (0x00000020) 712 #define NV30F1_CTRL_GSYNC_GET_STATUS_SWAP_READY (0x00000040) 713 #define NV30F1_CTRL_GSYNC_GET_STATUS_TIMING (0x00000080) 714 #define NV30F1_CTRL_GSYNC_GET_STATUS_STEREO_SYNC (0x00000100) 715 #define NV30F1_CTRL_GSYNC_GET_STATUS_HOUSE_SYNC (0x00000200) 716 #define NV30F1_CTRL_GSYNC_GET_STATUS_PORT_INPUT (0x00000400) 717 #define NV30F1_CTRL_GSYNC_GET_STATUS_PORT0_INPUT (0x00000400) 718 #define NV30F1_CTRL_GSYNC_GET_STATUS_PORT1_INPUT (0x00000400) 719 #define NV30F1_CTRL_GSYNC_GET_STATUS_PORT_ETHERNET (0x00000800) 720 #define NV30F1_CTRL_GSYNC_GET_STATUS_PORT0_ETHERNET (0x00000800) 721 #define NV30F1_CTRL_GSYNC_GET_STATUS_PORT1_ETHERNET (0x00000800) 722 #define NV30F1_CTRL_GSYNC_GET_STATUS_UNIVERSAL_FRAME_COUNT (0x00001000) 723 #define NV30F1_CTRL_GSYNC_GET_STATUS_INTERNAL_SLAVE (0x00002000) 724 725 /* 726 * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_TESTING 727 * 728 * This command controls the test signal on the gsync device. 729 * 730 * bEmitTestSignal 731 * This parameter is set by the client to emit or stop emitting the test 732 * signal. 733 * 734 * Possible status values returned are: 735 * NV_OK 736 * NV_ERR_GENERIC 737 * NV_ERR_INVALID_ARGUMENT 738 */ 739 #define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_TESTING (0x30f10120) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS_MESSAGE_ID" */ 740 741 #define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_TESTING (0x30f10121) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS_MESSAGE_ID" */ 742 743 typedef struct NV30F1_CTRL_GSYNC_CONTROL_TESTING_PARAMS { 744 NvU32 bEmitTestSignal; 745 } NV30F1_CTRL_GSYNC_CONTROL_TESTING_PARAMS; 746 747 #define NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS_MESSAGE_ID (0x20U) 748 749 typedef NV30F1_CTRL_GSYNC_CONTROL_TESTING_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_TESTING_PARAMS; 750 751 #define NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS_MESSAGE_ID (0x21U) 752 753 typedef NV30F1_CTRL_GSYNC_CONTROL_TESTING_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_TESTING_PARAMS; 754 755 /* 756 * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_WATCHDOG 757 * 758 * This command enables and disables the gsync watchdog 759 * 760 * enable 761 * This parameter is set by the client to enable or disable the 762 * gsync watchdog. 763 * 764 * Possible status values returned are: 765 * NV_OK 766 * NV_ERR_GENERIC 767 * NV_ERR_INVALID_ARGUMENT 768 */ 769 #define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_WATCHDOG (0x30f10130) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS_MESSAGE_ID" */ 770 771 #define NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS_MESSAGE_ID (0x30U) 772 773 typedef struct NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS { 774 NvU32 enable; 775 } NV30F1_CTRL_GSYNC_SET_CONTROL_WATCHDOG_PARAMS; 776 777 778 /* 779 * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_INTERLACE_MODE 780 * 781 * This command enables or disables interlace mode. 782 * 783 * enable 784 * This parameter is set by the client to enable or disable 785 * interlace mode 786 * 787 * Possible status values returned are: 788 * NV_OK 789 * NV_ERR_GENERIC 790 * NV_ERR_INVALID_ARGUMENT 791 * 792 */ 793 #define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_INTERLACE_MODE (0x30f10140) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID" */ 794 795 #define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_INTERLACE_MODE (0x30f10141) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID" */ 796 797 typedef struct NV30F1_CTRL_GSYNC_CONTROL_INTERLACE_MODE_PARAMS { 798 NvU32 enable; 799 } NV30F1_CTRL_GSYNC_CONTROL_INTERLACE_MODE_PARAMS; 800 801 #define NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID (0x40U) 802 803 typedef NV30F1_CTRL_GSYNC_CONTROL_INTERLACE_MODE_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_INTERLACE_MODE_PARAMS; 804 805 #define NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS_MESSAGE_ID (0x41U) 806 807 typedef NV30F1_CTRL_GSYNC_CONTROL_INTERLACE_MODE_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_INTERLACE_MODE_PARAMS; 808 809 /* 810 * 811 * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_BARRIER 812 * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SWAP_BARRIER 813 * 814 * These commands enables or disables the swap barrier 815 * connection between a GPU and the rest of the gsync 816 * network 817 * 818 * gpuId 819 * The parameter is set by the client to indicate which gpuId is to be 820 * queried. 821 * enable 822 * In a set command, this parameter is set by the client to 823 * indicate if the barrier should be enabled (i.e. connected 824 * to the rest of the network) or disabled (disconnected). 825 * In both a set and a get command, if successful, the RM 826 * uses this parameter to return the current (i.e. post-set) 827 * value. 828 * 829 * Possible status values returned are: 830 * NV_OK 831 * NV_ERR_GENERIC 832 * NV_ERR_INVALID_ARGUMENT 833 * 834 */ 835 #define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_BARRIER (0x30f10150) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID" */ 836 837 #define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_SWAP_BARRIER (0x30f10151) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID" */ 838 839 typedef struct NV30F1_CTRL_GSYNC_CONTROL_SWAP_BARRIER_PARAMS { 840 NvU32 gpuId; 841 NvBool enable; 842 } NV30F1_CTRL_GSYNC_CONTROL_SWAP_BARRIER_PARAMS; 843 844 #define NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID (0x50U) 845 846 typedef NV30F1_CTRL_GSYNC_CONTROL_SWAP_BARRIER_PARAMS NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_BARRIER_PARAMS; 847 848 #define NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS_MESSAGE_ID (0x51U) 849 850 typedef NV30F1_CTRL_GSYNC_CONTROL_SWAP_BARRIER_PARAMS NV30F1_CTRL_GSYNC_SET_CONTROL_SWAP_BARRIER_PARAMS; 851 852 /* 853 * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW 854 * 855 * This command allow clients to obtain time period for which SwapLock window will 856 * remain HIGH for GSYNC III (P2060) i.e. TswapRdyHi. RM clients will use this value 857 * for programming SWAP_LOCKOUT_START on all heads of GPU connected to P2060. 858 * 859 * tSwapRdyHi 860 * RM will return swap lock window High time period in this variable. By default 861 * tSwapRdyHi is 250 micro seconds. RM also provide regkey to change this value. 862 * tSwapRdyHi also used by RM to configure value of LSR_MIN_TIME while programming 863 * swap barrier. 864 * Client should consider tSwapRdyHi only for Gsync III (P2060) network. 865 * 866 * Possible status values returned are: 867 * NV_OK 868 * NV_ERR_GENERIC 869 */ 870 #define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW (0x30f10153) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS_MESSAGE_ID" */ 871 872 #define NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS_MESSAGE_ID (0x53U) 873 874 typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS { 875 NvU32 tSwapRdyHi; 876 } NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS; 877 878 879 /* 880 * NV30F1_CTRL_CMD_GSYNC_GET_OPTIMIZED_TIMING 881 * 882 * This command allows the client to obtain suggested 883 * adjustments to vertical and horizontal timing values 884 * that will improve the ability of gsync to lock. 885 * 886 * gpuId 887 * This parameter is set by the client to indicate the 888 * gpuId of the GPU to which the display to be optimized 889 * is attached. 890 * output 891 * This parameter is set by the client to indicate the 892 * output resource type of the display to be optimized. 893 * For example, CRTs use DAC output, while DFPs use SOR 894 * (Serial Output Resource) type. 895 * protocol 896 * This parameter is set by the client to indicate the 897 * data protocol of output resource. For DAC displays, 898 * the format of the standard mode most closely matching 899 * the desired mode is used. For SOR display devices, 900 * the LVDS/TMDS/etc format is the protocol. 901 * structure 902 * This parameter is set by the client to indicate the 903 * raster structure of the mode, either progressive or 904 * interlaced. Diagrams of the raster structures are 905 * provided below. 906 * adjust 907 * This parameter is set by the client to specify which 908 * of the timing values, other than hTotal and vTotal, 909 * may be adjusted during optimization. 910 * If the client does not obtain instructions from the 911 * user about where adjustments should be applied, safe 912 * default values for progressive/interlaced modes are 913 * provided below. 914 * hTotal 915 * This parameter is set by the client to specify the 916 * initial Horizontal Pixel Total, from which the 917 * RM will begin optimizing. The RM also uses the 918 * parameter to return the optimized value. 919 * vTotal 920 * This parameter is set by the client to specify the 921 * initial Vertical Pixel Total, from which the 922 * RM will begin optimizing. The RM also uses the 923 * parameter to return the optimized value. 924 * hBlankStart 925 * This parameter is set by the client to specify the 926 * initial Horizontal Blanking Start, from which the 927 * RM will begin optimizing. The RM also uses the 928 * parameter to return the optimized value. 929 * vBlankStart 930 * This parameter is set by the client to specify the 931 * initial Vertical Blanking Start, from which the 932 * RM will begin optimizing. The RM also uses the 933 * parameter to return the optimized value. 934 * hBlankEnd 935 * This parameter is set by the client to specify the 936 * initial Horizontal Blanking End, from which the 937 * RM will begin optimizing. The RM also uses the 938 * parameter to return the optimized value. 939 * vBlankEnd 940 * This parameter is set by the client to specify the 941 * initial Vertical Blanking End, from which the 942 * RM will begin optimizing. The RM also uses the 943 * parameter to return the optimized value. 944 * vInterlacedBlankStart 945 * This parameter is set by the client to specify the 946 * initial Interlaced Vertical Blanking Start, from 947 * which the RM will begin optimizing. The RM will 948 * ignore this parameter for non-interlaced modes, as 949 * it has no meaning in those modes. In modes where 950 * it is meaningful, the RM also uses the parameter 951 * to return the optimized value. 952 * vInterlacedBlankEnd 953 * This parameter is set by the client to specify the 954 * initial Interlaced Vertical Blanking End, from 955 * which the RM will begin optimizing. The RM will 956 * ignore this parameter for non-interlaced modes, as 957 * it has no meaning in those modes. In modes where 958 * it is meaningful, the RM also uses the parameter 959 * to return the optimized value. 960 * hSyncEnd 961 * This parameter is set by the client to specify the 962 * initial Horizontal Raster Sync End, from which the 963 * RM will begin optimizing. The RM also uses the 964 * parameter to return the optimized value. 965 * vSyncEnd 966 * This parameter is set by the client to specify the 967 * initial Vertical Raster Sync End, from which the 968 * RM will begin optimizing. The RM also uses the 969 * parameter to return the optimized value. 970 * hDeltaStep 971 * This parameter is set by the client to specify the 972 * increments by which the Horizontal Pixel Total may 973 * be adjusted by the RM, during optimization. 974 * If the client does not obtain a custom value for 975 * this parameter from the user, setting all four of 976 * hDeltaStep, vDeltaStep, hDeltaMax, and vDeltaMax 977 * to zero will result in a safe default for all four. 978 * vDeltaStep 979 * This parameter is set by the client to specify the 980 * increments by which the vertical timings of each 981 * frame (in interlaced modes, each field) may be 982 * adjusted by the RM, during optimization. 983 * In interlaced modes, the adjustments to vTotal, 984 * vInterlacedBlankStart, and vInterlacedBlankEnd may 985 * be in increments of vDeltaStep or twice vDeltaStep, 986 * depending on where adjustments are made. 987 * In progressive modes, the adjustment to the vTotal 988 * will simply be in increments of vDeltaStep. 989 * If the client does not obtain a custom value for 990 * this parameter from the user, setting all four of 991 * hDeltaStep, vDeltaStep, hDeltaMax, and vDeltaMax 992 * to zero will result in a safe default for all four. 993 * hDeltaMax 994 * This parameter is set by the client to specify the 995 * maximum amount that the Horizontal Pixel Total may 996 * be adjusted by the RM, during optimization. 997 * If the client does not obtain a custom value for 998 * this parameter from the user, setting all four of 999 * hDeltaStep, vDeltaStep, hDeltaMax, and vDeltaMax 1000 * to zero will result in a safe default for all four. 1001 * vDeltaMax 1002 * This parameter is set by the client to specify the 1003 * maximum amount that vertical timings of each frame 1004 * (in interlaced modes, each field) may be adjusted 1005 * by the RM, during optimization. 1006 * In interlaced modes, the adjustments to vTotal, 1007 * vInterlacedBlankStart, and vInterlacedBlankEnd may 1008 * be up to twice vDeltaMax. 1009 * In progressive modes, the adjustment to the vTotal 1010 * may simply be up to vDeltaMax. 1011 * If the client does not obtain a custom value for 1012 * this parameter from the user, setting all four of 1013 * hDeltaStep, vDeltaStep, hDeltaMax, and vDeltaMax 1014 * to zero will result in a safe default for all four. 1015 * refreshX10K 1016 * This parameter is set by the client to specify the 1017 * desired refresh rate, multiplied by 10000. This 1018 * allows refresh rate to be set in units of 0.0001 Hz. 1019 * For example, a 59.94 Hz rate would be set as 599400. 1020 * The client can alternatively specify a the 1021 * pixelClockHz parameter (if the passed in refreshX10K 1022 * parameter is set to 0, the pixelClockHz parameter 1023 * will be used). 1024 * pixelClockHz 1025 * This parameter is set by the client to specify the 1026 * desired pixel clock frequency in units of Hz. The 1027 * client can alternatively specify the refreshX10K parameter. 1028 * This parameter is returned by the RM to report the 1029 * optimal pixel clock to use with the adjusted mode, 1030 * in units of Hz. 1031 * 1032 * 1033 * bOptimized[out] 1034 * This is set to NV_TRUE if the timings were successfully optimized, and 1035 * NV_FALSE otherwise. 1036 * 1037 * 1038 * Progressive Raster Structure 1039 * 1040 * hSyncEnd hTotal 1041 * 0 | hBlankEnd hBlankStart | 1042 * | | | | | vSync vBlank 1043 * 0--+--------------------------------------------+ +-+ | 1044 * | Sync | | | 1045 * vSyncEnd--| +----------------------------------------+ +-+ | 1046 * | | Back Porch | | | 1047 * vBlankEnd--| | +--------------------------------+ | | +-+ 1048 * | | | Active Area | | | | 1049 * | | | +------------------------+ | | | | 1050 * | | | | | | | | | 1051 * | S | B | A | | A | F | | | 1052 * | y | a | c | | c | r | | | 1053 * | n | c | t | | t | o | | | 1054 * | c | k | i | | i | n | | | 1055 * | | | v | | v | t | | | 1056 * | | P | e | Output Viewport | e | | | | 1057 * | | o | | | | P | | | 1058 * | | r | A | | A | o | | | 1059 * | | c | r | | r | r | | | 1060 * | | h | e | | e | c | | | 1061 * | | | a | | a | h | | | 1062 * | | | | | | | | | 1063 * | | | +------------------------+ | | | | 1064 * | | | Active Area | | | | 1065 * vBlankStart-| | +--------------------------------+ | | +-+ 1066 * | | Front Porch | | | 1067 * vTotal--+---+----------------------------------------+ +-+ | 1068 * ___ 1069 * / \________________________________________/ hSync 1070 * ________ ____ 1071 * \________________________________/ hBlank 1072 * 1073 * 1074 * 1075 * Interlaced Raster Structure 1076 * 1077 * hSyncEnd hTotal 1078 * 0 | hBlankEnd hBlankStart | 1079 * | | | | | vSync vBlank 1080 * 0--+--------------------------------------------+ +-+ | 1081 * | Sync | | | 1082 * vSyncEnd--| +----------------------------------------+ +-+ | 1083 * | | Back Porch | | | 1084 * vBlankEnd--| | +--------------------------------+ | | +-+ 1085 * | | | Active Area | | | | 1086 * | | | +------------------------+ | | | | 1087 * | | | | | | | | | 1088 * | S | B | A | | A | F | | | 1089 * | y | a | c | | c | r | | | 1090 * | n | c | t | | t | o | | | 1091 * | c | k | i | | i | n | | | 1092 * | | | v | | v | t | | | 1093 * | | P | e | Output Viewport | e | | | | 1094 * | | o | | | | P | | | 1095 * | | r | A | | A | o | | | 1096 * | | c | r | | r | r | | | 1097 * | | h | e | | e | c | | | 1098 * | | | a | | a | h | | | 1099 * | | | | | | | | | 1100 * | | | +------------------------+ | | | | 1101 * | | | Active Area | | | | 1102 * vBlankStart-| | +--------------------------------+ | | +-+ 1103 * | | | | | 1104 * | | Front Porch +--------------------+ | | 1105 * | | | | +-+ | 1106 * | +-------------------+ | | | 1107 * | | | | 1108 * | Sync +--------------------+ | | 1109 * | | | +-+ | 1110 * | +-------------------+ | | | 1111 * vInterlaced | | Back Porch | | | 1112 * BlankEnd--| | +--------------------------------+ | | +-+ 1113 * | | | Active Area | | | | 1114 * | | | +------------------------+ | | | | 1115 * | | | | | | | | | 1116 * | S | B | A | | A | F | | | 1117 * | y | a | c | | c | r | | | 1118 * | n | c | t | | t | o | | | 1119 * | c | k | i | | i | n | | | 1120 * | | | v | | v | t | | | 1121 * | | P | e | Output Viewport | e | | | | 1122 * | | o | | | | P | | | 1123 * | | r | A | | A | o | | | 1124 * | | c | r | | r | r | | | 1125 * | | h | e | | e | c | | | 1126 * | | | a | | a | h | | | 1127 * | | | | | | | | | 1128 * | | | +------------------------+ | | | | 1129 * vInterlaced | | | Active Area | | | | 1130 * BlankStart-| | +--------------------------------+ | | +-+ 1131 * | | Front Porch | | | 1132 * vTotal--+---+----------------------------------------+ +-+ | 1133 * ___ 1134 * / \________________________________________/ hSync 1135 * ________ ____ 1136 * \________________________________/ hBlank 1137 * 1138 * Possible status values returned are: 1139 * NV_OK 1140 * NV_ERR_GENERIC 1141 * NV_ERR_INVALID_ARGUMENT 1142 * 1143 */ 1144 1145 #define NV30F1_CTRL_CMD_GSYNC_GET_OPTIMIZED_TIMING (0x30f10160) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS_MESSAGE_ID" */ 1146 1147 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS_MESSAGE_ID (0x60U) 1148 1149 typedef struct NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS { 1150 NvU32 gpuId; 1151 NvU32 output; 1152 NvU32 protocol; 1153 NvU32 structure; 1154 NvU32 adjust; 1155 NvU32 hDeltaStep; 1156 NvU32 hDeltaMax; 1157 NvU32 vDeltaStep; 1158 NvU32 vDeltaMax; 1159 NvU32 hSyncEnd; 1160 NvU32 hBlankEnd; 1161 NvU32 hBlankStart; 1162 NvU32 hTotal; 1163 NvU32 vSyncEnd; 1164 NvU32 vBlankEnd; 1165 NvU32 vBlankStart; 1166 NvU32 vInterlacedBlankEnd; 1167 NvU32 vInterlacedBlankStart; 1168 NvU32 vTotal; 1169 NvU32 refreshX10K; 1170 NvU32 pixelClockHz; 1171 1172 NvBool bOptimized; 1173 } NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS; 1174 1175 /* output values */ 1176 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_OUTPUT_DAC (0x00000001) 1177 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_OUTPUT_SOR (0x00000004) 1178 1179 /* protocol values for DAC displays (e.g. CRTs) */ 1180 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_DAC_RGB_CRT (0x00000000) 1181 1182 /* protocol values for SOR displays (e.g. DFPs) */ 1183 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_LVDS_CUSTOM (0x00000000) 1184 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_SINGLE_TMDS_A (0x00000001) 1185 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_SINGLE_TMDS_B (0x00000002) 1186 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_DUAL_TMDS (0x00000005) 1187 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_DP_A (0x00000008) 1188 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_DP_B (0x00000009) 1189 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PROTOCOL_SOR_HDMI_FRL (0x0000000C) 1190 1191 /* structure values */ 1192 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_STRUCTURE_PROGRESSIVE (0x00000000) 1193 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_STRUCTURE_INTERLACED (0x00000001) 1194 1195 /* adjust values */ 1196 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_H_FRONT_PORCH (0x00000001) 1197 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_V_FRONT_PORCH (0x00000002) 1198 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_H_ACTIVE_AREA (0x00000004) 1199 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_V_ACTIVE_AREA (0x00000008) 1200 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_H_BACK_PORCH (0x00000010) 1201 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_V_BACK_PORCH (0x00000020) 1202 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_H_RASTER_SYNC (0x00000040) 1203 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_V_RASTER_SYNC (0x00000080) 1204 1205 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_DEFAULT_CRT (0x00000030) 1206 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_ADJUST_DEFAULT_DFP (0x00000020) 1207 1208 /* DeltaStep and DeltaMax values to trigger default settings */ 1209 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_H_DELTA_STEP_USE_DEFAULTS (0x00000000) 1210 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_H_DELTA_MAX_USE_DEFAULTS (0x00000000) 1211 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_V_DELTA_STEP_USE_DEFAULTS (0x00000000) 1212 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_V_DELTA_MAX_USE_DEFAULTS (0x00000000) 1213 1214 /* 1215 * NV30F1_CTRL_CMD_GSYNC_SET_EVENT_NOTIFICATION 1216 * 1217 * This command sets event notification state for the associated Gsync 1218 * object. This command requires that an instance of NV01_EVENT has 1219 * been previously bound to the associated Gsync object. 1220 * 1221 * If one or more of the "smart event notification" options are set in the 1222 * action parameter, multiple sequential events of the same type will only 1223 * trigger one notification. After that, only an event of a different type 1224 * will trigger a new notification. 1225 * 1226 * action 1227 * This member specifies the desired event notification action. 1228 * Valid notification actions include: 1229 * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_DISABLE 1230 * This action disables event notification for the associated 1231 * Gsync object. 1232 * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_LOSS 1233 * This action enables smart event notification for the 1234 * associated Gsync object, for "sync loss" events. 1235 * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_GAIN 1236 * This action enables smart event notification for the 1237 * associated Gsync object, for "sync gained" events. 1238 * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_LOSS 1239 * This action enables smart event notification for the 1240 * associated Gsync object, for "stereo lost" events. 1241 * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_GAIN 1242 * This action enables smart event notification for the 1243 * associated Gsync object, for "stereo gained" events. 1244 * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_GAIN 1245 * This action enables smart event notification for the 1246 * associated Gsync object, for "house sync (BNC) plug in" events. 1247 * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_LOSS 1248 * This action enables smart event notification for the 1249 * associated Gsync object, for "house sync (BNC) plug out" events. 1250 * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_GAIN 1251 * This action enables smart event notification for the 1252 * associated Gsync object, for "ethernet (RJ45) plug in" events. 1253 * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_LOSS 1254 * This action enables smart event notification for the 1255 * associated Gsync object, for "ethernet (RJ45) plug out" events. 1256 * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_COUNT_MATCH 1257 * This action enables smart event notification for the 1258 * associated Gsync object, for "frame counter match" events. 1259 * NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_ALL 1260 * This action enables smart event notification for the 1261 * associated Gsync object, for any type of event. 1262 * 1263 * Possible status values returned are: 1264 * NV_OK 1265 * NV_ERR_INVALID_PARAM_STRUCT 1266 * NV_ERR_INVALID_ARGUMENT 1267 * NV_ERR_INVALID_STATE 1268 */ 1269 #define NV30F1_CTRL_CMD_GSYNC_SET_EVENT_NOTIFICATION (0x30f10170) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS_MESSAGE_ID" */ 1270 1271 #define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS_MESSAGE_ID (0x70U) 1272 1273 typedef struct NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS { 1274 NvU32 action; 1275 } NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_PARAMS; 1276 1277 /* valid action values */ 1278 1279 #define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_DISABLE (0x00000000) 1280 #define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_LOSS (0x00000001) 1281 #define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_SYNC_GAIN (0x00000002) 1282 #define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_LOSS (0x00000004) 1283 #define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_STEREO_GAIN (0x00000008) 1284 #define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_GAIN (0x00000010) 1285 #define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_HOUSE_LOSS (0x00000020) 1286 #define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_GAIN (0x00000040) 1287 #define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_RJ45_LOSS (0x00000080) 1288 #define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_COUNT_MATCH (0x00000100) 1289 #define NV30F1_CTRL_GSYNC_SET_EVENT_NOTIFICATION_ACTION_SMART_ALL (0x000001FF) 1290 1291 #define NV30F1_CTRL_GSYNC_EVENT_TYPES 9 1292 1293 /* 1294 * NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE 1295 * NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE 1296 * 1297 * These commands can be used to get/set the stereo lock assistance mode of 1298 * the GSYNC device. This is supported by GSYNC III device only. 1299 * 1] In this mode the GSYNC recreates the hidden VS either by -> 1300 * (a) using local stereo edge if stereo is toggle or 1301 * (b) counting lines and generate the missing VS. 1302 * 2] Master GSYNC card recreates the stereo and passes it along to 1303 * the slave GSYNC cards. 1304 * 3] Slave GSYNC cards generates the stereo raster sync structure to 1305 * synchronize the GPU. 1306 * 4] For stereo sync status reporting, under this mode, the GSYNC automatically 1307 * reports stereo lock whenever it gets the master stereo signal. The 1308 * assumption is local stereo will be in synced with the new structure. 1309 * 5] If the slave GSYNC card does not observed master stereo for any reason, 1310 * (a) it clears the stereo sync bit and 1311 * (b) it generates its own version of stereo and sync the GPU. 1312 * 1313 * Parameters: 1314 * gpuId 1315 * This parameter is set by the client to indicate the gpuId on which 1316 * the stereo lock mode should be enabled/disabled. 1317 * 1318 * enable 1319 * In SET query, this parameter is set by the client to indicate whether 1320 * RM should enable or disable stereo lock mode for GPU specified in gpuId. 1321 * 1 and 0 indicates enable and disable stereo lock mode respectively. In 1322 * GET query, RM will set this parameter to 1 or 0 depending on StereoLock 1323 * mode is enabled or not respectively for specified GPU. 1324 * 1325 * Possible status values returned are: 1326 * NV_OK 1327 * NV_ERR_GENERIC 1328 * NV_ERR_INVALID_ARGUMENT 1329 * 1330 */ 1331 #define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE (0x30f10172) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID" */ 1332 1333 #define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE (0x30f10173) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID" */ 1334 1335 typedef struct NV30F1_CTRL_CMD_GSYNC_CONTROL_STEREO_LOCK_MODE_PARAMS { 1336 NvU32 gpuId; 1337 NvU32 enable; 1338 } NV30F1_CTRL_CMD_GSYNC_CONTROL_STEREO_LOCK_MODE_PARAMS; 1339 1340 #define NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID (0x72U) 1341 1342 typedef NV30F1_CTRL_CMD_GSYNC_CONTROL_STEREO_LOCK_MODE_PARAMS NV30F1_CTRL_CMD_GSYNC_SET_CONTROL_STEREO_LOCK_MODE_PARAMS; 1343 1344 #define NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS_MESSAGE_ID (0x73U) 1345 1346 typedef NV30F1_CTRL_CMD_GSYNC_CONTROL_STEREO_LOCK_MODE_PARAMS NV30F1_CTRL_CMD_GSYNC_GET_CONTROL_STEREO_LOCK_MODE_PARAMS; 1347 1348 /* 1349 * NV30F1_CTRL_CMD_GSYNC_READ_REGISTER 1350 * 1351 * This command is used to read raw i2c registers from the gsync device, via 1352 * the given GPU (registers on the same gsync device may have different values 1353 * depending on which GPU is used to do the read). 1354 * 1355 * This may only be used by a privileged client. 1356 * 1357 * Parameters: 1358 * gpuId 1359 * This parameter is set by the client to specify which GPU to use to 1360 * perform the read. 1361 * 1362 * reg 1363 * This parameter is set by the client to specify which i2c register to 1364 * read. 1365 * 1366 * data 1367 * This parameter is written by the RM and returned to the client upon a 1368 * successful read. 1369 * 1370 * Possible status values returned are: 1371 * NV_OK 1372 * NV_ERR_GENERIC 1373 * NV_ERR_INVALID_ARGUMENT 1374 * NV_ERR_INSUFFICIENT_PERMISSIONS 1375 */ 1376 #define NV30F1_CTRL_CMD_GSYNC_READ_REGISTER (0x30f10180) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS_MESSAGE_ID" */ 1377 1378 #define NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS_MESSAGE_ID (0x80U) 1379 1380 typedef struct NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS { 1381 NvU32 gpuId; 1382 NvU8 reg; 1383 NvU8 data; 1384 } NV30F1_CTRL_GSYNC_READ_REGISTER_PARAMS; 1385 1386 /* 1387 * NV30F1_CTRL_CMD_GSYNC_WRITE_REGISTER 1388 * 1389 * This command is used to write raw i2c registers on the gsync device, via the 1390 * given GPU (registers on the same gsync device may have different values 1391 * depending on which GPU is used to do the write). 1392 * 1393 * This may only be used by a privileged client. 1394 * 1395 * Parameters: 1396 * gpuId 1397 * This parameter is set by the client to specify which GPU to use to 1398 * perform the write. 1399 * 1400 * reg 1401 * This parameter is set by the client to specify which i2c register to 1402 * write. 1403 * 1404 * data 1405 * This parameter is set by the client to specify what data to write to the 1406 * given i2c register. 1407 * 1408 * Possible status values returned are: 1409 * NV_OK 1410 * NV_ERR_GENERIC 1411 * NV_ERR_INVALID_ARGUMENT 1412 * NV_ERR_INSUFFICIENT_PERMISSIONS 1413 */ 1414 1415 #define NV30F1_CTRL_CMD_GSYNC_WRITE_REGISTER (0x30f10181) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS_MESSAGE_ID" */ 1416 1417 #define NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS_MESSAGE_ID (0x81U) 1418 1419 typedef struct NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS { 1420 NvU32 gpuId; 1421 NvU8 reg; 1422 NvU8 data; 1423 } NV30F1_CTRL_GSYNC_WRITE_REGISTER_PARAMS; 1424 1425 1426 1427 /* 1428 * NV30F1_CTRL_CMD_GSYNC_SET_LOCAL_SYNC 1429 * 1430 * This command enables/disables raster sync on displays i.e. 1431 * mosaic groups between gpus. 1432 * 1433 * gpuTimingSource 1434 * The parameter is set by the client to indicate the gpuId of the 1435 * Timing Source gpu for specified mosaic group. 1436 * gpuTimingSlaves[] 1437 * This parameter is set by the client to indicate the gpuIds of the 1438 * timing slave gpus for specified mosaic group. It should not contain 1439 * more gpuids than slaveGpuCount. 1440 * slaveGpuCount 1441 * This parameter is set by the client to indicate the count of timing 1442 * slave gpus under specified group. 1443 * Referring to gsync3-P2060, slaveGpuCount can vary from 0x01 to 0x03 1444 * as maximum possible connected gpus are four and one gpu must be 1445 * timing master for mosaic group. 1446 * mosaicGroupNumber 1447 * This parameter is set by the client to tell the RM to which mosaic 1448 * group it should refer. 1449 * Referring to gsync3-P2060, mosaicGroupNumber can contain 0x00 or 1450 * 0x01 as only two mosaic groups are possible. 1451 * enableMosaic 1452 * This parameter is set by the client to indicate RM that whether RM 1453 * should enable mosaic or disable mosaic. 1454 * 1455 * Possible status values returned are: 1456 * NV_OK 1457 * NV_ERR_GENERIC 1458 * NV_ERR_INVALID_ARGUMENT 1459 * 1460 */ 1461 #define NV30F1_CTRL_CMD_GSYNC_SET_LOCAL_SYNC (0x30f10185) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS_MESSAGE_ID" */ 1462 1463 #define NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS_MESSAGE_ID (0x85U) 1464 1465 typedef struct NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS { 1466 NvU32 gpuTimingSource; 1467 NvU32 gpuTimingSlaves[NV30F1_CTRL_MAX_GPUS_PER_GSYNC]; 1468 NvU32 slaveGpuCount; 1469 NvU32 mosaicGroupNumber; 1470 NvBool enableMosaic; 1471 } NV30F1_CTRL_GSYNC_SET_LOCAL_SYNC_PARAMS; 1472 1473 /* 1474 * NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH 1475 * 1476 * This command configure GSYNC registers for pre-flash and post-flash 1477 * operations. This is currenly used for GSYNC-3 (P2060) only. RM clients 1478 * has to make sure that they perform both pre-flash and post-flash 1479 * operations on GSYNC board. Avoiding, post-flash will cause mismatch 1480 * between RM cached-data and GSYNC register values. 1481 * 1482 * Parameters: 1483 * gpuId 1484 * This parameter is set by the client to indicate the gpuId for which 1485 * GSYNC board connected to that GPU will be configured for pre-flash 1486 * or post-flash operation depending on preFlash value. 1487 * 1488 * preFlash 1489 * This parameter is set by the client to indicate whether RM has to configure 1490 * GSYNC registers and SW state for pre-flash or post-flash operation. Values 1491 * 1 and 0 indicates that RM will configure GSYNC board for pre-flash and 1492 * post-flash operations respectively. 1493 * 1494 * Possible status values returned are: 1495 * NV_OK 1496 * NV_ERR_GENERIC 1497 * NV_ERR_INVALID_ARGUMENT 1498 * 1499 */ 1500 #define NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH (0x30f10186) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS_MESSAGE_ID" */ 1501 1502 #define NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS_MESSAGE_ID (0x86U) 1503 1504 typedef struct NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS { 1505 NvU32 gpuId; 1506 NvU32 preFlash; 1507 } NV30F1_CTRL_CMD_GSYNC_CONFIG_FLASH_PARAMS; 1508 1509 /* 1510 * NV30F1_CTRL_CMD_GSYNC_GET_HOUSE_SYNC_MODE 1511 * NV30F1_CTRL_CMD_GSYNC_SET_HOUSE_SYNC_MODE 1512 * 1513 * These two commands gets/sets house sync mode as input or output. 1514 * 1515 * Parameters: 1516 * houseSyncMode 1517 * This parameter indicates whether the house sync mode is input or 1518 * output. For GET_HOUSE_SYNC_MODE, the current mode will be written 1519 * by RM and returned to the client; for SET_HOUSE_SYNC_MODE, the client 1520 * will write the new mode value to this parameter and pass it to RM 1521 * for execution. 1522 * 1523 * Possible status values returned are: 1524 * NV_OK 1525 * NV_ERR_GENERIC 1526 * NV_ERR_INVALID_ARGUMENT 1527 * NV_ERR_INVALID_DEVICE 1528 * NV_ERR_INVALID_STATE 1529 * 1530 */ 1531 #define NV30F1_CTRL_CMD_GSYNC_GET_HOUSE_SYNC_MODE (0x30f10187) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_GET_HOUSE_SYNC_MODE_PARAMS_MESSAGE_ID" */ 1532 1533 typedef struct NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS { 1534 NvU8 houseSyncMode; 1535 } NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS; 1536 1537 #define NV30F1_CTRL_GSYNC_GET_HOUSE_SYNC_MODE_PARAMS_MESSAGE_ID (0x87U) 1538 1539 typedef NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS NV30F1_CTRL_GSYNC_GET_HOUSE_SYNC_MODE_PARAMS; 1540 1541 #define NV30F1_CTRL_CMD_GSYNC_SET_HOUSE_SYNC_MODE (0x30f10188) /* finn: Evaluated from "(FINN_NV30_GSYNC_GSYNC_INTERFACE_ID << 8) | NV30F1_CTRL_GSYNC_SET_HOUSE_SYNC_MODE_PARAMS_MESSAGE_ID" */ 1542 1543 #define NV30F1_CTRL_GSYNC_SET_HOUSE_SYNC_MODE_PARAMS_MESSAGE_ID (0x88U) 1544 1545 typedef NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_PARAMS NV30F1_CTRL_GSYNC_SET_HOUSE_SYNC_MODE_PARAMS; 1546 1547 #define NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_INPUT (0x00) 1548 #define NV30F1_CTRL_GSYNC_HOUSE_SYNC_MODE_OUTPUT (0x01) 1549 1550 /* _ctrl30f1_h_ */ 1551