1 /* $OpenBSD: stfpcie.c,v 1.4 2024/10/17 01:57:18 jsg Exp $ */
2 /*
3 * Copyright (c) 2023 Mark Kettenis <kettenis@openbsd.org>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #include <sys/param.h>
19 #include <sys/systm.h>
20 #include <sys/device.h>
21 #include <sys/evcount.h>
22 #include <sys/extent.h>
23 #include <sys/malloc.h>
24
25 #include <machine/intr.h>
26 #include <machine/bus.h>
27 #include <machine/fdt.h>
28
29 #include <dev/pci/pcireg.h>
30 #include <dev/pci/pcivar.h>
31
32 #include <dev/ofw/openfirm.h>
33 #include <dev/ofw/ofw_clock.h>
34 #include <dev/ofw/ofw_gpio.h>
35 #include <dev/ofw/ofw_misc.h>
36 #include <dev/ofw/ofw_pinctrl.h>
37 #include <dev/ofw/fdt.h>
38
39 /*
40 * This driver is based on preliminary device tree bindings and will
41 * almost certainly need changes once the official bindings land in
42 * mainline Linux. Support for these preliminary bindings will be
43 * dropped as soon as official bindings are available.
44 */
45
46 #define GEN_SETTINGS 0x80
47 #define PORT_TYPE_RP (1 << 0)
48 #define PCI_IDS_DW1 0x9c
49 #define PCIE_PCI_IOV_DW0 0xb4
50 #define PHY_FUNCTION_DIS (1 << 15)
51 #define PCIE_BAR_WIN 0xfc
52 #define PFETCH_MEMWIN_64BADDR (1 << 3)
53 #define IMASK_LOCAL 0x180
54 #define IMASK_INT_INTA (1 << 24)
55 #define IMASK_INT_INTB (1 << 25)
56 #define IMASK_INT_INTC (1 << 26)
57 #define IMASK_INT_INTD (1 << 27)
58 #define IMASK_INT_INTX (0xf << 24)
59 #define IMASK_INT_MSI (1 << 28)
60 #define ISTATUS_LOCAL 0x184
61 #define PM_MSI_INT_INTA (1 << 24)
62 #define PM_MSI_INT_INTB (1 << 25)
63 #define PM_MSI_INT_INTC (1 << 26)
64 #define PM_MSI_INT_INTD (1 << 27)
65 #define PM_MSI_INT_INTX (0xf << 24)
66 #define PM_MSI_INT_MSI (1 << 28)
67 #define IMSI_ADDR 0x190
68 #define ISTATUS_MSI 0x194
69 #define PMSG_SUPPORT_RX 0x3f0
70 #define PMSG_LTR_SUPPORT (1 << 2)
71 #define ATR_AXI4_SLV0_SRCADDR_PARAM(n) (0x800 + (n) * 0x20)
72 #define ATR_IMPL (1 << 0)
73 #define ATR_SIZE_SHIFT 1
74 #define ATR_AXI4_SLV0_SRC_ADDR(n) (0x804 + (n) * 0x20)
75 #define ATR_AXI4_SLV0_TRSL_ADDR_LSB(n) (0x808 + (n) * 0x20)
76 #define ATR_AXI4_SLV0_TRSL_ADDR_UDW(n) (0x80c + (n) * 0x20)
77 #define ATR_AXI4_SLV0_TRSL_PARAM(n) (0x810 + (n) * 0x20)
78 #define TRSL_ID_PCIE_RX_TX 0
79 #define TRSL_ID_PCIE_CONFIG 1
80
81 #define STG_PCIE0_BASE 0x048
82 #define STG_PCIE1_BASE 0x1f8
83
84 #define STG_ARFUN 0x078
85 #define STG_ARFUN_AXI4_SLVL_MASK (0x7ffff << 8)
86 #define STG_ARFUN_AXI4_SLVL_SHIFT 8
87 #define STG_PHY_FUNC_SHIFT 9
88 #define STG_AWFUN 0x07c
89 #define STG_AWFUN_AXI4_SLVL_MASK (0x7ffff << 0)
90 #define STG_AWFUN_AXI4_SLVL_SHIFT 0
91 #define STG_AWFUN_CKREF_SRC_MASK (0x3 << 18)
92 #define STG_AWFUN_CKREF_SRC_SHIFT 18
93 #define STG_AWFUN_CLKREQ (1 << 22)
94 #define STG_RP_NEP 0x0e8
95 #define STG_K_RP_NEP (1 << 8)
96 #define STG_LNKSTA 0x170
97 #define STG_DATA_LINK_ACTIVE (1 << 5)
98
99 #define HREAD4(sc, reg) \
100 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
101 #define HWRITE4(sc, reg, val) \
102 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
103
104 struct stfpcie_range {
105 uint32_t flags;
106 uint64_t pci_base;
107 uint64_t phys_base;
108 uint64_t size;
109 };
110
111 struct stfpcie_intx {
112 int (*si_func)(void *);
113 void *si_arg;
114 int si_ipl;
115 int si_flags;
116 int si_pin;
117 struct evcount si_count;
118 char *si_name;
119 struct stfpcie_softc *si_sc;
120 TAILQ_ENTRY(stfpcie_intx) si_next;
121 };
122
123 #define STFPCIE_NUM_MSI 32
124
125 struct stfpcie_msi {
126 int (*sm_func)(void *);
127 void *sm_arg;
128 int sm_ipl;
129 int sm_flags;
130 int sm_vec;
131 struct evcount sm_count;
132 char *sm_name;
133 };
134
135 struct stfpcie_softc {
136 struct device sc_dev;
137 bus_space_tag_t sc_iot;
138 bus_space_handle_t sc_ioh;
139 bus_space_handle_t sc_cfg_ioh;
140 bus_dma_tag_t sc_dmat;
141
142 int sc_node;
143 int sc_acells;
144 int sc_scells;
145 int sc_pacells;
146 int sc_pscells;
147 struct stfpcie_range *sc_ranges;
148 int sc_nranges;
149
150 struct bus_space sc_bus_iot;
151 struct bus_space sc_bus_memt;
152
153 struct machine_pci_chipset sc_pc;
154 struct extent *sc_busex;
155 struct extent *sc_memex;
156 struct extent *sc_pmemex;
157 struct extent *sc_ioex;
158 int sc_bus;
159
160 void *sc_ih;
161 struct interrupt_controller sc_ic;
162 TAILQ_HEAD(,stfpcie_intx) sc_intx[4];
163
164 uint32_t sc_msi_addr;
165 struct stfpcie_msi sc_msi[STFPCIE_NUM_MSI];
166 };
167
168 struct stfpcie_intr_handle {
169 struct machine_intr_handle pih_ih;
170 struct stfpcie_softc *pih_sc;
171 struct stfpcie_msi *pih_sm;
172 };
173
174 int stfpcie_match(struct device *, void *, void *);
175 void stfpcie_attach(struct device *, struct device *, void *);
176
177 const struct cfattach stfpcie_ca = {
178 sizeof (struct stfpcie_softc), stfpcie_match, stfpcie_attach
179 };
180
181 struct cfdriver stfpcie_cd = {
182 NULL, "stfpcie", DV_DULL
183 };
184
185 int
stfpcie_match(struct device * parent,void * match,void * aux)186 stfpcie_match(struct device *parent, void *match, void *aux)
187 {
188 struct fdt_attach_args *faa = aux;
189
190 return OF_is_compatible(faa->fa_node, "starfive,jh7110-pcie");
191 }
192
193 int stfpcie_intr(void *);
194 void *stfpcie_intx_intr_establish(void *, int *, int,
195 struct cpu_info *, int (*)(void *), void *, char *);
196 void stfpcie_intx_intr_disestablish(void *);
197 void stfpcie_intx_intr_barrier(void *);
198
199 void stfpcie_attach_hook(struct device *, struct device *,
200 struct pcibus_attach_args *);
201 int stfpcie_bus_maxdevs(void *, int);
202 pcitag_t stfpcie_make_tag(void *, int, int, int);
203 void stfpcie_decompose_tag(void *, pcitag_t, int *, int *, int *);
204 int stfpcie_conf_size(void *, pcitag_t);
205 pcireg_t stfpcie_conf_read(void *, pcitag_t, int);
206 void stfpcie_conf_write(void *, pcitag_t, int, pcireg_t);
207 int stfpcie_probe_device_hook(void *, struct pci_attach_args *);
208
209 int stfpcie_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
210 const char *stfpcie_intr_string(void *, pci_intr_handle_t);
211 void *stfpcie_intr_establish(void *, pci_intr_handle_t, int,
212 struct cpu_info *, int (*)(void *), void *, char *);
213 void stfpcie_intr_disestablish(void *, void *);
214
215 int stfpcie_bs_iomap(bus_space_tag_t, bus_addr_t, bus_size_t, int,
216 bus_space_handle_t *);
217 int stfpcie_bs_memmap(bus_space_tag_t, bus_addr_t, bus_size_t, int,
218 bus_space_handle_t *);
219
220 struct interrupt_controller stfpcie_ic = {
221 .ic_barrier = intr_barrier
222 };
223
224 void
stfpcie_attach(struct device * parent,struct device * self,void * aux)225 stfpcie_attach(struct device *parent, struct device *self, void *aux)
226 {
227 struct stfpcie_softc *sc = (struct stfpcie_softc *)self;
228 struct fdt_attach_args *faa = aux;
229 struct pcibus_attach_args pba;
230 struct regmap *rm;
231 uint32_t *ranges;
232 int i, j, nranges, rangeslen;
233 uint32_t bus_range[2];
234 bus_addr_t cfg_base;
235 bus_size_t cfg_size;
236 bus_size_t stg_base;
237 uint32_t *perst_gpio;
238 int perst_gpiolen;
239 uint32_t reg, stg;
240 int idx, node, timo;
241
242 sc->sc_iot = faa->fa_iot;
243
244 idx = OF_getindex(faa->fa_node, "apb", "reg-names");
245 /* XXX Preliminary bindings used a different name. */
246 if (idx < 0)
247 idx = OF_getindex(faa->fa_node, "reg", "reg-names");
248 if (idx < 0 || idx >= faa->fa_nreg ||
249 bus_space_map(sc->sc_iot, faa->fa_reg[idx].addr,
250 faa->fa_reg[idx].size, 0, &sc->sc_ioh)) {
251 printf(": can't map registers\n");
252 return;
253 }
254
255 idx = OF_getindex(faa->fa_node, "cfg", "reg-names");
256 /* XXX Preliminary bindings used a different name. */
257 if (idx < 0)
258 idx = OF_getindex(faa->fa_node, "config", "reg-names");
259 if (idx < 0 || idx >= faa->fa_nreg ||
260 bus_space_map(sc->sc_iot, faa->fa_reg[idx].addr,
261 faa->fa_reg[idx].size, 0, &sc->sc_cfg_ioh)) {
262 printf(": can't map registers\n");
263 return;
264 }
265 cfg_base = faa->fa_reg[idx].addr;
266 cfg_size = faa->fa_reg[idx].size;
267
268 sc->sc_dmat = faa->fa_dmat;
269 sc->sc_node = faa->fa_node;
270
271 switch (cfg_base) {
272 case 0x940000000:
273 stg_base = STG_PCIE0_BASE;
274 break;
275 case 0x9c0000000:
276 stg_base = STG_PCIE1_BASE;
277 break;
278 default:
279 printf(": unknown controller at 0x%lx\n", cfg_base);
280 return;
281 }
282
283 /*
284 * XXX This was an array in the preliminary bindings; simplify
285 * when we drop support for those.
286 */
287 if (OF_getpropintarray(sc->sc_node, "starfive,stg-syscon", &stg,
288 sizeof(stg)) < sizeof(stg)) {
289 printf(": failed to get starfive,stg-syscon\n");
290 return;
291 }
292
293 rm = regmap_byphandle(stg);
294 if (rm == NULL) {
295 printf(": can't get regmap\n");
296 return;
297 }
298
299 pinctrl_byname(sc->sc_node, "default");
300
301 reg = regmap_read_4(rm, stg_base + STG_RP_NEP);
302 reg |= STG_K_RP_NEP;
303 regmap_write_4(rm, stg_base + STG_RP_NEP, reg);
304
305 reg = regmap_read_4(rm, stg_base + STG_AWFUN);
306 reg &= ~STG_AWFUN_CKREF_SRC_MASK;
307 reg |= (2 << STG_AWFUN_CKREF_SRC_SHIFT);
308 regmap_write_4(rm, stg_base + STG_AWFUN, reg);
309
310 reg = regmap_read_4(rm, stg_base + STG_AWFUN);
311 reg |= STG_AWFUN_CLKREQ;
312 regmap_write_4(rm, stg_base + STG_AWFUN, reg);
313
314 clock_enable_all(sc->sc_node);
315 reset_deassert_all(sc->sc_node);
316
317 sc->sc_acells = OF_getpropint(sc->sc_node, "#address-cells",
318 faa->fa_acells);
319 sc->sc_scells = OF_getpropint(sc->sc_node, "#size-cells",
320 faa->fa_scells);
321 sc->sc_pacells = faa->fa_acells;
322 sc->sc_pscells = faa->fa_scells;
323
324 rangeslen = OF_getproplen(sc->sc_node, "ranges");
325 if (rangeslen <= 0 || (rangeslen % sizeof(uint32_t)) ||
326 (rangeslen / sizeof(uint32_t)) % (sc->sc_acells +
327 sc->sc_pacells + sc->sc_scells)) {
328 printf(": invalid ranges property\n");
329 return;
330 }
331
332 ranges = malloc(rangeslen, M_TEMP, M_WAITOK);
333 OF_getpropintarray(sc->sc_node, "ranges", ranges,
334 rangeslen);
335
336 nranges = (rangeslen / sizeof(uint32_t)) /
337 (sc->sc_acells + sc->sc_pacells + sc->sc_scells);
338 sc->sc_ranges = mallocarray(nranges,
339 sizeof(struct stfpcie_range), M_TEMP, M_WAITOK);
340 sc->sc_nranges = nranges;
341
342 for (i = 0, j = 0; i < sc->sc_nranges; i++) {
343 sc->sc_ranges[i].flags = ranges[j++];
344 sc->sc_ranges[i].pci_base = ranges[j++];
345 if (sc->sc_acells - 1 == 2) {
346 sc->sc_ranges[i].pci_base <<= 32;
347 sc->sc_ranges[i].pci_base |= ranges[j++];
348 }
349 sc->sc_ranges[i].phys_base = ranges[j++];
350 if (sc->sc_pacells == 2) {
351 sc->sc_ranges[i].phys_base <<= 32;
352 sc->sc_ranges[i].phys_base |= ranges[j++];
353 }
354 sc->sc_ranges[i].size = ranges[j++];
355 if (sc->sc_scells == 2) {
356 sc->sc_ranges[i].size <<= 32;
357 sc->sc_ranges[i].size |= ranges[j++];
358 }
359 }
360
361 free(ranges, M_TEMP, rangeslen);
362
363 /* Mask and acknowledge all interrupts. */
364 HWRITE4(sc, IMASK_LOCAL, 0);
365 HWRITE4(sc, ISTATUS_LOCAL, 0xffffffff);
366
367 sc->sc_ih = fdt_intr_establish(sc->sc_node, IPL_BIO | IPL_MPSAFE,
368 stfpcie_intr, sc, sc->sc_dev.dv_xname);
369 if (sc->sc_ih == NULL) {
370 printf(": can't establish interrupt\n");
371 return;
372 }
373
374 printf("\n");
375
376 perst_gpiolen = OF_getproplen(sc->sc_node, "perst-gpios");
377 /* XXX Preliminary bindings used a different name. */
378 if (perst_gpiolen <= 0)
379 perst_gpiolen = OF_getproplen(sc->sc_node, "reset-gpios");
380 if (perst_gpiolen <= 0)
381 return;
382
383 /* Assert PERST#. */
384 perst_gpio = malloc(perst_gpiolen, M_TEMP, M_WAITOK);
385 if (OF_getpropintarray(sc->sc_node, "perst-gpios",
386 perst_gpio, perst_gpiolen) != perst_gpiolen) {
387 OF_getpropintarray(sc->sc_node, "reset-gpios",
388 perst_gpio, perst_gpiolen);
389 }
390 gpio_controller_config_pin(perst_gpio, GPIO_CONFIG_OUTPUT);
391 gpio_controller_set_pin(perst_gpio, 1);
392
393 /* Disable additional functions. */
394 for (i = 1; i < 4; i++) {
395 reg = regmap_read_4(rm, stg_base + STG_ARFUN);
396 reg &= ~STG_ARFUN_AXI4_SLVL_MASK;
397 reg |= (i << STG_PHY_FUNC_SHIFT) << STG_ARFUN_AXI4_SLVL_SHIFT;
398 regmap_write_4(rm, stg_base + STG_ARFUN, reg);
399 reg = regmap_read_4(rm, stg_base + STG_AWFUN);
400 reg &= ~STG_AWFUN_AXI4_SLVL_MASK;
401 reg |= (i << STG_PHY_FUNC_SHIFT) << STG_AWFUN_AXI4_SLVL_SHIFT;
402 regmap_write_4(rm, stg_base + STG_AWFUN, reg);
403
404 reg = HREAD4(sc, PCIE_PCI_IOV_DW0);
405 reg |= PHY_FUNCTION_DIS;
406 HWRITE4(sc, PCIE_PCI_IOV_DW0, reg);
407 }
408 reg = regmap_read_4(rm, stg_base + STG_ARFUN);
409 reg &= ~STG_ARFUN_AXI4_SLVL_MASK;
410 regmap_write_4(rm, stg_base + STG_ARFUN, reg);
411 reg = regmap_read_4(rm, stg_base + STG_AWFUN);
412 reg &= ~STG_AWFUN_AXI4_SLVL_MASK;
413 regmap_write_4(rm, stg_base + STG_AWFUN, reg);
414
415 /* Configure controller as root port. */
416 reg = HREAD4(sc, GEN_SETTINGS);
417 reg |= PORT_TYPE_RP;
418 HWRITE4(sc, GEN_SETTINGS, reg);
419
420 /* Configure as PCI bridge. */
421 HWRITE4(sc, PCI_IDS_DW1,
422 PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT |
423 PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT);
424
425 /* Enable prefetchable memory windows. */
426 reg = HREAD4(sc, PCIE_BAR_WIN);
427 reg |= PFETCH_MEMWIN_64BADDR;
428 HWRITE4(sc, PCIE_BAR_WIN, reg);
429
430 /* Disable LTR message forwarding. */
431 reg = HREAD4(sc, PMSG_SUPPORT_RX);
432 reg &= ~PMSG_LTR_SUPPORT;
433 HWRITE4(sc, PMSG_SUPPORT_RX, reg);
434
435 /* Configure config space address translation. */
436 HWRITE4(sc, ATR_AXI4_SLV0_SRCADDR_PARAM(0),
437 cfg_base | ATR_IMPL | (flsl(cfg_size) - 1) << ATR_SIZE_SHIFT);
438 HWRITE4(sc, ATR_AXI4_SLV0_SRC_ADDR(0), cfg_base >> 32);
439 HWRITE4(sc, ATR_AXI4_SLV0_TRSL_ADDR_LSB(0), 0);
440 HWRITE4(sc, ATR_AXI4_SLV0_TRSL_ADDR_UDW(0), 0);
441 HWRITE4(sc, ATR_AXI4_SLV0_TRSL_PARAM(0), TRSL_ID_PCIE_CONFIG);
442
443 /* Configure mmio space address translation. */
444 for (i = 0; i < sc->sc_nranges; i++) {
445 HWRITE4(sc, ATR_AXI4_SLV0_SRCADDR_PARAM(i + 1),
446 sc->sc_ranges[0].phys_base | ATR_IMPL |
447 (flsl(sc->sc_ranges[0].size) - 1) << ATR_SIZE_SHIFT);
448 HWRITE4(sc, ATR_AXI4_SLV0_SRC_ADDR(i + 1),
449 sc->sc_ranges[0].phys_base >> 32);
450 HWRITE4(sc, ATR_AXI4_SLV0_TRSL_ADDR_LSB(i + 1),
451 sc->sc_ranges[0].pci_base);
452 HWRITE4(sc, ATR_AXI4_SLV0_TRSL_ADDR_UDW(i + 1),
453 sc->sc_ranges[0].pci_base >> 32);
454 HWRITE4(sc, ATR_AXI4_SLV0_TRSL_PARAM(i + 1),
455 TRSL_ID_PCIE_RX_TX);
456 }
457
458 /*
459 * PERST# must remain asserted for at least 100us after the
460 * reference clock becomes stable. But also has to remain
461 * active at least 100ms after power up. Since we may have
462 * just powered on the device, play it safe and use 100ms.
463 */
464 delay(100000);
465
466 /* Deassert PERST#. */
467 gpio_controller_set_pin(perst_gpio, 0);
468 free(perst_gpio, M_TEMP, perst_gpiolen);
469
470 /* Wait for link to come up. */
471 for (timo = 100; timo > 0; timo--) {
472 reg = regmap_read_4(rm, stg_base + STG_LNKSTA);
473 if (reg & STG_DATA_LINK_ACTIVE)
474 break;
475 delay(1000);
476 }
477
478 /* INTx handling. */
479 node = OF_getnodebyname(sc->sc_node, "interrupt-controller");
480 if (node) {
481 int pin;
482
483 for (pin = 0; pin < nitems(sc->sc_intx); pin++)
484 TAILQ_INIT(&sc->sc_intx[pin]);
485 sc->sc_ic.ic_node = node;
486 sc->sc_ic.ic_cookie = sc;
487 sc->sc_ic.ic_establish = stfpcie_intx_intr_establish;
488 sc->sc_ic.ic_disestablish = stfpcie_intx_intr_disestablish;
489 sc->sc_ic.ic_barrier = stfpcie_intx_intr_barrier;
490 fdt_intr_register(&sc->sc_ic);
491 }
492
493 /* MSI handling. */
494 sc->sc_msi_addr = HREAD4(sc, IMSI_ADDR);
495
496 /* Unmask interrupts. */
497 HWRITE4(sc, IMASK_LOCAL, IMASK_INT_MSI);
498
499 /* Create extents for our address spaces. */
500 sc->sc_busex = extent_create("pcibus", 0, 255,
501 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED);
502 sc->sc_memex = extent_create("pcimem", 0, (u_long)-1,
503 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED);
504 sc->sc_pmemex = extent_create("pcipmem", 0, (u_long)-1,
505 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED);
506 sc->sc_ioex = extent_create("pciio", 0, 0xffffffff,
507 M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED);
508 for (i = 0; i < sc->sc_nranges; i++) {
509 if ((sc->sc_ranges[i].flags & 0x03000000) == 0x01000000) {
510 extent_free(sc->sc_ioex, sc->sc_ranges[i].pci_base,
511 sc->sc_ranges[i].size, EX_WAITOK);
512 }
513 if ((sc->sc_ranges[i].flags & 0x03000000) == 0x02000000) {
514 extent_free(sc->sc_memex, sc->sc_ranges[i].pci_base,
515 sc->sc_ranges[i].size, EX_WAITOK);
516 }
517 if ((sc->sc_ranges[i].flags & 0x03000000) == 0x03000000) {
518 extent_free(sc->sc_pmemex, sc->sc_ranges[i].pci_base,
519 sc->sc_ranges[i].size, EX_WAITOK);
520 }
521 }
522
523 /* Set up bus range. */
524 if (OF_getpropintarray(sc->sc_node, "bus-range", bus_range,
525 sizeof(bus_range)) != sizeof(bus_range) ||
526 bus_range[0] >= 32 || bus_range[1] >= 32) {
527 bus_range[0] = 0;
528 bus_range[1] = 31;
529 }
530 sc->sc_bus = bus_range[0];
531 extent_free(sc->sc_busex, bus_range[0],
532 bus_range[1] - bus_range[0] + 1, EX_WAITOK);
533
534 memcpy(&sc->sc_bus_iot, sc->sc_iot, sizeof(sc->sc_bus_iot));
535 sc->sc_bus_iot.bus_private = sc;
536 sc->sc_bus_iot._space_map = stfpcie_bs_iomap;
537 memcpy(&sc->sc_bus_memt, sc->sc_iot, sizeof(sc->sc_bus_memt));
538 sc->sc_bus_memt.bus_private = sc;
539 sc->sc_bus_memt._space_map = stfpcie_bs_memmap;
540
541 sc->sc_pc.pc_conf_v = sc;
542 sc->sc_pc.pc_attach_hook = stfpcie_attach_hook;
543 sc->sc_pc.pc_bus_maxdevs = stfpcie_bus_maxdevs;
544 sc->sc_pc.pc_make_tag = stfpcie_make_tag;
545 sc->sc_pc.pc_decompose_tag = stfpcie_decompose_tag;
546 sc->sc_pc.pc_conf_size = stfpcie_conf_size;
547 sc->sc_pc.pc_conf_read = stfpcie_conf_read;
548 sc->sc_pc.pc_conf_write = stfpcie_conf_write;
549 sc->sc_pc.pc_probe_device_hook = stfpcie_probe_device_hook;
550
551 sc->sc_pc.pc_intr_v = sc;
552 sc->sc_pc.pc_intr_map = stfpcie_intr_map;
553 sc->sc_pc.pc_intr_map_msi = _pci_intr_map_msi;
554 sc->sc_pc.pc_intr_map_msix = _pci_intr_map_msix;
555 sc->sc_pc.pc_intr_string = stfpcie_intr_string;
556 sc->sc_pc.pc_intr_establish = stfpcie_intr_establish;
557 sc->sc_pc.pc_intr_disestablish = stfpcie_intr_disestablish;
558
559 memset(&pba, 0, sizeof(pba));
560 pba.pba_busname = "pci";
561 pba.pba_iot = &sc->sc_bus_iot;
562 pba.pba_memt = &sc->sc_bus_memt;
563 pba.pba_dmat = sc->sc_dmat;
564 pba.pba_pc = &sc->sc_pc;
565 pba.pba_busex = sc->sc_busex;
566 pba.pba_memex = sc->sc_memex;
567 pba.pba_pmemex = sc->sc_pmemex;
568 pba.pba_ioex = sc->sc_ioex;
569 pba.pba_domain = pci_ndomains++;
570 pba.pba_bus = sc->sc_bus;
571 #ifdef notyet
572 pba.pba_flags |= PCI_FLAGS_MSI_ENABLED;
573 #endif
574
575 config_found(self, &pba, NULL);
576 }
577
578 void *
stfpcie_intx_intr_establish(void * cookie,int * cell,int level,struct cpu_info * ci,int (* func)(void *),void * arg,char * name)579 stfpcie_intx_intr_establish(void *cookie, int *cell, int level,
580 struct cpu_info *ci, int (*func)(void *), void *arg, char *name)
581 {
582 struct stfpcie_softc *sc = (struct stfpcie_softc *)cookie;
583 struct stfpcie_intx *si;
584 int pin = cell[0] - 1;
585 uint32_t mask;
586
587 if (ci != NULL && !CPU_IS_PRIMARY(ci))
588 return NULL;
589
590 if (pin < 0 || pin >= nitems(sc->sc_intx))
591 return NULL;
592
593 /* Mask the interrupt. */
594 mask = HREAD4(sc, IMASK_LOCAL);
595 mask &= ~(IMASK_INT_INTA << pin);
596 HWRITE4(sc, IMASK_LOCAL, mask);
597 intr_barrier(sc->sc_ih);
598
599 si = malloc(sizeof(*si), M_DEVBUF, M_WAITOK | M_ZERO);
600 si->si_func = func;
601 si->si_arg = arg;
602 si->si_ipl = level & IPL_IRQMASK;
603 si->si_flags = level & IPL_FLAGMASK;
604 si->si_pin = pin;
605 si->si_name = name;
606 if (name != NULL)
607 evcount_attach(&si->si_count, name, &si->si_pin);
608 si->si_sc = sc;
609 TAILQ_INSERT_TAIL(&sc->sc_intx[pin], si, si_next);
610
611 /* Unmask the interrupt. */
612 mask = HREAD4(sc, IMASK_LOCAL);
613 mask |= (IMASK_INT_INTA << pin);
614 HWRITE4(sc, IMASK_LOCAL, mask);
615
616 return si;
617 }
618
619 void
stfpcie_intx_intr_disestablish(void * cookie)620 stfpcie_intx_intr_disestablish(void *cookie)
621 {
622 struct stfpcie_intx *si = cookie;
623 struct stfpcie_softc *sc = si->si_sc;
624 uint32_t mask;
625
626 /* Mask the interrupt. */
627 mask = HREAD4(sc, IMASK_LOCAL);
628 mask &= ~(IMASK_INT_INTA << si->si_pin);
629 HWRITE4(sc, IMASK_LOCAL, mask);
630 intr_barrier(sc->sc_ih);
631
632 if (si->si_name)
633 evcount_detach(&si->si_count);
634
635 TAILQ_REMOVE(&sc->sc_intx[si->si_pin], si, si_next);
636
637 if (!TAILQ_EMPTY(&sc->sc_intx[si->si_pin])) {
638 /* Unmask the interrupt. */
639 mask = HREAD4(sc, IMASK_LOCAL);
640 mask |= (IMASK_INT_INTA << si->si_pin);
641 HWRITE4(sc, IMASK_LOCAL, mask);
642 }
643
644 free(si, M_DEVBUF, sizeof(*si));
645 }
646
647 void
stfpcie_intx_intr_barrier(void * cookie)648 stfpcie_intx_intr_barrier(void *cookie)
649 {
650 struct stfpcie_intx *si = cookie;
651 struct stfpcie_softc *sc = si->si_sc;
652
653 intr_barrier(sc->sc_ih);
654 }
655
656 struct stfpcie_msi *
stfpcie_msi_establish(struct stfpcie_softc * sc,int level,int (* func)(void *),void * arg,char * name)657 stfpcie_msi_establish(struct stfpcie_softc *sc, int level,
658 int (*func)(void *), void *arg, char *name)
659 {
660 struct stfpcie_msi *sm;
661 int vec;
662
663 for (vec = 0; vec < STFPCIE_NUM_MSI; vec++) {
664 sm = &sc->sc_msi[vec];
665 if (sm->sm_func == NULL)
666 break;
667 }
668 if (vec == STFPCIE_NUM_MSI)
669 return NULL;
670
671 sm->sm_func = func;
672 sm->sm_arg = arg;
673 sm->sm_ipl = level & IPL_IRQMASK;
674 sm->sm_flags = level & IPL_FLAGMASK;
675 sm->sm_vec = vec;
676 sm->sm_name = name;
677 if (name != NULL)
678 evcount_attach(&sm->sm_count, name, &sm->sm_vec);
679
680 return sm;
681
682 }
683
684 void
stfpcie_msi_disestablish(struct stfpcie_softc * sc,struct stfpcie_msi * sm)685 stfpcie_msi_disestablish(struct stfpcie_softc *sc, struct stfpcie_msi *sm)
686 {
687 if (sm->sm_name)
688 evcount_detach(&sm->sm_count);
689 sm->sm_func = NULL;
690 }
691
692 void
stfpcie_intx_intr(struct stfpcie_softc * sc,uint32_t status)693 stfpcie_intx_intr(struct stfpcie_softc *sc, uint32_t status)
694 {
695 struct stfpcie_intx *si;
696 int pin, s;
697
698 for (pin = 0; pin < nitems(sc->sc_intx); pin++) {
699 if ((status & (PM_MSI_INT_INTA << pin)) == 0)
700 continue;
701
702 TAILQ_FOREACH(si, &sc->sc_intx[pin], si_next) {
703 if ((si->si_flags & IPL_MPSAFE) == 0)
704 KERNEL_LOCK();
705 s = splraise(si->si_ipl);
706 if (si->si_func(si->si_arg))
707 si->si_count.ec_count++;
708 splx(s);
709 if ((si->si_flags & IPL_MPSAFE) == 0)
710 KERNEL_UNLOCK();
711 }
712 }
713 }
714
715 void
stfpcie_msi_intr(struct stfpcie_softc * sc)716 stfpcie_msi_intr(struct stfpcie_softc *sc)
717 {
718 struct stfpcie_msi *sm;
719 uint32_t status;
720 int vec, s;
721
722 status = HREAD4(sc, ISTATUS_MSI);
723 if (status == 0)
724 return;
725 HWRITE4(sc, ISTATUS_MSI, status);
726
727 while (status) {
728 vec = ffs(status) - 1;
729 status &= ~(1U << vec);
730
731 sm = &sc->sc_msi[vec];
732 if (sm->sm_func == NULL)
733 continue;
734
735 if ((sm->sm_flags & IPL_MPSAFE) == 0)
736 KERNEL_LOCK();
737 s = splraise(sm->sm_ipl);
738 if (sm->sm_func(sm->sm_arg))
739 sm->sm_count.ec_count++;
740 splx(s);
741 if ((sm->sm_flags & IPL_MPSAFE) == 0)
742 KERNEL_UNLOCK();
743 }
744 }
745
746 int
stfpcie_intr(void * arg)747 stfpcie_intr(void *arg)
748 {
749 struct stfpcie_softc *sc = arg;
750 uint32_t status;
751
752 status = HREAD4(sc, ISTATUS_LOCAL);
753 if (status == 0)
754 return 0;
755
756 if (status & PM_MSI_INT_INTX)
757 stfpcie_intx_intr(sc, status);
758
759 /*
760 * Ack INTx late as they are level-triggered. Ack MSI early
761 * as they are edge-triggered.
762 */
763 HWRITE4(sc, ISTATUS_LOCAL, status);
764
765 if (status & PM_MSI_INT_MSI)
766 stfpcie_msi_intr(sc);
767
768 return 1;
769 }
770
771 void
stfpcie_attach_hook(struct device * parent,struct device * self,struct pcibus_attach_args * pba)772 stfpcie_attach_hook(struct device *parent, struct device *self,
773 struct pcibus_attach_args *pba)
774 {
775 }
776
777 int
stfpcie_bus_maxdevs(void * v,int bus)778 stfpcie_bus_maxdevs(void *v, int bus)
779 {
780 struct stfpcie_softc *sc = v;
781
782 if (bus == sc->sc_bus || bus == sc->sc_bus + 1)
783 return 1;
784 return 32;
785 }
786
787 int
stfpcie_find_node(int node,int bus,int device,int function)788 stfpcie_find_node(int node, int bus, int device, int function)
789 {
790 uint32_t reg[5];
791 uint32_t phys_hi;
792 int child;
793
794 phys_hi = ((bus << 16) | (device << 11) | (function << 8));
795
796 for (child = OF_child(node); child; child = OF_peer(child)) {
797 if (OF_getpropintarray(child, "reg",
798 reg, sizeof(reg)) != sizeof(reg))
799 continue;
800
801 if (reg[0] == phys_hi)
802 return child;
803
804 node = stfpcie_find_node(child, bus, device, function);
805 if (node)
806 return node;
807 }
808
809 return 0;
810 }
811
812 pcitag_t
stfpcie_make_tag(void * v,int bus,int device,int function)813 stfpcie_make_tag(void *v, int bus, int device, int function)
814 {
815 struct stfpcie_softc *sc = v;
816 int node;
817
818 node = stfpcie_find_node(sc->sc_node, bus, device, function);
819 return (((pcitag_t)node << 32) |
820 (bus << 20) | (device << 15) | (function << 12));
821 }
822
823 void
stfpcie_decompose_tag(void * v,pcitag_t tag,int * bp,int * dp,int * fp)824 stfpcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
825 {
826 if (bp != NULL)
827 *bp = (tag >> 20) & 0xff;
828 if (dp != NULL)
829 *dp = (tag >> 15) & 0x1f;
830 if (fp != NULL)
831 *fp = (tag >> 12) & 0x7;
832 }
833
834 int
stfpcie_conf_size(void * v,pcitag_t tag)835 stfpcie_conf_size(void *v, pcitag_t tag)
836 {
837 return PCIE_CONFIG_SPACE_SIZE;
838 }
839
840 pcireg_t
stfpcie_conf_read(void * v,pcitag_t tag,int reg)841 stfpcie_conf_read(void *v, pcitag_t tag, int reg)
842 {
843 struct stfpcie_softc *sc = v;
844
845 tag = PCITAG_OFFSET(tag);
846 return bus_space_read_4(sc->sc_iot, sc->sc_cfg_ioh, tag | reg);
847 }
848
849 void
stfpcie_conf_write(void * v,pcitag_t tag,int reg,pcireg_t data)850 stfpcie_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
851 {
852 struct stfpcie_softc *sc = v;
853
854 tag = PCITAG_OFFSET(tag);
855 bus_space_write_4(sc->sc_iot, sc->sc_cfg_ioh, tag | reg, data);
856 }
857
858 int
stfpcie_probe_device_hook(void * v,struct pci_attach_args * pa)859 stfpcie_probe_device_hook(void *v, struct pci_attach_args *pa)
860 {
861 struct stfpcie_softc *sc = v;
862 uint16_t rid;
863
864 rid = pci_requester_id(pa->pa_pc, pa->pa_tag);
865 pa->pa_dmat = iommu_device_map_pci(sc->sc_node, rid, pa->pa_dmat);
866
867 return 0;
868 }
869
870 int
stfpcie_intr_map(struct pci_attach_args * pa,pci_intr_handle_t * ihp)871 stfpcie_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
872 {
873 int pin = pa->pa_rawintrpin;
874
875 if (pin == 0 || pin > PCI_INTERRUPT_PIN_MAX)
876 return -1;
877
878 if (pa->pa_tag == 0)
879 return -1;
880
881 ihp->ih_pc = pa->pa_pc;
882 ihp->ih_tag = pa->pa_intrtag;
883 ihp->ih_intrpin = pa->pa_intrpin;
884 ihp->ih_type = PCI_INTX;
885
886 return 0;
887 }
888
889 const char *
stfpcie_intr_string(void * v,pci_intr_handle_t ih)890 stfpcie_intr_string(void *v, pci_intr_handle_t ih)
891 {
892 switch (ih.ih_type) {
893 case PCI_MSI:
894 return "msi";
895 case PCI_MSIX:
896 return "msix";
897 }
898
899 return "intx";
900 }
901
902 void *
stfpcie_intr_establish(void * v,pci_intr_handle_t ih,int level,struct cpu_info * ci,int (* func)(void *),void * arg,char * name)903 stfpcie_intr_establish(void *v, pci_intr_handle_t ih, int level,
904 struct cpu_info *ci, int (*func)(void *), void *arg, char *name)
905 {
906 struct stfpcie_softc *sc = v;
907 struct stfpcie_intr_handle *pih;
908 void *cookie;
909
910 KASSERT(ih.ih_type != PCI_NONE);
911
912 if (ih.ih_type != PCI_INTX) {
913 struct stfpcie_msi *sm;
914 uint64_t addr, data;
915
916 sm = stfpcie_msi_establish(sc, level, func, arg, name);
917 if (sm == NULL)
918 return NULL;
919 addr = sc->sc_msi_addr;
920 data = sm->sm_vec;
921
922 pih = malloc(sizeof(*pih), M_DEVBUF, M_WAITOK | M_ZERO);
923 pih->pih_ih.ih_ic = &stfpcie_ic;
924 pih->pih_sc = sc;
925 pih->pih_sm = sm;
926
927 if (ih.ih_type == PCI_MSIX) {
928 pci_msix_enable(ih.ih_pc, ih.ih_tag,
929 &sc->sc_bus_memt, ih.ih_intrpin, addr, data);
930 } else
931 pci_msi_enable(ih.ih_pc, ih.ih_tag, addr, data);
932 } else {
933 int bus, dev, fn;
934 uint32_t reg[4];
935
936 stfpcie_decompose_tag(sc, ih.ih_tag, &bus, &dev, &fn);
937
938 reg[0] = bus << 16 | dev << 11 | fn << 8;
939 reg[1] = reg[2] = 0;
940 reg[3] = ih.ih_intrpin;
941
942 cookie = fdt_intr_establish_imap_cpu(sc->sc_node, reg,
943 sizeof(reg), level, ci, func, arg, name);
944 if (cookie == NULL)
945 return NULL;
946
947 pih = malloc(sizeof(*pih), M_DEVBUF, M_WAITOK | M_ZERO);
948 pih->pih_ih.ih_ic = &stfpcie_ic;
949 pih->pih_ih.ih_ih = cookie;
950 }
951
952 return pih;
953 }
954
955 void
stfpcie_intr_disestablish(void * v,void * cookie)956 stfpcie_intr_disestablish(void *v, void *cookie)
957 {
958 struct stfpcie_intr_handle *pih = cookie;
959
960 if (pih->pih_sm)
961 stfpcie_msi_disestablish(pih->pih_sc, pih->pih_sm);
962 else
963 fdt_intr_disestablish(pih->pih_ih.ih_ih);
964
965 free(pih, M_DEVBUF, sizeof(*pih));
966 }
967
968 int
stfpcie_bs_iomap(bus_space_tag_t t,bus_addr_t addr,bus_size_t size,int flags,bus_space_handle_t * bshp)969 stfpcie_bs_iomap(bus_space_tag_t t, bus_addr_t addr, bus_size_t size,
970 int flags, bus_space_handle_t *bshp)
971 {
972 struct stfpcie_softc *sc = t->bus_private;
973 int i;
974
975 for (i = 0; i < sc->sc_nranges; i++) {
976 uint64_t pci_start = sc->sc_ranges[i].pci_base;
977 uint64_t pci_end = pci_start + sc->sc_ranges[i].size;
978 uint64_t phys_start = sc->sc_ranges[i].phys_base;
979
980 if ((sc->sc_ranges[i].flags & 0x03000000) == 0x01000000 &&
981 addr >= pci_start && addr + size <= pci_end) {
982 return bus_space_map(sc->sc_iot,
983 addr - pci_start + phys_start, size, flags, bshp);
984 }
985 }
986
987 return ENXIO;
988 }
989
990 int
stfpcie_bs_memmap(bus_space_tag_t t,bus_addr_t addr,bus_size_t size,int flags,bus_space_handle_t * bshp)991 stfpcie_bs_memmap(bus_space_tag_t t, bus_addr_t addr, bus_size_t size,
992 int flags, bus_space_handle_t *bshp)
993 {
994 struct stfpcie_softc *sc = t->bus_private;
995 int i;
996
997 for (i = 0; i < sc->sc_nranges; i++) {
998 uint64_t pci_start = sc->sc_ranges[i].pci_base;
999 uint64_t pci_end = pci_start + sc->sc_ranges[i].size;
1000 uint64_t phys_start = sc->sc_ranges[i].phys_base;
1001
1002 if ((sc->sc_ranges[i].flags & 0x02000000) == 0x02000000 &&
1003 addr >= pci_start && addr + size <= pci_end) {
1004 return bus_space_map(sc->sc_iot,
1005 addr - pci_start + phys_start, size, flags, bshp);
1006 }
1007 }
1008
1009 return ENXIO;
1010 }
1011