1 /* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */
2 /* $FreeBSD: src/sys/dev/stge/if_stge.c,v 1.2 2006/08/12 01:21:36 yongari Exp $ */
3
4 /*-
5 * Copyright (c) 2001 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Jason R. Thorpe.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 /*
41 * Device driver for the Sundance Tech. TC9021 10/100/1000
42 * Ethernet controller.
43 */
44
45 #include "opt_ifpoll.h"
46
47 #include <sys/param.h>
48 #include <sys/bus.h>
49 #include <sys/endian.h>
50 #include <sys/kernel.h>
51 #include <sys/interrupt.h>
52 #include <sys/malloc.h>
53 #include <sys/mbuf.h>
54 #include <sys/module.h>
55 #include <sys/rman.h>
56 #include <sys/serialize.h>
57 #include <sys/socket.h>
58 #include <sys/sockio.h>
59 #include <sys/sysctl.h>
60
61 #include <net/bpf.h>
62 #include <net/ethernet.h>
63 #include <net/if.h>
64 #include <net/if_arp.h>
65 #include <net/if_dl.h>
66 #include <net/if_media.h>
67 #include <net/if_poll.h>
68 #include <net/if_types.h>
69 #include <net/ifq_var.h>
70 #include <net/vlan/if_vlan_var.h>
71 #include <net/vlan/if_vlan_ether.h>
72
73 #include <dev/netif/mii_layer/mii.h>
74 #include <dev/netif/mii_layer/miivar.h>
75
76 #include <bus/pci/pcireg.h>
77 #include <bus/pci/pcivar.h>
78
79 #include "if_stgereg.h"
80 #include "if_stgevar.h"
81
82 #define STGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
83
84 /* "device miibus" required. See GENERIC if you get errors here. */
85 #include "miibus_if.h"
86
87 /*
88 * Devices supported by this driver.
89 */
90 static struct stge_product {
91 uint16_t stge_vendorid;
92 uint16_t stge_deviceid;
93 const char *stge_name;
94 } stge_products[] = {
95 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST1023,
96 "Sundance ST-1023 Gigabit Ethernet" },
97
98 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST2021,
99 "Sundance ST-2021 Gigabit Ethernet" },
100
101 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021,
102 "Tamarack TC9021 Gigabit Ethernet" },
103
104 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021_ALT,
105 "Tamarack TC9021 Gigabit Ethernet" },
106
107 /*
108 * The Sundance sample boards use the Sundance vendor ID,
109 * but the Tamarack product ID.
110 */
111 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021,
112 "Sundance TC9021 Gigabit Ethernet" },
113
114 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021_ALT,
115 "Sundance TC9021 Gigabit Ethernet" },
116
117 { VENDOR_DLINK, DEVICEID_DLINK_DL2000,
118 "D-Link DL-2000 Gigabit Ethernet" },
119
120 { VENDOR_ANTARES, DEVICEID_ANTARES_TC9021,
121 "Antares Gigabit Ethernet" },
122
123 { 0, 0, NULL }
124 };
125
126 static int stge_probe(device_t);
127 static int stge_attach(device_t);
128 static int stge_detach(device_t);
129 static void stge_shutdown(device_t);
130 static int stge_suspend(device_t);
131 static int stge_resume(device_t);
132
133 static int stge_encap(struct stge_softc *, struct mbuf **);
134 static void stge_start(struct ifnet *, struct ifaltq_subque *);
135 static void stge_watchdog(struct ifnet *);
136 static int stge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
137 static void stge_init(void *);
138 static void stge_vlan_setup(struct stge_softc *);
139 static void stge_stop(struct stge_softc *);
140 static void stge_start_tx(struct stge_softc *);
141 static void stge_start_rx(struct stge_softc *);
142 static void stge_stop_tx(struct stge_softc *);
143 static void stge_stop_rx(struct stge_softc *);
144
145 static void stge_reset(struct stge_softc *, uint32_t);
146 static int stge_eeprom_wait(struct stge_softc *);
147 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *);
148 static void stge_tick(void *);
149 static void stge_stats_update(struct stge_softc *);
150 static void stge_set_filter(struct stge_softc *);
151 static void stge_set_multi(struct stge_softc *);
152
153 static void stge_link(struct stge_softc *);
154 static void stge_intr(void *);
155 static __inline int stge_tx_error(struct stge_softc *);
156 static void stge_txeof(struct stge_softc *);
157 static void stge_rxeof(struct stge_softc *, int);
158 static __inline void stge_discard_rxbuf(struct stge_softc *, int);
159 static int stge_newbuf(struct stge_softc *, int, int);
160 #ifndef __x86_64__
161 static __inline struct mbuf *stge_fixup_rx(struct stge_softc *, struct mbuf *);
162 #endif
163
164 static void stge_mii_sync(struct stge_softc *);
165 static void stge_mii_send(struct stge_softc *, uint32_t, int);
166 static int stge_mii_readreg(struct stge_softc *, struct stge_mii_frame *);
167 static int stge_mii_writereg(struct stge_softc *, struct stge_mii_frame *);
168 static int stge_miibus_readreg(device_t, int, int);
169 static int stge_miibus_writereg(device_t, int, int, int);
170 static void stge_miibus_statchg(device_t);
171 static int stge_mediachange(struct ifnet *);
172 static void stge_mediastatus(struct ifnet *, struct ifmediareq *);
173
174 static int stge_dma_alloc(struct stge_softc *);
175 static void stge_dma_free(struct stge_softc *);
176 static void stge_dma_wait(struct stge_softc *);
177 static void stge_init_tx_ring(struct stge_softc *);
178 static int stge_init_rx_ring(struct stge_softc *);
179 #ifdef IFPOLL_ENABLE
180 static void stge_npoll(struct ifnet *, struct ifpoll_info *);
181 static void stge_npoll_compat(struct ifnet *, void *, int);
182 #endif
183
184 static int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS);
185 static int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS);
186
187 static device_method_t stge_methods[] = {
188 /* Device interface */
189 DEVMETHOD(device_probe, stge_probe),
190 DEVMETHOD(device_attach, stge_attach),
191 DEVMETHOD(device_detach, stge_detach),
192 DEVMETHOD(device_shutdown, stge_shutdown),
193 DEVMETHOD(device_suspend, stge_suspend),
194 DEVMETHOD(device_resume, stge_resume),
195
196 /* MII interface */
197 DEVMETHOD(miibus_readreg, stge_miibus_readreg),
198 DEVMETHOD(miibus_writereg, stge_miibus_writereg),
199 DEVMETHOD(miibus_statchg, stge_miibus_statchg),
200
201 DEVMETHOD_END
202
203 };
204
205 static driver_t stge_driver = {
206 "stge",
207 stge_methods,
208 sizeof(struct stge_softc)
209 };
210
211 static devclass_t stge_devclass;
212
213 DECLARE_DUMMY_MODULE(if_stge);
214 MODULE_DEPEND(if_stge, miibus, 1, 1, 1);
215 DRIVER_MODULE(if_stge, pci, stge_driver, stge_devclass, NULL, NULL);
216 DRIVER_MODULE(miibus, stge, miibus_driver, miibus_devclass, NULL, NULL);
217
218 #define MII_SET(x) \
219 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) | (x))
220 #define MII_CLR(x) \
221 CSR_WRITE_1(sc, STGE_PhyCtrl, CSR_READ_1(sc, STGE_PhyCtrl) & ~(x))
222
223 /*
224 * Sync the PHYs by setting data bit and strobing the clock 32 times.
225 */
226 static void
stge_mii_sync(struct stge_softc * sc)227 stge_mii_sync(struct stge_softc *sc)
228 {
229 int i;
230
231 MII_SET(PC_MgmtDir | PC_MgmtData);
232
233 for (i = 0; i < 32; i++) {
234 MII_SET(PC_MgmtClk);
235 DELAY(1);
236 MII_CLR(PC_MgmtClk);
237 DELAY(1);
238 }
239 }
240
241 /*
242 * Clock a series of bits through the MII.
243 */
244 static void
stge_mii_send(struct stge_softc * sc,uint32_t bits,int cnt)245 stge_mii_send(struct stge_softc *sc, uint32_t bits, int cnt)
246 {
247 int i;
248
249 MII_CLR(PC_MgmtClk);
250
251 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
252 if (bits & i)
253 MII_SET(PC_MgmtData);
254 else
255 MII_CLR(PC_MgmtData);
256 DELAY(1);
257 MII_CLR(PC_MgmtClk);
258 DELAY(1);
259 MII_SET(PC_MgmtClk);
260 }
261 }
262
263 /*
264 * Read an PHY register through the MII.
265 */
266 static int
stge_mii_readreg(struct stge_softc * sc,struct stge_mii_frame * frame)267 stge_mii_readreg(struct stge_softc *sc, struct stge_mii_frame *frame)
268 {
269 int i, ack;
270
271 /*
272 * Set up frame for RX.
273 */
274 frame->mii_stdelim = STGE_MII_STARTDELIM;
275 frame->mii_opcode = STGE_MII_READOP;
276 frame->mii_turnaround = 0;
277 frame->mii_data = 0;
278
279 CSR_WRITE_1(sc, STGE_PhyCtrl, 0 | sc->sc_PhyCtrl);
280 /*
281 * Turn on data xmit.
282 */
283 MII_SET(PC_MgmtDir);
284
285 stge_mii_sync(sc);
286
287 /*
288 * Send command/address info.
289 */
290 stge_mii_send(sc, frame->mii_stdelim, 2);
291 stge_mii_send(sc, frame->mii_opcode, 2);
292 stge_mii_send(sc, frame->mii_phyaddr, 5);
293 stge_mii_send(sc, frame->mii_regaddr, 5);
294
295 /* Turn off xmit. */
296 MII_CLR(PC_MgmtDir);
297
298 /* Idle bit */
299 MII_CLR((PC_MgmtClk | PC_MgmtData));
300 DELAY(1);
301 MII_SET(PC_MgmtClk);
302 DELAY(1);
303
304 /* Check for ack */
305 MII_CLR(PC_MgmtClk);
306 DELAY(1);
307 ack = CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData;
308 MII_SET(PC_MgmtClk);
309 DELAY(1);
310
311 /*
312 * Now try reading data bits. If the ack failed, we still
313 * need to clock through 16 cycles to keep the PHY(s) in sync.
314 */
315 if (ack) {
316 for(i = 0; i < 16; i++) {
317 MII_CLR(PC_MgmtClk);
318 DELAY(1);
319 MII_SET(PC_MgmtClk);
320 DELAY(1);
321 }
322 goto fail;
323 }
324
325 for (i = 0x8000; i; i >>= 1) {
326 MII_CLR(PC_MgmtClk);
327 DELAY(1);
328 if (!ack) {
329 if (CSR_READ_1(sc, STGE_PhyCtrl) & PC_MgmtData)
330 frame->mii_data |= i;
331 DELAY(1);
332 }
333 MII_SET(PC_MgmtClk);
334 DELAY(1);
335 }
336
337 fail:
338 MII_CLR(PC_MgmtClk);
339 DELAY(1);
340 MII_SET(PC_MgmtClk);
341 DELAY(1);
342
343 if (ack)
344 return(1);
345 return(0);
346 }
347
348 /*
349 * Write to a PHY register through the MII.
350 */
351 static int
stge_mii_writereg(struct stge_softc * sc,struct stge_mii_frame * frame)352 stge_mii_writereg(struct stge_softc *sc, struct stge_mii_frame *frame)
353 {
354
355 /*
356 * Set up frame for TX.
357 */
358 frame->mii_stdelim = STGE_MII_STARTDELIM;
359 frame->mii_opcode = STGE_MII_WRITEOP;
360 frame->mii_turnaround = STGE_MII_TURNAROUND;
361
362 /*
363 * Turn on data output.
364 */
365 MII_SET(PC_MgmtDir);
366
367 stge_mii_sync(sc);
368
369 stge_mii_send(sc, frame->mii_stdelim, 2);
370 stge_mii_send(sc, frame->mii_opcode, 2);
371 stge_mii_send(sc, frame->mii_phyaddr, 5);
372 stge_mii_send(sc, frame->mii_regaddr, 5);
373 stge_mii_send(sc, frame->mii_turnaround, 2);
374 stge_mii_send(sc, frame->mii_data, 16);
375
376 /* Idle bit. */
377 MII_SET(PC_MgmtClk);
378 DELAY(1);
379 MII_CLR(PC_MgmtClk);
380 DELAY(1);
381
382 /*
383 * Turn off xmit.
384 */
385 MII_CLR(PC_MgmtDir);
386
387 return(0);
388 }
389
390 /*
391 * sc_miibus_readreg: [mii interface function]
392 *
393 * Read a PHY register on the MII of the TC9021.
394 */
395 static int
stge_miibus_readreg(device_t dev,int phy,int reg)396 stge_miibus_readreg(device_t dev, int phy, int reg)
397 {
398 struct stge_softc *sc;
399 struct stge_mii_frame frame;
400 int error;
401
402 sc = device_get_softc(dev);
403
404 if (reg == STGE_PhyCtrl) {
405 /* XXX allow ip1000phy read STGE_PhyCtrl register. */
406 error = CSR_READ_1(sc, STGE_PhyCtrl);
407 return (error);
408 }
409 bzero(&frame, sizeof(frame));
410 frame.mii_phyaddr = phy;
411 frame.mii_regaddr = reg;
412
413 error = stge_mii_readreg(sc, &frame);
414
415 if (error != 0) {
416 /* Don't show errors for PHY probe request */
417 if (reg != 1)
418 device_printf(sc->sc_dev, "phy read fail\n");
419 return (0);
420 }
421 return (frame.mii_data);
422 }
423
424 /*
425 * stge_miibus_writereg: [mii interface function]
426 *
427 * Write a PHY register on the MII of the TC9021.
428 */
429 static int
stge_miibus_writereg(device_t dev,int phy,int reg,int val)430 stge_miibus_writereg(device_t dev, int phy, int reg, int val)
431 {
432 struct stge_softc *sc;
433 struct stge_mii_frame frame;
434 int error;
435
436 sc = device_get_softc(dev);
437
438 bzero(&frame, sizeof(frame));
439 frame.mii_phyaddr = phy;
440 frame.mii_regaddr = reg;
441 frame.mii_data = val;
442
443 error = stge_mii_writereg(sc, &frame);
444
445 if (error != 0)
446 device_printf(sc->sc_dev, "phy write fail\n");
447 return (0);
448 }
449
450 /*
451 * stge_miibus_statchg: [mii interface function]
452 *
453 * Callback from MII layer when media changes.
454 */
455 static void
stge_miibus_statchg(device_t dev)456 stge_miibus_statchg(device_t dev)
457 {
458 struct stge_softc *sc;
459 struct mii_data *mii;
460
461 sc = device_get_softc(dev);
462 mii = device_get_softc(sc->sc_miibus);
463
464 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)
465 return;
466
467 sc->sc_MACCtrl = 0;
468 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0)
469 sc->sc_MACCtrl |= MC_DuplexSelect;
470 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) != 0)
471 sc->sc_MACCtrl |= MC_RxFlowControlEnable;
472 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) != 0)
473 sc->sc_MACCtrl |= MC_TxFlowControlEnable;
474
475 stge_link(sc);
476 }
477
478 /*
479 * stge_mediastatus: [ifmedia interface function]
480 *
481 * Get the current interface media status.
482 */
483 static void
stge_mediastatus(struct ifnet * ifp,struct ifmediareq * ifmr)484 stge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
485 {
486 struct stge_softc *sc;
487 struct mii_data *mii;
488
489 sc = ifp->if_softc;
490 mii = device_get_softc(sc->sc_miibus);
491
492 mii_pollstat(mii);
493 ifmr->ifm_status = mii->mii_media_status;
494 ifmr->ifm_active = mii->mii_media_active;
495 }
496
497 /*
498 * stge_mediachange: [ifmedia interface function]
499 *
500 * Set hardware to newly-selected media.
501 */
502 static int
stge_mediachange(struct ifnet * ifp)503 stge_mediachange(struct ifnet *ifp)
504 {
505 struct stge_softc *sc;
506 struct mii_data *mii;
507
508 sc = ifp->if_softc;
509 mii = device_get_softc(sc->sc_miibus);
510 mii_mediachg(mii);
511
512 return (0);
513 }
514
515 static int
stge_eeprom_wait(struct stge_softc * sc)516 stge_eeprom_wait(struct stge_softc *sc)
517 {
518 int i;
519
520 for (i = 0; i < STGE_TIMEOUT; i++) {
521 DELAY(1000);
522 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0)
523 return (0);
524 }
525 return (1);
526 }
527
528 /*
529 * stge_read_eeprom:
530 *
531 * Read data from the serial EEPROM.
532 */
533 static void
stge_read_eeprom(struct stge_softc * sc,int offset,uint16_t * data)534 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data)
535 {
536
537 if (stge_eeprom_wait(sc))
538 device_printf(sc->sc_dev, "EEPROM failed to come ready\n");
539
540 CSR_WRITE_2(sc, STGE_EepromCtrl,
541 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR));
542 if (stge_eeprom_wait(sc))
543 device_printf(sc->sc_dev, "EEPROM read timed out\n");
544 *data = CSR_READ_2(sc, STGE_EepromData);
545 }
546
547
548 static int
stge_probe(device_t dev)549 stge_probe(device_t dev)
550 {
551 struct stge_product *sp;
552 uint16_t vendor, devid;
553
554 vendor = pci_get_vendor(dev);
555 devid = pci_get_device(dev);
556
557 for (sp = stge_products; sp->stge_name != NULL; sp++) {
558 if (vendor == sp->stge_vendorid &&
559 devid == sp->stge_deviceid) {
560 device_set_desc(dev, sp->stge_name);
561 return (0);
562 }
563 }
564
565 return (ENXIO);
566 }
567
568 static int
stge_attach(device_t dev)569 stge_attach(device_t dev)
570 {
571 struct stge_softc *sc;
572 struct ifnet *ifp;
573 struct sysctl_ctx_list *ctx;
574 struct sysctl_oid *tree;
575 uint8_t enaddr[ETHER_ADDR_LEN];
576 int error, i;
577 uint16_t cmd;
578 uint32_t val;
579
580 error = 0;
581 sc = device_get_softc(dev);
582 sc->sc_dev = dev;
583 ifp = &sc->arpcom.ac_if;
584
585 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
586
587 callout_init(&sc->sc_tick_ch);
588
589 #ifndef BURN_BRIDGES
590 /*
591 * Handle power management nonsense.
592 */
593 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
594 uint32_t iobase, membase, irq;
595
596 /* Save important PCI config data. */
597 iobase = pci_read_config(dev, STGE_PCIR_LOIO, 4);
598 membase = pci_read_config(dev, STGE_PCIR_LOMEM, 4);
599 irq = pci_read_config(dev, PCIR_INTLINE, 4);
600
601 /* Reset the power state. */
602 device_printf(dev, "chip is in D%d power mode "
603 "-- setting to D0\n", pci_get_powerstate(dev));
604
605 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
606
607 /* Restore PCI config data. */
608 pci_write_config(dev, STGE_PCIR_LOIO, iobase, 4);
609 pci_write_config(dev, STGE_PCIR_LOMEM, membase, 4);
610 pci_write_config(dev, PCIR_INTLINE, irq, 4);
611 }
612 #endif
613
614 /*
615 * Map the device.
616 */
617 pci_enable_busmaster(dev);
618 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
619 val = pci_read_config(dev, STGE_PCIR_LOMEM, 4);
620
621 if ((val & 0x01) != 0) {
622 sc->sc_res_rid = STGE_PCIR_LOMEM;
623 sc->sc_res_type = SYS_RES_MEMORY;
624 } else {
625 sc->sc_res_rid = STGE_PCIR_LOIO;
626 sc->sc_res_type = SYS_RES_IOPORT;
627
628 val = pci_read_config(dev, sc->sc_res_rid, 4);
629 if ((val & 0x01) == 0) {
630 device_printf(dev, "couldn't locate IO BAR\n");
631 return ENXIO;
632 }
633 }
634
635 sc->sc_res = bus_alloc_resource_any(dev, sc->sc_res_type,
636 &sc->sc_res_rid, RF_ACTIVE);
637 if (sc->sc_res == NULL) {
638 device_printf(dev, "couldn't allocate resource\n");
639 return ENXIO;
640 }
641 sc->sc_btag = rman_get_bustag(sc->sc_res);
642 sc->sc_bhandle = rman_get_bushandle(sc->sc_res);
643
644 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
645 &sc->sc_irq_rid,
646 RF_ACTIVE | RF_SHAREABLE);
647 if (sc->sc_irq == NULL) {
648 device_printf(dev, "couldn't allocate IRQ\n");
649 error = ENXIO;
650 goto fail;
651 }
652
653 sc->sc_rev = pci_get_revid(dev);
654
655 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
656 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
657
658 ctx = device_get_sysctl_ctx(dev);
659 tree = device_get_sysctl_tree(dev);
660 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
661 "rxint_nframe", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_nframe, 0,
662 sysctl_hw_stge_rxint_nframe, "I", "stge rx interrupt nframe");
663
664 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
665 "rxint_dmawait", CTLTYPE_INT|CTLFLAG_RW, &sc->sc_rxint_dmawait, 0,
666 sysctl_hw_stge_rxint_dmawait, "I", "stge rx interrupt dmawait");
667
668 error = stge_dma_alloc(sc);
669 if (error != 0)
670 goto fail;
671
672 /*
673 * Determine if we're copper or fiber. It affects how we
674 * reset the card.
675 */
676 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)
677 sc->sc_usefiber = 1;
678 else
679 sc->sc_usefiber = 0;
680
681 /* Load LED configuration from EEPROM. */
682 stge_read_eeprom(sc, STGE_EEPROM_LEDMode, &sc->sc_led);
683
684 /*
685 * Reset the chip to a known state.
686 */
687 stge_reset(sc, STGE_RESET_FULL);
688
689 /*
690 * Reading the station address from the EEPROM doesn't seem
691 * to work, at least on my sample boards. Instead, since
692 * the reset sequence does AutoInit, read it from the station
693 * address registers. For Sundance 1023 you can only read it
694 * from EEPROM.
695 */
696 if (pci_get_device(dev) != DEVICEID_SUNDANCETI_ST1023) {
697 uint16_t v;
698
699 v = CSR_READ_2(sc, STGE_StationAddress0);
700 enaddr[0] = v & 0xff;
701 enaddr[1] = v >> 8;
702 v = CSR_READ_2(sc, STGE_StationAddress1);
703 enaddr[2] = v & 0xff;
704 enaddr[3] = v >> 8;
705 v = CSR_READ_2(sc, STGE_StationAddress2);
706 enaddr[4] = v & 0xff;
707 enaddr[5] = v >> 8;
708 sc->sc_stge1023 = 0;
709 } else {
710 uint16_t myaddr[ETHER_ADDR_LEN / 2];
711 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) {
712 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i,
713 &myaddr[i]);
714 myaddr[i] = le16toh(myaddr[i]);
715 }
716 bcopy(myaddr, enaddr, sizeof(enaddr));
717 sc->sc_stge1023 = 1;
718 }
719
720 ifp->if_softc = sc;
721 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
722 ifp->if_ioctl = stge_ioctl;
723 ifp->if_start = stge_start;
724 ifp->if_watchdog = stge_watchdog;
725 ifp->if_init = stge_init;
726 #ifdef IFPOLL_ENABLE
727 ifp->if_npoll = stge_npoll;
728 #endif
729 ifp->if_mtu = ETHERMTU;
730 ifq_set_maxlen(&ifp->if_snd, STGE_TX_RING_CNT - 1);
731 ifq_set_ready(&ifp->if_snd);
732 /* Revision B3 and earlier chips have checksum bug. */
733 if (sc->sc_rev >= 0x0c) {
734 ifp->if_hwassist = STGE_CSUM_FEATURES;
735 ifp->if_capabilities = IFCAP_HWCSUM;
736 } else {
737 ifp->if_hwassist = 0;
738 ifp->if_capabilities = 0;
739 }
740 ifp->if_capenable = ifp->if_capabilities;
741
742 /*
743 * Read some important bits from the PhyCtrl register.
744 */
745 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
746 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
747
748 /* Set up MII bus. */
749 if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, stge_mediachange,
750 stge_mediastatus)) != 0) {
751 device_printf(sc->sc_dev, "no PHY found!\n");
752 goto fail;
753 }
754
755 ether_ifattach(ifp, enaddr, NULL);
756
757 #ifdef IFPOLL_ENABLE
758 ifpoll_compat_setup(&sc->sc_npoll, ctx, (struct sysctl_oid *)tree,
759 device_get_unit(dev), ifp->if_serializer);
760 #endif
761
762 /* VLAN capability setup */
763 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
764 #ifdef notyet
765 if (sc->sc_rev >= 0x0c)
766 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
767 #endif
768 ifp->if_capenable = ifp->if_capabilities;
769
770 /*
771 * Tell the upper layer(s) we support long frames.
772 * Must appear after the call to ether_ifattach() because
773 * ether_ifattach() sets ifi_hdrlen to the default value.
774 */
775 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
776
777 /*
778 * The manual recommends disabling early transmit, so we
779 * do. It's disabled anyway, if using IP checksumming,
780 * since the entire packet must be in the FIFO in order
781 * for the chip to perform the checksum.
782 */
783 sc->sc_txthresh = 0x0fff;
784
785 /*
786 * Disable MWI if the PCI layer tells us to.
787 */
788 sc->sc_DMACtrl = 0;
789 if ((cmd & PCIM_CMD_MWRICEN) == 0)
790 sc->sc_DMACtrl |= DMAC_MWIDisable;
791
792 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sc_irq));
793
794 /*
795 * Hookup IRQ
796 */
797 error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE, stge_intr, sc,
798 &sc->sc_ih, ifp->if_serializer);
799 if (error != 0) {
800 ether_ifdetach(ifp);
801 device_printf(sc->sc_dev, "couldn't set up IRQ\n");
802 goto fail;
803 }
804
805 fail:
806 if (error != 0)
807 stge_detach(dev);
808
809 return (error);
810 }
811
812 static int
stge_detach(device_t dev)813 stge_detach(device_t dev)
814 {
815 struct stge_softc *sc = device_get_softc(dev);
816 struct ifnet *ifp = &sc->arpcom.ac_if;
817
818 if (device_is_attached(dev)) {
819 lwkt_serialize_enter(ifp->if_serializer);
820 /* XXX */
821 sc->sc_detach = 1;
822 stge_stop(sc);
823 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
824 lwkt_serialize_exit(ifp->if_serializer);
825
826 ether_ifdetach(ifp);
827 }
828
829 if (sc->sc_miibus != NULL)
830 device_delete_child(dev, sc->sc_miibus);
831 bus_generic_detach(dev);
832
833 stge_dma_free(sc);
834
835 if (sc->sc_irq != NULL) {
836 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
837 sc->sc_irq);
838 }
839 if (sc->sc_res != NULL) {
840 bus_release_resource(dev, sc->sc_res_type, sc->sc_res_rid,
841 sc->sc_res);
842 }
843
844 return (0);
845 }
846
847 static int
stge_dma_alloc(struct stge_softc * sc)848 stge_dma_alloc(struct stge_softc *sc)
849 {
850 struct stge_txdesc *txd;
851 struct stge_rxdesc *rxd;
852 int error, i;
853
854 /* create parent tag. */
855 error = bus_dma_tag_create(NULL, /* parent */
856 1, 0, /* algnmnt, boundary */
857 STGE_DMA_MAXADDR, /* lowaddr */
858 BUS_SPACE_MAXADDR, /* highaddr */
859 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
860 0, /* nsegments */
861 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
862 0, /* flags */
863 &sc->sc_cdata.stge_parent_tag);
864 if (error != 0) {
865 device_printf(sc->sc_dev, "failed to create parent DMA tag\n");
866 return error;
867 }
868
869 /* allocate Tx ring. */
870 sc->sc_rdata.stge_tx_ring =
871 bus_dmamem_coherent_any(sc->sc_cdata.stge_parent_tag,
872 STGE_RING_ALIGN, STGE_TX_RING_SZ,
873 BUS_DMA_WAITOK | BUS_DMA_ZERO,
874 &sc->sc_cdata.stge_tx_ring_tag,
875 &sc->sc_cdata.stge_tx_ring_map,
876 &sc->sc_rdata.stge_tx_ring_paddr);
877 if (sc->sc_rdata.stge_tx_ring == NULL) {
878 device_printf(sc->sc_dev,
879 "failed to allocate Tx ring\n");
880 return ENOMEM;
881 }
882
883 /* allocate Rx ring. */
884 sc->sc_rdata.stge_rx_ring =
885 bus_dmamem_coherent_any(sc->sc_cdata.stge_parent_tag,
886 STGE_RING_ALIGN, STGE_RX_RING_SZ,
887 BUS_DMA_WAITOK | BUS_DMA_ZERO,
888 &sc->sc_cdata.stge_rx_ring_tag,
889 &sc->sc_cdata.stge_rx_ring_map,
890 &sc->sc_rdata.stge_rx_ring_paddr);
891 if (sc->sc_rdata.stge_rx_ring == NULL) {
892 device_printf(sc->sc_dev,
893 "failed to allocate Rx ring\n");
894 return ENOMEM;
895 }
896
897 /* create tag for Tx buffers. */
898 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
899 1, 0, /* algnmnt, boundary */
900 BUS_SPACE_MAXADDR, /* lowaddr */
901 BUS_SPACE_MAXADDR, /* highaddr */
902 STGE_JUMBO_FRAMELEN, /* maxsize */
903 STGE_MAXTXSEGS, /* nsegments */
904 STGE_MAXSGSIZE, /* maxsegsize */
905 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,/* flags */
906 &sc->sc_cdata.stge_tx_tag);
907 if (error != 0) {
908 device_printf(sc->sc_dev, "failed to allocate Tx DMA tag\n");
909 return error;
910 }
911
912 /* create DMA maps for Tx buffers. */
913 for (i = 0; i < STGE_TX_RING_CNT; i++) {
914 txd = &sc->sc_cdata.stge_txdesc[i];
915 error = bus_dmamap_create(sc->sc_cdata.stge_tx_tag,
916 BUS_DMA_WAITOK, &txd->tx_dmamap);
917 if (error != 0) {
918 int j;
919
920 for (j = 0; j < i; ++j) {
921 txd = &sc->sc_cdata.stge_txdesc[j];
922 bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag,
923 txd->tx_dmamap);
924 }
925 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag);
926 sc->sc_cdata.stge_tx_tag = NULL;
927
928 device_printf(sc->sc_dev,
929 "failed to create Tx dmamap\n");
930 return error;
931 }
932 }
933
934 /* create tag for Rx buffers. */
935 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
936 1, 0, /* algnmnt, boundary */
937 BUS_SPACE_MAXADDR, /* lowaddr */
938 BUS_SPACE_MAXADDR, /* highaddr */
939 MCLBYTES, /* maxsize */
940 1, /* nsegments */
941 MCLBYTES, /* maxsegsize */
942 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,/* flags */
943 &sc->sc_cdata.stge_rx_tag);
944 if (error != 0) {
945 device_printf(sc->sc_dev, "failed to allocate Rx DMA tag\n");
946 return error;
947 }
948
949 /* create DMA maps for Rx buffers. */
950 error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, BUS_DMA_WAITOK,
951 &sc->sc_cdata.stge_rx_sparemap);
952 if (error != 0) {
953 device_printf(sc->sc_dev, "failed to create spare Rx dmamap\n");
954 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag);
955 sc->sc_cdata.stge_rx_tag = NULL;
956 return error;
957 }
958 for (i = 0; i < STGE_RX_RING_CNT; i++) {
959 rxd = &sc->sc_cdata.stge_rxdesc[i];
960 error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag,
961 BUS_DMA_WAITOK, &rxd->rx_dmamap);
962 if (error != 0) {
963 int j;
964
965 for (j = 0; j < i; ++j) {
966 rxd = &sc->sc_cdata.stge_rxdesc[j];
967 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
968 rxd->rx_dmamap);
969 }
970 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
971 sc->sc_cdata.stge_rx_sparemap);
972 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag);
973 sc->sc_cdata.stge_rx_tag = NULL;
974
975 device_printf(sc->sc_dev,
976 "failed to create Rx dmamap\n");
977 return error;
978 }
979 }
980 return 0;
981 }
982
983 static void
stge_dma_free(struct stge_softc * sc)984 stge_dma_free(struct stge_softc *sc)
985 {
986 struct stge_txdesc *txd;
987 struct stge_rxdesc *rxd;
988 int i;
989
990 /* Tx ring */
991 if (sc->sc_cdata.stge_tx_ring_tag) {
992 bus_dmamap_unload(sc->sc_cdata.stge_tx_ring_tag,
993 sc->sc_cdata.stge_tx_ring_map);
994 bus_dmamem_free(sc->sc_cdata.stge_tx_ring_tag,
995 sc->sc_rdata.stge_tx_ring,
996 sc->sc_cdata.stge_tx_ring_map);
997 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_ring_tag);
998 }
999
1000 /* Rx ring */
1001 if (sc->sc_cdata.stge_rx_ring_tag) {
1002 bus_dmamap_unload(sc->sc_cdata.stge_rx_ring_tag,
1003 sc->sc_cdata.stge_rx_ring_map);
1004 bus_dmamem_free(sc->sc_cdata.stge_rx_ring_tag,
1005 sc->sc_rdata.stge_rx_ring,
1006 sc->sc_cdata.stge_rx_ring_map);
1007 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_ring_tag);
1008 }
1009
1010 /* Tx buffers */
1011 if (sc->sc_cdata.stge_tx_tag) {
1012 for (i = 0; i < STGE_TX_RING_CNT; i++) {
1013 txd = &sc->sc_cdata.stge_txdesc[i];
1014 bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag,
1015 txd->tx_dmamap);
1016 }
1017 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag);
1018 }
1019
1020 /* Rx buffers */
1021 if (sc->sc_cdata.stge_rx_tag) {
1022 for (i = 0; i < STGE_RX_RING_CNT; i++) {
1023 rxd = &sc->sc_cdata.stge_rxdesc[i];
1024 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
1025 rxd->rx_dmamap);
1026 }
1027 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
1028 sc->sc_cdata.stge_rx_sparemap);
1029 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag);
1030 }
1031
1032 /* Top level tag */
1033 if (sc->sc_cdata.stge_parent_tag)
1034 bus_dma_tag_destroy(sc->sc_cdata.stge_parent_tag);
1035 }
1036
1037 /*
1038 * stge_shutdown:
1039 *
1040 * Make sure the interface is stopped at reboot time.
1041 */
1042 static void
stge_shutdown(device_t dev)1043 stge_shutdown(device_t dev)
1044 {
1045 struct stge_softc *sc = device_get_softc(dev);
1046 struct ifnet *ifp = &sc->arpcom.ac_if;
1047
1048 lwkt_serialize_enter(ifp->if_serializer);
1049 stge_stop(sc);
1050 lwkt_serialize_exit(ifp->if_serializer);
1051 }
1052
1053 static int
stge_suspend(device_t dev)1054 stge_suspend(device_t dev)
1055 {
1056 struct stge_softc *sc = device_get_softc(dev);
1057 struct ifnet *ifp = &sc->arpcom.ac_if;
1058
1059 lwkt_serialize_enter(ifp->if_serializer);
1060 stge_stop(sc);
1061 sc->sc_suspended = 1;
1062 lwkt_serialize_exit(ifp->if_serializer);
1063
1064 return (0);
1065 }
1066
1067 static int
stge_resume(device_t dev)1068 stge_resume(device_t dev)
1069 {
1070 struct stge_softc *sc = device_get_softc(dev);
1071 struct ifnet *ifp = &sc->arpcom.ac_if;
1072
1073 lwkt_serialize_enter(ifp->if_serializer);
1074 if (ifp->if_flags & IFF_UP)
1075 stge_init(sc);
1076 sc->sc_suspended = 0;
1077 lwkt_serialize_exit(ifp->if_serializer);
1078
1079 return (0);
1080 }
1081
1082 static void
stge_dma_wait(struct stge_softc * sc)1083 stge_dma_wait(struct stge_softc *sc)
1084 {
1085 int i;
1086
1087 for (i = 0; i < STGE_TIMEOUT; i++) {
1088 DELAY(2);
1089 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)
1090 break;
1091 }
1092
1093 if (i == STGE_TIMEOUT)
1094 device_printf(sc->sc_dev, "DMA wait timed out\n");
1095 }
1096
1097 static int
stge_encap(struct stge_softc * sc,struct mbuf ** m_head)1098 stge_encap(struct stge_softc *sc, struct mbuf **m_head)
1099 {
1100 struct stge_txdesc *txd;
1101 struct stge_tfd *tfd;
1102 struct mbuf *m;
1103 bus_dma_segment_t txsegs[STGE_MAXTXSEGS];
1104 int error, i, si, nsegs;
1105 uint64_t csum_flags, tfc;
1106
1107 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txfreeq);
1108 KKASSERT(txd != NULL);
1109
1110 error = bus_dmamap_load_mbuf_defrag(sc->sc_cdata.stge_tx_tag,
1111 txd->tx_dmamap, m_head,
1112 txsegs, STGE_MAXTXSEGS, &nsegs, BUS_DMA_NOWAIT);
1113 if (error) {
1114 m_freem(*m_head);
1115 *m_head = NULL;
1116 return (error);
1117 }
1118 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1119 BUS_DMASYNC_PREWRITE);
1120
1121 m = *m_head;
1122
1123 csum_flags = 0;
1124 if ((m->m_pkthdr.csum_flags & STGE_CSUM_FEATURES) != 0) {
1125 if (m->m_pkthdr.csum_flags & CSUM_IP)
1126 csum_flags |= TFD_IPChecksumEnable;
1127 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1128 csum_flags |= TFD_TCPChecksumEnable;
1129 else if (m->m_pkthdr.csum_flags & CSUM_UDP)
1130 csum_flags |= TFD_UDPChecksumEnable;
1131 }
1132
1133 si = sc->sc_cdata.stge_tx_prod;
1134 tfd = &sc->sc_rdata.stge_tx_ring[si];
1135 for (i = 0; i < nsegs; i++) {
1136 tfd->tfd_frags[i].frag_word0 =
1137 htole64(FRAG_ADDR(txsegs[i].ds_addr) |
1138 FRAG_LEN(txsegs[i].ds_len));
1139 }
1140 sc->sc_cdata.stge_tx_cnt++;
1141
1142 tfc = TFD_FrameId(si) | TFD_WordAlign(TFD_WordAlign_disable) |
1143 TFD_FragCount(nsegs) | csum_flags;
1144 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT)
1145 tfc |= TFD_TxDMAIndicate;
1146
1147 /* Update producer index. */
1148 sc->sc_cdata.stge_tx_prod = (si + 1) % STGE_TX_RING_CNT;
1149
1150 /* Check if we have a VLAN tag to insert. */
1151 if (m->m_flags & M_VLANTAG)
1152 tfc |= TFD_VLANTagInsert | TFD_VID(m->m_pkthdr.ether_vlantag);
1153 tfd->tfd_control = htole64(tfc);
1154
1155 /* Update Tx Queue. */
1156 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txfreeq, tx_q);
1157 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txbusyq, txd, tx_q);
1158 txd->tx_m = m;
1159
1160 return (0);
1161 }
1162
1163 /*
1164 * stge_start: [ifnet interface function]
1165 *
1166 * Start packet transmission on the interface.
1167 */
1168 static void
stge_start(struct ifnet * ifp,struct ifaltq_subque * ifsq)1169 stge_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1170 {
1171 struct stge_softc *sc;
1172 struct mbuf *m_head;
1173 int enq;
1174
1175 sc = ifp->if_softc;
1176
1177 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1178 ASSERT_SERIALIZED(ifp->if_serializer);
1179
1180 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1181 return;
1182
1183 enq = 0;
1184 while (!ifq_is_empty(&ifp->if_snd)) {
1185 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) {
1186 ifq_set_oactive(&ifp->if_snd);
1187 break;
1188 }
1189
1190 m_head = ifq_dequeue(&ifp->if_snd);
1191 if (m_head == NULL)
1192 break;
1193
1194 /*
1195 * Pack the data into the transmit ring. If we
1196 * don't have room, set the OACTIVE flag and wait
1197 * for the NIC to drain the ring.
1198 */
1199 if (stge_encap(sc, &m_head)) {
1200 if (sc->sc_cdata.stge_tx_cnt == 0) {
1201 continue;
1202 } else {
1203 ifq_set_oactive(&ifp->if_snd);
1204 break;
1205 }
1206 }
1207 enq = 1;
1208
1209 /*
1210 * If there's a BPF listener, bounce a copy of this frame
1211 * to him.
1212 */
1213 ETHER_BPF_MTAP(ifp, m_head);
1214 }
1215
1216 if (enq) {
1217 /* Transmit */
1218 CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow);
1219
1220 /* Set a timeout in case the chip goes out to lunch. */
1221 ifp->if_timer = 5;
1222 }
1223 }
1224
1225 /*
1226 * stge_watchdog: [ifnet interface function]
1227 *
1228 * Watchdog timer handler.
1229 */
1230 static void
stge_watchdog(struct ifnet * ifp)1231 stge_watchdog(struct ifnet *ifp)
1232 {
1233 ASSERT_SERIALIZED(ifp->if_serializer);
1234
1235 if_printf(ifp, "device timeout\n");
1236 IFNET_STAT_INC(ifp, oerrors, 1);
1237 stge_init(ifp->if_softc);
1238 }
1239
1240 /*
1241 * stge_ioctl: [ifnet interface function]
1242 *
1243 * Handle control requests from the operator.
1244 */
1245 static int
stge_ioctl(struct ifnet * ifp,u_long cmd,caddr_t data,struct ucred * cr)1246 stge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1247 {
1248 struct stge_softc *sc;
1249 struct ifreq *ifr;
1250 struct mii_data *mii;
1251 int error, mask;
1252
1253 ASSERT_SERIALIZED(ifp->if_serializer);
1254
1255 sc = ifp->if_softc;
1256 ifr = (struct ifreq *)data;
1257 error = 0;
1258 switch (cmd) {
1259 case SIOCSIFMTU:
1260 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > STGE_JUMBO_MTU)
1261 error = EINVAL;
1262 else if (ifp->if_mtu != ifr->ifr_mtu) {
1263 ifp->if_mtu = ifr->ifr_mtu;
1264 stge_init(sc);
1265 }
1266 break;
1267 case SIOCSIFFLAGS:
1268 if ((ifp->if_flags & IFF_UP) != 0) {
1269 if ((ifp->if_flags & IFF_RUNNING) != 0) {
1270 if (((ifp->if_flags ^ sc->sc_if_flags)
1271 & IFF_PROMISC) != 0)
1272 stge_set_filter(sc);
1273 } else {
1274 if (sc->sc_detach == 0)
1275 stge_init(sc);
1276 }
1277 } else {
1278 if ((ifp->if_flags & IFF_RUNNING) != 0)
1279 stge_stop(sc);
1280 }
1281 sc->sc_if_flags = ifp->if_flags;
1282 break;
1283 case SIOCADDMULTI:
1284 case SIOCDELMULTI:
1285 if ((ifp->if_flags & IFF_RUNNING) != 0)
1286 stge_set_multi(sc);
1287 break;
1288 case SIOCSIFMEDIA:
1289 case SIOCGIFMEDIA:
1290 mii = device_get_softc(sc->sc_miibus);
1291 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1292 break;
1293 case SIOCSIFCAP:
1294 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1295 if ((mask & IFCAP_HWCSUM) != 0) {
1296 ifp->if_capenable ^= IFCAP_HWCSUM;
1297 if ((IFCAP_HWCSUM & ifp->if_capenable) != 0 &&
1298 (IFCAP_HWCSUM & ifp->if_capabilities) != 0)
1299 ifp->if_hwassist = STGE_CSUM_FEATURES;
1300 else
1301 ifp->if_hwassist = 0;
1302 }
1303 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
1304 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1305 if (ifp->if_flags & IFF_RUNNING)
1306 stge_vlan_setup(sc);
1307 }
1308 #if 0
1309 VLAN_CAPABILITIES(ifp);
1310 #endif
1311 break;
1312 default:
1313 error = ether_ioctl(ifp, cmd, data);
1314 break;
1315 }
1316
1317 return (error);
1318 }
1319
1320 static void
stge_link(struct stge_softc * sc)1321 stge_link(struct stge_softc *sc)
1322 {
1323 uint32_t v, ac;
1324 int i;
1325
1326 /*
1327 * Update STGE_MACCtrl register depending on link status.
1328 * (duplex, flow control etc)
1329 */
1330 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
1331 v &= ~(MC_DuplexSelect|MC_RxFlowControlEnable|MC_TxFlowControlEnable);
1332 v |= sc->sc_MACCtrl;
1333 CSR_WRITE_4(sc, STGE_MACCtrl, v);
1334 if (((ac ^ sc->sc_MACCtrl) & MC_DuplexSelect) != 0) {
1335 /* Duplex setting changed, reset Tx/Rx functions. */
1336 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1337 ac |= AC_TxReset | AC_RxReset;
1338 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1339 for (i = 0; i < STGE_TIMEOUT; i++) {
1340 DELAY(100);
1341 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1342 break;
1343 }
1344 if (i == STGE_TIMEOUT)
1345 device_printf(sc->sc_dev, "reset failed to complete\n");
1346 }
1347 }
1348
1349 static __inline int
stge_tx_error(struct stge_softc * sc)1350 stge_tx_error(struct stge_softc *sc)
1351 {
1352 uint32_t txstat;
1353 int error;
1354
1355 for (error = 0;;) {
1356 txstat = CSR_READ_4(sc, STGE_TxStatus);
1357 if ((txstat & TS_TxComplete) == 0)
1358 break;
1359 /* Tx underrun */
1360 if ((txstat & TS_TxUnderrun) != 0) {
1361 /*
1362 * XXX
1363 * There should be a more better way to recover
1364 * from Tx underrun instead of a full reset.
1365 */
1366 if (sc->sc_nerr++ < STGE_MAXERR)
1367 device_printf(sc->sc_dev, "Tx underrun, "
1368 "resetting...\n");
1369 if (sc->sc_nerr == STGE_MAXERR)
1370 device_printf(sc->sc_dev, "too many errors; "
1371 "not reporting any more\n");
1372 error = -1;
1373 break;
1374 }
1375 /* Maximum/Late collisions, Re-enable Tx MAC. */
1376 if ((txstat & (TS_MaxCollisions|TS_LateCollision)) != 0)
1377 CSR_WRITE_4(sc, STGE_MACCtrl,
1378 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) |
1379 MC_TxEnable);
1380 }
1381
1382 return (error);
1383 }
1384
1385 /*
1386 * stge_intr:
1387 *
1388 * Interrupt service routine.
1389 */
1390 static void
stge_intr(void * arg)1391 stge_intr(void *arg)
1392 {
1393 struct stge_softc *sc = arg;
1394 struct ifnet *ifp = &sc->arpcom.ac_if;
1395 int reinit;
1396 uint16_t status;
1397
1398 ASSERT_SERIALIZED(ifp->if_serializer);
1399
1400 status = CSR_READ_2(sc, STGE_IntStatus);
1401 if (sc->sc_suspended || (status & IS_InterruptStatus) == 0)
1402 return;
1403
1404 /* Disable interrupts. */
1405 for (reinit = 0;;) {
1406 status = CSR_READ_2(sc, STGE_IntStatusAck);
1407 status &= sc->sc_IntEnable;
1408 if (status == 0)
1409 break;
1410 /* Host interface errors. */
1411 if ((status & IS_HostError) != 0) {
1412 device_printf(sc->sc_dev,
1413 "Host interface error, resetting...\n");
1414 reinit = 1;
1415 goto force_init;
1416 }
1417
1418 /* Receive interrupts. */
1419 if ((status & IS_RxDMAComplete) != 0) {
1420 stge_rxeof(sc, -1);
1421 if ((status & IS_RFDListEnd) != 0)
1422 CSR_WRITE_4(sc, STGE_DMACtrl,
1423 DMAC_RxDMAPollNow);
1424 }
1425
1426 /* Transmit interrupts. */
1427 if ((status & (IS_TxDMAComplete | IS_TxComplete)) != 0)
1428 stge_txeof(sc);
1429
1430 /* Transmission errors.*/
1431 if ((status & IS_TxComplete) != 0) {
1432 if ((reinit = stge_tx_error(sc)) != 0)
1433 break;
1434 }
1435 }
1436
1437 force_init:
1438 if (reinit != 0)
1439 stge_init(sc);
1440
1441 /* Re-enable interrupts. */
1442 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1443
1444 /* Try to get more packets going. */
1445 if (!ifq_is_empty(&ifp->if_snd))
1446 if_devstart(ifp);
1447 }
1448
1449 /*
1450 * stge_txeof:
1451 *
1452 * Helper; handle transmit interrupts.
1453 */
1454 static void
stge_txeof(struct stge_softc * sc)1455 stge_txeof(struct stge_softc *sc)
1456 {
1457 struct ifnet *ifp = &sc->arpcom.ac_if;
1458 struct stge_txdesc *txd;
1459 uint64_t control;
1460 int cons;
1461
1462 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1463 if (txd == NULL)
1464 return;
1465
1466 /*
1467 * Go through our Tx list and free mbufs for those
1468 * frames which have been transmitted.
1469 */
1470 for (cons = sc->sc_cdata.stge_tx_cons;;
1471 cons = (cons + 1) % STGE_TX_RING_CNT) {
1472 if (sc->sc_cdata.stge_tx_cnt <= 0)
1473 break;
1474 control = le64toh(sc->sc_rdata.stge_tx_ring[cons].tfd_control);
1475 if ((control & TFD_TFDDone) == 0)
1476 break;
1477 sc->sc_cdata.stge_tx_cnt--;
1478
1479 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap);
1480
1481 /* Output counter is updated with statistics register */
1482 m_freem(txd->tx_m);
1483 txd->tx_m = NULL;
1484 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txbusyq, tx_q);
1485 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
1486 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1487 }
1488 sc->sc_cdata.stge_tx_cons = cons;
1489
1490 if (sc->sc_cdata.stge_tx_cnt < STGE_TX_HIWAT)
1491 ifq_clr_oactive(&ifp->if_snd);
1492 if (sc->sc_cdata.stge_tx_cnt == 0)
1493 ifp->if_timer = 0;
1494 }
1495
1496 static __inline void
stge_discard_rxbuf(struct stge_softc * sc,int idx)1497 stge_discard_rxbuf(struct stge_softc *sc, int idx)
1498 {
1499 struct stge_rfd *rfd;
1500
1501 rfd = &sc->sc_rdata.stge_rx_ring[idx];
1502 rfd->rfd_status = 0;
1503 }
1504
1505 #ifndef __x86_64__
1506 /*
1507 * It seems that TC9021's DMA engine has alignment restrictions in
1508 * DMA scatter operations. The first DMA segment has no address
1509 * alignment restrictins but the rest should be aligned on 4(?) bytes
1510 * boundary. Otherwise it would corrupt random memory. Since we don't
1511 * know which one is used for the first segment in advance we simply
1512 * don't align at all.
1513 * To avoid copying over an entire frame to align, we allocate a new
1514 * mbuf and copy ethernet header to the new mbuf. The new mbuf is
1515 * prepended into the existing mbuf chain.
1516 */
1517 static __inline struct mbuf *
stge_fixup_rx(struct stge_softc * sc,struct mbuf * m)1518 stge_fixup_rx(struct stge_softc *sc, struct mbuf *m)
1519 {
1520 struct mbuf *n;
1521
1522 n = NULL;
1523 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
1524 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
1525 m->m_data += ETHER_HDR_LEN;
1526 n = m;
1527 } else {
1528 MGETHDR(n, M_NOWAIT, MT_DATA);
1529 if (n != NULL) {
1530 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
1531 m->m_data += ETHER_HDR_LEN;
1532 m->m_len -= ETHER_HDR_LEN;
1533 n->m_len = ETHER_HDR_LEN;
1534 M_MOVE_PKTHDR(n, m);
1535 n->m_next = m;
1536 } else
1537 m_freem(m);
1538 }
1539
1540 return (n);
1541 }
1542 #endif
1543
1544 /*
1545 * stge_rxeof:
1546 *
1547 * Helper; handle receive interrupts.
1548 */
1549 static void
stge_rxeof(struct stge_softc * sc,int count)1550 stge_rxeof(struct stge_softc *sc, int count)
1551 {
1552 struct ifnet *ifp = &sc->arpcom.ac_if;
1553 struct stge_rxdesc *rxd;
1554 struct mbuf *mp, *m;
1555 uint64_t status64;
1556 uint32_t status;
1557 int cons, prog;
1558
1559 prog = 0;
1560 for (cons = sc->sc_cdata.stge_rx_cons; prog < STGE_RX_RING_CNT;
1561 prog++, cons = (cons + 1) % STGE_RX_RING_CNT) {
1562 #ifdef IFPOLL_ENABLE
1563 if (count >= 0 && count-- == 0)
1564 break;
1565 #endif
1566
1567 status64 = le64toh(sc->sc_rdata.stge_rx_ring[cons].rfd_status);
1568 status = RFD_RxStatus(status64);
1569 if ((status & RFD_RFDDone) == 0)
1570 break;
1571
1572 prog++;
1573 rxd = &sc->sc_cdata.stge_rxdesc[cons];
1574 mp = rxd->rx_m;
1575
1576 /*
1577 * If the packet had an error, drop it. Note we count
1578 * the error later in the periodic stats update.
1579 */
1580 if ((status & RFD_FrameEnd) != 0 && (status &
1581 (RFD_RxFIFOOverrun | RFD_RxRuntFrame |
1582 RFD_RxAlignmentError | RFD_RxFCSError |
1583 RFD_RxLengthError)) != 0) {
1584 stge_discard_rxbuf(sc, cons);
1585 if (sc->sc_cdata.stge_rxhead != NULL) {
1586 m_freem(sc->sc_cdata.stge_rxhead);
1587 STGE_RXCHAIN_RESET(sc);
1588 }
1589 continue;
1590 }
1591 /*
1592 * Add a new receive buffer to the ring.
1593 */
1594 if (stge_newbuf(sc, cons, 0) != 0) {
1595 IFNET_STAT_INC(ifp, iqdrops, 1);
1596 stge_discard_rxbuf(sc, cons);
1597 if (sc->sc_cdata.stge_rxhead != NULL) {
1598 m_freem(sc->sc_cdata.stge_rxhead);
1599 STGE_RXCHAIN_RESET(sc);
1600 }
1601 continue;
1602 }
1603
1604 if ((status & RFD_FrameEnd) != 0)
1605 mp->m_len = RFD_RxDMAFrameLen(status) -
1606 sc->sc_cdata.stge_rxlen;
1607 sc->sc_cdata.stge_rxlen += mp->m_len;
1608
1609 /* Chain mbufs. */
1610 if (sc->sc_cdata.stge_rxhead == NULL) {
1611 sc->sc_cdata.stge_rxhead = mp;
1612 sc->sc_cdata.stge_rxtail = mp;
1613 } else {
1614 mp->m_flags &= ~M_PKTHDR;
1615 sc->sc_cdata.stge_rxtail->m_next = mp;
1616 sc->sc_cdata.stge_rxtail = mp;
1617 }
1618
1619 if ((status & RFD_FrameEnd) != 0) {
1620 m = sc->sc_cdata.stge_rxhead;
1621 m->m_pkthdr.rcvif = ifp;
1622 m->m_pkthdr.len = sc->sc_cdata.stge_rxlen;
1623
1624 if (m->m_pkthdr.len > sc->sc_if_framesize) {
1625 m_freem(m);
1626 STGE_RXCHAIN_RESET(sc);
1627 continue;
1628 }
1629 /*
1630 * Set the incoming checksum information for
1631 * the packet.
1632 */
1633 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1634 if ((status & RFD_IPDetected) != 0) {
1635 m->m_pkthdr.csum_flags |=
1636 CSUM_IP_CHECKED;
1637 if ((status & RFD_IPError) == 0)
1638 m->m_pkthdr.csum_flags |=
1639 CSUM_IP_VALID;
1640 }
1641 if (((status & RFD_TCPDetected) != 0 &&
1642 (status & RFD_TCPError) == 0) ||
1643 ((status & RFD_UDPDetected) != 0 &&
1644 (status & RFD_UDPError) == 0)) {
1645 m->m_pkthdr.csum_flags |=
1646 (CSUM_DATA_VALID |
1647 CSUM_PSEUDO_HDR |
1648 CSUM_FRAG_NOT_CHECKED);
1649 m->m_pkthdr.csum_data = 0xffff;
1650 }
1651 }
1652
1653 #ifndef __x86_64__
1654 if (sc->sc_if_framesize > (MCLBYTES - ETHER_ALIGN)) {
1655 if ((m = stge_fixup_rx(sc, m)) == NULL) {
1656 STGE_RXCHAIN_RESET(sc);
1657 continue;
1658 }
1659 }
1660 #endif
1661
1662 /* Check for VLAN tagged packets. */
1663 if ((status & RFD_VLANDetected) != 0 &&
1664 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
1665 m->m_flags |= M_VLANTAG;
1666 m->m_pkthdr.ether_vlantag = RFD_TCI(status64);
1667 }
1668 /* Pass it on. */
1669 ifp->if_input(ifp, m, NULL, -1);
1670
1671 STGE_RXCHAIN_RESET(sc);
1672 }
1673 }
1674
1675 if (prog > 0) {
1676 /* Update the consumer index. */
1677 sc->sc_cdata.stge_rx_cons = cons;
1678 }
1679 }
1680
1681 #ifdef IFPOLL_ENABLE
1682
1683 static void
stge_npoll_compat(struct ifnet * ifp,void * arg __unused,int count)1684 stge_npoll_compat(struct ifnet *ifp, void *arg __unused, int count)
1685 {
1686 struct stge_softc *sc = ifp->if_softc;
1687
1688 ASSERT_SERIALIZED(ifp->if_serializer);
1689
1690 if (sc->sc_npoll.ifpc_stcount-- == 0) {
1691 uint16_t status;
1692
1693 sc->sc_npoll.ifpc_stcount = sc->sc_npoll.ifpc_stfrac;
1694
1695 status = CSR_READ_2(sc, STGE_IntStatus);
1696 status &= sc->sc_IntEnable;
1697 if (status != 0) {
1698 if (status & IS_HostError) {
1699 device_printf(sc->sc_dev,
1700 "Host interface error, "
1701 "resetting...\n");
1702 stge_init(sc);
1703 }
1704 if ((status & IS_TxComplete) != 0 &&
1705 stge_tx_error(sc) != 0)
1706 stge_init(sc);
1707 }
1708 }
1709
1710 stge_rxeof(sc, count);
1711 stge_txeof(sc);
1712
1713 if (!ifq_is_empty(&ifp->if_snd))
1714 if_devstart(ifp);
1715 }
1716
1717 static void
stge_npoll(struct ifnet * ifp,struct ifpoll_info * info)1718 stge_npoll(struct ifnet *ifp, struct ifpoll_info *info)
1719 {
1720 struct stge_softc *sc = ifp->if_softc;
1721
1722 ASSERT_SERIALIZED(ifp->if_serializer);
1723
1724 if (info != NULL) {
1725 int cpuid = sc->sc_npoll.ifpc_cpuid;
1726
1727 info->ifpi_rx[cpuid].poll_func = stge_npoll_compat;
1728 info->ifpi_rx[cpuid].arg = NULL;
1729 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
1730
1731 if (ifp->if_flags & IFF_RUNNING) {
1732 CSR_WRITE_2(sc, STGE_IntEnable, 0);
1733 sc->sc_npoll.ifpc_stcount = 0;
1734 }
1735 ifq_set_cpuid(&ifp->if_snd, cpuid);
1736 } else {
1737 if (ifp->if_flags & IFF_RUNNING)
1738 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1739 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sc_irq));
1740 }
1741 }
1742
1743 #endif /* IFPOLL_ENABLE */
1744
1745 /*
1746 * stge_tick:
1747 *
1748 * One second timer, used to tick the MII.
1749 */
1750 static void
stge_tick(void * arg)1751 stge_tick(void *arg)
1752 {
1753 struct stge_softc *sc = arg;
1754 struct ifnet *ifp = &sc->arpcom.ac_if;
1755 struct mii_data *mii;
1756
1757 lwkt_serialize_enter(ifp->if_serializer);
1758
1759 mii = device_get_softc(sc->sc_miibus);
1760 mii_tick(mii);
1761
1762 /* Update statistics counters. */
1763 stge_stats_update(sc);
1764
1765 /*
1766 * Relcaim any pending Tx descriptors to release mbufs in a
1767 * timely manner as we don't generate Tx completion interrupts
1768 * for every frame. This limits the delay to a maximum of one
1769 * second.
1770 */
1771 if (sc->sc_cdata.stge_tx_cnt != 0)
1772 stge_txeof(sc);
1773
1774 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
1775
1776 lwkt_serialize_exit(ifp->if_serializer);
1777 }
1778
1779 /*
1780 * stge_stats_update:
1781 *
1782 * Read the TC9021 statistics counters.
1783 */
1784 static void
stge_stats_update(struct stge_softc * sc)1785 stge_stats_update(struct stge_softc *sc)
1786 {
1787 struct ifnet *ifp = &sc->arpcom.ac_if;
1788
1789 CSR_READ_4(sc,STGE_OctetRcvOk);
1790
1791 IFNET_STAT_INC(ifp, ipackets, CSR_READ_4(sc, STGE_FramesRcvdOk));
1792
1793 IFNET_STAT_INC(ifp, ierrors, CSR_READ_2(sc, STGE_FramesLostRxErrors));
1794
1795 CSR_READ_4(sc, STGE_OctetXmtdOk);
1796
1797 IFNET_STAT_INC(ifp, opackets, CSR_READ_4(sc, STGE_FramesXmtdOk));
1798
1799 IFNET_STAT_INC(ifp, collisions,
1800 CSR_READ_4(sc, STGE_LateCollisions) +
1801 CSR_READ_4(sc, STGE_MultiColFrames) +
1802 CSR_READ_4(sc, STGE_SingleColFrames));
1803
1804 IFNET_STAT_INC(ifp, oerrors,
1805 CSR_READ_2(sc, STGE_FramesAbortXSColls) +
1806 CSR_READ_2(sc, STGE_FramesWEXDeferal));
1807 }
1808
1809 /*
1810 * stge_reset:
1811 *
1812 * Perform a soft reset on the TC9021.
1813 */
1814 static void
stge_reset(struct stge_softc * sc,uint32_t how)1815 stge_reset(struct stge_softc *sc, uint32_t how)
1816 {
1817 uint32_t ac;
1818 uint8_t v;
1819 int i, dv;
1820
1821 dv = 5000;
1822 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1823 switch (how) {
1824 case STGE_RESET_TX:
1825 ac |= AC_TxReset | AC_FIFO;
1826 dv = 100;
1827 break;
1828 case STGE_RESET_RX:
1829 ac |= AC_RxReset | AC_FIFO;
1830 dv = 100;
1831 break;
1832 case STGE_RESET_FULL:
1833 default:
1834 /*
1835 * Only assert RstOut if we're fiber. We need GMII clocks
1836 * to be present in order for the reset to complete on fiber
1837 * cards.
1838 */
1839 ac |= AC_GlobalReset | AC_RxReset | AC_TxReset |
1840 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit |
1841 (sc->sc_usefiber ? AC_RstOut : 0);
1842 break;
1843 }
1844
1845 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1846
1847 /* Account for reset problem at 10Mbps. */
1848 DELAY(dv);
1849
1850 for (i = 0; i < STGE_TIMEOUT; i++) {
1851 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1852 break;
1853 DELAY(dv);
1854 }
1855
1856 if (i == STGE_TIMEOUT)
1857 device_printf(sc->sc_dev, "reset failed to complete\n");
1858
1859 /* Set LED, from Linux IPG driver. */
1860 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1861 ac &= ~(AC_LEDMode | AC_LEDSpeed | AC_LEDModeBit1);
1862 if ((sc->sc_led & 0x01) != 0)
1863 ac |= AC_LEDMode;
1864 if ((sc->sc_led & 0x03) != 0)
1865 ac |= AC_LEDModeBit1;
1866 if ((sc->sc_led & 0x08) != 0)
1867 ac |= AC_LEDSpeed;
1868 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1869
1870 /* Set PHY, from Linux IPG driver */
1871 v = CSR_READ_1(sc, STGE_PhySet);
1872 v &= ~(PS_MemLenb9b | PS_MemLen | PS_NonCompdet);
1873 v |= ((sc->sc_led & 0x70) >> 4);
1874 CSR_WRITE_1(sc, STGE_PhySet, v);
1875 }
1876
1877 /*
1878 * stge_init: [ ifnet interface function ]
1879 *
1880 * Initialize the interface.
1881 */
1882 static void
stge_init(void * xsc)1883 stge_init(void *xsc)
1884 {
1885 struct stge_softc *sc = xsc;
1886 struct ifnet *ifp = &sc->arpcom.ac_if;
1887 struct mii_data *mii;
1888 uint16_t eaddr[3];
1889 uint32_t v;
1890 int error;
1891
1892 ASSERT_SERIALIZED(ifp->if_serializer);
1893
1894 mii = device_get_softc(sc->sc_miibus);
1895
1896 /*
1897 * Cancel any pending I/O.
1898 */
1899 stge_stop(sc);
1900
1901 /* Init descriptors. */
1902 error = stge_init_rx_ring(sc);
1903 if (error != 0) {
1904 device_printf(sc->sc_dev,
1905 "initialization failed: no memory for rx buffers\n");
1906 stge_stop(sc);
1907 goto out;
1908 }
1909 stge_init_tx_ring(sc);
1910
1911 /* Set the station address. */
1912 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
1913 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0]));
1914 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1]));
1915 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2]));
1916
1917 /*
1918 * Set the statistics masks. Disable all the RMON stats,
1919 * and disable selected stats in the non-RMON stats registers.
1920 */
1921 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff);
1922 CSR_WRITE_4(sc, STGE_StatisticsMask,
1923 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) |
1924 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) |
1925 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) |
1926 (1U << 21));
1927
1928 /* Set up the receive filter. */
1929 stge_set_filter(sc);
1930 /* Program multicast filter. */
1931 stge_set_multi(sc);
1932
1933 /*
1934 * Give the transmit and receive ring to the chip.
1935 */
1936 CSR_WRITE_4(sc, STGE_TFDListPtrHi,
1937 STGE_ADDR_HI(STGE_TX_RING_ADDR(sc, 0)));
1938 CSR_WRITE_4(sc, STGE_TFDListPtrLo,
1939 STGE_ADDR_LO(STGE_TX_RING_ADDR(sc, 0)));
1940
1941 CSR_WRITE_4(sc, STGE_RFDListPtrHi,
1942 STGE_ADDR_HI(STGE_RX_RING_ADDR(sc, 0)));
1943 CSR_WRITE_4(sc, STGE_RFDListPtrLo,
1944 STGE_ADDR_LO(STGE_RX_RING_ADDR(sc, 0)));
1945
1946 /*
1947 * Initialize the Tx auto-poll period. It's OK to make this number
1948 * large (255 is the max, but we use 127) -- we explicitly kick the
1949 * transmit engine when there's actually a packet.
1950 */
1951 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
1952
1953 /* ..and the Rx auto-poll period. */
1954 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
1955
1956 /* Initialize the Tx start threshold. */
1957 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
1958
1959 /* Rx DMA thresholds, from Linux */
1960 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
1961 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
1962
1963 /* Rx early threhold, from Linux */
1964 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
1965
1966 /* Tx DMA thresholds, from Linux */
1967 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
1968 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04);
1969
1970 /*
1971 * Initialize the Rx DMA interrupt control register. We
1972 * request an interrupt after every incoming packet, but
1973 * defer it for sc_rxint_dmawait us. When the number of
1974 * interrupts pending reaches STGE_RXINT_NFRAME, we stop
1975 * deferring the interrupt, and signal it immediately.
1976 */
1977 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl,
1978 RDIC_RxFrameCount(sc->sc_rxint_nframe) |
1979 RDIC_RxDMAWaitTime(STGE_RXINT_USECS2TICK(sc->sc_rxint_dmawait)));
1980
1981 /*
1982 * Initialize the interrupt mask.
1983 */
1984 sc->sc_IntEnable = IS_HostError | IS_TxComplete |
1985 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd;
1986 #ifdef IFPOLL_ENABLE
1987 /* Disable interrupts if we are polling. */
1988 if (ifp->if_flags & IFF_NPOLLING) {
1989 CSR_WRITE_2(sc, STGE_IntEnable, 0);
1990 sc->sc_npoll.ifpc_stcount = 0;
1991 } else
1992 #endif
1993 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1994
1995 /*
1996 * Configure the DMA engine.
1997 * XXX Should auto-tune TxBurstLimit.
1998 */
1999 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3));
2000
2001 /*
2002 * Send a PAUSE frame when we reach 29,696 bytes in the Rx
2003 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes
2004 * in the Rx FIFO.
2005 */
2006 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);
2007 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16);
2008
2009 /*
2010 * Set the maximum frame size.
2011 */
2012 sc->sc_if_framesize = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2013 CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize);
2014
2015 /*
2016 * Initialize MacCtrl -- do it before setting the media,
2017 * as setting the media will actually program the register.
2018 *
2019 * Note: We have to poke the IFS value before poking
2020 * anything else.
2021 */
2022 /* Tx/Rx MAC should be disabled before programming IFS.*/
2023 CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit));
2024
2025 stge_vlan_setup(sc);
2026
2027 if (sc->sc_rev >= 6) { /* >= B.2 */
2028 /* Multi-frag frame bug work-around. */
2029 CSR_WRITE_2(sc, STGE_DebugCtrl,
2030 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200);
2031
2032 /* Tx Poll Now bug work-around. */
2033 CSR_WRITE_2(sc, STGE_DebugCtrl,
2034 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010);
2035 /* Tx Poll Now bug work-around. */
2036 CSR_WRITE_2(sc, STGE_DebugCtrl,
2037 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020);
2038 }
2039
2040 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2041 v |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable;
2042 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2043 /*
2044 * It seems that transmitting frames without checking the state of
2045 * Rx/Tx MAC wedge the hardware.
2046 */
2047 stge_start_tx(sc);
2048 stge_start_rx(sc);
2049
2050 /*
2051 * Set the current media.
2052 */
2053 mii_mediachg(mii);
2054
2055 /*
2056 * Start the one second MII clock.
2057 */
2058 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
2059
2060 /*
2061 * ...all done!
2062 */
2063 ifp->if_flags |= IFF_RUNNING;
2064 ifq_clr_oactive(&ifp->if_snd);
2065
2066 out:
2067 if (error != 0)
2068 device_printf(sc->sc_dev, "interface not running\n");
2069 }
2070
2071 static void
stge_vlan_setup(struct stge_softc * sc)2072 stge_vlan_setup(struct stge_softc *sc)
2073 {
2074 struct ifnet *ifp = &sc->arpcom.ac_if;
2075 uint32_t v;
2076
2077 /*
2078 * The NIC always copy a VLAN tag regardless of STGE_MACCtrl
2079 * MC_AutoVLANuntagging bit.
2080 * MC_AutoVLANtagging bit selects which VLAN source to use
2081 * between STGE_VLANTag and TFC. However TFC TFD_VLANTagInsert
2082 * bit has priority over MC_AutoVLANtagging bit. So we always
2083 * use TFC instead of STGE_VLANTag register.
2084 */
2085 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2086 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2087 v |= MC_AutoVLANuntagging;
2088 else
2089 v &= ~MC_AutoVLANuntagging;
2090 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2091 }
2092
2093 /*
2094 * Stop transmission on the interface.
2095 */
2096 static void
stge_stop(struct stge_softc * sc)2097 stge_stop(struct stge_softc *sc)
2098 {
2099 struct ifnet *ifp = &sc->arpcom.ac_if;
2100 struct stge_txdesc *txd;
2101 struct stge_rxdesc *rxd;
2102 uint32_t v;
2103 int i;
2104
2105 ASSERT_SERIALIZED(ifp->if_serializer);
2106
2107 /*
2108 * Stop the one second clock.
2109 */
2110 callout_stop(&sc->sc_tick_ch);
2111
2112 /*
2113 * Reset the chip to a known state.
2114 */
2115 stge_reset(sc, STGE_RESET_FULL);
2116
2117 /*
2118 * Disable interrupts.
2119 */
2120 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2121
2122 /*
2123 * Stop receiver, transmitter, and stats update.
2124 */
2125 stge_stop_rx(sc);
2126 stge_stop_tx(sc);
2127 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2128 v |= MC_StatisticsDisable;
2129 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2130
2131 /*
2132 * Stop the transmit and receive DMA.
2133 */
2134 stge_dma_wait(sc);
2135 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0);
2136 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0);
2137 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0);
2138 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0);
2139
2140 /*
2141 * Free RX and TX mbufs still in the queues.
2142 */
2143 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2144 rxd = &sc->sc_cdata.stge_rxdesc[i];
2145 if (rxd->rx_m != NULL) {
2146 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag,
2147 rxd->rx_dmamap);
2148 m_freem(rxd->rx_m);
2149 rxd->rx_m = NULL;
2150 }
2151 }
2152 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2153 txd = &sc->sc_cdata.stge_txdesc[i];
2154 if (txd->tx_m != NULL) {
2155 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag,
2156 txd->tx_dmamap);
2157 m_freem(txd->tx_m);
2158 txd->tx_m = NULL;
2159 }
2160 }
2161
2162 /*
2163 * Mark the interface down and cancel the watchdog timer.
2164 */
2165 ifp->if_flags &= ~IFF_RUNNING;
2166 ifq_clr_oactive(&ifp->if_snd);
2167 ifp->if_timer = 0;
2168 }
2169
2170 static void
stge_start_tx(struct stge_softc * sc)2171 stge_start_tx(struct stge_softc *sc)
2172 {
2173 uint32_t v;
2174 int i;
2175
2176 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2177 if ((v & MC_TxEnabled) != 0)
2178 return;
2179 v |= MC_TxEnable;
2180 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2181 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2182 for (i = STGE_TIMEOUT; i > 0; i--) {
2183 DELAY(10);
2184 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2185 if ((v & MC_TxEnabled) != 0)
2186 break;
2187 }
2188 if (i == 0)
2189 device_printf(sc->sc_dev, "Starting Tx MAC timed out\n");
2190 }
2191
2192 static void
stge_start_rx(struct stge_softc * sc)2193 stge_start_rx(struct stge_softc *sc)
2194 {
2195 uint32_t v;
2196 int i;
2197
2198 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2199 if ((v & MC_RxEnabled) != 0)
2200 return;
2201 v |= MC_RxEnable;
2202 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2203 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2204 for (i = STGE_TIMEOUT; i > 0; i--) {
2205 DELAY(10);
2206 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2207 if ((v & MC_RxEnabled) != 0)
2208 break;
2209 }
2210 if (i == 0)
2211 device_printf(sc->sc_dev, "Starting Rx MAC timed out\n");
2212 }
2213
2214 static void
stge_stop_tx(struct stge_softc * sc)2215 stge_stop_tx(struct stge_softc *sc)
2216 {
2217 uint32_t v;
2218 int i;
2219
2220 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2221 if ((v & MC_TxEnabled) == 0)
2222 return;
2223 v |= MC_TxDisable;
2224 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2225 for (i = STGE_TIMEOUT; i > 0; i--) {
2226 DELAY(10);
2227 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2228 if ((v & MC_TxEnabled) == 0)
2229 break;
2230 }
2231 if (i == 0)
2232 device_printf(sc->sc_dev, "Stopping Tx MAC timed out\n");
2233 }
2234
2235 static void
stge_stop_rx(struct stge_softc * sc)2236 stge_stop_rx(struct stge_softc *sc)
2237 {
2238 uint32_t v;
2239 int i;
2240
2241 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2242 if ((v & MC_RxEnabled) == 0)
2243 return;
2244 v |= MC_RxDisable;
2245 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2246 for (i = STGE_TIMEOUT; i > 0; i--) {
2247 DELAY(10);
2248 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2249 if ((v & MC_RxEnabled) == 0)
2250 break;
2251 }
2252 if (i == 0)
2253 device_printf(sc->sc_dev, "Stopping Rx MAC timed out\n");
2254 }
2255
2256 static void
stge_init_tx_ring(struct stge_softc * sc)2257 stge_init_tx_ring(struct stge_softc *sc)
2258 {
2259 struct stge_ring_data *rd;
2260 struct stge_txdesc *txd;
2261 bus_addr_t addr;
2262 int i;
2263
2264 STAILQ_INIT(&sc->sc_cdata.stge_txfreeq);
2265 STAILQ_INIT(&sc->sc_cdata.stge_txbusyq);
2266
2267 sc->sc_cdata.stge_tx_prod = 0;
2268 sc->sc_cdata.stge_tx_cons = 0;
2269 sc->sc_cdata.stge_tx_cnt = 0;
2270
2271 rd = &sc->sc_rdata;
2272 bzero(rd->stge_tx_ring, STGE_TX_RING_SZ);
2273 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2274 if (i == (STGE_TX_RING_CNT - 1))
2275 addr = STGE_TX_RING_ADDR(sc, 0);
2276 else
2277 addr = STGE_TX_RING_ADDR(sc, i + 1);
2278 rd->stge_tx_ring[i].tfd_next = htole64(addr);
2279 rd->stge_tx_ring[i].tfd_control = htole64(TFD_TFDDone);
2280 txd = &sc->sc_cdata.stge_txdesc[i];
2281 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
2282 }
2283 }
2284
2285 static int
stge_init_rx_ring(struct stge_softc * sc)2286 stge_init_rx_ring(struct stge_softc *sc)
2287 {
2288 struct stge_ring_data *rd;
2289 bus_addr_t addr;
2290 int i;
2291
2292 sc->sc_cdata.stge_rx_cons = 0;
2293 STGE_RXCHAIN_RESET(sc);
2294
2295 rd = &sc->sc_rdata;
2296 bzero(rd->stge_rx_ring, STGE_RX_RING_SZ);
2297 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2298 if (stge_newbuf(sc, i, 1) != 0)
2299 return (ENOBUFS);
2300 if (i == (STGE_RX_RING_CNT - 1))
2301 addr = STGE_RX_RING_ADDR(sc, 0);
2302 else
2303 addr = STGE_RX_RING_ADDR(sc, i + 1);
2304 rd->stge_rx_ring[i].rfd_next = htole64(addr);
2305 rd->stge_rx_ring[i].rfd_status = 0;
2306 }
2307 return (0);
2308 }
2309
2310 /*
2311 * stge_newbuf:
2312 *
2313 * Add a receive buffer to the indicated descriptor.
2314 */
2315 static int
stge_newbuf(struct stge_softc * sc,int idx,int waitok)2316 stge_newbuf(struct stge_softc *sc, int idx, int waitok)
2317 {
2318 struct stge_rxdesc *rxd;
2319 struct stge_rfd *rfd;
2320 struct mbuf *m;
2321 bus_dma_segment_t seg;
2322 bus_dmamap_t map;
2323 int error, nseg;
2324
2325 m = m_getcl(waitok ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR);
2326 if (m == NULL)
2327 return ENOBUFS;
2328 m->m_len = m->m_pkthdr.len = MCLBYTES;
2329
2330 /*
2331 * The hardware requires 4bytes aligned DMA address when JUMBO
2332 * frame is used.
2333 */
2334 if (sc->sc_if_framesize <= (MCLBYTES - ETHER_ALIGN))
2335 m_adj(m, ETHER_ALIGN);
2336
2337 error = bus_dmamap_load_mbuf_segment(sc->sc_cdata.stge_rx_tag,
2338 sc->sc_cdata.stge_rx_sparemap, m,
2339 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2340 if (error) {
2341 m_freem(m);
2342 return error;
2343 }
2344
2345 rxd = &sc->sc_cdata.stge_rxdesc[idx];
2346 if (rxd->rx_m != NULL) {
2347 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2348 BUS_DMASYNC_POSTREAD);
2349 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap);
2350 }
2351
2352 map = rxd->rx_dmamap;
2353 rxd->rx_dmamap = sc->sc_cdata.stge_rx_sparemap;
2354 sc->sc_cdata.stge_rx_sparemap = map;
2355
2356 rxd->rx_m = m;
2357
2358 rfd = &sc->sc_rdata.stge_rx_ring[idx];
2359 rfd->rfd_frag.frag_word0 =
2360 htole64(FRAG_ADDR(seg.ds_addr) | FRAG_LEN(seg.ds_len));
2361 rfd->rfd_status = 0;
2362
2363 return 0;
2364 }
2365
2366 /*
2367 * stge_set_filter:
2368 *
2369 * Set up the receive filter.
2370 */
2371 static void
stge_set_filter(struct stge_softc * sc)2372 stge_set_filter(struct stge_softc *sc)
2373 {
2374 struct ifnet *ifp = &sc->arpcom.ac_if;
2375 uint16_t mode;
2376
2377 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2378 mode |= RM_ReceiveUnicast;
2379 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2380 mode |= RM_ReceiveBroadcast;
2381 else
2382 mode &= ~RM_ReceiveBroadcast;
2383 if ((ifp->if_flags & IFF_PROMISC) != 0)
2384 mode |= RM_ReceiveAllFrames;
2385 else
2386 mode &= ~RM_ReceiveAllFrames;
2387
2388 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2389 }
2390
2391 static void
stge_set_multi(struct stge_softc * sc)2392 stge_set_multi(struct stge_softc *sc)
2393 {
2394 struct ifnet *ifp = &sc->arpcom.ac_if;
2395 struct ifmultiaddr *ifma;
2396 uint32_t crc;
2397 uint32_t mchash[2];
2398 uint16_t mode;
2399 int count;
2400
2401 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2402 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2403 if ((ifp->if_flags & IFF_PROMISC) != 0)
2404 mode |= RM_ReceiveAllFrames;
2405 else if ((ifp->if_flags & IFF_ALLMULTI) != 0)
2406 mode |= RM_ReceiveMulticast;
2407 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2408 return;
2409 }
2410
2411 /* clear existing filters. */
2412 CSR_WRITE_4(sc, STGE_HashTable0, 0);
2413 CSR_WRITE_4(sc, STGE_HashTable1, 0);
2414
2415 /*
2416 * Set up the multicast address filter by passing all multicast
2417 * addresses through a CRC generator, and then using the low-order
2418 * 6 bits as an index into the 64 bit multicast hash table. The
2419 * high order bits select the register, while the rest of the bits
2420 * select the bit within the register.
2421 */
2422
2423 bzero(mchash, sizeof(mchash));
2424
2425 count = 0;
2426 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2427 if (ifma->ifma_addr->sa_family != AF_LINK)
2428 continue;
2429 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2430 ifma->ifma_addr), ETHER_ADDR_LEN);
2431
2432 /* Just want the 6 least significant bits. */
2433 crc &= 0x3f;
2434
2435 /* Set the corresponding bit in the hash table. */
2436 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2437 count++;
2438 }
2439
2440 mode &= ~(RM_ReceiveMulticast | RM_ReceiveAllFrames);
2441 if (count > 0)
2442 mode |= RM_ReceiveMulticastHash;
2443 else
2444 mode &= ~RM_ReceiveMulticastHash;
2445
2446 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]);
2447 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]);
2448 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2449 }
2450
2451 static int
sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS)2452 sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS)
2453 {
2454 return (sysctl_int_range(oidp, arg1, arg2, req,
2455 STGE_RXINT_NFRAME_MIN, STGE_RXINT_NFRAME_MAX));
2456 }
2457
2458 static int
sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS)2459 sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS)
2460 {
2461 return (sysctl_int_range(oidp, arg1, arg2, req,
2462 STGE_RXINT_DMAWAIT_MIN, STGE_RXINT_DMAWAIT_MAX));
2463 }
2464