1 /*
2 * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
3 * SPDX-License-Identifier: MIT
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef _DISPLAYPORT_H_
25 #define _DISPLAYPORT_H_
26 #include "nvcfg_sdk.h"
27
28 #include "nvmisc.h"
29 #include "dpcd.h"
30 #include "dpcd14.h"
31 #include "dpcd20.h"
32
33 /**************** Resource Manager Defines and Structures ******************\
34 * *
35 * Module: DISPLAYPORT.H *
36 * Defines DISPLAYPORT V1.2 *
37 * *
38 \***************************************************************************/
39
40 //
41 // 4 Legacy Link Rates: RBR, HBR, HBR2, HBR3
42 // 4 ILRs: 2.16G, 2.43G, 3.24G, 4.32G
43 //
44 #define NV_SUPPORTED_DP1X_LINK_RATES__SIZE 8
45
46 // Displayport interoperability with HDMI dongle i2c addr
47 #define DP2HDMI_DONGLE_I2C_ADDR 0x80
48 #define DP2HDMI_DONGLE_DDC_BUFFER_ID_LEN 16
49 #define DP2HDMI_DONGLE_CAP_BUFFER_LEN 32
50
51 // Offset to read the dongle identifier
52 #define NV_DP2HDMI_DONGLE_IDENTIFIER (0x00000010)
53 #define NV_DP2HDMI_DONGLE_IDENTIFIER_ADAPTER_REV 2:0
54 #define NV_DP2HDMI_DONGLE_IDENTIFIER_ADAPTER_REV_TYPE2 (0x00000000)
55 #define NV_DP2HDMI_DONGLE_IDENTIFIER_ADAPTER_ID 7:4
56 #define NV_DP2HDMI_DONGLE_IDENTIFIER_ADAPTER_ID_TYPE2 (0x0000000A)
57
58 // Offset to read the dongle TMDS clock rate
59 #define NV_DP2HDMI_DONGLE_TMDS_CLOCK_RATE (0x0000001D)
60
61 // HDMI dongle types
62 #define DP2HDMI_DONGLE_TYPE_1 0x1
63 #define DP2HDMI_DONGLE_TYPE_2 0x2
64
65 // HDMI dongle frequency limits
66 #define DP2HDMI_DONGLE_TYPE_1_PCLK_LIMIT 165*1000*1000
67 #define DP2HDMI_DONGLE_TYPE_2_PCLK_LIMIT 300*1000*1000
68
69 #define DPCD_VERSION_12 0x12
70 #define DPCD_VERSION_13 0x13
71 #define DPCD_VERSION_14 0x14
72
73 #define DP_LINKINDEX_0 0x0
74 #define DP_LINKINDEX_1 0x1
75
76 // Two Head One OR
77 #define NV_PRIMARY_HEAD_INDEX_0 0
78 #define NV_SECONDARY_HEAD_INDEX_1 1
79 #define NV_PRIMARY_HEAD_INDEX_2 2
80 #define NV_SECONDARY_HEAD_INDEX_3 3
81
82 typedef enum
83 {
84 displayPort_Lane0 = 0,
85 displayPort_Lane1 = 1,
86 displayPort_Lane2 = 2,
87 displayPort_Lane3 = 3,
88 displayPort_Lane4 = 4,
89 displayPort_Lane5 = 5,
90 displayPort_Lane6 = 6,
91 displayPort_Lane7 = 7,
92 displayPort_LaneSupported
93 } DP_LANE;
94
95 typedef enum
96 {
97 laneCount_0 = 0x0,
98 laneCount_1 = 0x1,
99 laneCount_2 = 0x2,
100 laneCount_4 = 0x4,
101 laneCount_8 = 0x8,
102 laneCount_Supported
103 } DP_LANE_COUNT;
104
105 typedef enum
106 {
107 // enum value unit = 270M
108 linkBW_1_62Gbps = 0x06,
109 linkBW_2_16Gbps = 0x08,
110 linkBW_2_43Gbps = 0x09,
111 linkBW_2_70Gbps = 0x0A,
112 linkBW_3_24Gbps = 0x0C,
113 linkBW_4_32Gbps = 0x10,
114 linkBW_5_40Gbps = 0x14,
115 linkBW_8_10Gbps = 0x1E,
116 linkBW_Supported
117 } DP_LINK_BANDWIDTH;
118
119 typedef enum
120 {
121 linkSpeedId_1_62Gbps = 0x00,
122 linkSpeedId_2_70Gbps = 0x01,
123 linkSpeedId_5_40Gbps = 0x02,
124 linkSpeedId_8_10Gbps = 0x03,
125 linkSpeedId_2_16Gbps = 0x04,
126 linkSpeedId_2_43Gbps = 0x05,
127 linkSpeedId_3_24Gbps = 0x06,
128 linkSpeedId_4_32Gbps = 0x07,
129 linkSpeedId_Supported
130 } DP_LINK_SPEED_INDEX;
131
132 typedef enum
133 {
134 postCursor2_Level0 = 0,
135 postCursor2_Level1 = 1,
136 postCursor2_Level2 = 2,
137 postCursor2_Level3 = 3,
138 postCursor2_Supported
139 } DP_POSTCURSOR2;
140
141 typedef enum
142 {
143 preEmphasis_Disabled = 0,
144 preEmphasis_Level1 = 1,
145 preEmphasis_Level2 = 2,
146 preEmphasis_Level3 = 3,
147 preEmphasis_Supported
148 } DP_PREEMPHASIS;
149
150 typedef enum
151 {
152 driveCurrent_Level0 = 0,
153 driveCurrent_Level1 = 1,
154 driveCurrent_Level2 = 2,
155 driveCurrent_Level3 = 3,
156 driveCurrent_Supported
157 } DP_DRIVECURRENT;
158
159 typedef enum
160 {
161 trainingPattern_Disabled = 0x0,
162 trainingPattern_1 = 0x1,
163 trainingPattern_2 = 0x2,
164 trainingPattern_3 = 0x3,
165 trainingPattern_4 = 0xB,
166 } DP_TRAININGPATTERN;
167
168 typedef enum
169 {
170 dpOverclock_Percentage_0 = 0,
171 dpOverclock_Percentage_10 = 10,
172 dpOverclock_Percentage_20 = 20
173 }DP_OVERCLOCKPERCENTAGE;
174
175 typedef enum
176 {
177 dpColorFormat_RGB = 0,
178 dpColorFormat_YCbCr444 = 0x1,
179 dpColorFormat_YCbCr422 = 0x2,
180 dpColorFormat_YCbCr420 = 0x3,
181 dpColorFormat_Unknown = 0xF
182 } DP_COLORFORMAT;
183
184 typedef enum
185 {
186 dp_pktType_VideoStreamconfig = 0x7,
187 dp_pktType_CeaHdrMetaData = 0x21,
188 dp_pktType_SRInfoFrame = 0x7f, // Self refresh infoframe for eDP enter/exit self refresh, SRS 1698
189 dp_pktType_Cea861BInfoFrame = 0x80,
190 dp_pktType_VendorSpecInfoFrame = 0x81,
191 dp_pktType_AviInfoFrame = 0x82,
192 dp_pktType_AudioInfoFrame = 0x84,
193 dp_pktType_SrcProdDescInfoFrame = 0x83,
194 dp_pktType_MpegSrcInfoFrame = 0x85,
195 dp_pktType_DynamicRangeMasteringInfoFrame = 0x87
196 } DP_PACKET_TYPE;
197
198 typedef enum
199 {
200 DSC_SLICES_PER_SINK_1 = 1,
201 DSC_SLICES_PER_SINK_2 = 2,
202 DSC_SLICES_PER_SINK_4 = 4,
203 DSC_SLICES_PER_SINK_6 = 6,
204 DSC_SLICES_PER_SINK_8 = 8,
205 DSC_SLICES_PER_SINK_10 = 10,
206 DSC_SLICES_PER_SINK_12 = 12,
207 DSC_SLICES_PER_SINK_16 = 16,
208 DSC_SLICES_PER_SINK_20 = 20,
209 DSC_SLICES_PER_SINK_24 = 24
210 } DscSliceCount;
211
212 typedef enum
213 {
214 DSC_BITS_PER_COLOR_MASK_8 = 1,
215 DSC_BITS_PER_COLOR_MASK_10 = 2,
216 DSC_BITS_PER_COLOR_MASK_12 = 4
217 }DscBitsPerColorMask;
218
219 enum DSC_MODE
220 {
221 DSC_SINGLE,
222 DSC_DUAL,
223 DSC_DROP,
224 DSC_MODE_NONE
225 };
226
227 typedef enum
228 {
229 BITS_PER_PIXEL_PRECISION_1_16 = 0,
230 BITS_PER_PIXEL_PRECISION_1_8 = 1,
231 BITS_PER_PIXEL_PRECISION_1_4 = 2,
232 BITS_PER_PIXEL_PRECISION_1_2 = 3,
233 BITS_PER_PIXEL_PRECISION_1 = 4
234 }BITS_PER_PIXEL_INCREMENT;
235
236 typedef enum
237 {
238 NV_DP_FEC_UNCORRECTED = 0,
239 NV_DP_FEC_CORRECTED = 1,
240 NV_DP_FEC_BIT = 2,
241 NV_DP_FEC_PARITY_BLOCK = 3,
242 NV_DP_FEC_PARITY_BIT = 4
243 }FEC_ERROR_COUNTER;
244
245 typedef struct DscCaps
246 {
247 NvBool bDSCSupported;
248 NvBool bDSCDecompressionSupported;
249 NvBool bDynamicPPSSupported;
250 NvBool bDynamicDscToggleSupported;
251 NvBool bDSCPassThroughSupported;
252 unsigned versionMajor, versionMinor;
253 unsigned rcBufferBlockSize;
254 unsigned rcBuffersize;
255 unsigned maxSlicesPerSink;
256 unsigned lineBufferBitDepth;
257 NvBool bDscBlockPredictionSupport;
258 unsigned maxBitsPerPixelX16;
259 unsigned sliceCountSupportedMask;
260
261 struct
262 {
263 NvBool bRgb;
264 NvBool bYCbCr444;
265 NvBool bYCbCrSimple422;
266 NvBool bYCbCrNative422;
267 NvBool bYCbCrNative420;
268 }dscDecoderColorFormatCaps;
269
270 unsigned dscDecoderColorDepthMask;
271 unsigned dscPeakThroughputMode0;
272 unsigned dscPeakThroughputMode1;
273 unsigned dscMaxSliceWidth;
274
275 unsigned branchDSCOverallThroughputMode0;
276 unsigned branchDSCOverallThroughputMode1;
277 unsigned branchDSCMaximumLineBufferWidth;
278
279 BITS_PER_PIXEL_INCREMENT dscBitsPerPixelIncrement;
280 } DscCaps;
281
282 typedef struct GpuDscCrc
283 {
284 NvU16 gpuCrc0;
285 NvU16 gpuCrc1;
286 NvU16 gpuCrc2;
287 } gpuDscCrc;
288
289 typedef struct SinkDscCrc
290 {
291 NvU16 sinkCrc0;
292 NvU16 sinkCrc1;
293 NvU16 sinkCrc2;
294 } sinkDscCrc;
295
296 typedef struct
297 {
298 NvBool bSourceControlModeSupported;
299 NvBool bConcurrentLTSupported;
300 NvBool bConv444To420Supported;
301 NvU32 maxTmdsClkRate;
302 NvU8 maxBpc;
303 NvU8 maxHdmiLinkBandwidthGbps;
304 } PCONCaps;
305
306 typedef enum
307 {
308 PCON_HDMI_LINK_BW_FRL_9GBPS = 0,
309 PCON_HDMI_LINK_BW_FRL_18GBPS,
310 PCON_HDMI_LINK_BW_FRL_24GBPS,
311 PCON_HDMI_LINK_BW_FRL_32GBPS,
312 PCON_HDMI_LINK_BW_FRL_40GBPS,
313 PCON_HDMI_LINK_BW_FRL_48GBPS,
314 PCON_HDMI_LINK_BW_FRL_INVALID
315 } PCONHdmiLinkBw;
316
317 typedef enum
318 {
319 NV_DP_PCON_CONTROL_STATUS_SUCCESS = 0,
320 NV_DP_PCON_CONTROL_STATUS_ERROR_TIMEOUT = 0x80000001,
321 NV_DP_PCON_CONTROL_STATUS_ERROR_FRL_LT_FAILURE = 0x80000002,
322 NV_DP_PCON_CONTROL_STATUS_ERROR_FRL_NOT_SUPPORTED = 0x80000003,
323 NV_DP_PCON_CONTROL_STATUS_ERROR_GENERIC = 0x8000000F
324 } NV_DP_PCON_CONTROL_STATUS;
325 //
326 // Poll HDMI-Link Status change and FRL Ready.
327 // Spec says it should be done in 500ms, we give it 20% extra time:
328 // 60 times with interval 10ms.
329 //
330 #define NV_PCON_SOURCE_CONTROL_MODE_TIMEOUT_THRESHOLD (60)
331 #define NV_PCON_SOURCE_CONTROL_MODE_TIMEOUT_INTERVAL_MS (10)
332 //
333 // Poll HDMI-Link Status change IRQ and Link Status.
334 // Spec says it should be done in 250ms, we give it 20% extra time:
335 // 30 times with interval 10ms.
336 //
337 #define NV_PCON_FRL_LT_TIMEOUT_THRESHOLD (30)
338 #define NV_PCON_FRL_LT_TIMEOUT_INTERVAL_MS (10)
339
340 typedef struct _PCONLinkControl
341 {
342 struct
343 {
344 // This struct is being passed in for assessPCONLink I/F
345 NvU32 bAssessLink : 1;
346
347 // Specify if client wants to use src control - set it false DPLib can just do DP LT alone.
348 // By default it should be true.
349 NvU32 bSourceControlMode : 1;
350
351 // Default is sequential mode, set this to choose concurrent mode
352 NvU32 bConcurrentMode : 1;
353
354 // Default is normal link training mode (stop once FRL-LT succeed).
355 // Set this to link train all requested FRL Bw in allowedFrlBwMask.
356 NvU32 bExtendedLTMode : 1;
357
358 // Keep PCON links (DP and FRL link) alive
359 NvU32 bKeepPCONLinkAlive : 1;
360
361 // Default DPLib will fallback to autonomous mode and perform DP assessLink.
362 NvU32 bSkipFallback : 1;
363 } flags;
364
365 // Input: Clients use this to specify the FRL BW PCON should try.
366 NvU32 frlHdmiBwMask;
367
368 struct
369 {
370 NV_DP_PCON_CONTROL_STATUS status;
371 PCONHdmiLinkBw maxFrlBwTrained;
372 NvU32 trainedFrlBwMask;
373 } result;
374 } PCONLinkControl;
375
getMaxFrlBwFromMask(NvU32 frlRateMask)376 static NV_INLINE PCONHdmiLinkBw getMaxFrlBwFromMask(NvU32 frlRateMask)
377 {
378 if (frlRateMask == 0)
379 {
380 // Nothing is set. Assume TMDS
381 return PCON_HDMI_LINK_BW_FRL_INVALID;
382 }
383
384 // find highest set bit (destructive operation)
385 HIGHESTBITIDX_32(frlRateMask);
386
387 return (PCONHdmiLinkBw)frlRateMask;
388 }
389
390 /*
391 EDP VESA PSR defines
392 */
393
394 // PSR state transitions
395 typedef enum
396 {
397 vesaPsrStatus_Inactive = 0,
398 vesaPsrStatus_Transition2Active = 1,
399 vesaPsrStatus_DisplayFromRfb = 2,
400 vesaPsrStatus_CaptureAndDisplay = 3,
401 vesaPsrStatus_Transition2Inactive = 4,
402 vesaPsrStatus_Undefined5 = 5,
403 vesaPsrStatus_Undefined6 = 6,
404 vesaPsrStatus_SinkError = 7
405 } vesaPsrState;
406
407 typedef struct VesaPsrConfig
408 {
409 NvU8 psrCfgEnable : 1;
410 NvU8 srcTxEnabledInPsrActive : 1;
411 NvU8 crcVerifEnabledInPsrActive : 1;
412 NvU8 frameCaptureSecondActiveFrame : 1;
413 NvU8 selectiveUpdateOnSecondActiveline : 1;
414 NvU8 enableHpdIrqOnCrcMismatch : 1;
415 NvU8 enablePsr2 : 1;
416 NvU8 reserved : 1;
417 } vesaPsrConfig;
418
419 typedef struct VesaPsrDebugStatus
420 {
421 NvBool lastSdpPsrState;
422 NvBool lastSdpUpdateRfb;
423 NvBool lastSdpCrcValid;
424 NvBool lastSdpSuValid;
425 NvBool lastSdpFirstSURcvd;
426 NvBool lastSdpLastSURcvd;
427 NvBool lastSdpYCoordValid;
428 NvU8 maxResyncFrames;
429 NvU8 actualResyncFrames;
430 } vesaPsrDebugStatus;
431
432 typedef struct VesaPsrErrorStatus
433 {
434 NvU8 linkCrcError : 1;
435 NvU8 rfbStoreError : 1;
436 NvU8 vscSdpError : 1;
437 NvU8 rsvd : 5;
438 } vesaPsrErrorStatus;
439
440 typedef struct VesaPsrEventIndicator
441 {
442 NvU8 sinkCapChange : 1;
443 NvU8 rsvd : 7;
444 } vesaPsrEventIndicator;
445
446 #pragma pack(1)
447 typedef struct VesaPsrSinkCaps
448 {
449 NvU8 psrVersion;
450 NvU8 linkTrainingRequired : 1;
451 NvU8 psrSetupTime : 3;
452 NvU8 yCoordinateRequired : 1;
453 NvU8 psr2UpdateGranularityRequired : 1;
454 NvU8 reserved : 2;
455 NvU16 suXGranularity;
456 NvU8 suYGranularity;
457 } vesaPsrSinkCaps;
458 #pragma pack()
459
460 typedef struct PanelReplayCaps
461 {
462 NvBool panelReplaySupported;
463 } panelReplayCaps;
464
465 typedef struct PanelReplayConfig
466 {
467 NvBool enablePanelReplay;
468 } panelReplayConfig;
469
470 // PR state
471 typedef enum
472 {
473 PanelReplay_Inactive = 0,
474 PanelReplay_CaptureAndDisplay = 1,
475 PanelReplay_DisplayFromRfb = 2,
476 PanelReplay_Undefined = 7
477 } PanelReplayState;
478
479 // PR Sink debug info
480 typedef struct PanelReplaySinkDebugInfo
481 {
482 NvU8 activeFrameCrcError : 1;
483 NvU8 rfbStorageError : 1;
484 NvU8 vscSdpUncorrectableError: 1;
485 NvU8 adaptiveSyncSdpMissing : 1;
486 NvU8 sinkPrStatus : 3;
487 NvU8 sinkFramelocked : 2;
488 NvU8 sinkFrameLockedValid : 1;
489 NvU8 currentPrState : 1;
490 NvU8 crcValid: 1;
491 NvU8 suCoordinatesValid: 1;
492 } panelReplaySinkDebugInfo;
493
494 typedef struct
495 {
496 PanelReplayState prState;
497 } PanelReplayStatus;
498
499 // Multiplier constant to get link frequency in KHZ
500 // Maximum link rate of Main Link lanes = Value x 270M.
501 // To get it to KHz unit, we need to multiply 270K.
502 #define DP_LINK_BW_FREQUENCY_MULTIPLIER_KHZ (270*1000)
503
504 // Multiplier constant to get link rate table's in KHZ
505 #define DP_LINK_RATE_TABLE_MULTIPLIER_KHZ 200
506
507 //
508 // Multiplier constant to get link frequency (multiplier of 270MHz) in MBps
509 // a * 270 * 1000 * 1000(270Mhz) * (8 / 10)(8b/10b) / 8(Byte)
510 // = a * 27000000
511 //
512 #define DP_LINK_BW_FREQ_MULTI_MBPS 27000000
513
514 //
515 // Get link rate in multiplier of 270MHz from KHz:
516 // a * 1000(KHz) / 270 * 1000 * 1000(270Mhz)
517 //
518 #define LINK_RATE_KHZ_TO_MULTP(a) ((a) / 270000)
519
520 //
521 // Get link rate in MBps from KHz:
522 // a * 1000 * (8 / 10)(8b/10b) / 8(Byte)
523 // = a * 100
524 //
525 #define LINK_RATE_KHZ_TO_MBPS(a) ((a) * 100)
526
527 #define DP_MAX_LANES 8 // This defines the maximum number of lanes supported on a chip.
528 #define DP_MAX_LANES_PER_LINK 4 // This defines the maximum number of lanes per link in a chip.
529 #define DP_AUX_CHANNEL_MAX_BYTES 16
530 #define DP_CLOCK_RECOVERY_TOT_TRIES 10
531 #define DP_CLOCK_RECOVERY_MAX_TRIES 5
532 #define DP_CH_EQ_MAX_RETRIES 5
533 #define DP_LT_MAX_FOR_MST_MAX_RETRIES 3
534 #define DP_READ_EDID_MAX_RETRIES 7
535 #define DP_AUX_CHANNEL_DEFAULT_DEFER_MAX_TRIES 7
536 #define DP_AUX_CHANNEL_TIMEOUT_MAX_TRIES 2
537 #define DP_SET_POWER_D0_NORMAL_MAX_TRIES 3
538 #define DP_SW_AUTO_READ_REQ_SIZE 6
539 #define NV_DP_RBR_FALLBACK_MAX_TRIES 3
540
541 #define DP_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_DEFAULT_MS 1
542
543 #define DP_AUX_CHANNEL_TIMEOUT_WAITIDLE 400 // source is required to wait at least 400us before it considers the AUX transaction to have timed out.
544 #define DP_AUX_CHANNEL_TIMEOUT_VALUE_DEFAULT 400
545 #define DP_AUX_CHANNEL_TIMEOUT_VALUE_MAX 3200
546
547 #define DP_PHY_REPEATER_INDEX_FOR_SINK 0xFFFFFFFF
548
549 #define DP_MESSAGEBOX_SIZE 48
550 #define DP_POST_LT_ADJ_REQ_LIMIT 6
551 #define DP_POST_LT_ADJ_REQ_TIMER 200000
552
553 #define DP_AUX_HYBRID_TIMEOUT 600
554 #define DP_AUX_SEMA_ACQUIRE_TIMEOUT 20000
555
556 #define DP_CONFIG_WATERMARK_ADJUST 2
557 #define DP_CONFIG_WATERMARK_LIMIT 20
558 #define DP_CONFIG_INCREASED_WATERMARK_ADJUST 8
559 #define DP_CONFIG_INCREASED_WATERMARK_LIMIT 22
560
561 #define NV_DP_MSA_PROPERTIES_MISC1_STEREO 2:1
562
563 #define DP_LANE_STATUS_ARRAY_SIZE ((displayPort_LaneSupported + 1) / 2)
564 #define DP_LANE_STATUS_ARRAY_INDEX(lane) ((lane) < displayPort_LaneSupported ? ((lane) / 2) : 0)
565
566 #define IS_VALID_LANECOUNT(val) (((NvU32)(val)==0) || ((NvU32)(val)==1) || \
567 ((NvU32)(val)==2) || ((NvU32)(val)==4) || \
568 ((NvU32)(val)==8))
569
570 #define IS_STANDARD_LINKBW(val) (((NvU32)(val)==linkBW_1_62Gbps) || \
571 ((NvU32)(val)==linkBW_2_70Gbps) || \
572 ((NvU32)(val)==linkBW_5_40Gbps) || \
573 ((NvU32)(val)==linkBW_8_10Gbps))
574
575 #define IS_INTERMEDIATE_LINKBW(val) (((NvU32)(val)==linkBW_2_16Gbps) || \
576 ((NvU32)(val)==linkBW_2_43Gbps) || \
577 ((NvU32)(val)==linkBW_3_24Gbps) || \
578 ((NvU32)(val)==linkBW_4_32Gbps))
579
580 #define IS_VALID_LINKBW(val) (IS_STANDARD_LINKBW(val) || \
581 IS_INTERMEDIATE_LINKBW(val))
582
583 //
584 // Phy Repeater count read from DPCD offset F0002h is an
585 // 8 bit value where each bit represents the total count
586 // 80h = 1 repeater, 40h = 2 , 20h = 3 ... 01h = 8
587 // This function maps it to decimal system
588 //
mapPhyRepeaterVal(NvU32 value)589 static NV_INLINE NvU32 mapPhyRepeaterVal(NvU32 value)
590 {
591 switch (value)
592 {
593 case NV_DPCD14_PHY_REPEATER_CNT_VAL_0:
594 return 0;
595 case NV_DPCD14_PHY_REPEATER_CNT_VAL_1:
596 return 1;
597 case NV_DPCD14_PHY_REPEATER_CNT_VAL_2:
598 return 2;
599 case NV_DPCD14_PHY_REPEATER_CNT_VAL_3:
600 return 3;
601 case NV_DPCD14_PHY_REPEATER_CNT_VAL_4:
602 return 4;
603 case NV_DPCD14_PHY_REPEATER_CNT_VAL_5:
604 return 5;
605 case NV_DPCD14_PHY_REPEATER_CNT_VAL_6:
606 return 6;
607 case NV_DPCD14_PHY_REPEATER_CNT_VAL_7:
608 return 7;
609 case NV_DPCD14_PHY_REPEATER_CNT_VAL_8:
610 return 8;
611 default:
612 return 0;
613 }
614 }
615
616 // HDCP specific definitions
617
618 #define HDCP22_RTX_SIMPLE_PATTERN 0x12345678
619 #define HDCP22_TX_CAPS_PATTERN_BIG_ENDIAN {0x02, 0x00, 0x00}
620
621 #define DP_MST_HEAD_TO_STREAMID(head, pipeId, numHeads) ((head) + 1 + (pipeId) * (numHeads))
622 #define DP_MST_STREAMID_TO_HEAD(streamid, pipeId, numHeads) ((streamid) - 1 - ((pipeId) * (numHeads)))
623 #define DP_MST_STREAMID_TO_PIPE(streamid, head, numHeads) (((streamid) - (head) - 1) / (numHeads))
624
625 typedef enum
626 {
627 NV_DP_SBMSG_REQUEST_ID_GET_MESSAGE_TRANSACTION_VERSION = 0x00,
628 NV_DP_SBMSG_REQUEST_ID_LINK_ADDRESS = 0x01,
629 NV_DP_SBMSG_REQUEST_ID_CONNECTION_STATUS_NOTIFY = 0x02,
630
631 NV_DP_SBMSG_REQUEST_ID_ENUM_PATH_RESOURCES = 0x10,
632 NV_DP_SBMSG_REQUEST_ID_ALLOCATE_PAYLOAD = 0x11,
633 NV_DP_SBMSG_REQUEST_ID_QUERY_PAYLOAD = 0x12,
634 NV_DP_SBMSG_REQUEST_ID_RESOURCE_STATUS_NOTIFY = 0x13,
635 NV_DP_SBMSG_REQUEST_ID_CLEAR_PAYLOAD_ID_TABLE = 0x14,
636
637 NV_DP_SBMSG_REQUEST_ID_REMOTE_DPCD_READ = 0x20,
638 NV_DP_SBMSG_REQUEST_ID_REMOTE_DPCD_WRITE = 0x21,
639 NV_DP_SBMSG_REQUEST_ID_REMOTE_I2C_READ = 0x22,
640 NV_DP_SBMSG_REQUEST_ID_REMOTE_I2C_WRITE = 0x23,
641 NV_DP_SBMSG_REQUEST_ID_POWER_UP_PHY = 0x24,
642 NV_DP_SBMSG_REQUEST_ID_POWER_DOWN_PHY = 0x25,
643
644 NV_DP_SBMSG_REQUEST_ID_SINK_EVENT_NOTIFY = 0x30,
645 NV_DP_SBMSG_REQUEST_ID_QUERY_STREAM_ENCRYPTION_STATUS = 0x38,
646
647 NV_DP_SBMSG_REQUEST_ID_UNDEFINED = 0xFF,
648 } NV_DP_SBMSG_REQUEST_ID;
649
650 // FEC
651
652 #define NV_DP_FEC_FLAGS_SELECT_ALL 0x7
653 #define NV_DP_ERROR_COUNTERS_PER_LANE 5
654 #define NV_DP_MAX_NUM_OF_LANES 4
655 #define NV_DP_FEC_ERROR_COUNT_INVALID 0xbadf
656 #define NV_DP_UNCORRECTED_ERROR NV_DP_FEC_UNCORRECTED : NV_DP_FEC_UNCORRECTED
657 #define NV_DP_CORRECTED_ERROR NV_DP_FEC_CORRECTED : NV_DP_FEC_CORRECTED
658 #define NV_DP_BIT_ERROR NV_DP_FEC_BIT : NV_DP_FEC_BIT
659 #define NV_DP_PARITY_BLOCK_ERROR NV_DP_FEC_PARITY_BLOCK : NV_DP_FEC_PARITY_BLOCK
660 #define NV_DP_PARITY_BIT_ERROR NV_DP_FEC_PARITY_BIT : NV_DP_FEC_PARITY_BIT
661 #define NV_DP_UNCORRECTED_ERROR_NO 0
662 #define NV_DP_UNCORRECTED_ERROR_YES 1
663 #define NV_DP_CORRECTED_ERROR_NO 0
664 #define NV_DP_CORRECTED_ERROR_YES 1
665 #define NV_DP_BIT_ERROR_NO 0
666 #define NV_DP_BIT_ERROR_YES 1
667 #define NV_DP_PARITY_BLOCK_ERROR_NO 0
668 #define NV_DP_PARITY_BLOCK_ERROR_YES 1
669 #define NV_DP_PARITY_BIT_ERROR_NO 0
670 #define NV_DP_PARITY_BIT_ERROR_YES 1
671
672
673 #endif // #ifndef _DISPLAYPORT_H_
674