1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <stdlib.h>
25 #include <unistd.h>
26 #include <sys/types.h>
27 #include <sys/stat.h>
28 #include <fcntl.h>
29 #if HAVE_ALLOCA_H
30 # include <alloca.h>
31 #endif
32
33 #include "CUnit/Basic.h"
34
35 #include "amdgpu_test.h"
36 #include "amdgpu_drm.h"
37 #include "amdgpu_internal.h"
38 #include "xf86drm.h"
39 #include <pthread.h>
40
41 #define GFX_COMPUTE_NOP 0xffff1000
42
43 static amdgpu_device_handle device_handle;
44 static uint32_t major_version;
45 static uint32_t minor_version;
46 static char *sysfs_remove = NULL;
47 static bool do_cs;
48
suite_hotunplug_tests_enable(void)49 CU_BOOL suite_hotunplug_tests_enable(void)
50 {
51 CU_BOOL enable = CU_TRUE;
52 drmDevicePtr device;
53
54 if (drmGetDevice2(drm_amdgpu[0], DRM_DEVICE_GET_PCI_REVISION, &device)) {
55 printf("\n\nGPU Failed to get DRM device PCI info!\n");
56 return CU_FALSE;
57 }
58
59 if (device->bustype != DRM_BUS_PCI) {
60 printf("\n\nGPU device is not on PCI bus!\n");
61 amdgpu_device_deinitialize(device_handle);
62 return CU_FALSE;
63 }
64
65 /* Disable until the hot-unplug support in kernel gets into drm-next */
66 if (major_version < 0xff)
67 enable = false;
68
69 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
70 &minor_version, &device_handle))
71 return CU_FALSE;
72
73 /* TODO Once DRM version for unplug feature ready compare here agains it*/
74
75 if (amdgpu_device_deinitialize(device_handle))
76 return CU_FALSE;
77
78 return enable;
79 }
80
suite_hotunplug_tests_init(void)81 int suite_hotunplug_tests_init(void)
82 {
83 /* We need to open/close device at each test manually */
84 amdgpu_close_devices();
85
86 return CUE_SUCCESS;
87 }
88
suite_hotunplug_tests_clean(void)89 int suite_hotunplug_tests_clean(void)
90 {
91
92
93 return CUE_SUCCESS;
94 }
95
amdgpu_hotunplug_trigger(const char * pathname)96 static int amdgpu_hotunplug_trigger(const char *pathname)
97 {
98 int fd, len;
99
100 fd = open(pathname, O_WRONLY);
101 if (fd < 0)
102 return -errno;
103
104 len = write(fd, "1", 1);
105 close(fd);
106
107 return len;
108 }
109
amdgpu_hotunplug_setup_test()110 static int amdgpu_hotunplug_setup_test()
111 {
112 int r;
113 char *tmp_str;
114
115 if (amdgpu_open_device_on_test_index(open_render_node) < 0) {
116 printf("\n\n Failed to reopen device file!\n");
117 return CUE_SINIT_FAILED;
118
119
120
121 }
122
123 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
124 &minor_version, &device_handle);
125
126 if (r) {
127 if ((r == -EACCES) && (errno == EACCES))
128 printf("\n\nError:%s. "
129 "Hint:Try to run this test program as root.",
130 strerror(errno));
131 return CUE_SINIT_FAILED;
132 }
133
134 tmp_str = amdgpu_get_device_from_fd(drm_amdgpu[0]);
135 if (!tmp_str){
136 printf("\n\n Device path not found!\n");
137 return CUE_SINIT_FAILED;
138 }
139
140 sysfs_remove = realloc(tmp_str, strlen(tmp_str) * 2);
141 strcat(sysfs_remove, "/remove");
142
143 return 0;
144 }
145
amdgpu_hotunplug_teardown_test()146 static int amdgpu_hotunplug_teardown_test()
147 {
148 if (amdgpu_device_deinitialize(device_handle))
149 return CUE_SCLEAN_FAILED;
150
151 amdgpu_close_devices();
152
153 if (sysfs_remove)
154 free(sysfs_remove);
155
156 return 0;
157 }
158
amdgpu_hotunplug_remove()159 static inline int amdgpu_hotunplug_remove()
160 {
161 return amdgpu_hotunplug_trigger(sysfs_remove);
162 }
163
amdgpu_hotunplug_rescan()164 static inline int amdgpu_hotunplug_rescan()
165 {
166 return amdgpu_hotunplug_trigger("/sys/bus/pci/rescan");
167 }
168
amdgpu_cs_sync(amdgpu_context_handle context,unsigned int ip_type,int ring,unsigned int seqno)169 static int amdgpu_cs_sync(amdgpu_context_handle context,
170 unsigned int ip_type,
171 int ring,
172 unsigned int seqno)
173 {
174 struct amdgpu_cs_fence fence = {
175 .context = context,
176 .ip_type = ip_type,
177 .ring = ring,
178 .fence = seqno,
179 };
180 uint32_t expired;
181
182 return amdgpu_cs_query_fence_status(&fence,
183 AMDGPU_TIMEOUT_INFINITE,
184 0, &expired);
185 }
186
amdgpu_nop_cs()187 static void *amdgpu_nop_cs()
188 {
189 amdgpu_bo_handle ib_result_handle;
190 void *ib_result_cpu;
191 uint64_t ib_result_mc_address;
192 uint32_t *ptr;
193 int i, r;
194 amdgpu_bo_list_handle bo_list;
195 amdgpu_va_handle va_handle;
196 amdgpu_context_handle context;
197 struct amdgpu_cs_request ibs_request;
198 struct amdgpu_cs_ib_info ib_info;
199
200 r = amdgpu_cs_ctx_create(device_handle, &context);
201 CU_ASSERT_EQUAL(r, 0);
202
203 r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
204 AMDGPU_GEM_DOMAIN_GTT, 0,
205 &ib_result_handle, &ib_result_cpu,
206 &ib_result_mc_address, &va_handle);
207 CU_ASSERT_EQUAL(r, 0);
208
209 ptr = ib_result_cpu;
210 for (i = 0; i < 16; ++i)
211 ptr[i] = GFX_COMPUTE_NOP;
212
213 r = amdgpu_bo_list_create(device_handle, 1, &ib_result_handle, NULL, &bo_list);
214 CU_ASSERT_EQUAL(r, 0);
215
216 memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
217 ib_info.ib_mc_address = ib_result_mc_address;
218 ib_info.size = 16;
219
220 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
221 ibs_request.ip_type = AMDGPU_HW_IP_GFX;
222 ibs_request.ring = 0;
223 ibs_request.number_of_ibs = 1;
224 ibs_request.ibs = &ib_info;
225 ibs_request.resources = bo_list;
226
227 while (do_cs)
228 amdgpu_cs_submit(context, 0, &ibs_request, 1);
229
230 amdgpu_cs_sync(context, AMDGPU_HW_IP_GFX, 0, ibs_request.seq_no);
231 amdgpu_bo_list_destroy(bo_list);
232 amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
233 ib_result_mc_address, 4096);
234
235 amdgpu_cs_ctx_free(context);
236
237 return (void *)0;
238 }
239
amdgpu_create_cs_thread()240 static pthread_t* amdgpu_create_cs_thread()
241 {
242 int r;
243 pthread_t *thread = malloc(sizeof(*thread));
244 if (!thread)
245 return NULL;
246
247 do_cs = true;
248
249 r = pthread_create(thread, NULL, amdgpu_nop_cs, NULL);
250 CU_ASSERT_EQUAL(r, 0);
251
252 /* Give thread enough time to start*/
253 usleep(100000);
254 return thread;
255 }
256
amdgpu_destroy_cs_thread(pthread_t * thread)257 static void amdgpu_destroy_cs_thread(pthread_t *thread)
258 {
259 void *status;
260
261 do_cs = false;
262
263 pthread_join(*thread, &status);
264 CU_ASSERT_EQUAL(status, 0);
265
266 free(thread);
267 }
268
269
amdgpu_hotunplug_test(bool with_cs)270 static void amdgpu_hotunplug_test(bool with_cs)
271 {
272 int r;
273 pthread_t *thread = NULL;
274
275 r = amdgpu_hotunplug_setup_test();
276 CU_ASSERT_EQUAL(r , 0);
277
278 if (with_cs) {
279 thread = amdgpu_create_cs_thread();
280 CU_ASSERT_NOT_EQUAL(thread, NULL);
281 }
282
283 r = amdgpu_hotunplug_remove();
284 CU_ASSERT_EQUAL(r > 0, 1);
285
286 if (with_cs)
287 amdgpu_destroy_cs_thread(thread);
288
289 r = amdgpu_hotunplug_teardown_test();
290 CU_ASSERT_EQUAL(r , 0);
291
292 r = amdgpu_hotunplug_rescan();
293 CU_ASSERT_EQUAL(r > 0, 1);
294 }
295
amdgpu_hotunplug_simple(void)296 static void amdgpu_hotunplug_simple(void)
297 {
298 amdgpu_hotunplug_test(false);
299 }
300
amdgpu_hotunplug_with_cs(void)301 static void amdgpu_hotunplug_with_cs(void)
302 {
303 amdgpu_hotunplug_test(true);
304 }
305
amdgpu_hotunplug_with_exported_bo(void)306 static void amdgpu_hotunplug_with_exported_bo(void)
307 {
308 int r;
309 uint32_t dma_buf_fd;
310 unsigned int *ptr;
311 amdgpu_bo_handle bo_handle;
312
313 struct amdgpu_bo_alloc_request request = {
314 .alloc_size = 4096,
315 .phys_alignment = 4096,
316 .preferred_heap = AMDGPU_GEM_DOMAIN_GTT,
317 .flags = 0,
318 };
319
320 r = amdgpu_hotunplug_setup_test();
321 CU_ASSERT_EQUAL(r , 0);
322
323 amdgpu_bo_alloc(device_handle, &request, &bo_handle);
324 CU_ASSERT_EQUAL(r, 0);
325
326 r = amdgpu_bo_export(bo_handle, amdgpu_bo_handle_type_dma_buf_fd, &dma_buf_fd);
327 CU_ASSERT_EQUAL(r, 0);
328
329 ptr = mmap(NULL, 4096, PROT_READ | PROT_WRITE, MAP_SHARED, dma_buf_fd, 0);
330 CU_ASSERT_NOT_EQUAL(ptr, MAP_FAILED);
331
332 r = amdgpu_hotunplug_remove();
333 CU_ASSERT_EQUAL(r > 0, 1);
334
335 amdgpu_bo_free(bo_handle);
336
337 r = amdgpu_hotunplug_teardown_test();
338 CU_ASSERT_EQUAL(r , 0);
339
340 *ptr = 0xdeafbeef;
341
342 munmap(ptr, 4096);
343 close (dma_buf_fd);
344
345 r = amdgpu_hotunplug_rescan();
346 CU_ASSERT_EQUAL(r > 0, 1);
347 }
348
amdgpu_hotunplug_with_exported_fence(void)349 static void amdgpu_hotunplug_with_exported_fence(void)
350 {
351 amdgpu_bo_handle ib_result_handle;
352 void *ib_result_cpu;
353 uint64_t ib_result_mc_address;
354 uint32_t *ptr, sync_obj_handle, sync_obj_handle2;
355 int i, r;
356 amdgpu_bo_list_handle bo_list;
357 amdgpu_va_handle va_handle;
358 uint32_t major2, minor2;
359 amdgpu_device_handle device2;
360 amdgpu_context_handle context;
361 struct amdgpu_cs_request ibs_request;
362 struct amdgpu_cs_ib_info ib_info;
363 struct amdgpu_cs_fence fence_status = {0};
364 int shared_fd;
365
366 r = amdgpu_hotunplug_setup_test();
367 CU_ASSERT_EQUAL(r , 0);
368
369 r = amdgpu_device_initialize(drm_amdgpu[1], &major2, &minor2, &device2);
370 CU_ASSERT_EQUAL(r, 0);
371
372 r = amdgpu_cs_ctx_create(device_handle, &context);
373 CU_ASSERT_EQUAL(r, 0);
374
375 r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
376 AMDGPU_GEM_DOMAIN_GTT, 0,
377 &ib_result_handle, &ib_result_cpu,
378 &ib_result_mc_address, &va_handle);
379 CU_ASSERT_EQUAL(r, 0);
380
381 ptr = ib_result_cpu;
382 for (i = 0; i < 16; ++i)
383 ptr[i] = GFX_COMPUTE_NOP;
384
385 r = amdgpu_bo_list_create(device_handle, 1, &ib_result_handle, NULL, &bo_list);
386 CU_ASSERT_EQUAL(r, 0);
387
388 memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
389 ib_info.ib_mc_address = ib_result_mc_address;
390 ib_info.size = 16;
391
392 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
393 ibs_request.ip_type = AMDGPU_HW_IP_GFX;
394 ibs_request.ring = 0;
395 ibs_request.number_of_ibs = 1;
396 ibs_request.ibs = &ib_info;
397 ibs_request.resources = bo_list;
398
399 CU_ASSERT_EQUAL(amdgpu_cs_submit(context, 0, &ibs_request, 1), 0);
400
401 fence_status.context = context;
402 fence_status.ip_type = AMDGPU_HW_IP_GFX;
403 fence_status.ip_instance = 0;
404 fence_status.fence = ibs_request.seq_no;
405
406 CU_ASSERT_EQUAL(amdgpu_cs_fence_to_handle(device_handle, &fence_status,
407 AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ,
408 &sync_obj_handle),
409 0);
410
411 CU_ASSERT_EQUAL(amdgpu_cs_export_syncobj(device_handle, sync_obj_handle, &shared_fd), 0);
412
413 CU_ASSERT_EQUAL(amdgpu_cs_import_syncobj(device2, shared_fd, &sync_obj_handle2), 0);
414
415 CU_ASSERT_EQUAL(amdgpu_cs_destroy_syncobj(device_handle, sync_obj_handle), 0);
416
417 CU_ASSERT_EQUAL(amdgpu_bo_list_destroy(bo_list), 0);
418 CU_ASSERT_EQUAL(amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
419 ib_result_mc_address, 4096), 0);
420 CU_ASSERT_EQUAL(amdgpu_cs_ctx_free(context), 0);
421
422 r = amdgpu_hotunplug_remove();
423 CU_ASSERT_EQUAL(r > 0, 1);
424
425 CU_ASSERT_EQUAL(amdgpu_cs_syncobj_wait(device2, &sync_obj_handle2, 1, 100000000, 0, NULL), 0);
426
427 CU_ASSERT_EQUAL(amdgpu_cs_destroy_syncobj(device2, sync_obj_handle2), 0);
428
429 amdgpu_device_deinitialize(device2);
430
431 r = amdgpu_hotunplug_teardown_test();
432 CU_ASSERT_EQUAL(r , 0);
433
434 r = amdgpu_hotunplug_rescan();
435 CU_ASSERT_EQUAL(r > 0, 1);
436 }
437
438
439 CU_TestInfo hotunplug_tests[] = {
440 { "Unplug card and rescan the bus to plug it back", amdgpu_hotunplug_simple },
441 { "Same as first test but with command submission", amdgpu_hotunplug_with_cs },
442 { "Unplug with exported bo", amdgpu_hotunplug_with_exported_bo },
443 { "Unplug with exported fence", amdgpu_hotunplug_with_exported_fence },
444 CU_TEST_INFO_NULL,
445 };
446