xref: /netbsd/sys/dev/pci/cxgb/cxgb_common.h (revision 94e40a0f)
1 /**************************************************************************
2 
3 Copyright (c) 2007, Chelsio Inc.
4 All rights reserved.
5 
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8 
9  1. Redistributions of source code must retain the above copyright notice,
10     this list of conditions and the following disclaimer.
11 
12  2. Neither the name of the Chelsio Corporation nor the names of its
13     contributors may be used to endorse or promote products derived from
14     this software without specific prior written permission.
15 
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 POSSIBILITY OF SUCH DAMAGE.
27 
28 ***************************************************************************/
29 #ifndef __CHELSIO_COMMON_H
30 #define __CHELSIO_COMMON_H
31 
32 #ifdef CONFIG_DEFINED
33 #include <cxgb_osdep.h>
34 #else
35 #include <dev/pci/cxgb/cxgb_osdep.h>
36 // ??? #include <dev/pci/cxgb/cxgb_toedev.h>
37 #endif
38 
39 enum {
40     MAX_FRAME_SIZE = 10240, /* max MAC frame size, includes header + FCS */
41     EEPROMSIZE     = 8192,  /* Serial EEPROM size */
42     SERNUM_LEN     = 16,    /* Serial # length */
43     RSS_TABLE_SIZE = 64,    /* size of RSS lookup and mapping tables */
44     TCB_SIZE       = 128,   /* TCB size */
45     NMTUS          = 16,    /* size of MTU table */
46     NCCTRL_WIN     = 32,    /* # of congestion control windows */
47     NTX_SCHED      = 8,     /* # of HW Tx scheduling queues */
48     PROTO_SRAM_LINES = 128, /* size of protocol sram */
49     MAX_NPORTS     = 4,
50     TP_TMR_RES     = 200,
51     TP_SRAM_OFFSET = 4096,  /* TP SRAM content offset in eeprom */
52     TP_SRAM_LEN    = 2112,  /* TP SRAM content offset in eeprom */
53 };
54 
55 #define MAX_RX_COALESCING_LEN 12288U
56 
57 enum {
58     PAUSE_RX      = 1 << 0,
59     PAUSE_TX      = 1 << 1,
60     PAUSE_AUTONEG = 1 << 2
61 };
62 
63 enum {
64     SUPPORTED_IRQ      = 1 << 24
65 };
66 
67 enum {                            /* adapter interrupt-maintained statistics */
68     STAT_ULP_CH0_PBL_OOB,
69     STAT_ULP_CH1_PBL_OOB,
70     STAT_PCI_CORR_ECC,
71 
72     IRQ_NUM_STATS             /* keep last */
73 };
74 
75 enum {
76     TP_VERSION_MAJOR    = 1,
77     TP_VERSION_MINOR    = 1,
78     TP_VERSION_MICRO    = 0
79 };
80 
81 #define S_TP_VERSION_MAJOR      16
82 #define M_TP_VERSION_MAJOR      0xFF
83 #define V_TP_VERSION_MAJOR(x)       ((x) << S_TP_VERSION_MAJOR)
84 #define G_TP_VERSION_MAJOR(x)       \
85         (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR)
86 
87 #define S_TP_VERSION_MINOR      8
88 #define M_TP_VERSION_MINOR      0xFF
89 #define V_TP_VERSION_MINOR(x)       ((x) << S_TP_VERSION_MINOR)
90 #define G_TP_VERSION_MINOR(x)       \
91         (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR)
92 
93 #define S_TP_VERSION_MICRO      0
94 #define M_TP_VERSION_MICRO      0xFF
95 #define V_TP_VERSION_MICRO(x)       ((x) << S_TP_VERSION_MICRO)
96 #define G_TP_VERSION_MICRO(x)       \
97         (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO)
98 
99 enum {
100     FW_VERSION_MAJOR = 4,
101     FW_VERSION_MINOR = 7,
102     FW_VERSION_MICRO = 0
103 };
104 
105 enum {
106     SGE_QSETS = 8,            /* # of SGE Tx/Rx/RspQ sets */
107     SGE_RXQ_PER_SET = 2,      /* # of Rx queues per set */
108     SGE_TXQ_PER_SET = 3       /* # of Tx queues per set */
109 };
110 
111 enum sge_context_type {           /* SGE egress context types */
112     SGE_CNTXT_RDMA  = 0,
113     SGE_CNTXT_ETH   = 2,
114     SGE_CNTXT_OFLD  = 4,
115     SGE_CNTXT_CTRL  = 5
116 };
117 
118 enum {
119     AN_PKT_SIZE    = 32,      /* async notification packet size */
120     IMMED_PKT_SIZE = 48       /* packet size for immediate data */
121 };
122 
123 struct sg_ent {                   /* SGE scatter/gather entry */
124     u32 len[2];
125     u64 addr[2];
126 };
127 
128 #ifndef SGE_NUM_GENBITS
129 /* Must be 1 or 2 */
130 # define SGE_NUM_GENBITS 2
131 #endif
132 
133 #define TX_DESC_FLITS 16U
134 #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
135 
136 struct cphy;
137 
138 struct mdio_ops {
139     int  (*read)(adapter_t *adapter, int phy_addr, int mmd_addr,
140              int reg_addr, unsigned int *val);
141         int  (*write)(adapter_t *adapter, int phy_addr, int mmd_addr,
142               int reg_addr, unsigned int val);
143 };
144 
145 struct adapter_info {
146     unsigned char          nports0;        /* # of ports on channel 0 */
147     unsigned char          nports1;        /* # of ports on channel 1 */
148     unsigned char          phy_base_addr;  /* MDIO PHY base address */
149     unsigned char          mdien:1;
150     unsigned char          mdiinv:1;
151     unsigned int           gpio_out;       /* GPIO output settings */
152     unsigned int           gpio_intr;      /* GPIO IRQ enable mask */
153     unsigned long          caps;           /* adapter capabilities */
154     const struct mdio_ops *mdio_ops;       /* MDIO operations */
155     const char            *desc;           /* product description */
156 };
157 
158 struct port_type_info {
159     void (*phy_prep)(struct cphy *phy, adapter_t *adapter, int phy_addr,
160              const struct mdio_ops *ops);
161     unsigned int caps;
162     const char *desc;
163 };
164 
165 struct mc5_stats {
166     unsigned long parity_err;
167     unsigned long active_rgn_full;
168     unsigned long nfa_srch_err;
169     unsigned long unknown_cmd;
170     unsigned long reqq_parity_err;
171     unsigned long dispq_parity_err;
172     unsigned long del_act_empty;
173 };
174 
175 struct mc7_stats {
176     unsigned long corr_err;
177     unsigned long uncorr_err;
178     unsigned long parity_err;
179     unsigned long addr_err;
180 };
181 
182 struct mac_stats {
183     u64 tx_octets;            /* total # of octets in good frames */
184     u64 tx_octets_bad;        /* total # of octets in error frames */
185     u64 tx_frames;            /* all good frames */
186     u64 tx_mcast_frames;      /* good multicast frames */
187     u64 tx_bcast_frames;      /* good broadcast frames */
188     u64 tx_pause;             /* # of transmitted pause frames */
189     u64 tx_deferred;          /* frames with deferred transmissions */
190     u64 tx_late_collisions;   /* # of late collisions */
191     u64 tx_total_collisions;  /* # of total collisions */
192     u64 tx_excess_collisions; /* frame errors from excessive collisions */
193     u64 tx_underrun;          /* # of Tx FIFO underruns */
194     u64 tx_len_errs;          /* # of Tx length errors */
195     u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */
196     u64 tx_excess_deferral;   /* # of frames with excessive deferral */
197     u64 tx_fcs_errs;          /* # of frames with bad FCS */
198 
199     u64 tx_frames_64;         /* # of Tx frames in a particular range */
200     u64 tx_frames_65_127;
201     u64 tx_frames_128_255;
202     u64 tx_frames_256_511;
203     u64 tx_frames_512_1023;
204     u64 tx_frames_1024_1518;
205     u64 tx_frames_1519_max;
206 
207     u64 rx_octets;            /* total # of octets in good frames */
208     u64 rx_octets_bad;        /* total # of octets in error frames */
209     u64 rx_frames;            /* all good frames */
210     u64 rx_mcast_frames;      /* good multicast frames */
211     u64 rx_bcast_frames;      /* good broadcast frames */
212     u64 rx_pause;             /* # of received pause frames */
213     u64 rx_fcs_errs;          /* # of received frames with bad FCS */
214     u64 rx_align_errs;        /* alignment errors */
215     u64 rx_symbol_errs;       /* symbol errors */
216     u64 rx_data_errs;         /* data errors */
217     u64 rx_sequence_errs;     /* sequence errors */
218     u64 rx_runt;              /* # of runt frames */
219     u64 rx_jabber;            /* # of jabber frames */
220     u64 rx_short;             /* # of short frames */
221     u64 rx_too_long;          /* # of oversized frames */
222     u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */
223 
224     u64 rx_frames_64;         /* # of Rx frames in a particular range */
225     u64 rx_frames_65_127;
226     u64 rx_frames_128_255;
227     u64 rx_frames_256_511;
228     u64 rx_frames_512_1023;
229     u64 rx_frames_1024_1518;
230     u64 rx_frames_1519_max;
231 
232     u64 rx_cong_drops;        /* # of Rx drops due to SGE congestion */
233 
234     unsigned long tx_fifo_parity_err;
235     unsigned long rx_fifo_parity_err;
236     unsigned long tx_fifo_urun;
237     unsigned long rx_fifo_ovfl;
238     unsigned long serdes_signal_loss;
239     unsigned long xaui_pcs_ctc_err;
240     unsigned long xaui_pcs_align_change;
241 
242     unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */
243     unsigned long num_resets;  /* # times reset due to stuck TX */
244 };
245 
246 struct tp_mib_stats {
247     u32 ipInReceive_hi;
248     u32 ipInReceive_lo;
249     u32 ipInHdrErrors_hi;
250     u32 ipInHdrErrors_lo;
251     u32 ipInAddrErrors_hi;
252     u32 ipInAddrErrors_lo;
253     u32 ipInUnknownProtos_hi;
254     u32 ipInUnknownProtos_lo;
255     u32 ipInDiscards_hi;
256     u32 ipInDiscards_lo;
257     u32 ipInDelivers_hi;
258     u32 ipInDelivers_lo;
259     u32 ipOutRequests_hi;
260     u32 ipOutRequests_lo;
261     u32 ipOutDiscards_hi;
262     u32 ipOutDiscards_lo;
263     u32 ipOutNoRoutes_hi;
264     u32 ipOutNoRoutes_lo;
265     u32 ipReasmTimeout;
266     u32 ipReasmReqds;
267     u32 ipReasmOKs;
268     u32 ipReasmFails;
269 
270     u32 reserved[8];
271 
272     u32 tcpActiveOpens;
273     u32 tcpPassiveOpens;
274     u32 tcpAttemptFails;
275     u32 tcpEstabResets;
276     u32 tcpOutRsts;
277     u32 tcpCurrEstab;
278     u32 tcpInSegs_hi;
279     u32 tcpInSegs_lo;
280     u32 tcpOutSegs_hi;
281     u32 tcpOutSegs_lo;
282     u32 tcpRetransSeg_hi;
283     u32 tcpRetransSeg_lo;
284     u32 tcpInErrs_hi;
285     u32 tcpInErrs_lo;
286     u32 tcpRtoMin;
287     u32 tcpRtoMax;
288 };
289 
290 struct tp_params {
291     unsigned int nchan;          /* # of channels */
292     unsigned int pmrx_size;      /* total PMRX capacity */
293     unsigned int pmtx_size;      /* total PMTX capacity */
294     unsigned int cm_size;        /* total CM capacity */
295     unsigned int chan_rx_size;   /* per channel Rx size */
296     unsigned int chan_tx_size;   /* per channel Tx size */
297     unsigned int rx_pg_size;     /* Rx page size */
298     unsigned int tx_pg_size;     /* Tx page size */
299     unsigned int rx_num_pgs;     /* # of Rx pages */
300     unsigned int tx_num_pgs;     /* # of Tx pages */
301     unsigned int ntimer_qs;      /* # of timer queues */
302     unsigned int tre;            /* log2 of core clocks per TP tick */
303     unsigned int dack_re;        /* DACK timer resolution */
304 };
305 
306 struct qset_params {                   /* SGE queue set parameters */
307     unsigned int polling;          /* polling/interrupt service for rspq */
308     unsigned int lro;              /* large receive offload */
309     unsigned int coalesce_nsecs;   /* irq coalescing timer */
310     unsigned int rspq_size;        /* # of entries in response queue */
311     unsigned int fl_size;          /* # of entries in regular free list */
312     unsigned int jumbo_size;       /* # of entries in jumbo free list */
313     unsigned int txq_size[SGE_TXQ_PER_SET];  /* Tx queue sizes */
314     unsigned int cong_thres;       /* FL congestion threshold */
315     unsigned int vector;           /* Interrupt (line or vector) number */
316 };
317 
318 struct sge_params {
319     unsigned int max_pkt_size;     /* max offload pkt size */
320     struct qset_params qset[SGE_QSETS];
321 };
322 
323 struct mc5_params {
324     unsigned int mode;       /* selects MC5 width */
325     unsigned int nservers;   /* size of server region */
326     unsigned int nfilters;   /* size of filter region */
327     unsigned int nroutes;    /* size of routing region */
328 };
329 
330 /* Default MC5 region sizes */
331 enum {
332     DEFAULT_NSERVERS = 512,
333     DEFAULT_NFILTERS = 128
334 };
335 
336 /* MC5 modes, these must be non-0 */
337 enum {
338     MC5_MODE_144_BIT = 1,
339     MC5_MODE_72_BIT  = 2
340 };
341 
342 /* MC5 min active region size */
343 enum { MC5_MIN_TIDS = 16 };
344 
345 struct vpd_params {
346     unsigned int cclk;
347     unsigned int mclk;
348     unsigned int uclk;
349     unsigned int mdc;
350     unsigned int mem_timing;
351     u8 sn[SERNUM_LEN + 1];
352     u8 eth_base[6];
353     u8 port_type[MAX_NPORTS];
354     unsigned short xauicfg[2];
355 };
356 
357 struct pci_params {
358     unsigned int   vpd_cap_addr;
359     unsigned int   pcie_cap_addr;
360     unsigned short speed;
361     unsigned char  width;
362     unsigned char  variant;
363 };
364 
365 enum {
366     PCI_VARIANT_PCI,
367     PCI_VARIANT_PCIX_MODE1_PARITY,
368     PCI_VARIANT_PCIX_MODE1_ECC,
369     PCI_VARIANT_PCIX_266_MODE2,
370     PCI_VARIANT_PCIE
371 };
372 
373 struct adapter_params {
374     struct sge_params sge;
375     struct mc5_params mc5;
376     struct tp_params  tp;
377     struct vpd_params vpd;
378     struct pci_params pci;
379 
380     const struct adapter_info *info;
381 
382 #ifdef CONFIG_CHELSIO_T3_CORE
383     unsigned short mtus[NMTUS];
384     unsigned short a_wnd[NCCTRL_WIN];
385     unsigned short b_wnd[NCCTRL_WIN];
386 #endif
387     unsigned int   nports;              /* # of ethernet ports */
388     unsigned int   chan_map;            /* bitmap of in-use Tx channels */
389     unsigned int   stats_update_period; /* MAC stats accumulation period */
390     unsigned int   linkpoll_period;     /* link poll period in 0.1s */
391     unsigned int   rev;                 /* chip revision */
392     unsigned int   offload;
393 };
394 
395 enum {                      /* chip revisions */
396     T3_REV_A  = 0,
397     T3_REV_B  = 2,
398     T3_REV_B2 = 3,
399     T3_REV_C  = 4,
400 };
401 
402 struct trace_params {
403     u32 sip;
404         u32 sip_mask;
405     u32 dip;
406         u32 dip_mask;
407     u16 sport;
408     u16 sport_mask;
409     u16 dport;
410     u16 dport_mask;
411     u32 vlan:12;
412     u32 vlan_mask:12;
413     u32 intf:4;
414     u32 intf_mask:4;
415     u8  proto;
416     u8  proto_mask;
417 };
418 
419 struct link_config {
420     unsigned int   supported;        /* link capabilities */
421     unsigned int   advertising;      /* advertised capabilities */
422         unsigned short requested_speed;  /* speed user has requested */
423     unsigned short speed;            /* actual link speed */
424         unsigned char  requested_duplex; /* duplex user has requested */
425     unsigned char  duplex;           /* actual link duplex */
426     unsigned char  requested_fc;     /* flow control user has requested */
427     unsigned char  fc;               /* actual link flow control */
428     unsigned char  autoneg;          /* autonegotiating? */
429     unsigned int link_ok;          /* link up? */
430 };
431 
432 #define SPEED_INVALID   0xffff
433 #define DUPLEX_INVALID  0xff
434 
435 struct mc5 {
436     adapter_t *adapter;
437     unsigned int tcam_size;
438     unsigned char part_type;
439     unsigned char parity_enabled;
440     unsigned char mode;
441     struct mc5_stats stats;
442 };
443 
t3_mc5_size(const struct mc5 * p)444 static __inline unsigned int t3_mc5_size(const struct mc5 *p)
445 {
446     return p->tcam_size;
447 }
448 
449 struct mc7 {
450     adapter_t *adapter;     /* backpointer to adapter */
451     unsigned int size;      /* memory size in bytes */
452     unsigned int width;     /* MC7 interface width */
453     unsigned int offset;    /* register address offset for MC7 instance */
454     const char *name;       /* name of MC7 instance */
455     struct mc7_stats stats; /* MC7 statistics */
456 };
457 
t3_mc7_size(const struct mc7 * p)458 static __inline unsigned int t3_mc7_size(const struct mc7 *p)
459 {
460     return p->size;
461 }
462 
463 struct cmac {
464     adapter_t *adapter;
465     unsigned int offset;
466     unsigned char nucast;    /* # of address filters for unicast MACs */
467     unsigned char multiport; /* multiple ports connected to this MAC */
468     unsigned char ext_port;  /* external MAC port */
469     unsigned char promisc_map;  /* which external ports are promiscuous */
470     unsigned int tx_tcnt;
471     unsigned int tx_xcnt;
472     u64 tx_mcnt;
473     unsigned int rx_xcnt;
474     unsigned int rx_ocnt;
475     u64 rx_mcnt;
476     unsigned int toggle_cnt;
477     unsigned int txen;
478     u64 rx_pause;
479     struct mac_stats stats;
480 };
481 
482 enum {
483     MAC_DIRECTION_RX = 1,
484     MAC_DIRECTION_TX = 2,
485     MAC_RXFIFO_SIZE  = 32768
486 };
487 
488 /* IEEE 802.3ae specified MDIO devices */
489 enum {
490     MDIO_DEV_PMA_PMD = 1,
491     MDIO_DEV_WIS     = 2,
492     MDIO_DEV_PCS     = 3,
493     MDIO_DEV_XGXS    = 4
494 };
495 
496 /* PHY loopback direction */
497 enum {
498     PHY_LOOPBACK_TX = 1,
499     PHY_LOOPBACK_RX = 2
500 };
501 
502 /* PHY interrupt types */
503 enum {
504     cphy_cause_link_change = 1,
505     cphy_cause_fifo_error = 2
506 };
507 
508 /* PHY operations */
509 struct cphy_ops {
510     void (*destroy)(struct cphy *phy);
511     int (*reset)(struct cphy *phy, int wait);
512 
513     int (*intr_enable)(struct cphy *phy);
514     int (*intr_disable)(struct cphy *phy);
515     int (*intr_clear)(struct cphy *phy);
516     int (*intr_handler)(struct cphy *phy);
517 
518     int (*autoneg_enable)(struct cphy *phy);
519     int (*autoneg_restart)(struct cphy *phy);
520 
521     int (*advertise)(struct cphy *phy, unsigned int advertise_map);
522     int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable);
523     int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
524     int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
525                    int *duplex, int *fc);
526     int (*power_down)(struct cphy *phy, int enable);
527 };
528 
529 /* A PHY instance */
530 struct cphy {
531     int addr;                            /* PHY address */
532     adapter_t *adapter;                  /* associated adapter */
533     unsigned long fifo_errors;           /* FIFO over/under-flows */
534     const struct cphy_ops *ops;          /* PHY operations */
535     int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr,
536              int reg_addr, unsigned int *val);
537     int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr,
538               int reg_addr, unsigned int val);
539 };
540 
541 /* Convenience MDIO read/write wrappers */
mdio_read(struct cphy * phy,int mmd,int reg,unsigned int * valp)542 static __inline int mdio_read(struct cphy *phy, int mmd, int reg,
543                 unsigned int *valp)
544 {
545         return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp);
546 }
547 
mdio_write(struct cphy * phy,int mmd,int reg,unsigned int val)548 static __inline int mdio_write(struct cphy *phy, int mmd, int reg,
549                  unsigned int val)
550 {
551         return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val);
552 }
553 
554 /* Convenience initializer */
cphy_init(struct cphy * phy,adapter_t * adapter,int phy_addr,struct cphy_ops * phy_ops,const struct mdio_ops * mdio_ops)555 static __inline void cphy_init(struct cphy *phy, adapter_t *adapter,
556                  int phy_addr, struct cphy_ops *phy_ops,
557                  const struct mdio_ops *mdio_ops)
558 {
559     phy->adapter = adapter;
560     phy->addr    = phy_addr;
561     phy->ops     = phy_ops;
562     if (mdio_ops) {
563         phy->mdio_read  = mdio_ops->read;
564         phy->mdio_write = mdio_ops->write;
565     }
566 }
567 
568 /* Accumulate MAC statistics every 180 seconds.  For 1G we multiply by 10. */
569 #define MAC_STATS_ACCUM_SECS 180
570 
571 /* The external MAC needs accumulation every 30 seconds */
572 #define VSC_STATS_ACCUM_SECS 30
573 
574 #define XGM_REG(reg_addr, idx) \
575     ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
576 
577 struct addr_val_pair {
578     unsigned int reg_addr;
579     unsigned int val;
580 };
581 
582 #ifdef CONFIG_DEFINED
583 #include <cxgb_adapter.h>
584 #else
585 #include <dev/pci/cxgb/cxgb_adapter.h>
586 #endif
587 
588 #ifndef PCI_VENDOR_ID_CHELSIO
589 # define PCI_VENDOR_ID_CHELSIO 0x1425
590 #endif
591 
592 #define for_each_port(adapter, iter) \
593     for (iter = 0; iter < (adapter)->params.nports; ++iter)
594 
595 #define adapter_info(adap) ((adap)->params.info)
596 
uses_xaui(const adapter_t * adap)597 static __inline int uses_xaui(const adapter_t *adap)
598 {
599     return adapter_info(adap)->caps & SUPPORTED_AUI;
600 }
601 
is_10G(const adapter_t * adap)602 static __inline int is_10G(const adapter_t *adap)
603 {
604     return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full;
605 }
606 
is_offload(const adapter_t * adap)607 static __inline int is_offload(const adapter_t *adap)
608 {
609 #ifdef CONFIG_CHELSIO_T3_CORE
610     return adap->params.offload;
611 #else
612     return 0;
613 #endif
614 }
615 
core_ticks_per_usec(const adapter_t * adap)616 static __inline unsigned int core_ticks_per_usec(const adapter_t *adap)
617 {
618     return adap->params.vpd.cclk / 1000;
619 }
620 
dack_ticks_to_usec(const adapter_t * adap,unsigned int ticks)621 static __inline unsigned int dack_ticks_to_usec(const adapter_t *adap,
622                           unsigned int ticks)
623 {
624     return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
625 }
626 
is_pcie(const adapter_t * adap)627 static __inline unsigned int is_pcie(const adapter_t *adap)
628 {
629     return adap->params.pci.variant == PCI_VARIANT_PCIE;
630 }
631 
632 void t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val);
633 void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n,
634            unsigned int offset);
635 int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity,
636             int attempts, int delay, u32 *valp);
637 
t3_wait_op_done(adapter_t * adapter,int reg,u32 mask,int polarity,int attempts,int delay)638 static __inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask,
639                   int polarity, int attempts, int delay)
640 {
641     return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,
642                    delay, NULL);
643 }
644 
645 int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
646             unsigned int set);
647 int t3_phy_reset(struct cphy *phy, int mmd, int wait);
648 int t3_phy_advertise(struct cphy *phy, unsigned int advert);
649 int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex);
650 
651 void t3_intr_enable(adapter_t *adapter);
652 void t3_intr_disable(adapter_t *adapter);
653 void t3_intr_clear(adapter_t *adapter);
654 void t3_port_intr_enable(adapter_t *adapter, int idx);
655 void t3_port_intr_disable(adapter_t *adapter, int idx);
656 void t3_port_intr_clear(adapter_t *adapter, int idx);
657 int t3_slow_intr_handler(adapter_t *adapter);
658 int t3_phy_intr_handler(adapter_t *adapter);
659 
660 void t3_link_changed(adapter_t *adapter, int port_id);
661 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
662 const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
663 int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data);
664 int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data);
665 int t3_seeprom_wp(adapter_t *adapter, int enable);
666 int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords,
667           u32 *data, int byte_oriented);
668 int t3_get_tp_version(adapter_t *adapter, u32 *vers);
669 int t3_check_tpsram_version(adapter_t *adapter);
670 int t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size);
671 int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size);
672 int t3_get_fw_version(adapter_t *adapter, u32 *vers);
673 int t3_check_fw_version(adapter_t *adapter);
674 int t3_init_hw(adapter_t *adapter, u32 fw_params);
675 void mac_prep(struct cmac *mac, adapter_t *adapter, int index);
676 void early_hw_init(adapter_t *adapter, const struct adapter_info *ai);
677 int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset);
678 void t3_led_ready(adapter_t *adapter);
679 void t3_fatal_err(adapter_t *adapter);
680 void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on);
681 void t3_enable_filters(adapter_t *adap);
682 void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus,
683            const u16 *rspq);
684 int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map);
685 int t3_set_proto_sram(adapter_t *adap, const u8 *data);
686 int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask);
687 void t3_port_failover(adapter_t *adapter, int port);
688 void t3_failover_done(adapter_t *adapter, int port);
689 void t3_failover_clear(adapter_t *adapter);
690 int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n,
691             unsigned int *valp);
692 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
693            u64 *buf);
694 
695 int t3_mac_reset(struct cmac *mac);
696 void t3b_pcs_reset(struct cmac *mac);
697 int t3_mac_enable(struct cmac *mac, int which);
698 int t3_mac_disable(struct cmac *mac, int which);
699 int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu);
700 int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm);
701 int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]);
702 int t3_mac_set_num_ucast(struct cmac *mac, unsigned char n);
703 const struct mac_stats *t3_mac_update_stats(struct cmac *mac);
704 int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex,
705                    int fc);
706 int t3b2_mac_watchdog_task(struct cmac *mac);
707 
708 void t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode);
709 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
710         unsigned int nroutes);
711 void t3_mc5_intr_handler(struct mc5 *mc5);
712 int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n,
713               u32 *buf);
714 
715 #ifdef CONFIG_CHELSIO_T3_CORE
716 int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh);
717 void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size);
718 void t3_tp_set_offload_mode(adapter_t *adap, int enable);
719 void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps);
720 void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS],
721                   unsigned short alpha[NCCTRL_WIN],
722           unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
723 void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]);
724 void t3_get_cong_cntl_tab(adapter_t *adap,
725               unsigned short incr[NMTUS][NCCTRL_WIN]);
726 void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp,
727                 int filter_index, int invert, int enable);
728 int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched);
729 int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg);
730 void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps,
731              unsigned int *ipg);
732 void t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED]);
733 void t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals,
734              unsigned int start, unsigned int n);
735 #endif
736 
737 void t3_sge_prep(adapter_t *adap, struct sge_params *p);
738 void t3_sge_init(adapter_t *adap, struct sge_params *p);
739 int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable,
740                enum sge_context_type type, int respq, u64 base_addr,
741                unsigned int size, unsigned int token, int gen,
742                unsigned int cidx);
743 int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable,
744             u64 base_addr, unsigned int size, unsigned int esize,
745             unsigned int cong_thres, int gen, unsigned int cidx);
746 int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx,
747              u64 base_addr, unsigned int size,
748              unsigned int fl_thres, int gen, unsigned int cidx);
749 int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr,
750             unsigned int size, int rspq, int ovfl_mode,
751             unsigned int credits, unsigned int credit_thres);
752 int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable);
753 int t3_sge_disable_fl(adapter_t *adapter, unsigned int id);
754 int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id);
755 int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id);
756 int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]);
757 int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]);
758 int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]);
759 int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]);
760 int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op,
761               unsigned int credits);
762 
763 int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n);
764 int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n);
765 int t3_vsc7323_init(adapter_t *adap, int nports);
766 int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port);
767 int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port);
768 int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port);
769 int t3_vsc7323_enable(adapter_t *adap, int port, int which);
770 int t3_vsc7323_disable(adapter_t *adap, int port, int which);
771 const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac);
772 
773 void t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
774                const struct mdio_ops *mdio_ops);
775 void t3_vsc8211_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
776              const struct mdio_ops *mdio_ops);
777 void t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
778              const struct mdio_ops *mdio_ops);
779 void t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
780              const struct mdio_ops *mdio_ops);
781 void t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
782             const struct mdio_ops *mdio_ops);
783 void t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
784                  const struct mdio_ops *mdio_ops);
785 #endif /* __CHELSIO_COMMON_H */
786