xref: /dragonfly/sys/dev/disk/buslogic/btreg.h (revision 5d302545)
1 /*
2  * Generic register and struct definitions for the BusLogic
3  * MultiMaster SCSI host adapters.  Product specific probe and
4  * attach routines can be found in:
5  * sys/dev/buslogic/bt_pci.c	BT-946, BT-948, BT-956, BT-958 cards
6  *
7  * Copyright (c) 1998, 1999 Justin T. Gibbs.
8  * All rights reserved.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions, and the following disclaimer,
15  *    without modification, immediately at the beginning of the file.
16  * 2. The name of the author may not be used to endorse or promote products
17  *    derived from this software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
23  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29  * SUCH DAMAGE.
30  *
31  * $FreeBSD: src/sys/dev/buslogic/btreg.h,v 1.18 2012/11/17 01:51:40 svnexp Exp $
32  */
33 
34 #ifndef _BTREG_H_
35 #define _BTREG_H_
36 
37 #include <sys/queue.h>
38 
39 #define BT_MAXTRANSFER_SIZE	 0xffffffff	/* limited by 32bit counter */
40 #define BT_NSEG		32	/* The number of dma segments supported.
41                                  * BT_NSEG can be maxed out at 8192 entries,
42                                  * but the kernel will never need to transfer
43                                  * such a large request.  To reduce the
44                                  * driver's memory consumption, we reduce the
45                                  * max to 32.  16 would work if all transfers
46                                  * are paged alined since the kernel will only
47                                  * generate at most a 64k transfer, but to
48                                  * handle non-page aligned transfers, you need
49                                  * 17, so we round to the next power of two
50                                  * to make allocating SG space easy and
51                                  * efficient.
52 				 */
53 
54 #define ALL_TARGETS (~0)
55 
56 /*
57  * Control Register pp. 1-8, 1-9 (Write Only)
58  */
59 #define	CONTROL_REG		0x00
60 #define		HARD_RESET	0x80	/* Hard Reset - return to POST state */
61 #define		SOFT_RESET	0x40	/* Soft Reset - Clears Adapter state */
62 #define		RESET_INTR	0x20	/* Reset/Ack Interrupt */
63 #define		RESET_SBUS	0x10	/* Drive SCSI bus reset signal */
64 
65 /*
66  * Status Register pp. 1-9, 1-10 (Read Only)
67  */
68 #define STATUS_REG			0x00
69 #define		DIAG_ACTIVE		0x80	/* Performing Internal Diags */
70 #define		DIAG_FAIL		0x40	/* Internal Diags failed */
71 #define		INIT_REQUIRED		0x20	/* MBOXes need initialization */
72 #define		HA_READY		0x10	/* HA ready for new commands */
73 #define		CMD_REG_BUSY		0x08	/* HA busy with last cmd byte */
74 #define		DATAIN_REG_READY	0x04	/* Data-in Byte available */
75 #define		STATUS_REG_RSVD		0x02
76 #define		CMD_INVALID		0x01	/* Invalid Command detected */
77 
78 /*
79  * Command/Parameter Register pp. 1-10, 1-11 (Write Only)
80  */
81 #define	COMMAND_REG			0x01
82 
83 /*
84  * Data in Register p. 1-11 (Read Only)
85  */
86 #define	DATAIN_REG			0x01
87 
88 /*
89  * Interrupt Status Register pp. 1-12 -> 1-14 (Read Only)
90  */
91 #define INTSTAT_REG			0x02
92 #define		INTR_PENDING		0x80	/* There is a pending INTR */
93 #define		INTSTAT_REG_RSVD	0x70
94 #define		SCSI_BUS_RESET		0x08	/* Bus Reset detected */
95 #define		CMD_COMPLETE		0x04
96 #define		OMB_READY		0x02	/* Outgoin Mailbox Ready */
97 #define		IMB_LOADED		0x01	/* Incoming Mailbox loaded */
98 
99 /*
100  * Definitions for the "undocumented" geometry register
101  */
102 typedef enum {
103 	GEOM_NODISK,
104 	GEOM_64x32,
105 	GEOM_128x32,
106 	GEOM_255x32
107 } disk_geom_t;
108 
109 #define GEOMETRY_REG			0x03
110 #define		DISK0_GEOMETRY		0x03
111 #define		DISK1_GEOMETRY		0x0c
112 #define		EXTENDED_TRANSLATION	0x80
113 #define		GEOMETRY_DISK0(g_reg) (greg & DISK0_GEOMETRY)
114 #define		GEOMETRY_DISK1(g_reg) ((greg & DISK1_GEOMETRY) >> 2)
115 
116 #define BT_NREGS	(4)
117 /*
118  * Opcodes for Adapter commands.
119  * pp 1-18 -> 1-20
120  */
121 typedef enum {
122 	BOP_TEST_CMDC_INTR	= 0x00,
123 	BOP_INITIALIZE_24BMBOX	= 0x01,
124 	BOP_START_MBOX		= 0x02,
125 	BOP_EXECUTE_BIOS_CMD	= 0x03,
126 	BOP_INQUIRE_BOARD_ID	= 0x04,
127 	BOP_ENABLE_OMBR_INT	= 0x05,
128 	BOP_SET_SEL_TIMOUT	= 0x06,
129 	BOP_SET_TIME_ON_BUS	= 0x07,
130 	BOP_SET_TIME_OFF_BUS	= 0x08,
131 	BOP_SET_BUS_TRANS_RATE	= 0x09,
132 	BOP_INQUIRE_INST_LDEVS	= 0x0A,
133 	BOP_INQUIRE_CONFIG	= 0x0B,
134 	BOP_ENABLE_TARGET_MODE	= 0x0C,
135 	BOP_INQUIRE_SETUP_INFO	= 0x0D,
136 	BOP_WRITE_LRAM		= 0x1A,
137 	BOP_READ_LRAM		= 0x1B,
138 	BOP_WRITE_CHIP_FIFO	= 0x1C,
139 	BOP_READ_CHIP_FIFO	= 0x1C,
140 	BOP_ECHO_DATA_BYTE	= 0x1F,
141 	BOP_ADAPTER_DIAGNOSTICS	= 0x20,
142 	BOP_SET_ADAPTER_OPTIONS	= 0x21,
143 	BOP_INQUIRE_INST_HDEVS	= 0x23,
144 	BOP_INQUIRE_TARG_DEVS	= 0x24,
145 	BOP_DISABLE_HAC_INTR	= 0x25,
146 	BOP_INITIALIZE_32BMBOX	= 0x81,
147 	BOP_EXECUTE_SCSI_CMD	= 0x83,
148 	BOP_INQUIRE_FW_VER_3DIG	= 0x84,
149 	BOP_INQUIRE_FW_VER_4DIG	= 0x85,
150 	BOP_INQUIRE_PCI_INFO	= 0x86,
151 	BOP_INQUIRE_MODEL	= 0x8B,
152 	BOP_TARG_SYNC_INFO	= 0x8C,
153 	BOP_INQUIRE_ESETUP_INFO	= 0x8D,
154 	BOP_ENABLE_STRICT_RR	= 0x8F,
155 	BOP_STORE_LRAM		= 0x90,
156 	BOP_FETCH_LRAM		= 0x91,
157 	BOP_SAVE_TO_EEPROM	= 0x92,
158 	BOP_UPLOAD_AUTO_SCSI	= 0x94,
159 	BOP_MODIFY_IO_ADDR	= 0x95,
160 	BOP_SET_CCB_FORMAT	= 0x96,
161 	BOP_FLASH_ROM_DOWNLOAD	= 0x97,
162 	BOP_FLASH_WRITE_ENABLE	= 0x98,
163 	BOP_WRITE_INQ_BUFFER	= 0x9A,
164 	BOP_READ_INQ_BUFFER	= 0x9B,
165 	BOP_FLASH_UP_DOWNLOAD	= 0xA7,
166 	BOP_READ_SCAM_DATA	= 0xA8,
167 	BOP_WRITE_SCAM_DATA	= 0xA9
168 } bt_op_t;
169 
170 /************** Definitions of Multi-byte commands and responses ************/
171 
172 typedef struct {
173 	u_int8_t num_mboxes;
174 	u_int8_t base_addr[3];
175 } init_24b_mbox_params_t;
176 
177 typedef struct {
178 	u_int8_t board_type;
179 #define		BOARD_TYPE_NON_MCA	0x41
180 #define		BOARD_TYPE_MCA		0x42
181 	u_int8_t cust_features;
182 #define		FEATURES_STANDARD	0x41
183 	u_int8_t firmware_rev_major;
184 	u_int8_t firmware_rev_minor;
185 } board_id_data_t;
186 
187 typedef struct {
188 	u_int8_t enable;
189 } enable_ombr_intr_params_t;
190 
191 typedef struct {
192 	u_int8_t enable;
193 	u_int8_t reserved;
194 	u_int8_t timeout[2];	/* timeout in milliseconds */
195 } set_selto_parmas_t;
196 
197 typedef struct {
198 	u_int8_t time;		/* time in milliseconds (2-15) */
199 } set_timeon_bus_params_t;
200 
201 typedef struct {
202 	u_int8_t time;		/* time in milliseconds (2-15) */
203 } set_timeoff_bus_params_t;
204 
205 typedef struct {
206 	u_int8_t rate;
207 } set_bus_trasfer_rate_params_t;
208 
209 typedef struct {
210 	u_int8_t targets[8];
211 } installed_ldevs_data_t;
212 
213 typedef struct {
214 	u_int8_t dma_chan;
215 #define		DMA_CHAN_5	0x20
216 #define		DMA_CHAN_6	0x40
217 #define		DMA_CHAN_7	0x80
218 	u_int8_t irq;
219 #define		IRQ_9		0x01
220 #define		IRQ_10		0x02
221 #define		IRQ_11		0x04
222 #define		IRQ_12		0x08
223 #define		IRQ_14		0x20
224 #define		IRQ_15		0x40
225 	u_int8_t scsi_id;
226 } config_data_t;
227 
228 typedef struct {
229 	u_int8_t enable;
230 } target_mode_params_t;
231 
232 typedef struct {
233 	u_int8_t offset : 4,
234 		 period : 3,
235 		 sync	: 1;
236 } targ_syncinfo_t;
237 
238 typedef enum {
239 	HAB_ISA		= 'A',
240 	HAB_MCA		= 'B',
241 	HAB_EISA	= 'C',
242 	HAB_NUBUS	= 'D',
243 	HAB_VESA	= 'E',
244 	HAB_PCI		= 'F'
245 } ha_type_t;
246 
247 typedef struct {
248 	u_int8_t	initiate_sync	: 1,
249 		 	parity_enable	: 1,
250 					: 6;
251 
252 	u_int8_t	bus_transfer_rate;
253 	u_int8_t	time_on_bus;
254 	u_int8_t	time_off_bus;
255 	u_int8_t	num_mboxes;
256 	u_int8_t	mbox_base_addr[3];
257 	targ_syncinfo_t	low_syncinfo[8];	/* For fast and ultra, use 8C */
258 	u_int8_t	low_discinfo;
259 	u_int8_t	customer_sig;
260 	u_int8_t	letter_d;
261 	u_int8_t	ha_type;
262 	u_int8_t	low_wide_allowed;
263 	u_int8_t	low_wide_active;
264 	targ_syncinfo_t	high_syncinfo[8];
265 	u_int8_t	high_discinfo;
266 	u_int8_t	high_wide_allowed;
267 	u_int8_t	high_wide_active;
268 } setup_data_t;
269 
270 typedef struct {
271 	u_int8_t phys_addr[3];
272 } write_adapter_lram_params_t;
273 
274 typedef struct {
275 	u_int8_t phys_addr[3];
276 } read_adapter_lram_params_t;
277 
278 typedef struct {
279 	u_int8_t phys_addr[3];
280 } write_chip_fifo_params_t;
281 
282 typedef struct {
283 	u_int8_t phys_addr[3];
284 } read_chip_fifo_params_t;
285 
286 typedef struct {
287 	u_int8_t length;		/* Excludes this member */
288 	u_int8_t low_disc_disable;
289 	u_int8_t low_busy_retry_disable;
290 	u_int8_t high_disc_disable;
291 	u_int8_t high_busy_retry_disable;
292 } set_adapter_options_params_t;
293 
294 typedef struct {
295 	u_int8_t targets[8];
296 } installed_hdevs_data_t;
297 
298 typedef struct {
299 	u_int8_t low_devs;
300 	u_int8_t high_devs;
301 } target_devs_data_t;
302 
303 typedef struct {
304 	u_int8_t enable;
305 } enable_hac_interrupt_params_t;
306 
307 typedef struct {
308 	u_int8_t num_boxes;
309 	u_int8_t base_addr[4];
310 } init_32b_mbox_params_t;
311 
312 typedef u_int8_t fw_ver_3dig_data_t;
313 
314 typedef u_int8_t fw_ver_4dig_data_t;
315 
316 typedef struct  {
317 	u_int8_t offset;
318 	u_int8_t response_len;
319 } fetch_lram_params_t;
320 
321 #define AUTO_SCSI_BYTE_OFFSET	64
322 typedef struct {
323 	u_int8_t	factory_sig[2];
324 	u_int8_t	auto_scsi_data_size;	/* 2 -> 64 bytes */
325 	u_int8_t	model_num[6];
326 	u_int8_t	adapter_ioport;
327 	u_int8_t	floppy_enabled	 :1,
328 			floppy_secondary :1,
329 			level_trigger	 :1,
330 					 :2,
331 			system_ram_area	 :3;
332 	u_int8_t	dma_channel	 :7,
333 			dma_autoconf	 :1;
334 	u_int8_t	irq_channel	 :7,
335 			irq_autoconf	 :1;
336 	u_int8_t	dma_trans_rate;
337 	u_int8_t	scsi_id;
338 	u_int8_t	low_termination	 :1,
339 			scsi_parity	 :1,
340 			high_termination :1,
341 			req_ack_filter	 :1,
342 			fast_sync	 :1,
343 			bus_reset	 :1,
344 					 :1,
345 			active_negation	 :1;
346 	u_int8_t	bus_on_delay;
347 	u_int8_t	bus_off_delay;
348 	u_int8_t	bios_enabled	 :1,
349 			int19h_redirect	 :1,
350 			extended_trans	 :1,
351 			removable_drives :1,
352 					 :1,
353 			morethan2disks	 :1,
354 			interrupt_mode	 :1,
355 			floptical_support:1;
356 	u_int8_t	low_device_enabled;
357 	u_int8_t	high_device_enabled;
358 	u_int8_t	low_wide_permitted;
359 	u_int8_t	high_wide_permitted;
360 	u_int8_t	low_fast_permitted;
361 	u_int8_t	high_fast_permitted;
362 	u_int8_t	low_sync_permitted;
363 	u_int8_t	high_sync_permitted;
364 	u_int8_t	low_disc_permitted;
365 	u_int8_t	high_disc_permitted;
366 	u_int8_t	low_send_start_unit;
367 	u_int8_t	high_send_start_unit;
368 	u_int8_t	low_ignore_in_bios_scan;
369 	u_int8_t	high_ignore_in_bios_scan;
370 	u_int8_t	pci_int_pin	 :2,
371 			host_ioport	 :2,
372 			round_robin	 :1,
373 			vesa_bus_over_33 :1,
374 			vesa_burst_write :1,
375 			vesa_burst_read	 :1;
376 	u_int8_t	low_ultra_permitted;
377 	u_int8_t	high_ultra_permitted;
378 	u_int8_t	reserved[5];
379 	u_int8_t	auto_scsi_max_lun;
380 	u_int8_t			 :1,
381 			scam_dominant	 :1,
382 			scam_enabled	 :1,
383 			scam_level2	 :1,
384 					 :4;
385 	u_int8_t	int13_extensions :1,
386 					 :1,
387 			cdrom_boot	 :1,
388 					 :2,
389 			multi_boot	 :1,
390 					 :2;
391 	u_int8_t	boot_target_id	 :4,
392 			boot_channel	 :4;
393 	u_int8_t	force_dev_scan	 :1,
394 					 :7;
395 	u_int8_t	low_tagged_lun_independance;
396 	u_int8_t	high_tagged_lun_independance;
397 	u_int8_t	low_renegotiate_after_cc;
398 	u_int8_t	high_renegotiate_after_cc;
399 	u_int8_t	reserverd2[10];
400 	u_int8_t	manufacturing_diagnotic[2];
401 	u_int8_t	checksum[2];
402 } auto_scsi_data_t;
403 
404 typedef struct {
405 	u_int8_t io_port;
406 	u_int8_t irq_num;
407 	u_int8_t low_byte_term	:1,
408 		 high_byte_term	:1,
409 		 		:2,
410 		 jp1_status	:1,
411 		 jp2_status	:1,
412 		 jp3_status	:1,
413 		 		:1;
414 	u_int8_t reserved;
415 } pci_info_data_t;
416 
417 typedef struct {
418 	u_int8_t ascii_model[5];	/* Fifth byte is always 0 */
419 } ha_model_data_t;
420 
421 typedef struct {
422 	u_int8_t sync_rate[16];		/* Sync in 10ns units */
423 } target_sync_info_data_t;
424 
425 typedef struct {
426 	u_int8_t  bus_type;
427 	u_int8_t  bios_addr;
428 	u_int16_t max_sg;
429 	u_int8_t  num_mboxes;
430 	u_int8_t  mbox_base[4];
431 	u_int8_t			:2,
432 		  sync_neg10MB		:1,
433 		  floppy_disable	:1,
434 		  floppy_secondary_port	:1,
435 		  burst_mode_enabled	:1,
436 		  level_trigger_ints	:1,
437 					:1;
438 	u_int8_t  fw_ver_bytes_2_to_4[3];
439 	u_int8_t  wide_bus		:1,
440 		  diff_bus		:1,
441 		  scam_capable		:1,
442 		  ultra_scsi		:1,
443 		  auto_term		:1,
444 		 			:3;
445 } esetup_info_data_t;
446 
447 typedef struct {
448 	u_int32_t len;
449 	u_int32_t addr;
450 } bt_sg_t;
451 
452 /********************** Mail Box definitions *******************************/
453 
454 typedef enum {
455 	BMBO_FREE		= 0x0,	/* MBO intry is free */
456 	BMBO_START		= 0x1,	/* MBO activate entry */
457 	BMBO_ABORT		= 0x2	/* MBO abort entry */
458 } bt_mbo_action_code_t;
459 
460 typedef struct bt_mbox_out {
461 	u_int32_t ccb_addr;
462 	u_int8_t  reserved[3];
463 	u_int8_t  action_code;
464 } bt_mbox_out_t;
465 
466 typedef enum {
467 	BMBI_FREE		= 0x0,	/* MBI entry is free */
468 	BMBI_OK			= 0x1,	/* completed without error */
469 	BMBI_ABORT		= 0x2,	/* aborted ccb */
470 	BMBI_NOT_FOUND		= 0x3,	/* Tried to abort invalid CCB */
471 	BMBI_ERROR		= 0x4	/* Completed with error */
472 } bt_mbi_comp_code_t;
473 
474 typedef struct bt_mbox_in {
475 	u_int32_t ccb_addr;
476 	u_int8_t  btstat;
477 	u_int8_t  sdstat;
478 	u_int8_t  reserved;
479 	u_int8_t  comp_code;
480 } bt_mbox_in_t;
481 
482 /***************** Compiled Probe Information *******************************/
483 struct bt_probe_info {
484 	int	drq;
485 	int	irq;
486 };
487 
488 /****************** Hardware CCB definition *********************************/
489 typedef enum {
490 	INITIATOR_CCB		= 0x00,
491 	INITIATOR_SG_CCB	= 0x02,
492 	INITIATOR_CCB_WRESID	= 0x03,
493 	INITIATOR_SG_CCB_WRESID	= 0x04,
494 	INITIATOR_BUS_DEV_RESET = 0x81
495 } bt_ccb_opcode_t;
496 
497 typedef enum {
498 	BTSTAT_NOERROR			= 0x00,
499 	BTSTAT_LINKED_CMD_COMPLETE	= 0x0A,
500 	BTSTAT_LINKED_CMD_FLAG_COMPLETE	= 0x0B,
501 	BTSTAT_DATAUNDERUN_ERROR	= 0x0C,
502 	BTSTAT_SELTIMEOUT		= 0x11,
503 	BTSTAT_DATARUN_ERROR		= 0x12,
504 	BTSTAT_UNEXPECTED_BUSFREE	= 0x13,
505 	BTSTAT_INVALID_PHASE		= 0x14,
506 	BTSTAT_INVALID_ACTION_CODE	= 0x15,
507 	BTSTAT_INVALID_OPCODE		= 0x16,
508 	BTSTAT_LINKED_CCB_LUN_MISMATCH	= 0x17,
509 	BTSTAT_INVALID_CCB_OR_SG_PARAM	= 0x1A,
510 	BTSTAT_AUTOSENSE_FAILED		= 0x1B,
511 	BTSTAT_TAGGED_MSG_REJECTED	= 0x1C,
512 	BTSTAT_UNSUPPORTED_MSG_RECEIVED	= 0x1D,
513 	BTSTAT_HARDWARE_FAILURE		= 0x20,
514 	BTSTAT_TARGET_IGNORED_ATN	= 0x21,
515 	BTSTAT_HA_SCSI_BUS_RESET	= 0x22,
516 	BTSTAT_OTHER_SCSI_BUS_RESET	= 0x23,
517 	BTSTAT_INVALID_RECONNECT	= 0x24,
518 	BTSTAT_HA_BDR			= 0x25,
519 	BTSTAT_ABORT_QUEUE_GENERATED	= 0x26,
520 	BTSTAT_HA_SOFTWARE_ERROR	= 0x27,
521 	BTSTAT_HA_WATCHDOG_ERROR	= 0x28,
522 	BTSTAT_SCSI_PERROR_DETECTED	= 0x30
523 } btstat_t;
524 
525 struct bt_hccb {
526 	u_int8_t  opcode;
527 	u_int8_t			:3,
528 		  datain		:1,
529 		  dataout		:1,
530 		  wide_tag_enable	:1,	/* Wide Lun CCB format */
531 		  wide_tag_type		:2;	/* Wide Lun CCB format */
532 	u_int8_t  cmd_len;
533 	u_int8_t  sense_len;
534 	int32_t	  data_len;			/* residuals can be negative */
535 	u_int32_t data_addr;
536 	u_int8_t  reserved[2];
537 	u_int8_t  btstat;
538 	u_int8_t  sdstat;
539 	u_int8_t  target_id;
540 	u_int8_t  target_lun	:5,
541 		  tag_enable	:1,
542 		  tag_type	:2;
543 	u_int8_t  scsi_cdb[12];
544 	u_int8_t  reserved2[6];
545 	u_int32_t sense_addr;
546 };
547 
548 typedef enum {
549 	BCCB_FREE		= 0x0,
550 	BCCB_ACTIVE		= 0x1,
551 	BCCB_DEVICE_RESET	= 0x2,
552 	BCCB_RELEASE_SIMQ	= 0x4
553 } bccb_flags_t;
554 
555 struct bt_ccb {
556 	struct	bt_hccb		 hccb;
557 	SLIST_ENTRY(bt_ccb)	 links;
558 	u_int32_t		 flags;
559 	union ccb		*ccb;
560 	bus_dmamap_t		 dmamap;
561 	struct callout		 timer;
562 	bt_sg_t			*sg_list;
563 	u_int32_t		 sg_list_phys;
564 };
565 
566 struct sg_map_node {
567 	bus_dmamap_t		 sg_dmamap;
568 	bus_addr_t		 sg_physaddr;
569 	bt_sg_t*		 sg_vaddr;
570 	SLIST_ENTRY(sg_map_node) links;
571 };
572 
573 struct bt_softc {
574 	device_t		dev;
575 	struct resource		*port;
576 	struct resource		*irq;
577 	struct resource		*drq;
578 	void			*ih;
579 	struct lock		 lock;
580 	struct	cam_sim		*sim;
581 	struct	cam_path	*path;
582 	bt_mbox_out_t		*cur_outbox;
583 	bt_mbox_in_t		*cur_inbox;
584 	bt_mbox_out_t		*last_outbox;
585 	bt_mbox_in_t		*last_inbox;
586 	struct	bt_ccb		*bt_ccb_array;
587 	SLIST_HEAD(,bt_ccb)	 free_bt_ccbs;
588 	LIST_HEAD(,ccb_hdr)	 pending_ccbs;
589 	u_int			 active_ccbs;
590 	u_int32_t		 bt_ccb_physbase;
591 	bt_mbox_in_t		*in_boxes;
592 	bt_mbox_out_t		*out_boxes;
593 	struct scsi_sense_data	*sense_buffers;
594 	u_int32_t		 sense_buffers_physbase;
595 	struct	bt_ccb		*recovery_bccb;
596 	u_int			 num_boxes;
597 	bus_dma_tag_t		 parent_dmat;	/*
598 						 * All dmat's derive from
599 						 * the dmat defined by our
600 						 * bus.
601 						 */
602 	bus_dma_tag_t		 buffer_dmat;	/* dmat for buffer I/O */
603 	bus_dma_tag_t		 mailbox_dmat;	/* dmat for our mailboxes */
604 	bus_dmamap_t		 mailbox_dmamap;
605 	bus_dma_tag_t		 ccb_dmat;	/* dmat for our ccb array */
606 	bus_dmamap_t		 ccb_dmamap;
607 	bus_dma_tag_t		 sg_dmat;	/* dmat for our sg segments */
608 	bus_dma_tag_t		 sense_dmat;	/* dmat for our sense buffers */
609 	bus_dmamap_t		 sense_dmamap;
610 	SLIST_HEAD(, sg_map_node) sg_maps;
611 	bus_addr_t		 mailbox_physbase;
612 	u_int			 num_ccbs;	/* Number of CCBs malloc'd */
613 	u_int			 max_ccbs;	/* Maximum allocatable CCBs */
614 	u_int			 max_sg;
615 	u_int			 scsi_id;
616 	u_int32_t		 extended_trans	   :1,
617 				 wide_bus	   :1,
618 				 diff_bus	   :1,
619 				 ultra_scsi	   :1,
620 				 extended_lun	   :1,
621 				 strict_rr	   :1,
622 				 tag_capable	   :1,
623 				 wide_lun_ccb	   :1,
624 				 resource_shortage :1,
625 				 level_trigger_ints:1,
626 						   :22;
627 	u_int16_t		 tags_permitted;
628 	u_int16_t		 disc_permitted;
629 	u_int16_t		 sync_permitted;
630 	u_int16_t		 fast_permitted;
631 	u_int16_t		 ultra_permitted;
632 	u_int16_t		 wide_permitted;
633 	u_int8_t		 init_level;
634 	volatile u_int8_t	 command_cmp;
635 	volatile u_int8_t	 latched_status;
636 	u_int32_t		 bios_addr;
637 	char			 firmware_ver[6];
638 	char			 model[5];
639 };
640 
641 #define BT_TEMP_UNIT 0xFF		/* Unit for probes */
642 void			bt_init_softc(device_t dev,
643 				      struct resource *port,
644 				      struct resource *irq,
645 				      struct resource *drq);
646 void			bt_free_softc(device_t dev);
647 int			bt_probe(device_t dev);
648 int			bt_fetch_adapter_info(device_t dev);
649 int			bt_init(device_t dev);
650 int			bt_attach(device_t dev);
651 void			bt_intr(void *arg);
652 
653 #define DEFAULT_CMD_TIMEOUT 100000	/* 10 sec */
654 int			bt_cmd(struct bt_softc *bt, bt_op_t opcode,
655 			       u_int8_t *params, u_int param_len,
656 			       u_int8_t *reply_data, u_int reply_len,
657 			       u_int cmd_timeout);
658 
659 #define bt_name(bt)	device_get_nameunit(bt->dev)
660 
661 #define bt_inb(bt, reg)				\
662 	bus_read_1((bt)->port, reg)
663 
664 #define bt_outb(bt, reg, value)			\
665 	bus_write_1((bt)->port, reg, value)
666 
667 #endif	/* _BT_H_ */
668