1 /* $NetBSD: tegra124_car.c,v 1.24 2022/03/19 11:37:17 riastradh Exp $ */
2
3 /*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: tegra124_car.c,v 1.24 2022/03/19 11:37:17 riastradh Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/device.h>
35 #include <sys/intr.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/rndsource.h>
39 #include <sys/atomic.h>
40 #include <sys/kmem.h>
41
42 #include <dev/clk/clk_backend.h>
43
44 #include <arm/nvidia/tegra_reg.h>
45 #include <arm/nvidia/tegra124_carreg.h>
46 #include <arm/nvidia/tegra_clock.h>
47 #include <arm/nvidia/tegra_pmcreg.h>
48 #include <arm/nvidia/tegra_var.h>
49
50 #include <dev/fdt/fdtvar.h>
51
52 static int tegra124_car_match(device_t, cfdata_t, void *);
53 static void tegra124_car_attach(device_t, device_t, void *);
54
55 static struct clk *tegra124_car_clock_decode(device_t, int, const void *,
56 size_t);
57
58 static const struct fdtbus_clock_controller_func tegra124_car_fdtclock_funcs = {
59 .decode = tegra124_car_clock_decode
60 };
61
62 /* DT clock ID to clock name mappings */
63 static struct tegra124_car_clock_id {
64 u_int id;
65 const char *name;
66 } tegra124_car_clock_ids[] = {
67 { 3, "ispb" },
68 { 4, "rtc" },
69 { 5, "timer" },
70 { 6, "uarta" },
71 { 9, "sdmmc2" },
72 { 11, "i2s1" },
73 { 12, "i2c1" },
74 { 14, "sdmmc1" },
75 { 15, "sdmmc4" },
76 { 17, "pwm" },
77 { 18, "i2s2" },
78 { 22, "usbd" },
79 { 23, "isp" },
80 { 26, "disp2" },
81 { 27, "disp1" },
82 { 28, "host1x" },
83 { 29, "vcp" },
84 { 30, "i2s0" },
85 { 32, "mc" },
86 { 34, "apbdma" },
87 { 36, "kbc" },
88 { 40, "kfuse" },
89 { 41, "spi1" },
90 { 42, "nor" },
91 { 44, "spi2" },
92 { 46, "spi3" },
93 { 47, "i2c5" },
94 { 48, "dsia" },
95 { 50, "mipi" },
96 { 51, "hdmi" },
97 { 52, "csi" },
98 { 54, "i2c2" },
99 { 55, "uartc" },
100 { 56, "mipi_cal" },
101 { 57, "emc" },
102 { 58, "usb2" },
103 { 59, "usb3" },
104 { 61, "vde" },
105 { 62, "bsea" },
106 { 63, "bsev" },
107 { 65, "uartd" },
108 { 67, "i2c3" },
109 { 68, "spi4" },
110 { 69, "sdmmc3" },
111 { 70, "pcie" },
112 { 71, "owr" },
113 { 72, "afi" },
114 { 73, "csite" },
115 { 76, "la" },
116 { 77, "trace" },
117 { 78, "soc_therm" },
118 { 79, "dtv" },
119 { 81, "i2cslow" },
120 { 82, "dsib" },
121 { 83, "tsec" },
122 { 89, "xusb_host" },
123 { 91, "msenc" },
124 { 92, "csus" },
125 { 99, "mselect" },
126 { 100, "tsensor" },
127 { 101, "i2s3" },
128 { 102, "i2s4" },
129 { 103, "i2c4" },
130 { 104, "spi5" },
131 { 105, "spi6" },
132 { 106, "d_audio" },
133 { 107, "apbif" },
134 { 108, "dam0" },
135 { 109, "dam1" },
136 { 110, "dam2" },
137 { 111, "hda2codec_2x" },
138 { 113, "audio0_2x" },
139 { 114, "audio1_2x" },
140 { 115, "audio2_2x" },
141 { 116, "audio3_2x" },
142 { 117, "audio4_2x" },
143 { 118, "spdif_2x" },
144 { 119, "actmon" },
145 { 120, "extern1" },
146 { 121, "extern2" },
147 { 122, "extern3" },
148 { 123, "sata_oob" },
149 { 124, "sata" },
150 { 125, "hda" },
151 { 127, "se" },
152 { 128, "hda2hdmi" },
153 { 129, "sata_cold" },
154 { 136, "cec" },
155 { 144, "cilab" },
156 { 145, "cilcd" },
157 { 146, "cile" },
158 { 147, "dsialp" },
159 { 148, "dsiblp" },
160 { 149, "entropy" },
161 { 150, "dds" },
162 { 152, "dp2" },
163 { 153, "amx" },
164 { 154, "adx" },
165 { 156, "xusb_ss" },
166 { 166, "i2c6" },
167 { 171, "vim2_clk" },
168 { 176, "hdmi_audio" },
169 { 177, "clk72mhz" },
170 { 178, "vic03" },
171 { 180, "adx1" },
172 { 181, "dpaux" },
173 { 182, "sor0" },
174 { 184, "gpu" },
175 { 185, "amx1" },
176 { 192, "uartb" },
177 { 193, "vfir" },
178 { 194, "spdif_in" },
179 { 195, "spdif_out" },
180 { 196, "vi" },
181 { 197, "vi_sensor" },
182 { 198, "fuse" },
183 { 199, "fuse_burn" },
184 { 200, "clk_32k" },
185 { 201, "clk_m" },
186 { 202, "clk_m_div2" },
187 { 203, "clk_m_div4" },
188 { 204, "pll_ref" },
189 { 205, "pll_c" },
190 { 206, "pll_c_out1" },
191 { 207, "pll_c2" },
192 { 208, "pll_c3" },
193 { 209, "pll_m" },
194 { 210, "pll_m_out1" },
195 { 211, "pll_p_out0" },
196 { 212, "pll_p_out1" },
197 { 213, "pll_p_out2" },
198 { 214, "pll_p_out3" },
199 { 215, "pll_p_out4" },
200 { 216, "pll_a" },
201 { 217, "pll_a_out0" },
202 { 218, "pll_d" },
203 { 219, "pll_d_out0" },
204 { 220, "pll_d2" },
205 { 221, "pll_d2_out0" },
206 { 222, "pll_u" },
207 { 223, "pll_u_480m" },
208 { 224, "pll_u_60m" },
209 { 225, "pll_u_48m" },
210 { 226, "pll_u_12m" },
211 { 229, "pll_re_vco" },
212 { 230, "pll_re_out" },
213 { 231, "pll_e" },
214 { 232, "spdif_in_sync" },
215 { 233, "i2s0_sync" },
216 { 234, "i2s1_sync" },
217 { 235, "i2s2_sync" },
218 { 236, "i2s3_sync" },
219 { 237, "i2s4_sync" },
220 { 238, "vimclk_sync" },
221 { 239, "audio0" },
222 { 240, "audio1" },
223 { 241, "audio2" },
224 { 242, "audio3" },
225 { 243, "audio4" },
226 { 244, "spdif" },
227 { 245, "clk_out_1" },
228 { 246, "clk_out_2" },
229 { 247, "clk_out_3" },
230 { 248, "blink" },
231 { 252, "xusb_host_src" },
232 { 253, "xusb_falcon_src" },
233 { 254, "xusb_fs_src" },
234 { 255, "xusb_ss_src" },
235 { 256, "xusb_dev_src" },
236 { 257, "xusb_dev" },
237 { 258, "xusb_hs_src" },
238 { 259, "sclk" },
239 { 260, "hclk" },
240 { 261, "pclk" },
241 { 264, "dfll_ref" },
242 { 265, "dfll_soc" },
243 { 266, "vi_sensor2" },
244 { 267, "pll_p_out5" },
245 { 268, "cml0" },
246 { 269, "cml1" },
247 { 270, "pll_c4" },
248 { 271, "pll_dp" },
249 { 272, "pll_e_mux" },
250 { 273, "pll_d_dsi_out" },
251 { 300, "audio0_mux" },
252 { 301, "audio1_mux" },
253 { 302, "audio2_mux" },
254 { 303, "audio3_mux" },
255 { 304, "audio4_mux" },
256 { 305, "spdif_mux" },
257 { 306, "clk_out_1_mux" },
258 { 307, "clk_out_2_mux" },
259 { 308, "clk_out_3_mux" },
260 { 311, "sor0_lvds" },
261 { 312, "xusb_ss_div2" },
262 { 313, "pll_m_ud" },
263 { 314, "pll_c_ud" },
264 { 227, "pll_x" },
265 { 228, "pll_x_out0" },
266 { 262, "cclk_g" },
267 { 263, "cclk_lp" },
268 { 315, "clk_max" },
269 };
270
271 static struct clk *tegra124_car_clock_get(void *, const char *);
272 static void tegra124_car_clock_put(void *, struct clk *);
273 static u_int tegra124_car_clock_get_rate(void *, struct clk *);
274 static int tegra124_car_clock_set_rate(void *, struct clk *, u_int);
275 static int tegra124_car_clock_enable(void *, struct clk *);
276 static int tegra124_car_clock_disable(void *, struct clk *);
277 static int tegra124_car_clock_set_parent(void *, struct clk *,
278 struct clk *);
279 static struct clk *tegra124_car_clock_get_parent(void *, struct clk *);
280
281 static const struct clk_funcs tegra124_car_clock_funcs = {
282 .get = tegra124_car_clock_get,
283 .put = tegra124_car_clock_put,
284 .get_rate = tegra124_car_clock_get_rate,
285 .set_rate = tegra124_car_clock_set_rate,
286 .enable = tegra124_car_clock_enable,
287 .disable = tegra124_car_clock_disable,
288 .set_parent = tegra124_car_clock_set_parent,
289 .get_parent = tegra124_car_clock_get_parent,
290 };
291
292 #define CLK_FIXED(_name, _rate) { \
293 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED, \
294 .u = { .fixed = { .rate = (_rate) } } \
295 }
296
297 #define CLK_PLL(_name, _parent, _base, _divm, _divn, _divp) { \
298 .base = { .name = (_name) }, .type = TEGRA_CLK_PLL, \
299 .parent = (_parent), \
300 .u = { \
301 .pll = { \
302 .base_reg = (_base), \
303 .divm_mask = (_divm), \
304 .divn_mask = (_divn), \
305 .divp_mask = (_divp), \
306 } \
307 } \
308 }
309
310 #define CLK_MUX(_name, _reg, _bits, _p) { \
311 .base = { .name = (_name) }, .type = TEGRA_CLK_MUX, \
312 .u = { \
313 .mux = { \
314 .nparents = __arraycount(_p), \
315 .parents = (_p), \
316 .reg = (_reg), \
317 .bits = (_bits) \
318 } \
319 } \
320 }
321
322 #define CLK_FIXED_DIV(_name, _parent, _div) { \
323 .base = { .name = (_name) }, .type = TEGRA_CLK_FIXED_DIV, \
324 .parent = (_parent), \
325 .u = { \
326 .fixed_div = { \
327 .div = (_div) \
328 } \
329 } \
330 }
331
332 #define CLK_DIV(_name, _parent, _reg, _bits) { \
333 .base = { .name = (_name) }, .type = TEGRA_CLK_DIV, \
334 .parent = (_parent), \
335 .u = { \
336 .div = { \
337 .reg = (_reg), \
338 .bits = (_bits) \
339 } \
340 } \
341 }
342
343 #define CLK_GATE(_name, _parent, _set, _clr, _bits) { \
344 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \
345 .type = TEGRA_CLK_GATE, \
346 .parent = (_parent), \
347 .u = { \
348 .gate = { \
349 .set_reg = (_set), \
350 .clr_reg = (_clr), \
351 .bits = (_bits), \
352 } \
353 } \
354 }
355
356 #define CLK_GATE_L(_name, _parent, _bits) \
357 CLK_GATE(_name, _parent, \
358 CAR_CLK_ENB_L_SET_REG, CAR_CLK_ENB_L_CLR_REG, \
359 _bits)
360
361 #define CLK_GATE_H(_name, _parent, _bits) \
362 CLK_GATE(_name, _parent, \
363 CAR_CLK_ENB_H_SET_REG, CAR_CLK_ENB_H_CLR_REG, \
364 _bits)
365
366 #define CLK_GATE_U(_name, _parent, _bits) \
367 CLK_GATE(_name, _parent, \
368 CAR_CLK_ENB_U_SET_REG, CAR_CLK_ENB_U_CLR_REG, \
369 _bits)
370
371 #define CLK_GATE_V(_name, _parent, _bits) \
372 CLK_GATE(_name, _parent, \
373 CAR_CLK_ENB_V_SET_REG, CAR_CLK_ENB_V_CLR_REG, \
374 _bits)
375
376 #define CLK_GATE_W(_name, _parent, _bits) \
377 CLK_GATE(_name, _parent, \
378 CAR_CLK_ENB_W_SET_REG, CAR_CLK_ENB_W_CLR_REG, \
379 _bits)
380
381 #define CLK_GATE_X(_name, _parent, _bits) \
382 CLK_GATE(_name, _parent, \
383 CAR_CLK_ENB_X_SET_REG, CAR_CLK_ENB_X_CLR_REG, \
384 _bits)
385
386 #define CLK_GATE_SIMPLE(_name, _parent, _reg, _bits) \
387 CLK_GATE(_name, _parent, _reg, _reg, _bits)
388
389 static const char *mux_uart_p[] =
390 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0",
391 "pll_m_out0", NULL, "clk_m" };
392 static const char *mux_sdmmc_p[] =
393 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0",
394 "pll_m_out0", "pll_e_out0", "clk_m" };
395 static const char *mux_i2c_p[] =
396 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0",
397 "pll_m_out0", NULL, "clk_m" };
398 static const char *mux_spi_p[] =
399 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0",
400 "pll_m_out0", NULL, "clk_m" };
401 static const char *mux_sata_p[] =
402 { "pll_p_out0", NULL, "pll_c_out0", NULL, "pll_m_out0", NULL, "clk_m" };
403 static const char *mux_hda_p[] =
404 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0",
405 "pll_m_out0", NULL, "clk_m" };
406 static const char *mux_mselect_p[] =
407 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0",
408 "pll_m_out0", "clk_s", "clk_m" };
409 static const char *mux_tsensor_p[] =
410 { "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0", "clk_m",
411 NULL, "clk_s" };
412 static const char *mux_soc_therm_p[] =
413 { "pll_m_out0", "pll_c_out0", "pll_p_out0", "pll_a_out0", "pll_c2_out0",
414 "pll_c3_out0" };
415 static const char *mux_host1x_p[] =
416 { "pll_m_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0",
417 "pll_p_out0", NULL, "pll_a_out0" };
418 static const char *mux_disp_p[] =
419 { "pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0",
420 "pll_d2_out0", "clk_m" };
421 static const char *mux_hdmi_p[] =
422 { "pll_p_out0", "pll_m_out0", "pll_d_out0", "pll_a_out0", "pll_c_out0",
423 "pll_d2_out0", "clk_m" };
424 static const char *mux_xusb_host_p[] =
425 { "clk_m", "pll_p_out0", "pll_c2_out0", "pll_c_out0", "pll_c3_out0",
426 "pll_re_out" };
427 static const char *mux_xusb_ss_p[] =
428 { "clk_m", "pll_re_out", "clk_s", "pll_u_480",
429 "pll_c_out0", "pll_c2_out0", "pll_c3_out0", NULL };
430 static const char *mux_xusb_fs_p[] =
431 { "clk_m", NULL, "pll_u_48", NULL, "pll_p_out0", NULL, "pll_u_480" };
432
433 static struct tegra_clk tegra124_car_clocks[] = {
434 CLK_FIXED("clk_m", TEGRA124_REF_FREQ),
435
436 CLK_PLL("pll_p", "clk_m", CAR_PLLP_BASE_REG,
437 CAR_PLLP_BASE_DIVM, CAR_PLLP_BASE_DIVN, CAR_PLLP_BASE_DIVP),
438 CLK_PLL("pll_c", "clk_m", CAR_PLLC_BASE_REG,
439 CAR_PLLC_BASE_DIVM, CAR_PLLC_BASE_DIVN, CAR_PLLC_BASE_DIVP),
440 CLK_PLL("pll_u", "clk_m", CAR_PLLU_BASE_REG,
441 CAR_PLLU_BASE_DIVM, CAR_PLLU_BASE_DIVN, CAR_PLLU_BASE_VCO_FREQ),
442 CLK_PLL("pll_x", "clk_m", CAR_PLLX_BASE_REG,
443 CAR_PLLX_BASE_DIVM, CAR_PLLX_BASE_DIVN, CAR_PLLX_BASE_DIVP),
444 CLK_PLL("pll_e", "clk_m", CAR_PLLE_BASE_REG,
445 CAR_PLLE_BASE_DIVM, CAR_PLLE_BASE_DIVN, CAR_PLLE_BASE_DIVP_CML),
446 CLK_PLL("pll_d", "clk_m", CAR_PLLD_BASE_REG,
447 CAR_PLLD_BASE_DIVM, CAR_PLLD_BASE_DIVN, CAR_PLLD_BASE_DIVP),
448 CLK_PLL("pll_d2", "clk_m", CAR_PLLD2_BASE_REG,
449 CAR_PLLD2_BASE_DIVM, CAR_PLLD2_BASE_DIVN, CAR_PLLD2_BASE_DIVP),
450 CLK_PLL("pll_re", "clk_m", CAR_PLLREFE_BASE_REG,
451 CAR_PLLREFE_BASE_DIVM, CAR_PLLREFE_BASE_DIVN, CAR_PLLREFE_BASE_DIVP),
452
453 CLK_FIXED_DIV("pll_p_out0", "pll_p", 1),
454 CLK_FIXED_DIV("pll_u_480", "pll_u", 1),
455 CLK_FIXED_DIV("pll_u_60", "pll_u", 8),
456 CLK_FIXED_DIV("pll_u_48", "pll_u", 10),
457 CLK_FIXED_DIV("pll_u_12", "pll_u", 40),
458 CLK_FIXED_DIV("pll_d_out", "pll_d", 1),
459 CLK_FIXED_DIV("pll_d_out0", "pll_d", 2),
460 CLK_FIXED_DIV("pll_d2_out0", "pll_d2", 1),
461 CLK_FIXED_DIV("pll_re_out", "pll_re", 1),
462
463 CLK_MUX("mux_uarta", CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_SRC,
464 mux_uart_p),
465 CLK_MUX("mux_uartb", CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_SRC,
466 mux_uart_p),
467 CLK_MUX("mux_uartc", CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_SRC,
468 mux_uart_p),
469 CLK_MUX("mux_uartd", CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_SRC,
470 mux_uart_p),
471 CLK_MUX("mux_sdmmc1", CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_SRC,
472 mux_sdmmc_p),
473 CLK_MUX("mux_sdmmc2", CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_SRC,
474 mux_sdmmc_p),
475 CLK_MUX("mux_sdmmc3", CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_SRC,
476 mux_sdmmc_p),
477 CLK_MUX("mux_sdmmc4", CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_SRC,
478 mux_sdmmc_p),
479 CLK_MUX("mux_i2c1", CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p),
480 CLK_MUX("mux_i2c2", CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p),
481 CLK_MUX("mux_i2c3", CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p),
482 CLK_MUX("mux_i2c4", CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p),
483 CLK_MUX("mux_i2c5", CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p),
484 CLK_MUX("mux_i2c6", CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_SRC, mux_i2c_p),
485 CLK_MUX("mux_spi1", CAR_CLKSRC_SPI1_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p),
486 CLK_MUX("mux_spi2", CAR_CLKSRC_SPI2_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p),
487 CLK_MUX("mux_spi3", CAR_CLKSRC_SPI3_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p),
488 CLK_MUX("mux_spi4", CAR_CLKSRC_SPI4_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p),
489 CLK_MUX("mux_spi5", CAR_CLKSRC_SPI5_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p),
490 CLK_MUX("mux_spi6", CAR_CLKSRC_SPI6_REG, CAR_CLKSRC_SPI_SRC, mux_spi_p),
491 CLK_MUX("mux_sata_oob",
492 CAR_CLKSRC_SATA_OOB_REG, CAR_CLKSRC_SATA_OOB_SRC, mux_sata_p),
493 CLK_MUX("mux_sata",
494 CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_SRC, mux_sata_p),
495 CLK_MUX("mux_hda2codec_2x",
496 CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_SRC,
497 mux_hda_p),
498 CLK_MUX("mux_hda",
499 CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_SRC, mux_hda_p),
500 CLK_MUX("mux_soc_therm",
501 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_SRC,
502 mux_soc_therm_p),
503 CLK_MUX("mux_mselect",
504 CAR_CLKSRC_MSELECT_REG, CAR_CLKSRC_MSELECT_SRC,
505 mux_mselect_p),
506 CLK_MUX("mux_tsensor",
507 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_SRC,
508 mux_tsensor_p),
509 CLK_MUX("mux_host1x",
510 CAR_CLKSRC_HOST1X_REG, CAR_CLKSRC_HOST1X_SRC,
511 mux_host1x_p),
512 CLK_MUX("mux_disp1",
513 CAR_CLKSRC_DISP1_REG, CAR_CLKSRC_DISP_SRC,
514 mux_disp_p),
515 CLK_MUX("mux_disp2",
516 CAR_CLKSRC_DISP2_REG, CAR_CLKSRC_DISP_SRC,
517 mux_disp_p),
518 CLK_MUX("mux_hdmi",
519 CAR_CLKSRC_HDMI_REG, CAR_CLKSRC_HDMI_SRC,
520 mux_hdmi_p),
521 CLK_MUX("mux_xusb_host",
522 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_SRC,
523 mux_xusb_host_p),
524 CLK_MUX("mux_xusb_falcon",
525 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_SRC,
526 mux_xusb_host_p),
527 CLK_MUX("mux_xusb_ss",
528 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_SRC,
529 mux_xusb_ss_p),
530 CLK_MUX("mux_xusb_fs",
531 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_SRC,
532 mux_xusb_fs_p),
533
534 CLK_DIV("div_uarta", "mux_uarta",
535 CAR_CLKSRC_UARTA_REG, CAR_CLKSRC_UART_DIV),
536 CLK_DIV("div_uartb", "mux_uartb",
537 CAR_CLKSRC_UARTB_REG, CAR_CLKSRC_UART_DIV),
538 CLK_DIV("div_uartc", "mux_uartc",
539 CAR_CLKSRC_UARTC_REG, CAR_CLKSRC_UART_DIV),
540 CLK_DIV("div_uartd", "mux_uartd",
541 CAR_CLKSRC_UARTD_REG, CAR_CLKSRC_UART_DIV),
542 CLK_DIV("div_sdmmc1", "mux_sdmmc1",
543 CAR_CLKSRC_SDMMC1_REG, CAR_CLKSRC_SDMMC_DIV),
544 CLK_DIV("div_sdmmc2", "mux_sdmmc2",
545 CAR_CLKSRC_SDMMC2_REG, CAR_CLKSRC_SDMMC_DIV),
546 CLK_DIV("div_sdmmc3", "mux_sdmmc3",
547 CAR_CLKSRC_SDMMC3_REG, CAR_CLKSRC_SDMMC_DIV),
548 CLK_DIV("div_sdmmc4", "mux_sdmmc4",
549 CAR_CLKSRC_SDMMC4_REG, CAR_CLKSRC_SDMMC_DIV),
550 CLK_DIV("div_i2c1", "mux_i2c1",
551 CAR_CLKSRC_I2C1_REG, CAR_CLKSRC_I2C_DIV),
552 CLK_DIV("div_i2c2", "mux_i2c2",
553 CAR_CLKSRC_I2C2_REG, CAR_CLKSRC_I2C_DIV),
554 CLK_DIV("div_i2c3", "mux_i2c3",
555 CAR_CLKSRC_I2C3_REG, CAR_CLKSRC_I2C_DIV),
556 CLK_DIV("div_i2c4", "mux_i2c4",
557 CAR_CLKSRC_I2C4_REG, CAR_CLKSRC_I2C_DIV),
558 CLK_DIV("div_i2c5", "mux_i2c5",
559 CAR_CLKSRC_I2C5_REG, CAR_CLKSRC_I2C_DIV),
560 CLK_DIV("div_i2c6", "mux_i2c6",
561 CAR_CLKSRC_I2C6_REG, CAR_CLKSRC_I2C_DIV),
562 CLK_DIV("div_spi1", "mux_spi1",
563 CAR_CLKSRC_SPI1_REG, CAR_CLKSRC_SPI_DIV),
564 CLK_DIV("div_spi2", "mux_spi2",
565 CAR_CLKSRC_SPI2_REG, CAR_CLKSRC_SPI_DIV),
566 CLK_DIV("div_spi3", "mux_spi3",
567 CAR_CLKSRC_SPI3_REG, CAR_CLKSRC_SPI_DIV),
568 CLK_DIV("div_spi4", "mux_spi4",
569 CAR_CLKSRC_SPI4_REG, CAR_CLKSRC_SPI_DIV),
570 CLK_DIV("div_spi5", "mux_spi5",
571 CAR_CLKSRC_SPI5_REG, CAR_CLKSRC_SPI_DIV),
572 CLK_DIV("div_spi6", "mux_spi6",
573 CAR_CLKSRC_SPI6_REG, CAR_CLKSRC_SPI_DIV),
574 CLK_DIV("div_sata_oob", "mux_sata_oob",
575 CAR_CLKSRC_SATA_OOB_REG, CAR_CLKSRC_SATA_OOB_DIV),
576 CLK_DIV("div_sata", "mux_sata",
577 CAR_CLKSRC_SATA_REG, CAR_CLKSRC_SATA_DIV),
578 CLK_DIV("div_hda2codec_2x", "mux_hda2codec_2x",
579 CAR_CLKSRC_HDA2CODEC_2X_REG, CAR_CLKSRC_HDA2CODEC_2X_DIV),
580 CLK_DIV("div_hda", "mux_hda",
581 CAR_CLKSRC_HDA_REG, CAR_CLKSRC_HDA_DIV),
582 CLK_DIV("div_soc_therm", "mux_soc_therm",
583 CAR_CLKSRC_SOC_THERM_REG, CAR_CLKSRC_SOC_THERM_DIV),
584 CLK_DIV("div_mselect", "mux_mselect",
585 CAR_CLKSRC_MSELECT_REG, CAR_CLKSRC_MSELECT_DIV),
586 CLK_DIV("div_tsensor", "mux_tsensor",
587 CAR_CLKSRC_TSENSOR_REG, CAR_CLKSRC_TSENSOR_DIV),
588 CLK_DIV("div_host1x", "mux_host1x",
589 CAR_CLKSRC_HOST1X_REG, CAR_CLKSRC_HOST1X_CLK_DIVISOR),
590 CLK_DIV("div_hdmi", "mux_hdmi",
591 CAR_CLKSRC_HDMI_REG, CAR_CLKSRC_HDMI_DIV),
592 CLK_DIV("div_pll_p_out5", "pll_p",
593 CAR_PLLP_OUTC_REG, CAR_PLLP_OUTC_OUT5_RATIO),
594 CLK_DIV("xusb_host_src", "mux_xusb_host",
595 CAR_CLKSRC_XUSB_HOST_REG, CAR_CLKSRC_XUSB_HOST_DIV),
596 CLK_DIV("xusb_ss_src", "mux_xusb_ss",
597 CAR_CLKSRC_XUSB_SS_REG, CAR_CLKSRC_XUSB_SS_DIV),
598 CLK_DIV("xusb_fs_src", "mux_xusb_fs",
599 CAR_CLKSRC_XUSB_FS_REG, CAR_CLKSRC_XUSB_FS_DIV),
600 CLK_DIV("xusb_falcon_src", "mux_xusb_falcon",
601 CAR_CLKSRC_XUSB_FALCON_REG, CAR_CLKSRC_XUSB_FALCON_DIV),
602
603 CLK_GATE_L("uarta", "div_uarta", CAR_DEV_L_UARTA),
604 CLK_GATE_L("uartb", "div_uartb", CAR_DEV_L_UARTB),
605 CLK_GATE_H("uartc", "div_uartc", CAR_DEV_H_UARTC),
606 CLK_GATE_U("uartd", "div_uartd", CAR_DEV_U_UARTD),
607 CLK_GATE_L("sdmmc1", "div_sdmmc1", CAR_DEV_L_SDMMC1),
608 CLK_GATE_L("sdmmc2", "div_sdmmc2", CAR_DEV_L_SDMMC2),
609 CLK_GATE_U("sdmmc3", "div_sdmmc3", CAR_DEV_U_SDMMC3),
610 CLK_GATE_L("sdmmc4", "div_sdmmc4", CAR_DEV_L_SDMMC4),
611 CLK_GATE_L("i2c1", "div_i2c1", CAR_DEV_L_I2C1),
612 CLK_GATE_H("i2c2", "div_i2c2", CAR_DEV_H_I2C2),
613 CLK_GATE_U("i2c3", "div_i2c3", CAR_DEV_U_I2C3),
614 CLK_GATE_V("i2c4", "div_i2c4", CAR_DEV_V_I2C4),
615 CLK_GATE_H("i2c5", "div_i2c5", CAR_DEV_H_I2C5),
616 CLK_GATE_X("i2c6", "div_i2c6", CAR_DEV_X_I2C6),
617 CLK_GATE_H("spi1", "div_spi1", CAR_DEV_H_SPI1),
618 CLK_GATE_H("spi2", "div_spi2", CAR_DEV_H_SPI2),
619 CLK_GATE_H("spi3", "div_spi3", CAR_DEV_H_SPI3),
620 CLK_GATE_U("spi4", "div_spi4", CAR_DEV_U_SPI4),
621 CLK_GATE_V("spi5", "div_spi5", CAR_DEV_V_SPI5),
622 CLK_GATE_V("spi6", "div_spi6", CAR_DEV_V_SPI6),
623 CLK_GATE_L("usbd", "pll_u_480", CAR_DEV_L_USBD),
624 CLK_GATE_H("usb2", "pll_u_480", CAR_DEV_H_USB2),
625 CLK_GATE_H("usb3", "pll_u_480", CAR_DEV_H_USB3),
626 CLK_GATE_V("sata_oob", "div_sata_oob", CAR_DEV_V_SATA_OOB),
627 CLK_GATE_V("sata", "div_sata", CAR_DEV_V_SATA),
628 CLK_GATE_SIMPLE("cml0", "pll_e",
629 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML0_OEN),
630 CLK_GATE_SIMPLE("cml1", "pll_e",
631 CAR_PLLE_AUX_REG, CAR_PLLE_AUX_CML1_OEN),
632 CLK_GATE_V("hda2codec_2x", "div_hda2codec_2x", CAR_DEV_V_HDA2CODEC_2X),
633 CLK_GATE_V("hda", "div_hda", CAR_DEV_V_HDA),
634 CLK_GATE_W("hda2hdmi", "clk_m", CAR_DEV_W_HDA2HDMICODEC),
635 CLK_GATE_W("cec", "clk_m", CAR_DEV_W_CEC),
636 CLK_GATE_H("fuse", "clk_m", CAR_DEV_H_FUSE),
637 CLK_GATE_U("soc_therm", "div_soc_therm", CAR_DEV_U_SOC_THERM),
638 CLK_GATE_V("mselect", "div_mselect", CAR_DEV_V_MSELECT),
639 CLK_GATE_V("tsensor", "div_tsensor", CAR_DEV_V_TSENSOR),
640 CLK_GATE_L("host1x", "div_host1x", CAR_DEV_L_HOST1X),
641 CLK_GATE_L("disp1", "mux_disp1", CAR_DEV_L_DISP1),
642 CLK_GATE_L("disp2", "mux_disp2", CAR_DEV_L_DISP2),
643 CLK_GATE_H("hdmi", "div_hdmi", CAR_DEV_H_HDMI),
644 CLK_GATE_SIMPLE("pll_p_out5", "div_pll_p_out5",
645 CAR_PLLP_OUTC_REG, CAR_PLLP_OUTC_OUT5_CLKEN),
646 CLK_GATE_U("xusb_host", "xusb_host_src", CAR_DEV_U_XUSB_HOST),
647 CLK_GATE_W("xusb_ss", "xusb_ss_src", CAR_DEV_W_XUSB_SS),
648 CLK_GATE_X("gpu", "pll_ref", CAR_DEV_X_GPU),
649 CLK_GATE_H("apbdma", "clk_m", CAR_DEV_H_APBDMA),
650 CLK_GATE_U("pcie", "mselect", CAR_DEV_U_PCIE),
651 CLK_GATE_U("afi", "mselect", CAR_DEV_U_AFI),
652 };
653
654 struct tegra124_init_parent {
655 const char *clock;
656 const char *parent;
657 } tegra124_init_parents[] = {
658 { "sata_oob", "pll_p_out0" },
659 { "sata", "pll_p_out0" },
660 { "hda", "pll_p_out0" },
661 { "hda2codec_2x", "pll_p_out0" },
662 { "soc_therm", "pll_p_out0" },
663 { "tsensor", "clk_m" },
664 { "xusb_host_src", "pll_p_out0" },
665 { "xusb_falcon_src", "pll_p_out0" },
666 { "xusb_ss_src", "pll_u_480" },
667 { "xusb_fs_src", "pll_u_48" },
668 { "host1x", "pll_p_out0" },
669 };
670
671 struct tegra124_car_rst {
672 u_int set_reg;
673 u_int clr_reg;
674 u_int mask;
675 };
676
677 static struct tegra124_car_reset_reg {
678 u_int set_reg;
679 u_int clr_reg;
680 } tegra124_car_reset_regs[] = {
681 { CAR_RST_DEV_L_SET_REG, CAR_RST_DEV_L_CLR_REG },
682 { CAR_RST_DEV_H_SET_REG, CAR_RST_DEV_H_CLR_REG },
683 { CAR_RST_DEV_U_SET_REG, CAR_RST_DEV_U_CLR_REG },
684 { CAR_RST_DEV_V_SET_REG, CAR_RST_DEV_V_CLR_REG },
685 { CAR_RST_DEV_W_SET_REG, CAR_RST_DEV_W_CLR_REG },
686 { CAR_RST_DEV_X_SET_REG, CAR_RST_DEV_X_CLR_REG },
687 };
688
689 static void * tegra124_car_reset_acquire(device_t, const void *, size_t);
690 static void tegra124_car_reset_release(device_t, void *);
691 static int tegra124_car_reset_assert(device_t, void *);
692 static int tegra124_car_reset_deassert(device_t, void *);
693
694 static const struct fdtbus_reset_controller_func tegra124_car_fdtreset_funcs = {
695 .acquire = tegra124_car_reset_acquire,
696 .release = tegra124_car_reset_release,
697 .reset_assert = tegra124_car_reset_assert,
698 .reset_deassert = tegra124_car_reset_deassert,
699 };
700
701 struct tegra124_car_softc {
702 device_t sc_dev;
703 bus_space_tag_t sc_bst;
704 bus_space_handle_t sc_bsh;
705
706 struct clk_domain sc_clkdom;
707
708 u_int sc_clock_cells;
709 u_int sc_reset_cells;
710
711 krndsource_t sc_rndsource;
712 };
713
714 static void tegra124_car_init(struct tegra124_car_softc *);
715 static void tegra124_car_utmip_init(struct tegra124_car_softc *);
716 static void tegra124_car_xusb_init(struct tegra124_car_softc *);
717 static void tegra124_car_watchdog_init(struct tegra124_car_softc *);
718 static void tegra124_car_parent_init(struct tegra124_car_softc *);
719
720 static void tegra124_car_rnd_attach(device_t);
721 static void tegra124_car_rnd_callback(size_t, void *);
722
723 CFATTACH_DECL_NEW(tegra124_car, sizeof(struct tegra124_car_softc),
724 tegra124_car_match, tegra124_car_attach, NULL, NULL);
725
726 static const struct device_compatible_entry compat_data[] = {
727 { .compat = "nvidia,tegra124-car" },
728 DEVICE_COMPAT_EOL
729 };
730
731 static int
tegra124_car_match(device_t parent,cfdata_t cf,void * aux)732 tegra124_car_match(device_t parent, cfdata_t cf, void *aux)
733 {
734 struct fdt_attach_args * const faa = aux;
735
736 #if 0
737 return of_compatible_match(faa->faa_phandle, compat_data);
738 #else
739 return of_compatible_match(faa->faa_phandle, compat_data) ? 999 : 0;
740 #endif
741 }
742
743 static void
tegra124_car_attach(device_t parent,device_t self,void * aux)744 tegra124_car_attach(device_t parent, device_t self, void *aux)
745 {
746 struct tegra124_car_softc * const sc = device_private(self);
747 struct fdt_attach_args * const faa = aux;
748 const int phandle = faa->faa_phandle;
749 bus_addr_t addr;
750 bus_size_t size;
751 int error, n;
752
753 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
754 aprint_error(": couldn't get registers\n");
755 return;
756 }
757
758 sc->sc_dev = self;
759 sc->sc_bst = faa->faa_bst;
760 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
761 if (error) {
762 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error);
763 return;
764 }
765 if (of_getprop_uint32(phandle, "#clock-cells", &sc->sc_clock_cells))
766 sc->sc_clock_cells = 1;
767 if (of_getprop_uint32(phandle, "#reset-cells", &sc->sc_reset_cells))
768 sc->sc_reset_cells = 1;
769
770 aprint_naive("\n");
771 aprint_normal(": CAR\n");
772
773 sc->sc_clkdom.name = device_xname(self);
774 sc->sc_clkdom.funcs = &tegra124_car_clock_funcs;
775 sc->sc_clkdom.priv = sc;
776 for (n = 0; n < __arraycount(tegra124_car_clocks); n++) {
777 tegra124_car_clocks[n].base.domain = &sc->sc_clkdom;
778 clk_attach(&tegra124_car_clocks[n].base);
779 }
780
781 fdtbus_register_clock_controller(self, phandle,
782 &tegra124_car_fdtclock_funcs);
783 fdtbus_register_reset_controller(self, phandle,
784 &tegra124_car_fdtreset_funcs);
785
786 tegra124_car_init(sc);
787
788 tegra124_car_rnd_attach(self);
789 }
790
791 static void
tegra124_car_init(struct tegra124_car_softc * sc)792 tegra124_car_init(struct tegra124_car_softc *sc)
793 {
794 tegra124_car_parent_init(sc);
795 tegra124_car_utmip_init(sc);
796 tegra124_car_xusb_init(sc);
797 tegra124_car_watchdog_init(sc);
798 }
799
800 static void
tegra124_car_parent_init(struct tegra124_car_softc * sc)801 tegra124_car_parent_init(struct tegra124_car_softc *sc)
802 {
803 struct clk *clk, *clk_parent;
804 int error;
805 u_int n;
806
807 for (n = 0; n < __arraycount(tegra124_init_parents); n++) {
808 clk = clk_get(&sc->sc_clkdom, tegra124_init_parents[n].clock);
809 KASSERT(clk != NULL);
810 clk_parent = clk_get(&sc->sc_clkdom,
811 tegra124_init_parents[n].parent);
812 KASSERT(clk_parent != NULL);
813
814 error = clk_set_parent(clk, clk_parent);
815 if (error) {
816 aprint_error_dev(sc->sc_dev,
817 "couldn't set '%s' parent to '%s': %d\n",
818 clk->name, clk_parent->name, error);
819 }
820 clk_put(clk_parent);
821 clk_put(clk);
822 }
823 }
824
825 static void
tegra124_car_utmip_init(struct tegra124_car_softc * sc)826 tegra124_car_utmip_init(struct tegra124_car_softc *sc)
827 {
828 bus_space_tag_t bst = sc->sc_bst;
829 bus_space_handle_t bsh = sc->sc_bsh;
830
831 const u_int enable_dly_count = 0x02;
832 const u_int stable_count = 0x2f;
833 const u_int active_dly_count = 0x04;
834 const u_int xtal_freq_count = 0x76;
835
836 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG2_REG,
837 __SHIFTIN(stable_count, CAR_UTMIP_PLL_CFG2_STABLE_COUNT) |
838 __SHIFTIN(active_dly_count, CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT),
839 CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN |
840 CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN |
841 CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN |
842 CAR_UTMIP_PLL_CFG2_STABLE_COUNT |
843 CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT);
844
845 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG,
846 __SHIFTIN(enable_dly_count, CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT) |
847 __SHIFTIN(xtal_freq_count, CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT),
848 CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT |
849 CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT);
850
851 tegra_reg_set_clear(bst, bsh, CAR_UTMIP_PLL_CFG1_REG,
852 0,
853 CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN |
854 CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN);
855
856 }
857
858 static void
tegra124_car_xusb_init(struct tegra124_car_softc * sc)859 tegra124_car_xusb_init(struct tegra124_car_softc *sc)
860 {
861 const bus_space_tag_t bst = sc->sc_bst;
862 const bus_space_handle_t bsh = sc->sc_bsh;
863 uint32_t val;
864
865 /* XXX do this all better */
866
867 bus_space_write_4(bst, bsh, CAR_CLK_ENB_W_SET_REG, CAR_DEV_W_XUSB);
868
869 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG,
870 0, CAR_PLLREFE_MISC_IDDQ);
871 val = __SHIFTIN(25, CAR_PLLREFE_BASE_DIVN) |
872 __SHIFTIN(1, CAR_PLLREFE_BASE_DIVM);
873 bus_space_write_4(bst, bsh, CAR_PLLREFE_BASE_REG, val);
874
875 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG,
876 0, CAR_PLLREFE_MISC_LOCK_OVERRIDE);
877 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_BASE_REG,
878 CAR_PLLREFE_BASE_ENABLE, 0);
879 tegra_reg_set_clear(bst, bsh, CAR_PLLREFE_MISC_REG,
880 CAR_PLLREFE_MISC_LOCK_ENABLE, 0);
881
882 do {
883 delay(2);
884 val = bus_space_read_4(bst, bsh, CAR_PLLREFE_MISC_REG);
885 } while ((val & CAR_PLLREFE_MISC_LOCK) == 0);
886
887 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG,
888 CAR_PLLE_MISC_IDDQ_SWCTL, CAR_PLLE_MISC_IDDQ_OVERRIDE);
889 tegra_reg_set_clear(bst, bsh, CAR_PLLE_BASE_REG,
890 CAR_PLLE_BASE_ENABLE, 0);
891 tegra_reg_set_clear(bst, bsh, CAR_PLLE_MISC_REG,
892 CAR_PLLE_MISC_LOCK_ENABLE, 0);
893
894 do {
895 delay(2);
896 val = bus_space_read_4(bst, bsh, CAR_PLLE_MISC_REG);
897 } while ((val & CAR_PLLE_MISC_LOCK) == 0);
898
899 tegra_reg_set_clear(bst, bsh, CAR_CLKSRC_XUSB_SS_REG,
900 CAR_CLKSRC_XUSB_SS_HS_CLK_BYPASS, 0);
901 }
902
903 static void
tegra124_car_watchdog_init(struct tegra124_car_softc * sc)904 tegra124_car_watchdog_init(struct tegra124_car_softc *sc)
905 {
906 const bus_space_tag_t bst = sc->sc_bst;
907 const bus_space_handle_t bsh = sc->sc_bsh;
908
909 /* Enable watchdog timer reset for system */
910 tegra_reg_set_clear(bst, bsh, CAR_RST_SOURCE_REG,
911 CAR_RST_SOURCE_WDT_EN|CAR_RST_SOURCE_WDT_SYS_RST_EN, 0);
912 }
913
914 static void
tegra124_car_rnd_attach(device_t self)915 tegra124_car_rnd_attach(device_t self)
916 {
917 struct tegra124_car_softc * const sc = device_private(self);
918
919 rndsource_setcb(&sc->sc_rndsource, tegra124_car_rnd_callback, sc);
920 rnd_attach_source(&sc->sc_rndsource, device_xname(sc->sc_dev),
921 RND_TYPE_RNG, RND_FLAG_COLLECT_VALUE|RND_FLAG_HASCB);
922 }
923
924 static void
tegra124_car_rnd_callback(size_t bytes_wanted,void * priv)925 tegra124_car_rnd_callback(size_t bytes_wanted, void *priv)
926 {
927 struct tegra124_car_softc * const sc = priv;
928 uint16_t buf[512];
929 uint32_t cnt;
930
931 while (bytes_wanted) {
932 const u_int nbytes = MIN(bytes_wanted, 1024);
933 for (cnt = 0; cnt < bytes_wanted / 2; cnt++) {
934 buf[cnt] = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
935 CAR_PLL_LFSR_REG) & 0xffff;
936 }
937 rnd_add_data_sync(&sc->sc_rndsource, buf, nbytes,
938 nbytes * NBBY);
939 bytes_wanted -= MIN(bytes_wanted, nbytes);
940 }
941 explicit_memset(buf, 0, sizeof(buf));
942 }
943
944 static struct tegra_clk *
tegra124_car_clock_find(const char * name)945 tegra124_car_clock_find(const char *name)
946 {
947 u_int n;
948
949 for (n = 0; n < __arraycount(tegra124_car_clocks); n++) {
950 if (strcmp(tegra124_car_clocks[n].base.name, name) == 0) {
951 return &tegra124_car_clocks[n];
952 }
953 }
954
955 return NULL;
956 }
957
958 static struct tegra_clk *
tegra124_car_clock_find_by_id(u_int clock_id)959 tegra124_car_clock_find_by_id(u_int clock_id)
960 {
961 u_int n;
962
963 for (n = 0; n < __arraycount(tegra124_car_clock_ids); n++) {
964 if (tegra124_car_clock_ids[n].id == clock_id) {
965 const char *name = tegra124_car_clock_ids[n].name;
966 return tegra124_car_clock_find(name);
967 }
968 }
969
970 return NULL;
971 }
972
973 static struct clk *
tegra124_car_clock_decode(device_t dev,int cc_phandle,const void * data,size_t len)974 tegra124_car_clock_decode(device_t dev, int cc_phandle, const void *data,
975 size_t len)
976 {
977 struct tegra124_car_softc * const sc = device_private(dev);
978 struct tegra_clk *tclk;
979
980 if (len != sc->sc_clock_cells * 4) {
981 return NULL;
982 }
983
984 const u_int clock_id = be32dec(data);
985
986 tclk = tegra124_car_clock_find_by_id(clock_id);
987 if (tclk)
988 return TEGRA_CLK_BASE(tclk);
989
990 return NULL;
991 }
992
993 static struct clk *
tegra124_car_clock_get(void * priv,const char * name)994 tegra124_car_clock_get(void *priv, const char *name)
995 {
996 struct tegra_clk *tclk;
997
998 tclk = tegra124_car_clock_find(name);
999 if (tclk == NULL)
1000 return NULL;
1001
1002 atomic_inc_uint(&tclk->refcnt);
1003
1004 return TEGRA_CLK_BASE(tclk);
1005 }
1006
1007 static void
tegra124_car_clock_put(void * priv,struct clk * clk)1008 tegra124_car_clock_put(void *priv, struct clk *clk)
1009 {
1010 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1011
1012 KASSERT(tclk->refcnt > 0);
1013
1014 atomic_dec_uint(&tclk->refcnt);
1015 }
1016
1017 static u_int
tegra124_car_clock_get_rate_pll(struct tegra124_car_softc * sc,struct tegra_clk * tclk)1018 tegra124_car_clock_get_rate_pll(struct tegra124_car_softc *sc,
1019 struct tegra_clk *tclk)
1020 {
1021 struct tegra_pll_clk *tpll = &tclk->u.pll;
1022 struct tegra_clk *tclk_parent;
1023 bus_space_tag_t bst = sc->sc_bst;
1024 bus_space_handle_t bsh = sc->sc_bsh;
1025 u_int divm, divn, divp;
1026 uint64_t rate;
1027
1028 KASSERT(tclk->type == TEGRA_CLK_PLL);
1029
1030 tclk_parent = tegra124_car_clock_find(tclk->parent);
1031 KASSERT(tclk_parent != NULL);
1032
1033 const u_int rate_parent = tegra124_car_clock_get_rate(sc,
1034 TEGRA_CLK_BASE(tclk_parent));
1035
1036 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg);
1037 divm = __SHIFTOUT(base, tpll->divm_mask);
1038 divn = __SHIFTOUT(base, tpll->divn_mask);
1039 if (tpll->base_reg == CAR_PLLU_BASE_REG) {
1040 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1;
1041 } else {
1042 divp = __SHIFTOUT(base, tpll->divp_mask);
1043 }
1044
1045 rate = (uint64_t)rate_parent * divn;
1046 return rate / (divm << divp);
1047 }
1048
1049 static int
tegra124_car_clock_set_rate_pll(struct tegra124_car_softc * sc,struct tegra_clk * tclk,u_int rate)1050 tegra124_car_clock_set_rate_pll(struct tegra124_car_softc *sc,
1051 struct tegra_clk *tclk, u_int rate)
1052 {
1053 struct tegra_pll_clk *tpll = &tclk->u.pll;
1054 bus_space_tag_t bst = sc->sc_bst;
1055 bus_space_handle_t bsh = sc->sc_bsh;
1056 struct clk *clk_parent;
1057 uint32_t bp, base;
1058
1059 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
1060 if (clk_parent == NULL)
1061 return EIO;
1062 const u_int rate_parent = tegra124_car_clock_get_rate(sc, clk_parent);
1063 if (rate_parent == 0)
1064 return EIO;
1065
1066 if (tpll->base_reg == CAR_PLLX_BASE_REG) {
1067 const u_int divm = 1;
1068 const u_int divn = rate / rate_parent;
1069 const u_int divp = 0;
1070
1071 bp = bus_space_read_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG);
1072 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE;
1073 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE,
1074 CAR_CCLKG_BURST_POLICY_CPU_STATE);
1075 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE;
1076 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM,
1077 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE);
1078 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp);
1079
1080 base = bus_space_read_4(bst, bsh, CAR_PLLX_BASE_REG);
1081 base &= ~CAR_PLLX_BASE_DIVM;
1082 base &= ~CAR_PLLX_BASE_DIVN;
1083 base &= ~CAR_PLLX_BASE_DIVP;
1084 base |= __SHIFTIN(divm, CAR_PLLX_BASE_DIVM);
1085 base |= __SHIFTIN(divn, CAR_PLLX_BASE_DIVN);
1086 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP);
1087 bus_space_write_4(bst, bsh, CAR_PLLX_BASE_REG, base);
1088
1089 tegra_reg_set_clear(bst, bsh, CAR_PLLX_MISC_REG,
1090 CAR_PLLX_MISC_LOCK_ENABLE, 0);
1091 do {
1092 delay(2);
1093 base = bus_space_read_4(bst, bsh, tpll->base_reg);
1094 } while ((base & CAR_PLLX_BASE_LOCK) == 0);
1095 delay(100);
1096
1097 bp &= ~CAR_CCLKG_BURST_POLICY_CPU_STATE;
1098 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN,
1099 CAR_CCLKG_BURST_POLICY_CPU_STATE);
1100 bp &= ~CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE;
1101 bp |= __SHIFTIN(CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ,
1102 CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE);
1103 bus_space_write_4(bst, bsh, CAR_CCLKG_BURST_POLICY_REG, bp);
1104
1105 return 0;
1106 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) {
1107 const u_int divm = 1;
1108 const u_int pldiv = 1;
1109 const u_int divn = (rate << pldiv) / rate_parent;
1110
1111 /* Set frequency */
1112 tegra_reg_set_clear(bst, bsh, tpll->base_reg,
1113 __SHIFTIN(divm, CAR_PLLD2_BASE_DIVM) |
1114 __SHIFTIN(divn, CAR_PLLD2_BASE_DIVN) |
1115 __SHIFTIN(pldiv, CAR_PLLD2_BASE_DIVP),
1116 CAR_PLLD2_BASE_REF_SRC_SEL |
1117 CAR_PLLD2_BASE_DIVM |
1118 CAR_PLLD2_BASE_DIVN |
1119 CAR_PLLD2_BASE_DIVP);
1120
1121 return 0;
1122 } else {
1123 /* TODO */
1124 return EOPNOTSUPP;
1125 }
1126 }
1127
1128 static int
tegra124_car_clock_set_parent_mux(struct tegra124_car_softc * sc,struct tegra_clk * tclk,struct tegra_clk * tclk_parent)1129 tegra124_car_clock_set_parent_mux(struct tegra124_car_softc *sc,
1130 struct tegra_clk *tclk, struct tegra_clk *tclk_parent)
1131 {
1132 struct tegra_mux_clk *tmux = &tclk->u.mux;
1133 bus_space_tag_t bst = sc->sc_bst;
1134 bus_space_handle_t bsh = sc->sc_bsh;
1135 uint32_t v;
1136 u_int src;
1137
1138 KASSERT(tclk->type == TEGRA_CLK_MUX);
1139
1140 for (src = 0; src < tmux->nparents; src++) {
1141 if (tmux->parents[src] == NULL) {
1142 continue;
1143 }
1144 if (strcmp(tmux->parents[src], tclk_parent->base.name) == 0) {
1145 break;
1146 }
1147 }
1148 if (src == tmux->nparents) {
1149 return EINVAL;
1150 }
1151
1152 if (tmux->reg == CAR_CLKSRC_HDMI_REG &&
1153 src == CAR_CLKSRC_HDMI_SRC_PLLD2_OUT0) {
1154 /* Change IDDQ from 1 to 0 */
1155 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG,
1156 0, CAR_PLLD2_BASE_IDDQ);
1157 delay(2);
1158
1159 /* Enable lock */
1160 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_MISC_REG,
1161 CAR_PLLD2_MISC_LOCK_ENABLE, 0);
1162
1163 /* Enable PLLD2 */
1164 tegra_reg_set_clear(bst, bsh, CAR_PLLD2_BASE_REG,
1165 CAR_PLLD2_BASE_ENABLE, 0);
1166
1167 /* Wait for lock */
1168 do {
1169 delay(2);
1170 v = bus_space_read_4(bst, bsh, CAR_PLLD2_BASE_REG);
1171 } while ((v & CAR_PLLD2_BASE_LOCK) == 0);
1172
1173 delay(200);
1174 }
1175
1176 v = bus_space_read_4(bst, bsh, tmux->reg);
1177 v &= ~tmux->bits;
1178 v |= __SHIFTIN(src, tmux->bits);
1179 bus_space_write_4(bst, bsh, tmux->reg, v);
1180
1181 return 0;
1182 }
1183
1184 static struct tegra_clk *
tegra124_car_clock_get_parent_mux(struct tegra124_car_softc * sc,struct tegra_clk * tclk)1185 tegra124_car_clock_get_parent_mux(struct tegra124_car_softc *sc,
1186 struct tegra_clk *tclk)
1187 {
1188 struct tegra_mux_clk *tmux = &tclk->u.mux;
1189 bus_space_tag_t bst = sc->sc_bst;
1190 bus_space_handle_t bsh = sc->sc_bsh;
1191
1192 KASSERT(tclk->type == TEGRA_CLK_MUX);
1193
1194 const uint32_t v = bus_space_read_4(bst, bsh, tmux->reg);
1195 const u_int src = __SHIFTOUT(v, tmux->bits);
1196
1197 KASSERT(src < tmux->nparents);
1198
1199 if (tmux->parents[src] == NULL) {
1200 return NULL;
1201 }
1202
1203 return tegra124_car_clock_find(tmux->parents[src]);
1204 }
1205
1206 static u_int
tegra124_car_clock_get_rate_fixed_div(struct tegra124_car_softc * sc,struct tegra_clk * tclk)1207 tegra124_car_clock_get_rate_fixed_div(struct tegra124_car_softc *sc,
1208 struct tegra_clk *tclk)
1209 {
1210 struct tegra_fixed_div_clk *tfixed_div = &tclk->u.fixed_div;
1211 struct clk *clk_parent;
1212
1213 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
1214 if (clk_parent == NULL)
1215 return 0;
1216 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent);
1217
1218 return parent_rate / tfixed_div->div;
1219 }
1220
1221 static u_int
tegra124_car_clock_calc_rate_frac_div(u_int rate,u_int raw_div)1222 tegra124_car_clock_calc_rate_frac_div(u_int rate, u_int raw_div)
1223 {
1224 raw_div += 2;
1225 rate *= 2;
1226 rate += raw_div - 1;
1227 rate /= raw_div;
1228 return rate;
1229 }
1230
1231 static u_int
tegra124_car_clock_get_rate_div(struct tegra124_car_softc * sc,struct tegra_clk * tclk)1232 tegra124_car_clock_get_rate_div(struct tegra124_car_softc *sc,
1233 struct tegra_clk *tclk)
1234 {
1235 struct tegra_div_clk *tdiv = &tclk->u.div;
1236 bus_space_tag_t bst = sc->sc_bst;
1237 bus_space_handle_t bsh = sc->sc_bsh;
1238 struct clk *clk_parent;
1239 u_int rate;
1240
1241 KASSERT(tclk->type == TEGRA_CLK_DIV);
1242
1243 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
1244 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent);
1245
1246 const uint32_t v = bus_space_read_4(bst, bsh, tdiv->reg);
1247 const u_int raw_div = __SHIFTOUT(v, tdiv->bits);
1248
1249 switch (tdiv->reg) {
1250 case CAR_CLKSRC_I2C1_REG:
1251 case CAR_CLKSRC_I2C2_REG:
1252 case CAR_CLKSRC_I2C3_REG:
1253 case CAR_CLKSRC_I2C4_REG:
1254 case CAR_CLKSRC_I2C5_REG:
1255 case CAR_CLKSRC_I2C6_REG:
1256 rate = parent_rate * 1 / (raw_div + 1);
1257 break;
1258 case CAR_CLKSRC_UARTA_REG:
1259 case CAR_CLKSRC_UARTB_REG:
1260 case CAR_CLKSRC_UARTC_REG:
1261 case CAR_CLKSRC_UARTD_REG:
1262 if (v & CAR_CLKSRC_UART_DIV_ENB) {
1263 rate = tegra124_car_clock_calc_rate_frac_div(
1264 parent_rate, raw_div);
1265 } else {
1266 rate = parent_rate;
1267 }
1268 break;
1269 default:
1270 rate = tegra124_car_clock_calc_rate_frac_div(parent_rate,
1271 raw_div);
1272 break;
1273 }
1274
1275 return rate;
1276 }
1277
1278 static int
tegra124_car_clock_set_rate_div(struct tegra124_car_softc * sc,struct tegra_clk * tclk,u_int rate)1279 tegra124_car_clock_set_rate_div(struct tegra124_car_softc *sc,
1280 struct tegra_clk *tclk, u_int rate)
1281 {
1282 struct tegra_div_clk *tdiv = &tclk->u.div;
1283 bus_space_tag_t bst = sc->sc_bst;
1284 bus_space_handle_t bsh = sc->sc_bsh;
1285 struct clk *clk_parent;
1286 u_int raw_div;
1287 uint32_t v;
1288
1289 KASSERT(tclk->type == TEGRA_CLK_DIV);
1290
1291 clk_parent = tegra124_car_clock_get_parent(sc, TEGRA_CLK_BASE(tclk));
1292 if (clk_parent == NULL)
1293 return EINVAL;
1294 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent);
1295
1296 v = bus_space_read_4(bst, bsh, tdiv->reg);
1297
1298 raw_div = __SHIFTOUT(tdiv->bits, tdiv->bits);
1299
1300 switch (tdiv->reg) {
1301 case CAR_CLKSRC_UARTA_REG:
1302 case CAR_CLKSRC_UARTB_REG:
1303 case CAR_CLKSRC_UARTC_REG:
1304 case CAR_CLKSRC_UARTD_REG:
1305 if (rate == parent_rate) {
1306 v &= ~CAR_CLKSRC_UART_DIV_ENB;
1307 } else {
1308 v |= CAR_CLKSRC_UART_DIV_ENB;
1309 raw_div = (parent_rate * 2) / rate - 2;
1310 }
1311 break;
1312 case CAR_CLKSRC_SATA_REG:
1313 if (rate) {
1314 tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG,
1315 0, CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL);
1316 v |= CAR_CLKSRC_SATA_AUX_CLK_ENB;
1317 raw_div = (parent_rate * 2) / rate - 2;
1318 } else {
1319 v &= ~CAR_CLKSRC_SATA_AUX_CLK_ENB;
1320 }
1321 break;
1322 case CAR_CLKSRC_I2C1_REG:
1323 case CAR_CLKSRC_I2C2_REG:
1324 case CAR_CLKSRC_I2C3_REG:
1325 case CAR_CLKSRC_I2C4_REG:
1326 case CAR_CLKSRC_I2C5_REG:
1327 case CAR_CLKSRC_I2C6_REG:
1328 if (rate)
1329 raw_div = parent_rate / rate - 1;
1330 break;
1331 case CAR_CLKSRC_SDMMC1_REG:
1332 case CAR_CLKSRC_SDMMC2_REG:
1333 case CAR_CLKSRC_SDMMC3_REG:
1334 case CAR_CLKSRC_SDMMC4_REG:
1335 if (rate) {
1336 for (raw_div = 0x00; raw_div <= 0xff; raw_div++) {
1337 u_int calc_rate =
1338 tegra124_car_clock_calc_rate_frac_div(
1339 parent_rate, raw_div);
1340 if (calc_rate <= rate)
1341 break;
1342 }
1343 if (raw_div == 0x100)
1344 return EINVAL;
1345 }
1346 break;
1347 default:
1348 if (rate)
1349 raw_div = (parent_rate * 2) / rate - 2;
1350 break;
1351 }
1352
1353 v &= ~tdiv->bits;
1354 v |= __SHIFTIN(raw_div, tdiv->bits);
1355
1356 bus_space_write_4(bst, bsh, tdiv->reg, v);
1357
1358 return 0;
1359 }
1360
1361 static int
tegra124_car_clock_enable_gate(struct tegra124_car_softc * sc,struct tegra_clk * tclk,bool enable)1362 tegra124_car_clock_enable_gate(struct tegra124_car_softc *sc,
1363 struct tegra_clk *tclk, bool enable)
1364 {
1365 struct tegra_gate_clk *tgate = &tclk->u.gate;
1366 bus_space_tag_t bst = sc->sc_bst;
1367 bus_space_handle_t bsh = sc->sc_bsh;
1368 bus_size_t reg;
1369
1370 KASSERT(tclk->type == TEGRA_CLK_GATE);
1371
1372 if (tgate->set_reg == tgate->clr_reg) {
1373 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg);
1374 if (enable) {
1375 v |= tgate->bits;
1376 } else {
1377 v &= ~tgate->bits;
1378 }
1379 bus_space_write_4(bst, bsh, tgate->set_reg, v);
1380 } else {
1381 if (enable) {
1382 reg = tgate->set_reg;
1383 } else {
1384 reg = tgate->clr_reg;
1385 }
1386
1387 if (reg == CAR_CLK_ENB_V_SET_REG &&
1388 tgate->bits == CAR_DEV_V_SATA) {
1389 /* De-assert reset to SATA PADPLL */
1390 tegra_reg_set_clear(bst, bsh, CAR_SATA_PLL_CFG0_REG,
1391 0, CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE);
1392 delay(15);
1393 }
1394 bus_space_write_4(bst, bsh, reg, tgate->bits);
1395 }
1396
1397 return 0;
1398 }
1399
1400 static u_int
tegra124_car_clock_get_rate(void * priv,struct clk * clk)1401 tegra124_car_clock_get_rate(void *priv, struct clk *clk)
1402 {
1403 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1404 struct clk *clk_parent;
1405
1406 switch (tclk->type) {
1407 case TEGRA_CLK_FIXED:
1408 return tclk->u.fixed.rate;
1409 case TEGRA_CLK_PLL:
1410 return tegra124_car_clock_get_rate_pll(priv, tclk);
1411 case TEGRA_CLK_MUX:
1412 case TEGRA_CLK_GATE:
1413 clk_parent = tegra124_car_clock_get_parent(priv, clk);
1414 if (clk_parent == NULL)
1415 return EINVAL;
1416 return tegra124_car_clock_get_rate(priv, clk_parent);
1417 case TEGRA_CLK_FIXED_DIV:
1418 return tegra124_car_clock_get_rate_fixed_div(priv, tclk);
1419 case TEGRA_CLK_DIV:
1420 return tegra124_car_clock_get_rate_div(priv, tclk);
1421 default:
1422 panic("tegra124: unknown tclk type %d", tclk->type);
1423 }
1424 }
1425
1426 static int
tegra124_car_clock_set_rate(void * priv,struct clk * clk,u_int rate)1427 tegra124_car_clock_set_rate(void *priv, struct clk *clk, u_int rate)
1428 {
1429 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1430 struct clk *clk_parent;
1431
1432 KASSERT((clk->flags & CLK_SET_RATE_PARENT) == 0);
1433
1434 switch (tclk->type) {
1435 case TEGRA_CLK_FIXED:
1436 case TEGRA_CLK_MUX:
1437 return EIO;
1438 case TEGRA_CLK_FIXED_DIV:
1439 clk_parent = tegra124_car_clock_get_parent(priv, clk);
1440 if (clk_parent == NULL)
1441 return EIO;
1442 return tegra124_car_clock_set_rate(priv, clk_parent,
1443 rate * tclk->u.fixed_div.div);
1444 case TEGRA_CLK_GATE:
1445 return EINVAL;
1446 case TEGRA_CLK_PLL:
1447 return tegra124_car_clock_set_rate_pll(priv, tclk, rate);
1448 case TEGRA_CLK_DIV:
1449 return tegra124_car_clock_set_rate_div(priv, tclk, rate);
1450 default:
1451 panic("tegra124: unknown tclk type %d", tclk->type);
1452 }
1453 }
1454
1455 static int
tegra124_car_clock_enable(void * priv,struct clk * clk)1456 tegra124_car_clock_enable(void *priv, struct clk *clk)
1457 {
1458 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1459 struct clk *clk_parent;
1460
1461 if (tclk->type != TEGRA_CLK_GATE) {
1462 clk_parent = tegra124_car_clock_get_parent(priv, clk);
1463 if (clk_parent == NULL)
1464 return 0;
1465 return tegra124_car_clock_enable(priv, clk_parent);
1466 }
1467
1468 return tegra124_car_clock_enable_gate(priv, tclk, true);
1469 }
1470
1471 static int
tegra124_car_clock_disable(void * priv,struct clk * clk)1472 tegra124_car_clock_disable(void *priv, struct clk *clk)
1473 {
1474 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1475
1476 if (tclk->type != TEGRA_CLK_GATE)
1477 return EINVAL;
1478
1479 return tegra124_car_clock_enable_gate(priv, tclk, false);
1480 }
1481
1482 static int
tegra124_car_clock_set_parent(void * priv,struct clk * clk,struct clk * clk_parent)1483 tegra124_car_clock_set_parent(void *priv, struct clk *clk,
1484 struct clk *clk_parent)
1485 {
1486 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1487 struct tegra_clk *tclk_parent = TEGRA_CLK_PRIV(clk_parent);
1488 struct clk *nclk_parent;
1489
1490 if (tclk->type != TEGRA_CLK_MUX) {
1491 nclk_parent = tegra124_car_clock_get_parent(priv, clk);
1492 if (nclk_parent == clk_parent || nclk_parent == NULL)
1493 return EINVAL;
1494 return tegra124_car_clock_set_parent(priv, nclk_parent,
1495 clk_parent);
1496 }
1497
1498 return tegra124_car_clock_set_parent_mux(priv, tclk, tclk_parent);
1499 }
1500
1501 static struct clk *
tegra124_car_clock_get_parent(void * priv,struct clk * clk)1502 tegra124_car_clock_get_parent(void *priv, struct clk *clk)
1503 {
1504 struct tegra_clk *tclk = TEGRA_CLK_PRIV(clk);
1505 struct tegra_clk *tclk_parent = NULL;
1506
1507 switch (tclk->type) {
1508 case TEGRA_CLK_FIXED:
1509 case TEGRA_CLK_PLL:
1510 case TEGRA_CLK_FIXED_DIV:
1511 case TEGRA_CLK_DIV:
1512 case TEGRA_CLK_GATE:
1513 if (tclk->parent) {
1514 tclk_parent = tegra124_car_clock_find(tclk->parent);
1515 }
1516 break;
1517 case TEGRA_CLK_MUX:
1518 tclk_parent = tegra124_car_clock_get_parent_mux(priv, tclk);
1519 break;
1520 }
1521
1522 if (tclk_parent == NULL)
1523 return NULL;
1524
1525 return TEGRA_CLK_BASE(tclk_parent);
1526 }
1527
1528 static void *
tegra124_car_reset_acquire(device_t dev,const void * data,size_t len)1529 tegra124_car_reset_acquire(device_t dev, const void *data, size_t len)
1530 {
1531 struct tegra124_car_softc * const sc = device_private(dev);
1532 struct tegra124_car_rst *rst;
1533
1534 if (len != sc->sc_reset_cells * 4)
1535 return NULL;
1536
1537 const u_int reset_id = be32dec(data);
1538
1539 if (reset_id >= __arraycount(tegra124_car_reset_regs) * 32)
1540 return NULL;
1541
1542 const u_int reg = reset_id / 32;
1543
1544 rst = kmem_alloc(sizeof(*rst), KM_SLEEP);
1545 rst->set_reg = tegra124_car_reset_regs[reg].set_reg;
1546 rst->clr_reg = tegra124_car_reset_regs[reg].clr_reg;
1547 rst->mask = __BIT(reset_id % 32);
1548
1549 return rst;
1550 }
1551
1552 static void
tegra124_car_reset_release(device_t dev,void * priv)1553 tegra124_car_reset_release(device_t dev, void *priv)
1554 {
1555 struct tegra124_car_rst *rst = priv;
1556
1557 kmem_free(rst, sizeof(*rst));
1558 }
1559
1560 static int
tegra124_car_reset_assert(device_t dev,void * priv)1561 tegra124_car_reset_assert(device_t dev, void *priv)
1562 {
1563 struct tegra124_car_softc * const sc = device_private(dev);
1564 struct tegra124_car_rst *rst = priv;
1565
1566 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask);
1567
1568 return 0;
1569 }
1570
1571 static int
tegra124_car_reset_deassert(device_t dev,void * priv)1572 tegra124_car_reset_deassert(device_t dev, void *priv)
1573 {
1574 struct tegra124_car_softc * const sc = device_private(dev);
1575 struct tegra124_car_rst *rst = priv;
1576
1577 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->clr_reg, rst->mask);
1578
1579 return 0;
1580 }
1581