1 /* $NetBSD: if_ti.c,v 1.123 2022/05/23 13:53:37 rin Exp $ */
2
3 /*
4 * Copyright (c) 1997, 1998, 1999
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp
35 */
36
37 /*
38 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
39 * Manuals, sample driver and firmware source kits are available
40 * from http://www.alteon.com/support/openkits.
41 *
42 * Written by Bill Paul <wpaul@ctr.columbia.edu>
43 * Electrical Engineering Department
44 * Columbia University, New York City
45 */
46
47 /*
48 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
49 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
50 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
51 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
52 * filtering and jumbo (9014 byte) frames. The hardware is largely
53 * controlled by firmware, which must be loaded into the NIC during
54 * initialization.
55 *
56 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
57 * revision, which supports new features such as extended commands,
58 * extended jumbo receive ring descriptors and a mini receive ring.
59 *
60 * Alteon Networks is to be commended for releasing such a vast amount
61 * of development material for the Tigon NIC without requiring an NDA
62 * (although they really should have done it a long time ago). With
63 * any luck, the other vendors will finally wise up and follow Alteon's
64 * stellar example.
65 *
66 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
67 * this driver by #including it as a C header file. This bloats the
68 * driver somewhat, but it's the easiest method considering that the
69 * driver code and firmware code need to be kept in sync. The source
70 * for the firmware is not provided with the FreeBSD distribution since
71 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
72 *
73 * The following people deserve special thanks:
74 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
75 * for testing
76 * - Raymond Lee of Netgear, for providing a pair of Netgear
77 * GA620 Tigon 2 boards for testing
78 * - Ulf Zimmermann, for bringing the GA620 to my attention and
79 * convincing me to write this driver.
80 * - Andrew Gallatin for providing FreeBSD/Alpha support.
81 */
82
83 #include <sys/cdefs.h>
84 __KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.123 2022/05/23 13:53:37 rin Exp $");
85
86 #include "opt_inet.h"
87
88 #include <sys/param.h>
89 #include <sys/systm.h>
90 #include <sys/sockio.h>
91 #include <sys/mbuf.h>
92 #include <sys/malloc.h>
93 #include <sys/kernel.h>
94 #include <sys/socket.h>
95 #include <sys/queue.h>
96 #include <sys/device.h>
97 #include <sys/reboot.h>
98
99 #include <net/if.h>
100 #include <net/if_arp.h>
101 #include <net/if_ether.h>
102 #include <net/if_dl.h>
103 #include <net/if_media.h>
104
105 #include <net/bpf.h>
106
107 #ifdef INET
108 #include <netinet/in.h>
109 #include <netinet/if_inarp.h>
110 #include <netinet/in_systm.h>
111 #include <netinet/ip.h>
112 #endif
113
114
115 #include <sys/bus.h>
116
117 #include <dev/pci/pcireg.h>
118 #include <dev/pci/pcivar.h>
119 #include <dev/pci/pcidevs.h>
120
121 #include <dev/pci/if_tireg.h>
122
123 #include <dev/microcode/tigon/ti_fw.h>
124 #include <dev/microcode/tigon/ti_fw2.h>
125
126 /*
127 * Various supported device vendors/types and their names.
128 */
129
130 static const struct ti_type ti_devs[] = {
131 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC,
132 "Alteon AceNIC 1000BASE-SX Ethernet" },
133 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_ACENIC_COPPER,
134 "Alteon AceNIC 1000BASE-T Ethernet" },
135 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C985,
136 "3Com 3c985-SX Gigabit Ethernet" },
137 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620,
138 "Netgear GA620 1000BASE-SX Ethernet" },
139 { PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T,
140 "Netgear GA620 1000BASE-T Ethernet" },
141 { PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON,
142 "Silicon Graphics Gigabit Ethernet" },
143 { PCI_VENDOR_DEC, PCI_PRODUCT_DEC_PN9000SX,
144 "Farallon PN9000SX Gigabit Ethernet" },
145 { 0, 0, NULL }
146 };
147
148 static const struct ti_type *ti_type_match(struct pci_attach_args *);
149 static int ti_probe(device_t, cfdata_t, void *);
150 static void ti_attach(device_t, device_t, void *);
151 static bool ti_shutdown(device_t, int);
152 static void ti_txeof_tigon1(struct ti_softc *);
153 static void ti_txeof_tigon2(struct ti_softc *);
154 static void ti_rxeof(struct ti_softc *);
155
156 static void ti_stats_update(struct ti_softc *);
157 static int ti_encap_tigon1(struct ti_softc *, struct mbuf *, uint32_t *);
158 static int ti_encap_tigon2(struct ti_softc *, struct mbuf *, uint32_t *);
159
160 static int ti_intr(void *);
161 static void ti_start(struct ifnet *);
162 static int ti_ioctl(struct ifnet *, u_long, void *);
163 static void ti_init(void *);
164 static void ti_init2(struct ti_softc *);
165 static void ti_stop(struct ti_softc *);
166 static void ti_watchdog(struct ifnet *);
167 static int ti_ifmedia_upd(struct ifnet *);
168 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
169
170 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int);
171 static uint8_t ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *);
172 static int ti_read_eeprom(struct ti_softc *, void *, int, int);
173
174 static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
175 static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
176 static void ti_setmulti(struct ti_softc *);
177
178 static void ti_mem(struct ti_softc *, uint32_t, uint32_t, const void *);
179 static void ti_loadfw(struct ti_softc *);
180 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
181 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, void *, int);
182 static void ti_handle_events(struct ti_softc *);
183 static int ti_alloc_jumbo_mem(struct ti_softc *);
184 static void *ti_jalloc(struct ti_softc *);
185 static void ti_jfree(struct mbuf *, void *, size_t, void *);
186 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *, bus_dmamap_t);
187 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *, bus_dmamap_t);
188 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
189 static int ti_init_rx_ring_std(struct ti_softc *);
190 static void ti_free_rx_ring_std(struct ti_softc *);
191 static int ti_init_rx_ring_jumbo(struct ti_softc *);
192 static void ti_free_rx_ring_jumbo(struct ti_softc *);
193 static int ti_init_rx_ring_mini(struct ti_softc *);
194 static void ti_free_rx_ring_mini(struct ti_softc *);
195 static void ti_free_tx_ring(struct ti_softc *);
196 static int ti_init_tx_ring(struct ti_softc *);
197
198 static int ti_64bitslot_war(struct ti_softc *);
199 static int ti_chipinit(struct ti_softc *);
200 static int ti_gibinit(struct ti_softc *);
201
202 static int ti_ether_ioctl(struct ifnet *, u_long, void *);
203
204 CFATTACH_DECL_NEW(ti, sizeof(struct ti_softc),
205 ti_probe, ti_attach, NULL, NULL);
206
207 /*
208 * Send an instruction or address to the EEPROM, check for ACK.
209 */
210 static uint32_t
ti_eeprom_putbyte(struct ti_softc * sc,int byte)211 ti_eeprom_putbyte(struct ti_softc *sc, int byte)
212 {
213 int i, ack = 0;
214
215 /*
216 * Make sure we're in TX mode.
217 */
218 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
219
220 /*
221 * Feed in each bit and strobe the clock.
222 */
223 for (i = 0x80; i; i >>= 1) {
224 if (byte & i) {
225 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
226 } else {
227 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
228 }
229 DELAY(1);
230 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
231 DELAY(1);
232 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
233 }
234
235 /*
236 * Turn off TX mode.
237 */
238 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
239
240 /*
241 * Check for ack.
242 */
243 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
244 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
245 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
246
247 return (ack);
248 }
249
250 /*
251 * Read a byte of data stored in the EEPROM at address 'addr.'
252 * We have to send two address bytes since the EEPROM can hold
253 * more than 256 bytes of data.
254 */
255 static uint8_t
ti_eeprom_getbyte(struct ti_softc * sc,int addr,uint8_t * dest)256 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest)
257 {
258 int i;
259 uint8_t byte = 0;
260
261 EEPROM_START();
262
263 /*
264 * Send write control code to EEPROM.
265 */
266 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
267 printf("%s: failed to send write command, status: %x\n",
268 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
269 return (1);
270 }
271
272 /*
273 * Send first byte of address of byte we want to read.
274 */
275 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
276 printf("%s: failed to send address, status: %x\n",
277 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
278 return (1);
279 }
280 /*
281 * Send second byte address of byte we want to read.
282 */
283 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
284 printf("%s: failed to send address, status: %x\n",
285 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
286 return (1);
287 }
288
289 EEPROM_STOP();
290 EEPROM_START();
291 /*
292 * Send read control code to EEPROM.
293 */
294 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
295 printf("%s: failed to send read command, status: %x\n",
296 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
297 return (1);
298 }
299
300 /*
301 * Start reading bits from EEPROM.
302 */
303 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
304 for (i = 0x80; i; i >>= 1) {
305 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
306 DELAY(1);
307 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
308 byte |= i;
309 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
310 DELAY(1);
311 }
312
313 EEPROM_STOP();
314
315 /*
316 * No ACK generated for read, so just return byte.
317 */
318
319 *dest = byte;
320
321 return (0);
322 }
323
324 /*
325 * Read a sequence of bytes from the EEPROM.
326 */
327 static int
ti_read_eeprom(struct ti_softc * sc,void * destv,int off,int cnt)328 ti_read_eeprom(struct ti_softc *sc, void *destv, int off, int cnt)
329 {
330 char *dest = destv;
331 int err = 0, i;
332 uint8_t byte = 0;
333
334 for (i = 0; i < cnt; i++) {
335 err = ti_eeprom_getbyte(sc, off + i, &byte);
336 if (err)
337 break;
338 *(dest + i) = byte;
339 }
340
341 return (err ? 1 : 0);
342 }
343
344 /*
345 * NIC memory access function. Can be used to either clear a section
346 * of NIC local memory or (if tbuf is non-NULL) copy data into it.
347 */
348 static void
ti_mem(struct ti_softc * sc,uint32_t addr,uint32_t len,const void * xbuf)349 ti_mem(struct ti_softc *sc, uint32_t addr, uint32_t len, const void *xbuf)
350 {
351 int segptr, segsize, cnt;
352 const void *ptr;
353
354 segptr = addr;
355 cnt = len;
356 ptr = xbuf;
357
358 while (cnt) {
359 if (cnt < TI_WINLEN)
360 segsize = cnt;
361 else
362 segsize = TI_WINLEN - (segptr % TI_WINLEN);
363 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
364 if (xbuf == NULL) {
365 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle,
366 TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0,
367 segsize / 4);
368 } else {
369 #ifdef __BUS_SPACE_HAS_STREAM_METHODS
370 bus_space_write_region_stream_4(sc->ti_btag,
371 sc->ti_bhandle,
372 TI_WINDOW + (segptr & (TI_WINLEN - 1)),
373 (const uint32_t *)ptr, segsize / 4);
374 #else
375 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
376 TI_WINDOW + (segptr & (TI_WINLEN - 1)),
377 (const uint32_t *)ptr, segsize / 4);
378 #endif
379 ptr = (const char *)ptr + segsize;
380 }
381 segptr += segsize;
382 cnt -= segsize;
383 }
384
385 return;
386 }
387
388 /*
389 * Load firmware image into the NIC. Check that the firmware revision
390 * is acceptable and see if we want the firmware for the Tigon 1 or
391 * Tigon 2.
392 */
393 static void
ti_loadfw(struct ti_softc * sc)394 ti_loadfw(struct ti_softc *sc)
395 {
396 switch (sc->ti_hwrev) {
397 case TI_HWREV_TIGON:
398 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
399 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
400 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
401 printf("%s: firmware revision mismatch; want "
402 "%d.%d.%d, got %d.%d.%d\n", device_xname(sc->sc_dev),
403 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
404 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
405 tigonFwReleaseMinor, tigonFwReleaseFix);
406 return;
407 }
408 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText);
409 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData);
410 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, tigonFwRodata);
411 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
412 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
413 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
414 break;
415 case TI_HWREV_TIGON_II:
416 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
417 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
418 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
419 printf("%s: firmware revision mismatch; want "
420 "%d.%d.%d, got %d.%d.%d\n", device_xname(sc->sc_dev),
421 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
422 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
423 tigon2FwReleaseMinor, tigon2FwReleaseFix);
424 return;
425 }
426 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, tigon2FwText);
427 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, tigon2FwData);
428 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
429 tigon2FwRodata);
430 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
431 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
432 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
433 break;
434 default:
435 printf("%s: can't load firmware: unknown hardware rev\n",
436 device_xname(sc->sc_dev));
437 break;
438 }
439
440 return;
441 }
442
443 /*
444 * Send the NIC a command via the command ring.
445 */
446 static void
ti_cmd(struct ti_softc * sc,struct ti_cmd_desc * cmd)447 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd)
448 {
449 uint32_t index;
450
451 index = sc->ti_cmd_saved_prodidx;
452 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
453 TI_INC(index, TI_CMD_RING_CNT);
454 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
455 sc->ti_cmd_saved_prodidx = index;
456 }
457
458 /*
459 * Send the NIC an extended command. The 'len' parameter specifies the
460 * number of command slots to include after the initial command.
461 */
462 static void
ti_cmd_ext(struct ti_softc * sc,struct ti_cmd_desc * cmd,void * argv,int len)463 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, void *argv, int len)
464 {
465 char *arg = argv;
466 uint32_t index;
467 int i;
468
469 index = sc->ti_cmd_saved_prodidx;
470 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
471 TI_INC(index, TI_CMD_RING_CNT);
472 for (i = 0; i < len; i++) {
473 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
474 *(uint32_t *)(&arg[i * 4]));
475 TI_INC(index, TI_CMD_RING_CNT);
476 }
477 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
478 sc->ti_cmd_saved_prodidx = index;
479 }
480
481 /*
482 * Handle events that have triggered interrupts.
483 */
484 static void
ti_handle_events(struct ti_softc * sc)485 ti_handle_events(struct ti_softc *sc)
486 {
487 struct ti_event_desc *e;
488
489 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
490 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
491 switch (TI_EVENT_EVENT(e)) {
492 case TI_EV_LINKSTAT_CHANGED:
493 sc->ti_linkstat = TI_EVENT_CODE(e);
494 if (sc->ti_linkstat == TI_EV_CODE_LINK_UP)
495 printf("%s: 10/100 link up\n",
496 device_xname(sc->sc_dev));
497 else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP)
498 printf("%s: gigabit link up\n",
499 device_xname(sc->sc_dev));
500 else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
501 printf("%s: link down\n",
502 device_xname(sc->sc_dev));
503 break;
504 case TI_EV_ERROR:
505 if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD)
506 printf("%s: invalid command\n",
507 device_xname(sc->sc_dev));
508 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD)
509 printf("%s: unknown command\n",
510 device_xname(sc->sc_dev));
511 else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG)
512 printf("%s: bad config data\n",
513 device_xname(sc->sc_dev));
514 break;
515 case TI_EV_FIRMWARE_UP:
516 ti_init2(sc);
517 break;
518 case TI_EV_STATS_UPDATED:
519 ti_stats_update(sc);
520 break;
521 case TI_EV_RESET_JUMBO_RING:
522 case TI_EV_MCAST_UPDATED:
523 /* Who cares. */
524 break;
525 default:
526 printf("%s: unknown event: %d\n",
527 device_xname(sc->sc_dev), TI_EVENT_EVENT(e));
528 break;
529 }
530 /* Advance the consumer index. */
531 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
532 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
533 }
534
535 return;
536 }
537
538 /*
539 * Memory management for the jumbo receive ring is a pain in the
540 * butt. We need to allocate at least 9018 bytes of space per frame,
541 * _and_ it has to be contiguous (unless you use the extended
542 * jumbo descriptor format). Using malloc() all the time won't
543 * work: malloc() allocates memory in powers of two, which means we
544 * would end up wasting a considerable amount of space by allocating
545 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
546 * to do our own memory management.
547 *
548 * The driver needs to allocate a contiguous chunk of memory at boot
549 * time. We then chop this up ourselves into 9K pieces and use them
550 * as external mbuf storage.
551 *
552 * One issue here is how much memory to allocate. The jumbo ring has
553 * 256 slots in it, but at 9K per slot than can consume over 2MB of
554 * RAM. This is a bit much, especially considering we also need
555 * RAM for the standard ring and mini ring (on the Tigon 2). To
556 * save space, we only actually allocate enough memory for 64 slots
557 * by default, which works out to between 500 and 600K. This can
558 * be tuned by changing a #define in if_tireg.h.
559 */
560
561 static int
ti_alloc_jumbo_mem(struct ti_softc * sc)562 ti_alloc_jumbo_mem(struct ti_softc *sc)
563 {
564 char *ptr;
565 int i;
566 struct ti_jpool_entry *entry;
567 bus_dma_segment_t dmaseg;
568 int error, dmanseg;
569
570 /* Grab a big chunk o' storage. */
571 if ((error = bus_dmamem_alloc(sc->sc_dmat,
572 TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg,
573 BUS_DMA_NOWAIT)) != 0) {
574 aprint_error_dev(sc->sc_dev,
575 "can't allocate jumbo buffer, error = %d\n", error);
576 return (error);
577 }
578
579 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg,
580 TI_JMEM, (void **)&sc->ti_cdata.ti_jumbo_buf,
581 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
582 aprint_error_dev(sc->sc_dev,
583 "can't map jumbo buffer, error = %d\n", error);
584 return (error);
585 }
586
587 if ((error = bus_dmamap_create(sc->sc_dmat,
588 TI_JMEM, 1,
589 TI_JMEM, 0, BUS_DMA_NOWAIT,
590 &sc->jumbo_dmamap)) != 0) {
591 aprint_error_dev(sc->sc_dev,
592 "can't create jumbo buffer DMA map, error = %d\n", error);
593 return (error);
594 }
595
596 if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap,
597 sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL,
598 BUS_DMA_NOWAIT)) != 0) {
599 aprint_error_dev(sc->sc_dev,
600 "can't load jumbo buffer DMA map, error = %d\n", error);
601 return (error);
602 }
603 sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr;
604
605 SIMPLEQ_INIT(&sc->ti_jfree_listhead);
606 SIMPLEQ_INIT(&sc->ti_jinuse_listhead);
607
608 /*
609 * Now divide it up into 9K pieces and save the addresses
610 * in an array.
611 */
612 ptr = sc->ti_cdata.ti_jumbo_buf;
613 for (i = 0; i < TI_JSLOTS; i++) {
614 sc->ti_cdata.ti_jslots[i] = ptr;
615 ptr += TI_JLEN;
616 entry = malloc(sizeof(struct ti_jpool_entry),
617 M_DEVBUF, M_WAITOK);
618 entry->slot = i;
619 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry,
620 jpool_entries);
621 }
622
623 return (0);
624 }
625
626 /*
627 * Allocate a jumbo buffer.
628 */
629 static void *
ti_jalloc(struct ti_softc * sc)630 ti_jalloc(struct ti_softc *sc)
631 {
632 struct ti_jpool_entry *entry;
633
634 entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead);
635
636 if (entry == NULL) {
637 printf("%s: no free jumbo buffers\n", device_xname(sc->sc_dev));
638 return (NULL);
639 }
640
641 SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
642 SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
643
644 return (sc->ti_cdata.ti_jslots[entry->slot]);
645 }
646
647 /*
648 * Release a jumbo buffer.
649 */
650 static void
ti_jfree(struct mbuf * m,void * tbuf,size_t size,void * arg)651 ti_jfree(struct mbuf *m, void *tbuf, size_t size, void *arg)
652 {
653 struct ti_softc *sc;
654 int i, s;
655 struct ti_jpool_entry *entry;
656
657 /* Extract the softc struct pointer. */
658 sc = (struct ti_softc *)arg;
659
660 if (sc == NULL)
661 panic("ti_jfree: didn't get softc pointer!");
662
663 /* calculate the slot this buffer belongs to */
664
665 i = ((char *)tbuf
666 - (char *)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
667
668 if ((i < 0) || (i >= TI_JSLOTS))
669 panic("ti_jfree: asked to free buffer that we don't manage!");
670
671 s = splvm();
672 entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead);
673 if (entry == NULL)
674 panic("ti_jfree: buffer not in use!");
675 entry->slot = i;
676 SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries);
677 SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
678
679 if (__predict_true(m != NULL))
680 pool_cache_put(mb_cache, m);
681 splx(s);
682 }
683
684
685 /*
686 * Initialize a standard receive ring descriptor.
687 */
688 static int
ti_newbuf_std(struct ti_softc * sc,int i,struct mbuf * m,bus_dmamap_t dmamap)689 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap)
690 {
691 struct mbuf *m_new = NULL;
692 struct ti_rx_desc *r;
693 int error;
694
695 if (dmamap == NULL) {
696 /* if (m) panic() */
697
698 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
699 MCLBYTES, 0, BUS_DMA_NOWAIT,
700 &dmamap)) != 0) {
701 aprint_error_dev(sc->sc_dev,
702 "can't create recv map, error = %d\n", error);
703 return (ENOMEM);
704 }
705 }
706 sc->std_dmamap[i] = dmamap;
707
708 if (m == NULL) {
709 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
710 if (m_new == NULL) {
711 aprint_error_dev(sc->sc_dev,
712 "mbuf allocation failed -- packet dropped!\n");
713 return (ENOBUFS);
714 }
715
716 MCLGET(m_new, M_DONTWAIT);
717 if (!(m_new->m_flags & M_EXT)) {
718 aprint_error_dev(sc->sc_dev,
719 "cluster allocation failed -- packet dropped!\n");
720 m_freem(m_new);
721 return (ENOBUFS);
722 }
723 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
724 m_adj(m_new, ETHER_ALIGN);
725
726 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap,
727 mtod(m_new, void *), m_new->m_len, NULL,
728 BUS_DMA_READ | BUS_DMA_NOWAIT)) != 0) {
729 aprint_error_dev(sc->sc_dev,
730 "can't load recv map, error = %d\n", error);
731 m_freem(m_new);
732 return (ENOMEM);
733 }
734 } else {
735 m_new = m;
736 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
737 m_new->m_data = m_new->m_ext.ext_buf;
738 m_adj(m_new, ETHER_ALIGN);
739
740 /* reuse the dmamap */
741 }
742
743 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
744 r = &sc->ti_rdata->ti_rx_std_ring[i];
745 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr;
746 r->ti_type = TI_BDTYPE_RECV_BD;
747 r->ti_flags = 0;
748 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx)
749 r->ti_flags |= TI_BDFLAG_IP_CKSUM;
750 if (sc->ethercom.ec_if.if_capenable &
751 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
752 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
753 r->ti_len = m_new->m_len; /* == ds_len */
754 r->ti_idx = i;
755
756 return (0);
757 }
758
759 /*
760 * Initialize a mini receive ring descriptor. This only applies to
761 * the Tigon 2.
762 */
763 static int
ti_newbuf_mini(struct ti_softc * sc,int i,struct mbuf * m,bus_dmamap_t dmamap)764 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap)
765 {
766 struct mbuf *m_new = NULL;
767 struct ti_rx_desc *r;
768 int error;
769
770 if (dmamap == NULL) {
771 /* if (m) panic() */
772
773 if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1,
774 MHLEN, 0, BUS_DMA_NOWAIT,
775 &dmamap)) != 0) {
776 aprint_error_dev(sc->sc_dev,
777 "can't create recv map, error = %d\n", error);
778 return (ENOMEM);
779 }
780 }
781 sc->mini_dmamap[i] = dmamap;
782
783 if (m == NULL) {
784 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
785 if (m_new == NULL) {
786 aprint_error_dev(sc->sc_dev,
787 "mbuf allocation failed -- packet dropped!\n");
788 return (ENOBUFS);
789 }
790 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
791 m_adj(m_new, ETHER_ALIGN);
792
793 if ((error = bus_dmamap_load(sc->sc_dmat, dmamap,
794 mtod(m_new, void *), m_new->m_len, NULL,
795 BUS_DMA_READ | BUS_DMA_NOWAIT)) != 0) {
796 aprint_error_dev(sc->sc_dev,
797 "can't load recv map, error = %d\n", error);
798 m_freem(m_new);
799 return (ENOMEM);
800 }
801 } else {
802 m_new = m;
803 m_new->m_data = m_new->m_pktdat;
804 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
805 m_adj(m_new, ETHER_ALIGN);
806
807 /* reuse the dmamap */
808 }
809
810 r = &sc->ti_rdata->ti_rx_mini_ring[i];
811 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
812 TI_HOSTADDR(r->ti_addr) = dmamap->dm_segs[0].ds_addr;
813 r->ti_type = TI_BDTYPE_RECV_BD;
814 r->ti_flags = TI_BDFLAG_MINI_RING;
815 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx)
816 r->ti_flags |= TI_BDFLAG_IP_CKSUM;
817 if (sc->ethercom.ec_if.if_capenable &
818 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
819 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
820 r->ti_len = m_new->m_len; /* == ds_len */
821 r->ti_idx = i;
822
823 return (0);
824 }
825
826 /*
827 * Initialize a jumbo receive ring descriptor. This allocates
828 * a jumbo buffer from the pool managed internally by the driver.
829 */
830 static int
ti_newbuf_jumbo(struct ti_softc * sc,int i,struct mbuf * m)831 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m)
832 {
833 struct mbuf *m_new = NULL;
834 struct ti_rx_desc *r;
835
836 if (m == NULL) {
837 void * tbuf = NULL;
838
839 /* Allocate the mbuf. */
840 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
841 if (m_new == NULL) {
842 aprint_error_dev(sc->sc_dev,
843 "mbuf allocation failed -- packet dropped!\n");
844 return (ENOBUFS);
845 }
846
847 /* Allocate the jumbo buffer */
848 tbuf = ti_jalloc(sc);
849 if (tbuf == NULL) {
850 m_freem(m_new);
851 aprint_error_dev(sc->sc_dev,
852 "jumbo allocation failed -- packet dropped!\n");
853 return (ENOBUFS);
854 }
855
856 /* Attach the buffer to the mbuf. */
857 MEXTADD(m_new, tbuf, ETHER_MAX_LEN_JUMBO,
858 M_DEVBUF, ti_jfree, sc);
859 m_new->m_flags |= M_EXT_RW;
860 m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO;
861 } else {
862 m_new = m;
863 m_new->m_data = m_new->m_ext.ext_buf;
864 m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO;
865 }
866
867 m_adj(m_new, ETHER_ALIGN);
868 /* Set up the descriptor. */
869 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
870 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
871 TI_HOSTADDR(r->ti_addr) = sc->jumbo_dmaaddr +
872 (mtod(m_new, char *) - (char *)sc->ti_cdata.ti_jumbo_buf);
873 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
874 r->ti_flags = TI_BDFLAG_JUMBO_RING;
875 if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx)
876 r->ti_flags |= TI_BDFLAG_IP_CKSUM;
877 if (sc->ethercom.ec_if.if_capenable &
878 (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
879 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
880 r->ti_len = m_new->m_len;
881 r->ti_idx = i;
882
883 return (0);
884 }
885
886 /*
887 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
888 * that's 1MB or memory, which is a lot. For now, we fill only the first
889 * 256 ring entries and hope that our CPU is fast enough to keep up with
890 * the NIC.
891 */
892 static int
ti_init_rx_ring_std(struct ti_softc * sc)893 ti_init_rx_ring_std(struct ti_softc *sc)
894 {
895 int i;
896 struct ti_cmd_desc cmd;
897
898 for (i = 0; i < TI_SSLOTS; i++) {
899 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS)
900 return (ENOBUFS);
901 }
902
903 TI_UPDATE_STDPROD(sc, i - 1);
904 sc->ti_std = i - 1;
905
906 return (0);
907 }
908
909 static void
ti_free_rx_ring_std(struct ti_softc * sc)910 ti_free_rx_ring_std(struct ti_softc *sc)
911 {
912 int i;
913
914 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
915 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
916 /* if (sc->std_dmamap[i] == 0) panic() */
917 bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]);
918 sc->std_dmamap[i] = 0;
919
920 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
921 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
922 }
923 memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0,
924 sizeof(struct ti_rx_desc));
925 }
926
927 return;
928 }
929
930 static int
ti_init_rx_ring_jumbo(struct ti_softc * sc)931 ti_init_rx_ring_jumbo(struct ti_softc *sc)
932 {
933 int i;
934 struct ti_cmd_desc cmd;
935
936 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
937 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
938 return (ENOBUFS);
939 }
940
941 TI_UPDATE_JUMBOPROD(sc, i - 1);
942 sc->ti_jumbo = i - 1;
943
944 return (0);
945 }
946
947 static void
ti_free_rx_ring_jumbo(struct ti_softc * sc)948 ti_free_rx_ring_jumbo(struct ti_softc *sc)
949 {
950 int i;
951
952 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
953 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
954 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
955 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
956 }
957 memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0,
958 sizeof(struct ti_rx_desc));
959 }
960
961 return;
962 }
963
964 static int
ti_init_rx_ring_mini(struct ti_softc * sc)965 ti_init_rx_ring_mini(struct ti_softc *sc)
966 {
967 int i;
968
969 for (i = 0; i < TI_MSLOTS; i++) {
970 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS)
971 return (ENOBUFS);
972 }
973
974 TI_UPDATE_MINIPROD(sc, i - 1);
975 sc->ti_mini = i - 1;
976
977 return (0);
978 }
979
980 static void
ti_free_rx_ring_mini(struct ti_softc * sc)981 ti_free_rx_ring_mini(struct ti_softc *sc)
982 {
983 int i;
984
985 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
986 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
987 /* if (sc->mini_dmamap[i] == 0) panic() */
988 bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]);
989 sc->mini_dmamap[i] = 0;
990
991 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
992 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
993 }
994 memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0,
995 sizeof(struct ti_rx_desc));
996 }
997
998 return;
999 }
1000
1001 static void
ti_free_tx_ring(struct ti_softc * sc)1002 ti_free_tx_ring(struct ti_softc *sc)
1003 {
1004 int i;
1005 struct txdmamap_pool_entry *dma;
1006
1007 for (i = 0; i < TI_TX_RING_CNT; i++) {
1008 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
1009 dma = sc->txdma[i];
1010 KDASSERT(dma != NULL);
1011 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0,
1012 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1013 bus_dmamap_unload(sc->sc_dmat, dma->dmamap);
1014
1015 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i],
1016 link);
1017 sc->txdma[i] = NULL;
1018
1019 m_freem(sc->ti_cdata.ti_tx_chain[i]);
1020 sc->ti_cdata.ti_tx_chain[i] = NULL;
1021 }
1022 memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0,
1023 sizeof(struct ti_tx_desc));
1024 }
1025
1026 while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) {
1027 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link);
1028 bus_dmamap_destroy(sc->sc_dmat, dma->dmamap);
1029 free(dma, M_DEVBUF);
1030 }
1031
1032 return;
1033 }
1034
1035 static int
ti_init_tx_ring(struct ti_softc * sc)1036 ti_init_tx_ring(struct ti_softc *sc)
1037 {
1038 int i, error;
1039 bus_dmamap_t dmamap;
1040 struct txdmamap_pool_entry *dma;
1041
1042 sc->ti_txcnt = 0;
1043 sc->ti_tx_saved_considx = 0;
1044 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1045
1046 SIMPLEQ_INIT(&sc->txdma_list);
1047 for (i = 0; i < TI_RSLOTS; i++) {
1048 /* I've seen mbufs with 30 fragments. */
1049 if ((error = bus_dmamap_create(sc->sc_dmat,
1050 ETHER_MAX_LEN_JUMBO, 40, ETHER_MAX_LEN_JUMBO, 0,
1051 BUS_DMA_NOWAIT, &dmamap)) != 0) {
1052 aprint_error_dev(sc->sc_dev,
1053 "can't create tx map, error = %d\n", error);
1054 return (ENOMEM);
1055 }
1056 dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT);
1057 if (!dma) {
1058 aprint_error_dev(sc->sc_dev,
1059 "can't alloc txdmamap_pool_entry\n");
1060 bus_dmamap_destroy(sc->sc_dmat, dmamap);
1061 return (ENOMEM);
1062 }
1063 dma->dmamap = dmamap;
1064 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link);
1065 }
1066
1067 return (0);
1068 }
1069
1070 /*
1071 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
1072 * but we have to support the old way too so that Tigon 1 cards will
1073 * work.
1074 */
1075 static void
ti_add_mcast(struct ti_softc * sc,struct ether_addr * addr)1076 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr)
1077 {
1078 struct ti_cmd_desc cmd;
1079 uint16_t *m;
1080 uint32_t ext[2] = {0, 0};
1081
1082 m = (uint16_t *)&addr->ether_addr_octet[0]; /* XXX */
1083
1084 switch (sc->ti_hwrev) {
1085 case TI_HWREV_TIGON:
1086 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1087 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1088 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
1089 break;
1090 case TI_HWREV_TIGON_II:
1091 ext[0] = htons(m[0]);
1092 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1093 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (void *)&ext, 2);
1094 break;
1095 default:
1096 printf("%s: unknown hwrev\n", device_xname(sc->sc_dev));
1097 break;
1098 }
1099
1100 return;
1101 }
1102
1103 static void
ti_del_mcast(struct ti_softc * sc,struct ether_addr * addr)1104 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr)
1105 {
1106 struct ti_cmd_desc cmd;
1107 uint16_t *m;
1108 uint32_t ext[2] = {0, 0};
1109
1110 m = (uint16_t *)&addr->ether_addr_octet[0]; /* XXX */
1111
1112 switch (sc->ti_hwrev) {
1113 case TI_HWREV_TIGON:
1114 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1115 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1116 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1117 break;
1118 case TI_HWREV_TIGON_II:
1119 ext[0] = htons(m[0]);
1120 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1121 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (void *)&ext, 2);
1122 break;
1123 default:
1124 printf("%s: unknown hwrev\n", device_xname(sc->sc_dev));
1125 break;
1126 }
1127
1128 return;
1129 }
1130
1131 /*
1132 * Configure the Tigon's multicast address filter.
1133 *
1134 * The actual multicast table management is a bit of a pain, thanks to
1135 * slight brain damage on the part of both Alteon and us. With our
1136 * multicast code, we are only alerted when the multicast address table
1137 * changes and at that point we only have the current list of addresses:
1138 * we only know the current state, not the previous state, so we don't
1139 * actually know what addresses were removed or added. The firmware has
1140 * state, but we can't get our grubby mits on it, and there is no 'delete
1141 * all multicast addresses' command. Hence, we have to maintain our own
1142 * state so we know what addresses have been programmed into the NIC at
1143 * any given time.
1144 */
1145 static void
ti_setmulti(struct ti_softc * sc)1146 ti_setmulti(struct ti_softc *sc)
1147 {
1148 struct ethercom *ec = &sc->ethercom;
1149 struct ifnet *ifp = &ec->ec_if;
1150 struct ti_cmd_desc cmd;
1151 struct ti_mc_entry *mc;
1152 uint32_t intrs;
1153 struct ether_multi *enm;
1154 struct ether_multistep step;
1155
1156 /* Disable interrupts. */
1157 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1158 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1159
1160 /* First, zot all the existing filters. */
1161 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) {
1162 ti_del_mcast(sc, &mc->mc_addr);
1163 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1164 free(mc, M_DEVBUF);
1165 }
1166
1167 /*
1168 * Remember all multicast addresses so that we can delete them
1169 * later. Punt if there is a range of addresses or memory shortage.
1170 */
1171 ETHER_LOCK(ec);
1172 ETHER_FIRST_MULTI(step, ec, enm);
1173 while (enm != NULL) {
1174 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
1175 ETHER_ADDR_LEN) != 0) {
1176 ETHER_UNLOCK(ec);
1177 goto allmulti;
1178 }
1179 if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF,
1180 M_NOWAIT)) == NULL) {
1181 ETHER_UNLOCK(ec);
1182 goto allmulti;
1183 }
1184 memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN);
1185 SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1186 ETHER_NEXT_MULTI(step, enm);
1187 }
1188 ETHER_UNLOCK(ec);
1189
1190 /* Accept only programmed multicast addresses */
1191 ifp->if_flags &= ~IFF_ALLMULTI;
1192 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1193
1194 /* Now program new ones. */
1195 SIMPLEQ_FOREACH(mc, &sc->ti_mc_listhead, mc_entries)
1196 ti_add_mcast(sc, &mc->mc_addr);
1197
1198 /* Re-enable interrupts. */
1199 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1200
1201 return;
1202
1203 allmulti:
1204 /* No need to keep individual multicast addresses */
1205 while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) {
1206 SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1207 free(mc, M_DEVBUF);
1208 }
1209
1210 /* Accept all multicast addresses */
1211 ifp->if_flags |= IFF_ALLMULTI;
1212 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1213
1214 /* Re-enable interrupts. */
1215 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1216 }
1217
1218 /*
1219 * Check to see if the BIOS has configured us for a 64 bit slot when
1220 * we aren't actually in one. If we detect this condition, we can work
1221 * around it on the Tigon 2 by setting a bit in the PCI state register,
1222 * but for the Tigon 1 we must give up and abort the interface attach.
1223 */
1224 static int
ti_64bitslot_war(struct ti_softc * sc)1225 ti_64bitslot_war(struct ti_softc *sc)
1226 {
1227 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1228 CSR_WRITE_4(sc, 0x600, 0);
1229 CSR_WRITE_4(sc, 0x604, 0);
1230 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1231 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1232 if (sc->ti_hwrev == TI_HWREV_TIGON)
1233 return (EINVAL);
1234 else {
1235 TI_SETBIT(sc, TI_PCI_STATE,
1236 TI_PCISTATE_32BIT_BUS);
1237 return (0);
1238 }
1239 }
1240 }
1241
1242 return (0);
1243 }
1244
1245 /*
1246 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1247 * self-test results.
1248 */
1249 static int
ti_chipinit(struct ti_softc * sc)1250 ti_chipinit(struct ti_softc *sc)
1251 {
1252 uint32_t cacheline;
1253 uint32_t pci_writemax = 0;
1254 uint32_t rev;
1255
1256 /* Initialize link to down state. */
1257 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1258
1259 /* Set endianness before we access any non-PCI registers. */
1260 #if BYTE_ORDER == BIG_ENDIAN
1261 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1262 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1263 #else
1264 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1265 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1266 #endif
1267
1268 /* Check the ROM failed bit to see if self-tests passed. */
1269 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1270 printf("%s: board self-diagnostics failed!\n",
1271 device_xname(sc->sc_dev));
1272 return (ENODEV);
1273 }
1274
1275 /* Halt the CPU. */
1276 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1277
1278 /* Figure out the hardware revision. */
1279 rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK;
1280 switch (rev) {
1281 case TI_REV_TIGON_I:
1282 sc->ti_hwrev = TI_HWREV_TIGON;
1283 break;
1284 case TI_REV_TIGON_II:
1285 sc->ti_hwrev = TI_HWREV_TIGON_II;
1286 break;
1287 default:
1288 printf("%s: unsupported chip revision 0x%x\n",
1289 device_xname(sc->sc_dev), rev);
1290 return (ENODEV);
1291 }
1292
1293 /* Do special setup for Tigon 2. */
1294 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1295 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1296 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K);
1297 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1298 }
1299
1300 /* Set up the PCI state register. */
1301 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD | TI_PCI_WRITE_CMD);
1302 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1303 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1304 }
1305
1306 /* Clear the read/write max DMA parameters. */
1307 TI_CLRBIT(sc, TI_PCI_STATE,
1308 (TI_PCISTATE_WRITE_MAXDMA | TI_PCISTATE_READ_MAXDMA));
1309
1310 /* Get cache line size. */
1311 cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG));
1312
1313 /*
1314 * If the system has set enabled the PCI memory write
1315 * and invalidate command in the command register, set
1316 * the write max parameter accordingly. This is necessary
1317 * to use MWI with the Tigon 2.
1318 */
1319 if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG)
1320 & PCI_COMMAND_INVALIDATE_ENABLE) {
1321 switch (cacheline) {
1322 case 1:
1323 case 4:
1324 case 8:
1325 case 16:
1326 case 32:
1327 case 64:
1328 break;
1329 default:
1330 /* Disable PCI memory write and invalidate. */
1331 if (bootverbose)
1332 printf("%s: cache line size %d not "
1333 "supported; disabling PCI MWI\n",
1334 device_xname(sc->sc_dev), cacheline);
1335 CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG,
1336 CSR_READ_4(sc, PCI_COMMAND_STATUS_REG)
1337 & ~PCI_COMMAND_INVALIDATE_ENABLE);
1338 break;
1339 }
1340 }
1341
1342 #ifdef __brokenalpha__
1343 /*
1344 * From the Alteon sample driver:
1345 * Must insure that we do not cross an 8K (bytes) boundary
1346 * for DMA reads. Our highest limit is 1K bytes. This is a
1347 * restriction on some ALPHA platforms with early revision
1348 * 21174 PCI chipsets, such as the AlphaPC 164lx
1349 */
1350 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax | TI_PCI_READMAX_1024);
1351 #else
1352 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1353 #endif
1354
1355 /* This sets the min dma param all the way up (0xff). */
1356 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1357
1358 /* Configure DMA variables. */
1359 #if BYTE_ORDER == BIG_ENDIAN
1360 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1361 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1362 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1363 TI_OPMODE_DONT_FRAG_JUMBO);
1364 #else
1365 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA |
1366 TI_OPMODE_WORDSWAP_BD | TI_OPMODE_DONT_FRAG_JUMBO |
1367 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB);
1368 #endif
1369
1370 /*
1371 * Only allow 1 DMA channel to be active at a time.
1372 * I don't think this is a good idea, but without it
1373 * the firmware racks up lots of nicDmaReadRingFull
1374 * errors.
1375 * Incompatible with hardware assisted checksums.
1376 */
1377 if ((sc->ethercom.ec_if.if_capenable &
1378 (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
1379 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
1380 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx)) == 0)
1381 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1382
1383 /* Recommended settings from Tigon manual. */
1384 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1385 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1386
1387 if (ti_64bitslot_war(sc)) {
1388 printf("%s: bios thinks we're in a 64 bit slot, "
1389 "but we aren't", device_xname(sc->sc_dev));
1390 return (EINVAL);
1391 }
1392
1393 return (0);
1394 }
1395
1396 /*
1397 * Initialize the general information block and firmware, and
1398 * start the CPU(s) running.
1399 */
1400 static int
ti_gibinit(struct ti_softc * sc)1401 ti_gibinit(struct ti_softc *sc)
1402 {
1403 struct ti_rcb *rcb;
1404 int i;
1405 struct ifnet *ifp;
1406
1407 ifp = &sc->ethercom.ec_if;
1408
1409 /* Disable interrupts for now. */
1410 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1411
1412 /* Tell the chip where to find the general information block. */
1413 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
1414 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc));
1415
1416 /* Load the firmware into SRAM. */
1417 ti_loadfw(sc);
1418
1419 /* Set up the contents of the general info and ring control blocks. */
1420
1421 /* Set up the event ring and producer pointer. */
1422 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
1423
1424 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDEVENTADDR(sc, 0);
1425 rcb->ti_flags = 0;
1426 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
1427 TI_CDEVPRODADDR(sc);
1428
1429 sc->ti_ev_prodidx.ti_idx = 0;
1430 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
1431 sc->ti_ev_saved_considx = 0;
1432
1433 /* Set up the command ring and producer mailbox. */
1434 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
1435
1436 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
1437 rcb->ti_flags = 0;
1438 rcb->ti_max_len = 0;
1439 for (i = 0; i < TI_CMD_RING_CNT; i++) {
1440 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
1441 }
1442 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
1443 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
1444 sc->ti_cmd_saved_prodidx = 0;
1445
1446 /*
1447 * Assign the address of the stats refresh buffer.
1448 * We re-use the current stats buffer for this to
1449 * conserve memory.
1450 */
1451 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
1452 TI_CDSTATSADDR(sc);
1453
1454 /* Set up the standard receive ring. */
1455 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
1456 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXSTDADDR(sc, 0);
1457 rcb->ti_max_len = ETHER_MAX_LEN;
1458 rcb->ti_flags = 0;
1459 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
1460 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM;
1461 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
1462 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM;
1463 if (VLAN_ATTACHED(&sc->ethercom))
1464 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1465
1466 /* Set up the jumbo receive ring. */
1467 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
1468 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXJUMBOADDR(sc, 0);
1469 rcb->ti_max_len = ETHER_MAX_LEN_JUMBO;
1470 rcb->ti_flags = 0;
1471 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
1472 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM;
1473 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
1474 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM;
1475 if (VLAN_ATTACHED(&sc->ethercom))
1476 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1477
1478 /*
1479 * Set up the mini ring. Only activated on the
1480 * Tigon 2 but the slot in the config block is
1481 * still there on the Tigon 1.
1482 */
1483 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
1484 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXMINIADDR(sc, 0);
1485 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
1486 if (sc->ti_hwrev == TI_HWREV_TIGON)
1487 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
1488 else
1489 rcb->ti_flags = 0;
1490 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
1491 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM;
1492 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
1493 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM;
1494 if (VLAN_ATTACHED(&sc->ethercom))
1495 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1496
1497 /*
1498 * Set up the receive return ring.
1499 */
1500 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
1501 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDRXRTNADDR(sc, 0);
1502 rcb->ti_flags = 0;
1503 rcb->ti_max_len = TI_RETURN_RING_CNT;
1504 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
1505 TI_CDRTNPRODADDR(sc);
1506
1507 /*
1508 * Set up the tx ring. Note: for the Tigon 2, we have the option
1509 * of putting the transmit ring in the host's address space and
1510 * letting the chip DMA it instead of leaving the ring in the NIC's
1511 * memory and accessing it through the shared memory region. We
1512 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
1513 * so we have to revert to the shared memory scheme if we detect
1514 * a Tigon 1 chip.
1515 */
1516 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
1517 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1518 sc->ti_tx_ring_nic =
1519 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
1520 }
1521 memset((char *)sc->ti_rdata->ti_tx_ring, 0,
1522 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
1523 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
1524 if (sc->ti_hwrev == TI_HWREV_TIGON)
1525 rcb->ti_flags = 0;
1526 else
1527 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
1528 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Tx)
1529 rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM;
1530 /*
1531 * When we get the packet, there is a pseudo-header seed already
1532 * in the th_sum or uh_sum field. Make sure the firmware doesn't
1533 * compute the pseudo-header checksum again!
1534 */
1535 if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx))
1536 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1537 TI_RCB_FLAG_NO_PHDR_CKSUM;
1538 if (VLAN_ATTACHED(&sc->ethercom))
1539 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1540 rcb->ti_max_len = TI_TX_RING_CNT;
1541 if (sc->ti_hwrev == TI_HWREV_TIGON)
1542 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
1543 else
1544 TI_HOSTADDR(rcb->ti_hostaddr) = TI_CDTXADDR(sc, 0);
1545 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
1546 TI_CDTXCONSADDR(sc);
1547
1548 /*
1549 * We're done frobbing the General Information Block. Sync
1550 * it. Note we take care of the first stats sync here, as
1551 * well.
1552 */
1553 TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1554
1555 /* Set up tuneables */
1556 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) ||
1557 (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU))
1558 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
1559 (sc->ti_rx_coal_ticks / 10));
1560 else
1561 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
1562 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
1563 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
1564 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
1565 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
1566 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
1567
1568 /* Turn interrupts on. */
1569 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
1570 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1571
1572 /* Start CPU. */
1573 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT | TI_CPUSTATE_STEP));
1574
1575 return (0);
1576 }
1577
1578 /*
1579 * look for id in the device list, returning the first match
1580 */
1581 static const struct ti_type *
ti_type_match(struct pci_attach_args * pa)1582 ti_type_match(struct pci_attach_args *pa)
1583 {
1584 const struct ti_type *t;
1585
1586 t = ti_devs;
1587 while (t->ti_name != NULL) {
1588 if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) &&
1589 (PCI_PRODUCT(pa->pa_id) == t->ti_did)) {
1590 return (t);
1591 }
1592 t++;
1593 }
1594
1595 return (NULL);
1596 }
1597
1598 /*
1599 * Probe for a Tigon chip. Check the PCI vendor and device IDs
1600 * against our list and return its name if we find a match.
1601 */
1602 static int
ti_probe(device_t parent,cfdata_t match,void * aux)1603 ti_probe(device_t parent, cfdata_t match, void *aux)
1604 {
1605 struct pci_attach_args *pa = aux;
1606 const struct ti_type *t;
1607
1608 t = ti_type_match(pa);
1609
1610 return ((t == NULL) ? 0 : 1);
1611 }
1612
1613 static void
ti_attach(device_t parent,device_t self,void * aux)1614 ti_attach(device_t parent, device_t self, void *aux)
1615 {
1616 uint32_t command;
1617 struct ifnet *ifp;
1618 struct ti_softc *sc;
1619 uint8_t eaddr[ETHER_ADDR_LEN];
1620 struct pci_attach_args *pa = aux;
1621 pci_chipset_tag_t pc = pa->pa_pc;
1622 pci_intr_handle_t ih;
1623 const char *intrstr = NULL;
1624 bus_dma_segment_t dmaseg;
1625 int error, dmanseg, nolinear;
1626 const struct ti_type *t;
1627 char intrbuf[PCI_INTRSTR_LEN];
1628
1629 t = ti_type_match(pa);
1630 if (t == NULL) {
1631 aprint_error("ti_attach: were did the card go ?\n");
1632 return;
1633 }
1634
1635 aprint_normal(": %s (rev. 0x%02x)\n", t->ti_name,
1636 PCI_REVISION(pa->pa_class));
1637
1638 sc = device_private(self);
1639 sc->sc_dev = self;
1640
1641 /*
1642 * Map control/status registers.
1643 */
1644 nolinear = 0;
1645 if (pci_mapreg_map(pa, 0x10,
1646 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
1647 BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle,
1648 NULL, NULL)) {
1649 nolinear = 1;
1650 if (pci_mapreg_map(pa, 0x10,
1651 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
1652 0 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) {
1653 aprint_error_dev(self, "can't map memory space\n");
1654 return;
1655 }
1656 }
1657 if (nolinear == 0)
1658 sc->ti_vhandle = bus_space_vaddr(sc->ti_btag, sc->ti_bhandle);
1659 else
1660 sc->ti_vhandle = NULL;
1661
1662 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
1663 command |= PCI_COMMAND_MASTER_ENABLE;
1664 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
1665
1666 /* Allocate interrupt */
1667 if (pci_intr_map(pa, &ih)) {
1668 aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n");
1669 return;
1670 }
1671 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
1672 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, ti_intr, sc,
1673 device_xname(self));
1674 if (sc->sc_ih == NULL) {
1675 aprint_error_dev(sc->sc_dev, "couldn't establish interrupt");
1676 if (intrstr != NULL)
1677 aprint_error(" at %s", intrstr);
1678 aprint_error("\n");
1679 return;
1680 }
1681 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
1682
1683 if (ti_chipinit(sc)) {
1684 aprint_error_dev(self, "chip initialization failed\n");
1685 goto fail2;
1686 }
1687
1688 /*
1689 * Deal with some chip diffrences.
1690 */
1691 switch (sc->ti_hwrev) {
1692 case TI_HWREV_TIGON:
1693 sc->sc_tx_encap = ti_encap_tigon1;
1694 sc->sc_tx_eof = ti_txeof_tigon1;
1695 if (nolinear == 1)
1696 aprint_error_dev(self,
1697 "memory space not mapped linear\n");
1698 break;
1699
1700 case TI_HWREV_TIGON_II:
1701 sc->sc_tx_encap = ti_encap_tigon2;
1702 sc->sc_tx_eof = ti_txeof_tigon2;
1703 break;
1704
1705 default:
1706 aprint_error_dev(self, "Unknown chip version: %d\n",
1707 sc->ti_hwrev);
1708 goto fail2;
1709 }
1710
1711 /* Zero out the NIC's on-board SRAM. */
1712 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
1713
1714 /* Init again -- zeroing memory may have clobbered some registers. */
1715 if (ti_chipinit(sc)) {
1716 aprint_error_dev(self, "chip initialization failed\n");
1717 goto fail2;
1718 }
1719
1720 /*
1721 * Get station address from the EEPROM. Note: the manual states
1722 * that the MAC address is at offset 0x8c, however the data is
1723 * stored as two longwords (since that's how it's loaded into
1724 * the NIC). This means the MAC address is actually preceded
1725 * by two zero bytes. We need to skip over those.
1726 */
1727 if (ti_read_eeprom(sc, (void *)&eaddr,
1728 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1729 aprint_error_dev(self, "failed to read station address\n");
1730 goto fail2;
1731 }
1732
1733 /*
1734 * A Tigon chip was detected. Inform the world.
1735 */
1736 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr));
1737
1738 sc->sc_dmat = pa->pa_dmat;
1739
1740 /* Allocate the general information block and ring buffers. */
1741 if ((error = bus_dmamem_alloc(sc->sc_dmat,
1742 sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg,
1743 BUS_DMA_NOWAIT)) != 0) {
1744 aprint_error_dev(self,
1745 "can't allocate ring buffer, error = %d\n", error);
1746 goto fail2;
1747 }
1748
1749 if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg,
1750 sizeof(struct ti_ring_data), (void **)&sc->ti_rdata,
1751 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
1752 aprint_error_dev(self,
1753 "can't map ring buffer, error = %d\n", error);
1754 goto fail2;
1755 }
1756
1757 if ((error = bus_dmamap_create(sc->sc_dmat,
1758 sizeof(struct ti_ring_data), 1,
1759 sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT,
1760 &sc->info_dmamap)) != 0) {
1761 aprint_error_dev(self,
1762 "can't create ring buffer DMA map, error = %d\n", error);
1763 goto fail2;
1764 }
1765
1766 if ((error = bus_dmamap_load(sc->sc_dmat, sc->info_dmamap,
1767 sc->ti_rdata, sizeof(struct ti_ring_data), NULL,
1768 BUS_DMA_NOWAIT)) != 0) {
1769 aprint_error_dev(self,
1770 "can't load ring buffer DMA map, error = %d\n", error);
1771 goto fail2;
1772 }
1773
1774 sc->info_dmaaddr = sc->info_dmamap->dm_segs[0].ds_addr;
1775
1776 memset(sc->ti_rdata, 0, sizeof(struct ti_ring_data));
1777
1778 /* Try to allocate memory for jumbo buffers. */
1779 if (ti_alloc_jumbo_mem(sc)) {
1780 aprint_error_dev(self, "jumbo buffer allocation failed\n");
1781 goto fail2;
1782 }
1783
1784 SIMPLEQ_INIT(&sc->ti_mc_listhead);
1785
1786 /*
1787 * We really need a better way to tell a 1000baseT card
1788 * from a 1000baseSX one, since in theory there could be
1789 * OEMed 1000baseT cards from lame vendors who aren't
1790 * clever enough to change the PCI ID. For the moment
1791 * though, the AceNIC is the only copper card available.
1792 */
1793 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALTEON &&
1794 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALTEON_ACENIC_COPPER) ||
1795 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NETGEAR &&
1796 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETGEAR_GA620T))
1797 sc->ti_copper = 1;
1798 else
1799 sc->ti_copper = 0;
1800
1801 /* Set default tuneable values. */
1802 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
1803 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
1804 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
1805 sc->ti_rx_max_coal_bds = 64;
1806 sc->ti_tx_max_coal_bds = 128;
1807 sc->ti_tx_buf_ratio = 21;
1808
1809 /* Set up ifnet structure */
1810 ifp = &sc->ethercom.ec_if;
1811 ifp->if_softc = sc;
1812 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
1813 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1814 ifp->if_ioctl = ti_ioctl;
1815 ifp->if_start = ti_start;
1816 ifp->if_watchdog = ti_watchdog;
1817 IFQ_SET_READY(&ifp->if_snd);
1818
1819 #if 0
1820 /*
1821 * XXX This is not really correct -- we don't necessarily
1822 * XXX want to queue up as many as we can transmit at the
1823 * XXX upper layer like that. Someone with a board should
1824 * XXX check to see how this affects performance.
1825 */
1826 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
1827 #endif
1828
1829 /*
1830 * We can support 802.1Q VLAN-sized frames.
1831 */
1832 sc->ethercom.ec_capabilities |=
1833 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING;
1834 sc->ethercom.ec_capenable |= ETHERCAP_VLAN_HWTAGGING;
1835
1836 /*
1837 * We can do IPv4, TCPv4, and UDPv4 checksums in hardware.
1838 */
1839 ifp->if_capabilities |=
1840 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
1841 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
1842 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx;
1843
1844 /* Set up ifmedia support. */
1845 sc->ethercom.ec_ifmedia = &sc->ifmedia;
1846 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
1847 if (sc->ti_copper) {
1848 /*
1849 * Copper cards allow manual 10/100 mode selection,
1850 * but not manual 1000baseT mode selection. Why?
1851 * Because currently there's no way to specify the
1852 * master/slave setting through the firmware interface,
1853 * so Alteon decided to just bag it and handle it
1854 * via autonegotiation.
1855 */
1856 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
1857 ifmedia_add(&sc->ifmedia,
1858 IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
1859 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
1860 ifmedia_add(&sc->ifmedia,
1861 IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
1862 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
1863 ifmedia_add(&sc->ifmedia,
1864 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1865 } else {
1866 /* Fiber cards don't support 10/100 modes. */
1867 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
1868 ifmedia_add(&sc->ifmedia,
1869 IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL);
1870 }
1871 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
1872 ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_AUTO);
1873
1874 /*
1875 * Call MI attach routines.
1876 */
1877 if_attach(ifp);
1878 if_deferred_start_init(ifp, NULL);
1879 ether_ifattach(ifp, eaddr);
1880
1881 /*
1882 * Add shutdown hook so that DMA is disabled prior to reboot. Not
1883 * doing do could allow DMA to corrupt kernel memory during the
1884 * reboot before the driver initializes.
1885 */
1886 if (pmf_device_register1(self, NULL, NULL, ti_shutdown))
1887 pmf_class_network_register(self, ifp);
1888 else
1889 aprint_error_dev(self, "couldn't establish power handler\n");
1890
1891 return;
1892 fail2:
1893 pci_intr_disestablish(pc, sc->sc_ih);
1894 return;
1895 }
1896
1897 /*
1898 * Frame reception handling. This is called if there's a frame
1899 * on the receive return list.
1900 *
1901 * Note: we have to be able to handle three possibilities here:
1902 * 1) the frame is from the mini receive ring (can only happen)
1903 * on Tigon 2 boards)
1904 * 2) the frame is from the jumbo receive ring
1905 * 3) the frame is from the standard receive ring
1906 */
1907
1908 static void
ti_rxeof(struct ti_softc * sc)1909 ti_rxeof(struct ti_softc *sc)
1910 {
1911 struct ifnet *ifp;
1912 struct ti_cmd_desc cmd;
1913
1914 ifp = &sc->ethercom.ec_if;
1915
1916 while (sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
1917 struct ti_rx_desc *cur_rx;
1918 uint32_t rxidx;
1919 struct mbuf *m = NULL;
1920 struct ether_header *eh;
1921 bus_dmamap_t dmamap;
1922
1923 cur_rx =
1924 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
1925 rxidx = cur_rx->ti_idx;
1926 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
1927
1928 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
1929 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
1930 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
1931 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
1932 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1933 if_statinc(ifp, if_ierrors);
1934 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1935 continue;
1936 }
1937 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL)
1938 == ENOBUFS) {
1939 if_statinc(ifp, if_ierrors);
1940 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1941 continue;
1942 }
1943 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
1944 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
1945 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
1946 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
1947 dmamap = sc->mini_dmamap[rxidx];
1948 sc->mini_dmamap[rxidx] = 0;
1949 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1950 if_statinc(ifp, if_ierrors);
1951 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap);
1952 continue;
1953 }
1954 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap)
1955 == ENOBUFS) {
1956 if_statinc(ifp, if_ierrors);
1957 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap);
1958 continue;
1959 }
1960 } else {
1961 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
1962 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
1963 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
1964 dmamap = sc->std_dmamap[rxidx];
1965 sc->std_dmamap[rxidx] = 0;
1966 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1967 if_statinc(ifp, if_ierrors);
1968 ti_newbuf_std(sc, sc->ti_std, m, dmamap);
1969 continue;
1970 }
1971 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap)
1972 == ENOBUFS) {
1973 if_statinc(ifp, if_ierrors);
1974 ti_newbuf_std(sc, sc->ti_std, m, dmamap);
1975 continue;
1976 }
1977 }
1978
1979 m->m_pkthdr.len = m->m_len = cur_rx->ti_len;
1980 m_set_rcvif(m, ifp);
1981
1982 eh = mtod(m, struct ether_header *);
1983 switch (ntohs(eh->ether_type)) {
1984 #ifdef INET
1985 case ETHERTYPE_IP:
1986 {
1987 struct ip *ip = (struct ip *) (eh + 1);
1988
1989 /*
1990 * Note the Tigon firmware does not invert
1991 * the checksum for us, hence the XOR.
1992 */
1993 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
1994 if ((cur_rx->ti_ip_cksum ^ 0xffff) != 0)
1995 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
1996 /*
1997 * ntohs() the constant so the compiler can
1998 * optimize...
1999 *
2000 * XXX Figure out a sane way to deal with
2001 * fragmented packets.
2002 */
2003 if ((ip->ip_off & htons(IP_MF | IP_OFFMASK)) == 0) {
2004 switch (ip->ip_p) {
2005 case IPPROTO_TCP:
2006 m->m_pkthdr.csum_data =
2007 cur_rx->ti_tcp_udp_cksum;
2008 m->m_pkthdr.csum_flags |=
2009 M_CSUM_TCPv4 | M_CSUM_DATA;
2010 break;
2011 case IPPROTO_UDP:
2012 m->m_pkthdr.csum_data =
2013 cur_rx->ti_tcp_udp_cksum;
2014 m->m_pkthdr.csum_flags |=
2015 M_CSUM_UDPv4 | M_CSUM_DATA;
2016 break;
2017 default:
2018 /* Nothing */;
2019 }
2020 }
2021 break;
2022 }
2023 #endif
2024 default:
2025 /* Nothing. */
2026 break;
2027 }
2028
2029 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG)
2030 vlan_set_tag(m, cur_rx->ti_vlan_tag);
2031
2032 if_percpuq_enqueue(ifp->if_percpuq, m);
2033 }
2034
2035 /* Only necessary on the Tigon 1. */
2036 if (sc->ti_hwrev == TI_HWREV_TIGON)
2037 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
2038 sc->ti_rx_saved_considx);
2039
2040 TI_UPDATE_STDPROD(sc, sc->ti_std);
2041 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
2042 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
2043 }
2044
2045 static void
ti_txeof_tigon1(struct ti_softc * sc)2046 ti_txeof_tigon1(struct ti_softc *sc)
2047 {
2048 struct ti_tx_desc *cur_tx = NULL;
2049 struct ifnet *ifp;
2050 struct txdmamap_pool_entry *dma;
2051
2052 ifp = &sc->ethercom.ec_if;
2053
2054 /*
2055 * Go through our tx ring and free mbufs for those
2056 * frames that have been sent.
2057 */
2058 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
2059 uint32_t idx = 0;
2060
2061 idx = sc->ti_tx_saved_considx;
2062 if (idx > 383)
2063 CSR_WRITE_4(sc, TI_WINBASE,
2064 TI_TX_RING_BASE + 6144);
2065 else if (idx > 255)
2066 CSR_WRITE_4(sc, TI_WINBASE,
2067 TI_TX_RING_BASE + 4096);
2068 else if (idx > 127)
2069 CSR_WRITE_4(sc, TI_WINBASE,
2070 TI_TX_RING_BASE + 2048);
2071 else
2072 CSR_WRITE_4(sc, TI_WINBASE,
2073 TI_TX_RING_BASE);
2074 cur_tx = &sc->ti_tx_ring_nic[idx % 128];
2075 if (cur_tx->ti_flags & TI_BDFLAG_END)
2076 if_statinc(ifp, if_opackets);
2077 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
2078 dma = sc->txdma[idx];
2079 KDASSERT(dma != NULL);
2080 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0,
2081 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
2082 bus_dmamap_unload(sc->sc_dmat, dma->dmamap);
2083
2084 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link);
2085 sc->txdma[idx] = NULL;
2086
2087 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
2088 sc->ti_cdata.ti_tx_chain[idx] = NULL;
2089 }
2090 sc->ti_txcnt--;
2091 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
2092 ifp->if_timer = 0;
2093 }
2094
2095 if (cur_tx != NULL)
2096 ifp->if_flags &= ~IFF_OACTIVE;
2097 }
2098
2099 static void
ti_txeof_tigon2(struct ti_softc * sc)2100 ti_txeof_tigon2(struct ti_softc *sc)
2101 {
2102 struct ti_tx_desc *cur_tx = NULL;
2103 struct ifnet *ifp;
2104 struct txdmamap_pool_entry *dma;
2105 int firstidx, cnt;
2106
2107 ifp = &sc->ethercom.ec_if;
2108
2109 /*
2110 * Go through our tx ring and free mbufs for those
2111 * frames that have been sent.
2112 */
2113 firstidx = sc->ti_tx_saved_considx;
2114 cnt = 0;
2115 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
2116 uint32_t idx = 0;
2117
2118 idx = sc->ti_tx_saved_considx;
2119 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
2120 if (cur_tx->ti_flags & TI_BDFLAG_END)
2121 if_statinc(ifp, if_opackets);
2122 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
2123 dma = sc->txdma[idx];
2124 KDASSERT(dma != NULL);
2125 bus_dmamap_sync(sc->sc_dmat, dma->dmamap, 0,
2126 dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
2127 bus_dmamap_unload(sc->sc_dmat, dma->dmamap);
2128
2129 SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link);
2130 sc->txdma[idx] = NULL;
2131
2132 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
2133 sc->ti_cdata.ti_tx_chain[idx] = NULL;
2134 }
2135 cnt++;
2136 sc->ti_txcnt--;
2137 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
2138 ifp->if_timer = 0;
2139 }
2140
2141 if (cnt != 0)
2142 TI_CDTXSYNC(sc, firstidx, cnt, BUS_DMASYNC_POSTWRITE);
2143
2144 if (cur_tx != NULL)
2145 ifp->if_flags &= ~IFF_OACTIVE;
2146 }
2147
2148 static int
ti_intr(void * xsc)2149 ti_intr(void *xsc)
2150 {
2151 struct ti_softc *sc;
2152 struct ifnet *ifp;
2153
2154 sc = xsc;
2155 ifp = &sc->ethercom.ec_if;
2156
2157 #ifdef notdef
2158 /* Avoid this for now -- checking this register is expensive. */
2159 /* Make sure this is really our interrupt. */
2160 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE))
2161 return (0);
2162 #endif
2163
2164 /* Ack interrupt and stop others from occurring. */
2165 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2166
2167 if (ifp->if_flags & IFF_RUNNING) {
2168 /* Check RX return ring producer/consumer */
2169 ti_rxeof(sc);
2170
2171 /* Check TX ring producer/consumer */
2172 (*sc->sc_tx_eof)(sc);
2173 }
2174
2175 ti_handle_events(sc);
2176
2177 /* Re-enable interrupts. */
2178 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2179
2180 if ((ifp->if_flags & IFF_RUNNING) != 0)
2181 if_schedule_deferred_start(ifp);
2182
2183 return (1);
2184 }
2185
2186 static void
ti_stats_update(struct ti_softc * sc)2187 ti_stats_update(struct ti_softc *sc)
2188 {
2189 struct ifnet *ifp = &sc->ethercom.ec_if;
2190
2191 TI_CDSTATSSYNC(sc, BUS_DMASYNC_POSTREAD);
2192
2193 uint64_t collisions =
2194 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
2195 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
2196 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
2197 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions);
2198 if_statadd(ifp, if_collisions, collisions - sc->ti_if_collisions);
2199 sc->ti_if_collisions = collisions;
2200
2201 TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD);
2202 }
2203
2204 /*
2205 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2206 * pointers to descriptors.
2207 */
2208 static int
ti_encap_tigon1(struct ti_softc * sc,struct mbuf * m_head,uint32_t * txidx)2209 ti_encap_tigon1(struct ti_softc *sc, struct mbuf *m_head, uint32_t *txidx)
2210 {
2211 struct ti_tx_desc *f = NULL;
2212 uint32_t frag, cur, cnt = 0;
2213 struct txdmamap_pool_entry *dma;
2214 bus_dmamap_t dmamap;
2215 int error, i;
2216 uint16_t csum_flags = 0;
2217
2218 dma = SIMPLEQ_FIRST(&sc->txdma_list);
2219 if (dma == NULL) {
2220 return ENOMEM;
2221 }
2222 dmamap = dma->dmamap;
2223
2224 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head,
2225 BUS_DMA_WRITE | BUS_DMA_NOWAIT);
2226 if (error) {
2227 struct mbuf *m;
2228 int j = 0;
2229 for (m = m_head; m; m = m->m_next)
2230 j++;
2231 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) "
2232 "error %d\n", m_head->m_pkthdr.len, j, error);
2233 return (ENOMEM);
2234 }
2235
2236 cur = frag = *txidx;
2237
2238 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) {
2239 /* IP header checksum field must be 0! */
2240 csum_flags |= TI_BDFLAG_IP_CKSUM;
2241 }
2242 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4))
2243 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
2244
2245 /* XXX fragmented packet checksum capability? */
2246
2247 /*
2248 * Start packing the mbufs in this chain into
2249 * the fragment pointers. Stop when we run out
2250 * of fragments or hit the end of the mbuf chain.
2251 */
2252 for (i = 0; i < dmamap->dm_nsegs; i++) {
2253 if (frag > 383)
2254 CSR_WRITE_4(sc, TI_WINBASE,
2255 TI_TX_RING_BASE + 6144);
2256 else if (frag > 255)
2257 CSR_WRITE_4(sc, TI_WINBASE,
2258 TI_TX_RING_BASE + 4096);
2259 else if (frag > 127)
2260 CSR_WRITE_4(sc, TI_WINBASE,
2261 TI_TX_RING_BASE + 2048);
2262 else
2263 CSR_WRITE_4(sc, TI_WINBASE,
2264 TI_TX_RING_BASE);
2265 f = &sc->ti_tx_ring_nic[frag % 128];
2266 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
2267 break;
2268 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr;
2269 f->ti_len = dmamap->dm_segs[i].ds_len;
2270 f->ti_flags = csum_flags;
2271 if (vlan_has_tag(m_head)) {
2272 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2273 f->ti_vlan_tag = vlan_get_tag(m_head);
2274 } else {
2275 f->ti_vlan_tag = 0;
2276 }
2277 /*
2278 * Sanity check: avoid coming within 16 descriptors
2279 * of the end of the ring.
2280 */
2281 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
2282 return (ENOBUFS);
2283 cur = frag;
2284 TI_INC(frag, TI_TX_RING_CNT);
2285 cnt++;
2286 }
2287
2288 if (i < dmamap->dm_nsegs)
2289 return (ENOBUFS);
2290
2291 if (frag == sc->ti_tx_saved_considx)
2292 return (ENOBUFS);
2293
2294 sc->ti_tx_ring_nic[cur % 128].ti_flags |=
2295 TI_BDFLAG_END;
2296
2297 /* Sync the packet's DMA map. */
2298 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
2299 BUS_DMASYNC_PREWRITE);
2300
2301 sc->ti_cdata.ti_tx_chain[cur] = m_head;
2302 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link);
2303 sc->txdma[cur] = dma;
2304 sc->ti_txcnt += cnt;
2305
2306 *txidx = frag;
2307
2308 return (0);
2309 }
2310
2311 static int
ti_encap_tigon2(struct ti_softc * sc,struct mbuf * m_head,uint32_t * txidx)2312 ti_encap_tigon2(struct ti_softc *sc, struct mbuf *m_head, uint32_t *txidx)
2313 {
2314 struct ti_tx_desc *f = NULL;
2315 uint32_t frag, firstfrag, cur, cnt = 0;
2316 struct txdmamap_pool_entry *dma;
2317 bus_dmamap_t dmamap;
2318 int error, i;
2319 uint16_t csum_flags = 0;
2320
2321 dma = SIMPLEQ_FIRST(&sc->txdma_list);
2322 if (dma == NULL) {
2323 return ENOMEM;
2324 }
2325 dmamap = dma->dmamap;
2326
2327 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m_head,
2328 BUS_DMA_WRITE | BUS_DMA_NOWAIT);
2329 if (error) {
2330 struct mbuf *m;
2331 int j = 0;
2332 for (m = m_head; m; m = m->m_next)
2333 j++;
2334 printf("ti_encap: bus_dmamap_load_mbuf (len %d, %d frags) "
2335 "error %d\n", m_head->m_pkthdr.len, j, error);
2336 return (ENOMEM);
2337 }
2338
2339 cur = firstfrag = frag = *txidx;
2340
2341 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) {
2342 /* IP header checksum field must be 0! */
2343 csum_flags |= TI_BDFLAG_IP_CKSUM;
2344 }
2345 if (m_head->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4))
2346 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
2347
2348 /* XXX fragmented packet checksum capability? */
2349
2350 /*
2351 * Start packing the mbufs in this chain into
2352 * the fragment pointers. Stop when we run out
2353 * of fragments or hit the end of the mbuf chain.
2354 */
2355 for (i = 0; i < dmamap->dm_nsegs; i++) {
2356 f = &sc->ti_rdata->ti_tx_ring[frag];
2357 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
2358 break;
2359 TI_HOSTADDR(f->ti_addr) = dmamap->dm_segs[i].ds_addr;
2360 f->ti_len = dmamap->dm_segs[i].ds_len;
2361 f->ti_flags = csum_flags;
2362 if (vlan_has_tag(m_head)) {
2363 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
2364 f->ti_vlan_tag = vlan_get_tag(m_head);
2365 } else {
2366 f->ti_vlan_tag = 0;
2367 }
2368 /*
2369 * Sanity check: avoid coming within 16 descriptors
2370 * of the end of the ring.
2371 */
2372 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
2373 return (ENOBUFS);
2374 cur = frag;
2375 TI_INC(frag, TI_TX_RING_CNT);
2376 cnt++;
2377 }
2378
2379 if (i < dmamap->dm_nsegs)
2380 return (ENOBUFS);
2381
2382 if (frag == sc->ti_tx_saved_considx)
2383 return (ENOBUFS);
2384
2385 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
2386
2387 /* Sync the packet's DMA map. */
2388 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
2389 BUS_DMASYNC_PREWRITE);
2390
2391 /* Sync the descriptors we are using. */
2392 TI_CDTXSYNC(sc, firstfrag, cnt, BUS_DMASYNC_PREWRITE);
2393
2394 sc->ti_cdata.ti_tx_chain[cur] = m_head;
2395 SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link);
2396 sc->txdma[cur] = dma;
2397 sc->ti_txcnt += cnt;
2398
2399 *txidx = frag;
2400
2401 return (0);
2402 }
2403
2404 /*
2405 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2406 * to the mbuf data regions directly in the transmit descriptors.
2407 */
2408 static void
ti_start(struct ifnet * ifp)2409 ti_start(struct ifnet *ifp)
2410 {
2411 struct ti_softc *sc;
2412 struct mbuf *m_head = NULL;
2413 uint32_t prodidx = 0;
2414
2415 sc = ifp->if_softc;
2416
2417 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
2418
2419 while (sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
2420 IFQ_POLL(&ifp->if_snd, m_head);
2421 if (m_head == NULL)
2422 break;
2423
2424 /*
2425 * Pack the data into the transmit ring. If we
2426 * don't have room, set the OACTIVE flag and wait
2427 * for the NIC to drain the ring.
2428 */
2429 if ((*sc->sc_tx_encap)(sc, m_head, &prodidx)) {
2430 ifp->if_flags |= IFF_OACTIVE;
2431 break;
2432 }
2433
2434 IFQ_DEQUEUE(&ifp->if_snd, m_head);
2435
2436 /*
2437 * If there's a BPF listener, bounce a copy of this frame
2438 * to him.
2439 */
2440 bpf_mtap(ifp, m_head, BPF_D_OUT);
2441 }
2442
2443 /* Transmit */
2444 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
2445
2446 /* Set a timeout in case the chip goes out to lunch. */
2447 ifp->if_timer = 5;
2448 }
2449
2450 static void
ti_init(void * xsc)2451 ti_init(void *xsc)
2452 {
2453 struct ti_softc *sc = xsc;
2454 int s;
2455
2456 s = splnet();
2457
2458 /* Cancel pending I/O and flush buffers. */
2459 ti_stop(sc);
2460
2461 /* Init the gen info block, ring control blocks and firmware. */
2462 if (ti_gibinit(sc)) {
2463 aprint_error_dev(sc->sc_dev, "initialization failure\n");
2464 splx(s);
2465 return;
2466 }
2467
2468 splx(s);
2469 }
2470
2471 static void
ti_init2(struct ti_softc * sc)2472 ti_init2(struct ti_softc *sc)
2473 {
2474 struct ti_cmd_desc cmd;
2475 struct ifnet *ifp;
2476 const uint8_t *m;
2477 struct ifmedia *ifm;
2478 int tmp;
2479
2480 ifp = &sc->ethercom.ec_if;
2481
2482 /* Specify MTU and interface index. */
2483 CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_unit(sc->sc_dev)); /* ??? */
2484
2485 tmp = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2486 if (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU)
2487 tmp += ETHER_VLAN_ENCAP_LEN;
2488 CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp);
2489
2490 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
2491
2492 /* Load our MAC address. */
2493 m = (const uint8_t *)CLLADDR(ifp->if_sadl);
2494 CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]);
2495 CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16)
2496 | (m[4] << 8) | m[5]);
2497 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
2498
2499 /* Enable or disable promiscuous mode as needed. */
2500 if (ifp->if_flags & IFF_PROMISC) {
2501 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
2502 } else {
2503 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
2504 }
2505
2506 /* Program multicast filter. */
2507 ti_setmulti(sc);
2508
2509 /*
2510 * If this is a Tigon 1, we should tell the
2511 * firmware to use software packet filtering.
2512 */
2513 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2514 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
2515 }
2516
2517 /* Init RX ring. */
2518 ti_init_rx_ring_std(sc);
2519
2520 /* Init jumbo RX ring. */
2521 if (ifp->if_mtu > (MCLBYTES - ETHER_HDR_LEN - ETHER_CRC_LEN))
2522 ti_init_rx_ring_jumbo(sc);
2523
2524 /*
2525 * If this is a Tigon 2, we can also configure the
2526 * mini ring.
2527 */
2528 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
2529 ti_init_rx_ring_mini(sc);
2530
2531 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2532 sc->ti_rx_saved_considx = 0;
2533
2534 /* Init TX ring. */
2535 ti_init_tx_ring(sc);
2536
2537 /* Tell firmware we're alive. */
2538 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
2539
2540 /* Enable host interrupts. */
2541 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2542
2543 ifp->if_flags |= IFF_RUNNING;
2544 ifp->if_flags &= ~IFF_OACTIVE;
2545
2546 /*
2547 * Make sure to set media properly. We have to do this
2548 * here since we have to issue commands in order to set
2549 * the link negotiation and we can't issue commands until
2550 * the firmware is running.
2551 */
2552 ifm = &sc->ifmedia;
2553 tmp = ifm->ifm_media;
2554 ifm->ifm_media = ifm->ifm_cur->ifm_media;
2555 ti_ifmedia_upd(ifp);
2556 ifm->ifm_media = tmp;
2557 }
2558
2559 /*
2560 * Set media options.
2561 */
2562 static int
ti_ifmedia_upd(struct ifnet * ifp)2563 ti_ifmedia_upd(struct ifnet *ifp)
2564 {
2565 struct ti_softc *sc;
2566 struct ifmedia *ifm;
2567 struct ti_cmd_desc cmd;
2568
2569 sc = ifp->if_softc;
2570 ifm = &sc->ifmedia;
2571
2572 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2573 return (EINVAL);
2574
2575 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2576 case IFM_AUTO:
2577 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF | TI_GLNK_1000MB |
2578 TI_GLNK_FULL_DUPLEX | TI_GLNK_RX_FLOWCTL_Y |
2579 TI_GLNK_AUTONEGENB | TI_GLNK_ENB);
2580 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB | TI_LNK_10MB |
2581 TI_LNK_FULL_DUPLEX | TI_LNK_HALF_DUPLEX |
2582 TI_LNK_AUTONEGENB | TI_LNK_ENB);
2583 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2584 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
2585 break;
2586 case IFM_1000_SX:
2587 case IFM_1000_T:
2588 if ((ifm->ifm_media & IFM_FDX) != 0) {
2589 CSR_WRITE_4(sc, TI_GCR_GLINK,
2590 TI_GLNK_PREF | TI_GLNK_1000MB | TI_GLNK_FULL_DUPLEX
2591 | TI_GLNK_RX_FLOWCTL_Y | TI_GLNK_ENB);
2592 } else {
2593 CSR_WRITE_4(sc, TI_GCR_GLINK,
2594 TI_GLNK_PREF | TI_GLNK_1000MB |
2595 TI_GLNK_RX_FLOWCTL_Y | TI_GLNK_ENB);
2596 }
2597 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
2598 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2599 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
2600 break;
2601 case IFM_100_FX:
2602 case IFM_10_FL:
2603 case IFM_100_TX:
2604 case IFM_10_T:
2605 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
2606 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB | TI_LNK_PREF);
2607 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
2608 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
2609 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
2610 } else {
2611 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
2612 }
2613 if ((ifm->ifm_media & IFM_FDX) != 0) {
2614 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
2615 } else {
2616 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
2617 }
2618 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2619 TI_CMD_CODE_NEGOTIATE_10_100, 0);
2620 break;
2621 }
2622
2623 sc->ethercom.ec_if.if_baudrate =
2624 ifmedia_baudrate(ifm->ifm_media);
2625
2626 return (0);
2627 }
2628
2629 /*
2630 * Report current media status.
2631 */
2632 static void
ti_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)2633 ti_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2634 {
2635 struct ti_softc *sc;
2636 uint32_t media = 0;
2637
2638 sc = ifp->if_softc;
2639
2640 ifmr->ifm_status = IFM_AVALID;
2641 ifmr->ifm_active = IFM_ETHER;
2642
2643 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
2644 return;
2645
2646 ifmr->ifm_status |= IFM_ACTIVE;
2647
2648 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
2649 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
2650 if (sc->ti_copper)
2651 ifmr->ifm_active |= IFM_1000_T;
2652 else
2653 ifmr->ifm_active |= IFM_1000_SX;
2654 if (media & TI_GLNK_FULL_DUPLEX)
2655 ifmr->ifm_active |= IFM_FDX;
2656 else
2657 ifmr->ifm_active |= IFM_HDX;
2658 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
2659 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
2660 if (sc->ti_copper) {
2661 if (media & TI_LNK_100MB)
2662 ifmr->ifm_active |= IFM_100_TX;
2663 if (media & TI_LNK_10MB)
2664 ifmr->ifm_active |= IFM_10_T;
2665 } else {
2666 if (media & TI_LNK_100MB)
2667 ifmr->ifm_active |= IFM_100_FX;
2668 if (media & TI_LNK_10MB)
2669 ifmr->ifm_active |= IFM_10_FL;
2670 }
2671 if (media & TI_LNK_FULL_DUPLEX)
2672 ifmr->ifm_active |= IFM_FDX;
2673 if (media & TI_LNK_HALF_DUPLEX)
2674 ifmr->ifm_active |= IFM_HDX;
2675 }
2676
2677 sc->ethercom.ec_if.if_baudrate =
2678 ifmedia_baudrate(sc->ifmedia.ifm_media);
2679 }
2680
2681 static int
ti_ether_ioctl(struct ifnet * ifp,u_long cmd,void * data)2682 ti_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data)
2683 {
2684 struct ifaddr *ifa = (struct ifaddr *)data;
2685 struct ti_softc *sc = ifp->if_softc;
2686
2687 if ((ifp->if_flags & IFF_UP) == 0) {
2688 ifp->if_flags |= IFF_UP;
2689 ti_init(sc);
2690 }
2691
2692 switch (cmd) {
2693 case SIOCINITIFADDR:
2694
2695 switch (ifa->ifa_addr->sa_family) {
2696 #ifdef INET
2697 case AF_INET:
2698 arp_ifinit(ifp, ifa);
2699 break;
2700 #endif
2701 default:
2702 break;
2703 }
2704 break;
2705
2706 default:
2707 return (EINVAL);
2708 }
2709
2710 return (0);
2711 }
2712
2713 static int
ti_ioctl(struct ifnet * ifp,u_long command,void * data)2714 ti_ioctl(struct ifnet *ifp, u_long command, void *data)
2715 {
2716 struct ti_softc *sc = ifp->if_softc;
2717 struct ifreq *ifr = (struct ifreq *)data;
2718 int s, error = 0;
2719 struct ti_cmd_desc cmd;
2720
2721 s = splnet();
2722
2723 switch (command) {
2724 case SIOCINITIFADDR:
2725 error = ti_ether_ioctl(ifp, command, data);
2726 break;
2727 case SIOCSIFMTU:
2728 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO)
2729 error = EINVAL;
2730 else if ((error = ifioctl_common(ifp, command, data))
2731 == ENETRESET) {
2732 ti_init(sc);
2733 error = 0;
2734 }
2735 break;
2736 case SIOCSIFFLAGS:
2737 if ((error = ifioctl_common(ifp, command, data)) != 0)
2738 break;
2739 if (ifp->if_flags & IFF_UP) {
2740 /*
2741 * If only the state of the PROMISC flag changed,
2742 * then just use the 'set promisc mode' command
2743 * instead of reinitializing the entire NIC. Doing
2744 * a full re-init means reloading the firmware and
2745 * waiting for it to start up, which may take a
2746 * second or two.
2747 */
2748 if (ifp->if_flags & IFF_RUNNING &&
2749 ifp->if_flags & IFF_PROMISC &&
2750 !(sc->ti_if_flags & IFF_PROMISC)) {
2751 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2752 TI_CMD_CODE_PROMISC_ENB, 0);
2753 } else if (ifp->if_flags & IFF_RUNNING &&
2754 !(ifp->if_flags & IFF_PROMISC) &&
2755 sc->ti_if_flags & IFF_PROMISC) {
2756 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2757 TI_CMD_CODE_PROMISC_DIS, 0);
2758 } else
2759 ti_init(sc);
2760 } else {
2761 if (ifp->if_flags & IFF_RUNNING) {
2762 ti_stop(sc);
2763 }
2764 }
2765 sc->ti_if_flags = ifp->if_flags;
2766 error = 0;
2767 break;
2768 default:
2769 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET)
2770 break;
2771
2772 error = 0;
2773
2774 if (command == SIOCSIFCAP)
2775 ti_init(sc);
2776 else if (command != SIOCADDMULTI && command != SIOCDELMULTI)
2777 ;
2778 else if (ifp->if_flags & IFF_RUNNING)
2779 ti_setmulti(sc);
2780 break;
2781 }
2782
2783 (void)splx(s);
2784
2785 return (error);
2786 }
2787
2788 static void
ti_watchdog(struct ifnet * ifp)2789 ti_watchdog(struct ifnet *ifp)
2790 {
2791 struct ti_softc *sc;
2792
2793 sc = ifp->if_softc;
2794
2795 aprint_error_dev(sc->sc_dev, "watchdog timeout -- resetting\n");
2796 ti_stop(sc);
2797 ti_init(sc);
2798
2799 if_statinc(ifp, if_oerrors);
2800 }
2801
2802 /*
2803 * Stop the adapter and free any mbufs allocated to the
2804 * RX and TX lists.
2805 */
2806 static void
ti_stop(struct ti_softc * sc)2807 ti_stop(struct ti_softc *sc)
2808 {
2809 struct ifnet *ifp;
2810 struct ti_cmd_desc cmd;
2811
2812 ifp = &sc->ethercom.ec_if;
2813
2814 /* Disable host interrupts. */
2815 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2816 /*
2817 * Tell firmware we're shutting down.
2818 */
2819 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
2820
2821 /* Halt and reinitialize. */
2822 ti_chipinit(sc);
2823 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
2824 ti_chipinit(sc);
2825
2826 /* Free the RX lists. */
2827 ti_free_rx_ring_std(sc);
2828
2829 /* Free jumbo RX list. */
2830 ti_free_rx_ring_jumbo(sc);
2831
2832 /* Free mini RX list. */
2833 ti_free_rx_ring_mini(sc);
2834
2835 /* Free TX buffers. */
2836 ti_free_tx_ring(sc);
2837
2838 sc->ti_ev_prodidx.ti_idx = 0;
2839 sc->ti_return_prodidx.ti_idx = 0;
2840 sc->ti_tx_considx.ti_idx = 0;
2841 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
2842
2843 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2844 }
2845
2846 /*
2847 * Stop all chip I/O so that the kernel's probe routines don't
2848 * get confused by errant DMAs when rebooting.
2849 */
2850 static bool
ti_shutdown(device_t self,int howto)2851 ti_shutdown(device_t self, int howto)
2852 {
2853 struct ti_softc *sc;
2854
2855 sc = device_private(self);
2856 ti_chipinit(sc);
2857
2858 return true;
2859 }
2860