1 /* $OpenBSD: ti_iic.c,v 1.15 2021/10/24 17:52:28 mpi Exp $ */
2 /* $NetBSD: ti_iic.c,v 1.4 2013/04/25 13:04:27 rkujawa Exp $ */
3
4 /*
5 * Copyright (c) 2013 Manuel Bouyer. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 /*-
29 * Copyright (c) 2012 Jared D. McNeill <jmcneill@invisible.ca>
30 * All rights reserved.
31 *
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
34 * are met:
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. The name of the author may not be used to endorse or promote products
38 * derived from this software without specific prior written permission.
39 *
40 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
41 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
42 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
43 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
44 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
45 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
46 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
47 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
48 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
50 * SUCH DAMAGE.
51 */
52
53 #include <sys/param.h>
54 #include <sys/systm.h>
55 #include <sys/device.h>
56 #include <sys/rwlock.h>
57
58 #include <machine/bus.h>
59 #include <machine/intr.h>
60 #include <machine/fdt.h>
61
62 #include <dev/i2c/i2cvar.h>
63
64 #include <armv7/omap/prcmvar.h>
65 #include <armv7/omap/ti_iicreg.h>
66
67 #include <dev/ofw/openfirm.h>
68 #include <dev/ofw/ofw_pinctrl.h>
69 #include <dev/ofw/fdt.h>
70
71 #ifndef AM335X_I2C_SLAVE_ADDR
72 #define AM335X_I2C_SLAVE_ADDR 0x01
73 #endif
74
75 #ifdef I2CDEBUG
76 #define DPRINTF(args) printf args
77 #else
78 #define DPRINTF(args)
79 #endif
80
81 /* operation in progress */
82 typedef enum {
83 TI_I2CREAD,
84 TI_I2CWRITE,
85 TI_I2CDONE,
86 TI_I2CERROR
87 } ti_i2cop_t;
88
89 struct ti_iic_softc {
90 struct device sc_dev;
91 struct i2c_controller sc_ic;
92 struct rwlock sc_buslock;
93 struct device *sc_i2cdev;
94
95 bus_space_tag_t sc_iot;
96 bus_space_handle_t sc_ioh;
97
98 void *sc_ih;
99 int sc_node;
100 ti_i2cop_t sc_op;
101 int sc_buflen;
102 int sc_bufidx;
103 char *sc_buf;
104
105 int sc_rxthres;
106 int sc_txthres;
107 };
108
109
110 #define I2C_READ_REG(sc, reg) \
111 bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, (reg))
112 #define I2C_READ_DATA(sc) \
113 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, AM335X_I2C_DATA);
114 #define I2C_WRITE_REG(sc, reg, val) \
115 bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
116 #define I2C_WRITE_DATA(sc, val) \
117 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, AM335X_I2C_DATA, (val))
118
119 #define DEVNAME(sc) ((sc)->sc_dev.dv_xname)
120
121 int ti_iic_match(struct device *, void *, void *);
122 void ti_iic_attach(struct device *, struct device *, void *);
123 int ti_iic_intr(void *);
124
125 int ti_iic_acquire_bus(void *, int);
126 void ti_iic_release_bus(void *, int);
127 int ti_iic_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, void *,
128 size_t, int);
129 void ti_iic_scan(struct device *, struct i2cbus_attach_args *, void *);
130
131 int ti_iic_reset(struct ti_iic_softc *);
132 int ti_iic_op(struct ti_iic_softc *, i2c_addr_t, ti_i2cop_t, uint8_t *,
133 size_t, int);
134 void ti_iic_handle_intr(struct ti_iic_softc *, uint32_t);
135 void ti_iic_do_read(struct ti_iic_softc *, uint32_t);
136 void ti_iic_do_write(struct ti_iic_softc *, uint32_t);
137
138 int ti_iic_wait(struct ti_iic_softc *, uint16_t, uint16_t, int);
139 uint32_t ti_iic_stat(struct ti_iic_softc *, uint32_t);
140 int ti_iic_flush(struct ti_iic_softc *);
141
142 const struct cfattach tiiic_ca = {
143 sizeof (struct ti_iic_softc), ti_iic_match, ti_iic_attach
144 };
145
146 struct cfdriver tiiic_cd = {
147 NULL, "tiiic", DV_DULL
148 };
149
150 int
ti_iic_match(struct device * parent,void * match,void * aux)151 ti_iic_match(struct device *parent, void *match, void *aux)
152 {
153 struct fdt_attach_args *faa = aux;
154
155 return OF_is_compatible(faa->fa_node, "ti,omap4-i2c");
156 }
157
158 void
ti_iic_attach(struct device * parent,struct device * self,void * aux)159 ti_iic_attach(struct device *parent, struct device *self, void *aux)
160 {
161 struct ti_iic_softc *sc = (struct ti_iic_softc *)self;
162 struct fdt_attach_args *faa = aux;
163 struct i2cbus_attach_args iba;
164 uint16_t rev;
165 int unit, len;
166 char hwmods[128];
167
168 if (faa->fa_nreg < 1)
169 return;
170
171 sc->sc_iot = faa->fa_iot;
172 sc->sc_node = faa->fa_node;
173
174 unit = -1;
175 if ((len = OF_getprop(faa->fa_node, "ti,hwmods", hwmods,
176 sizeof(hwmods))) == 5) {
177 if (!strncmp(hwmods, "i2c", 3) &&
178 (hwmods[3] > '0') && (hwmods[3] <= '9'))
179 unit = hwmods[3] - '1';
180 }
181
182 rw_init(&sc->sc_buslock, "tiiilk");
183
184 sc->sc_rxthres = sc->sc_txthres = 4;
185
186 if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr,
187 faa->fa_reg[0].size, 0, &sc->sc_ioh))
188 panic("%s: bus_space_map failed!", DEVNAME(sc));
189
190 pinctrl_byname(faa->fa_node, "default");
191
192 sc->sc_ih = arm_intr_establish_fdt(faa->fa_node, IPL_NET,
193 ti_iic_intr, sc, DEVNAME(sc));
194
195 if (unit != -1)
196 prcm_enablemodule(PRCM_I2C0 + unit);
197
198 rev = I2C_READ_REG(sc, AM335X_I2C_REVNB_LO);
199 printf(" rev %d.%d\n",
200 (int)I2C_REVNB_LO_MAJOR(rev),
201 (int)I2C_REVNB_LO_MINOR(rev));
202
203 ti_iic_reset(sc);
204 ti_iic_flush(sc);
205
206 sc->sc_ic.ic_cookie = sc;
207 sc->sc_ic.ic_acquire_bus = ti_iic_acquire_bus;
208 sc->sc_ic.ic_release_bus = ti_iic_release_bus;
209 sc->sc_ic.ic_exec = ti_iic_exec;
210
211 bzero(&iba, sizeof iba);
212 iba.iba_name = "iic";
213 iba.iba_tag = &sc->sc_ic;
214 iba.iba_bus_scan = ti_iic_scan;
215 iba.iba_bus_scan_arg = &sc->sc_node;
216 (void) config_found(&sc->sc_dev, &iba, iicbus_print);
217 }
218
219 int
ti_iic_intr(void * arg)220 ti_iic_intr(void *arg)
221 {
222 struct ti_iic_softc *sc = arg;
223 uint32_t stat;
224
225 DPRINTF(("ti_iic_intr\n"));
226 stat = I2C_READ_REG(sc, AM335X_I2C_IRQSTATUS);
227 I2C_WRITE_REG(sc, AM335X_I2C_IRQSTATUS, stat);
228 DPRINTF(("ti_iic_intr pre handle sc->sc_op eq %#x\n", sc->sc_op));
229
230 ti_iic_handle_intr(sc, stat);
231
232 if (sc->sc_op == TI_I2CERROR || sc->sc_op == TI_I2CDONE) {
233 DPRINTF(("ti_iic_intr post handle sc->sc_op %#x\n", sc->sc_op));
234 wakeup(&sc->sc_dev);
235 }
236
237 DPRINTF(("ti_iic_intr status 0x%x\n", stat));
238
239 return 1;
240 }
241
242 int
ti_iic_acquire_bus(void * opaque,int flags)243 ti_iic_acquire_bus(void *opaque, int flags)
244 {
245 struct ti_iic_softc *sc = opaque;
246
247 if (flags & I2C_F_POLL)
248 return 0;
249
250 return (rw_enter(&sc->sc_buslock, RW_WRITE));
251 }
252
253 void
ti_iic_release_bus(void * opaque,int flags)254 ti_iic_release_bus(void *opaque, int flags)
255 {
256 struct ti_iic_softc *sc = opaque;
257
258 if (flags & I2C_F_POLL)
259 return;
260
261 rw_exit(&sc->sc_buslock);
262 }
263
264 int
ti_iic_exec(void * opaque,i2c_op_t op,i2c_addr_t addr,const void * cmdbuf,size_t cmdlen,void * buf,size_t len,int flags)265 ti_iic_exec(void *opaque, i2c_op_t op, i2c_addr_t addr,
266 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags)
267 {
268 struct ti_iic_softc *sc = opaque;
269 int err = 0;
270
271 DPRINTF(("ti_iic_exec: op 0x%x cmdlen %zd len %zd flags 0x%x\n",
272 op, cmdlen, len, flags));
273
274 #define __UNCONST(a) ((void *)(unsigned long)(const void *)(a))
275 if (cmdlen > 0) {
276 err = ti_iic_op(sc, addr, TI_I2CWRITE, __UNCONST(cmdbuf),
277 cmdlen, (I2C_OP_READ_P(op) ? 0 : I2C_F_STOP) | flags);
278 if (err)
279 goto done;
280 }
281 if (I2C_OP_STOP_P(op))
282 flags |= I2C_F_STOP;
283
284 /*
285 * I2C controller doesn't allow for zero-byte transfers.
286 */
287 if (len == 0)
288 goto done;
289
290 if (I2C_OP_READ_P(op))
291 err = ti_iic_op(sc, addr, TI_I2CREAD, buf, len, flags);
292 else
293 err = ti_iic_op(sc, addr, TI_I2CWRITE, buf, len, flags);
294
295 done:
296 if (err)
297 ti_iic_reset(sc);
298
299 ti_iic_flush(sc);
300
301 DPRINTF(("ti_iic_exec: done %d\n", err));
302 return err;
303 }
304
305 int
ti_iic_reset(struct ti_iic_softc * sc)306 ti_iic_reset(struct ti_iic_softc *sc)
307 {
308 uint32_t psc, scll, sclh;
309 int i;
310
311 DPRINTF(("ti_iic_reset\n"));
312
313 /* Disable */
314 I2C_WRITE_REG(sc, AM335X_I2C_CON, 0);
315 /* Soft reset */
316 I2C_WRITE_REG(sc, AM335X_I2C_SYSC, I2C_SYSC_SRST);
317 delay(1000);
318 /* enable so that we can check for reset complete */
319 I2C_WRITE_REG(sc, AM335X_I2C_CON, I2C_CON_EN);
320 delay(1000);
321 for (i = 0; i < 1000; i++) { /* 1s delay for reset */
322 if (I2C_READ_REG(sc, AM335X_I2C_SYSS) & I2C_SYSS_RDONE)
323 break;
324 }
325 /* Disable again */
326 I2C_WRITE_REG(sc, AM335X_I2C_CON, 0);
327 delay(50000);
328
329 if (i >= 1000) {
330 printf("%s: couldn't reset module\n", DEVNAME(sc));
331 return 1;
332 }
333
334 /* XXX standard speed only */
335 psc = 3;
336 scll = 53;
337 sclh = 55;
338
339 /* Clocks */
340 I2C_WRITE_REG(sc, AM335X_I2C_PSC, psc);
341 I2C_WRITE_REG(sc, AM335X_I2C_SCLL, scll);
342 I2C_WRITE_REG(sc, AM335X_I2C_SCLH, sclh);
343
344 /* Own I2C address */
345 I2C_WRITE_REG(sc, AM335X_I2C_OA, AM335X_I2C_SLAVE_ADDR);
346
347 /* 5 bytes fifo */
348 I2C_WRITE_REG(sc, AM335X_I2C_BUF,
349 I2C_BUF_RXTRSH(sc->sc_rxthres) | I2C_BUF_TXTRSH(sc->sc_txthres));
350
351 /* Enable */
352 I2C_WRITE_REG(sc, AM335X_I2C_CON, I2C_CON_EN);
353
354 return 0;
355 }
356
357 int
ti_iic_op(struct ti_iic_softc * sc,i2c_addr_t addr,ti_i2cop_t op,uint8_t * buf,size_t buflen,int flags)358 ti_iic_op(struct ti_iic_softc *sc, i2c_addr_t addr, ti_i2cop_t op,
359 uint8_t *buf, size_t buflen, int flags)
360 {
361 uint16_t con, stat, mask;
362 int err, retry;
363
364 KASSERT(op == TI_I2CREAD || op == TI_I2CWRITE);
365 DPRINTF(("ti_iic_op: addr %#x op %#x buf %p buflen %#x flags %#x\n",
366 addr, op, buf, (unsigned int) buflen, flags));
367
368 mask = I2C_IRQSTATUS_ARDY | I2C_IRQSTATUS_NACK | I2C_IRQSTATUS_AL;
369 if (op == TI_I2CREAD)
370 mask |= I2C_IRQSTATUS_RDR | I2C_IRQSTATUS_RRDY;
371 else
372 mask |= I2C_IRQSTATUS_XDR | I2C_IRQSTATUS_XRDY;
373
374 err = ti_iic_wait(sc, I2C_IRQSTATUS_BB, 0, flags);
375 if (err) {
376 DPRINTF(("ti_iic_op: wait error %d\n", err));
377 return err;
378 }
379
380 con = I2C_CON_EN;
381 con |= I2C_CON_MST;
382 con |= I2C_CON_STT;
383 if (flags & I2C_F_STOP)
384 con |= I2C_CON_STP;
385 if (addr & ~0x7f)
386 con |= I2C_CON_XSA;
387 if (op == TI_I2CWRITE)
388 con |= I2C_CON_TRX;
389
390 sc->sc_op = op;
391 sc->sc_buf = buf;
392 sc->sc_buflen = buflen;
393 sc->sc_bufidx = 0;
394
395 I2C_WRITE_REG(sc,
396 AM335X_I2C_CON, I2C_CON_EN | I2C_CON_MST | I2C_CON_STP);
397 DPRINTF(("ti_iic_op: op %d con 0x%x ", op, con));
398 I2C_WRITE_REG(sc, AM335X_I2C_CNT, buflen);
399 I2C_WRITE_REG(sc, AM335X_I2C_SA, (addr & I2C_SA_MASK));
400 DPRINTF(("SA 0x%x len %d\n",
401 I2C_READ_REG(sc, AM335X_I2C_SA), I2C_READ_REG(sc, AM335X_I2C_CNT)));
402
403 if ((flags & I2C_F_POLL) == 0) {
404 /* clear any pending interrupt */
405 I2C_WRITE_REG(sc, AM335X_I2C_IRQSTATUS,
406 I2C_READ_REG(sc, AM335X_I2C_IRQSTATUS));
407 /* and enable */
408 I2C_WRITE_REG(sc, AM335X_I2C_IRQENABLE_SET, mask);
409 }
410 /* start transfer */
411 I2C_WRITE_REG(sc, AM335X_I2C_CON, con);
412
413 if ((flags & I2C_F_POLL) == 0) {
414 /* and wait for completion */
415 DPRINTF(("ti_iic_op waiting, op %#x\n", sc->sc_op));
416 while (sc->sc_op == op) {
417 if (tsleep_nsec(&sc->sc_dev, PWAIT, "tiiic",
418 SEC_TO_NSEC(5)) == EWOULDBLOCK) {
419 /* timeout */
420 op = TI_I2CERROR;
421 }
422 }
423 DPRINTF(("ti_iic_op waiting done, op %#x\n", sc->sc_op));
424
425 /* disable interrupts */
426 I2C_WRITE_REG(sc, AM335X_I2C_IRQENABLE_CLR, 0xffff);
427 } else {
428 /* poll for completion */
429 DPRINTF(("ti_iic_op polling, op %x\n", sc->sc_op));
430 while (sc->sc_op == op) {
431 stat = ti_iic_stat(sc, mask);
432 DPRINTF(("ti_iic_op stat 0x%x\n", stat));
433 if (stat == 0) /* timeout */
434 sc->sc_op = TI_I2CERROR;
435 else
436 ti_iic_handle_intr(sc, stat);
437 I2C_WRITE_REG(sc, AM335X_I2C_IRQSTATUS, stat);
438 }
439 DPRINTF(("ti_iic_op polling done, op now %x\n", sc->sc_op));
440 }
441 retry = 10000;
442 I2C_WRITE_REG(sc, AM335X_I2C_CON, 0);
443 while (I2C_READ_REG(sc, AM335X_I2C_CON) & I2C_CON_MST) {
444 delay(100);
445 if (--retry == 0)
446 break;
447 }
448
449 return (sc->sc_op == TI_I2CDONE) ? 0 : EIO;
450 }
451
452 void
ti_iic_handle_intr(struct ti_iic_softc * sc,uint32_t stat)453 ti_iic_handle_intr(struct ti_iic_softc *sc, uint32_t stat)
454 {
455 KASSERT(stat != 0);
456 DPRINTF(("ti_iic_handle_intr stat %#x\n", stat));
457
458 if (stat & (I2C_IRQSTATUS_NACK|I2C_IRQSTATUS_AL)) {
459 sc->sc_op = TI_I2CERROR;
460 return;
461 }
462 if (stat & I2C_IRQSTATUS_ARDY) {
463 sc->sc_op = TI_I2CDONE;
464 return;
465 }
466 if (sc->sc_op == TI_I2CREAD)
467 ti_iic_do_read(sc, stat);
468 else if (sc->sc_op == TI_I2CWRITE)
469 ti_iic_do_write(sc, stat);
470 else
471 return;
472 }
473 void
ti_iic_do_read(struct ti_iic_softc * sc,uint32_t stat)474 ti_iic_do_read(struct ti_iic_softc *sc, uint32_t stat)
475 {
476 int len = 0;
477
478 DPRINTF(("ti_iic_do_read stat %#x\n", stat));
479 if (stat & I2C_IRQSTATUS_RDR) {
480 len = I2C_READ_REG(sc, AM335X_I2C_BUFSTAT);
481 len = I2C_BUFSTAT_RXSTAT(len);
482 DPRINTF(("ti_iic_do_read receive drain len %d left %d\n",
483 len, I2C_READ_REG(sc, AM335X_I2C_CNT)));
484 } else if (stat & I2C_IRQSTATUS_RRDY) {
485 len = sc->sc_rxthres + 1;
486 DPRINTF(("ti_iic_do_read receive len %d left %d\n",
487 len, I2C_READ_REG(sc, AM335X_I2C_CNT)));
488 }
489 for (;
490 sc->sc_bufidx < sc->sc_buflen && len > 0;
491 sc->sc_bufidx++, len--) {
492 sc->sc_buf[sc->sc_bufidx] = I2C_READ_DATA(sc);
493 DPRINTF(("ti_iic_do_read got b[%d]=0x%x\n", sc->sc_bufidx,
494 sc->sc_buf[sc->sc_bufidx]));
495 }
496 DPRINTF(("ti_iic_do_read done\n"));
497 }
498
499 void
ti_iic_do_write(struct ti_iic_softc * sc,uint32_t stat)500 ti_iic_do_write(struct ti_iic_softc *sc, uint32_t stat)
501 {
502 int len = 0;
503
504 DPRINTF(("ti_iic_do_write stat %#x\n", stat));
505
506 if (stat & I2C_IRQSTATUS_XDR) {
507 len = I2C_READ_REG(sc, AM335X_I2C_BUFSTAT);
508 len = I2C_BUFSTAT_TXSTAT(len);
509 DPRINTF(("ti_iic_do_write xmit drain len %d left %d\n",
510 len, I2C_READ_REG(sc, AM335X_I2C_CNT)));
511 } else if (stat & I2C_IRQSTATUS_XRDY) {
512 len = sc->sc_txthres + 1;
513 DPRINTF(("ti_iic_do_write xmit len %d left %d\n",
514 len, I2C_READ_REG(sc, AM335X_I2C_CNT)));
515 }
516 for (;
517 sc->sc_bufidx < sc->sc_buflen && len > 0;
518 sc->sc_bufidx++, len--) {
519 DPRINTF(("ti_iic_do_write send b[%d]=0x%x\n",
520 sc->sc_bufidx, sc->sc_buf[sc->sc_bufidx]));
521 I2C_WRITE_DATA(sc, sc->sc_buf[sc->sc_bufidx]);
522 }
523 DPRINTF(("ti_iic_do_write done\n"));
524 }
525
526 int
ti_iic_wait(struct ti_iic_softc * sc,uint16_t mask,uint16_t val,int flags)527 ti_iic_wait(struct ti_iic_softc *sc, uint16_t mask, uint16_t val, int flags)
528 {
529 int retry = 10;
530 uint16_t v;
531 DPRINTF(("ti_iic_wait mask %#x val %#x flags %#x\n", mask, val, flags));
532
533 while (((v = I2C_READ_REG(sc, AM335X_I2C_IRQSTATUS_RAW)) & mask) != val) {
534 --retry;
535 if (retry == 0) {
536 printf("%s: wait timeout, mask=%#x val=%#x stat=%#x\n",
537 DEVNAME(sc), mask, val, v);
538 return EBUSY;
539 }
540 if (flags & I2C_F_POLL)
541 delay(50000);
542 else
543 tsleep_nsec(&sc->sc_dev, PWAIT, "tiiic",
544 MSEC_TO_NSEC(50));
545 }
546 DPRINTF(("ti_iic_wait done retry %#x\n", retry));
547
548 return 0;
549 }
550
551 uint32_t
ti_iic_stat(struct ti_iic_softc * sc,uint32_t mask)552 ti_iic_stat(struct ti_iic_softc *sc, uint32_t mask)
553 {
554 uint32_t v;
555 int retry = 500;
556 DPRINTF(("ti_iic_wait mask %#x\n", mask));
557 while (--retry > 0) {
558 v = I2C_READ_REG(sc, AM335X_I2C_IRQSTATUS_RAW) & mask;
559 if (v != 0)
560 break;
561 delay(100);
562 }
563 DPRINTF(("ti_iic_wait done retry %#x\n", retry));
564 return v;
565 }
566
567 int
ti_iic_flush(struct ti_iic_softc * sc)568 ti_iic_flush(struct ti_iic_softc *sc)
569 {
570 DPRINTF(("ti_iic_flush\n"));
571 #if 0
572 int retry = 1000;
573 uint16_t v;
574
575 while ((v =
576 I2C_READ_REG(sc, AM335X_I2C_IRQSTATUS_RAW)) & I2C_IRQSTATUS_RRDY) {
577 if (--retry == 0) {
578 printf("%s: flush timeout, stat = %#x\n", DEVNAME(sc), v);
579 return EBUSY;
580 }
581 (void)I2C_READ_DATA(sc);
582 delay(1000);
583 }
584 #endif
585
586 I2C_WRITE_REG(sc, AM335X_I2C_CNT, 0);
587 return 0;
588 }
589
590 void
ti_iic_scan(struct device * self,struct i2cbus_attach_args * iba,void * aux)591 ti_iic_scan(struct device *self, struct i2cbus_attach_args *iba, void *aux)
592 {
593 int iba_node = *(int *)aux;
594 extern int iic_print(void *, const char *);
595 struct i2c_attach_args ia;
596 char name[32];
597 uint32_t reg[1];
598 int node;
599
600 for (node = OF_child(iba_node); node; node = OF_peer(node)) {
601 memset(name, 0, sizeof(name));
602 memset(reg, 0, sizeof(reg));
603
604 if (OF_getprop(node, "compatible", name, sizeof(name)) == -1)
605 continue;
606 if (name[0] == '\0')
607 continue;
608
609 if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg))
610 continue;
611
612 memset(&ia, 0, sizeof(ia));
613 ia.ia_tag = iba->iba_tag;
614 ia.ia_addr = bemtoh32(®[0]);
615 ia.ia_name = name;
616 ia.ia_cookie = &node;
617
618 config_found(self, &ia, iic_print);
619 }
620 }
621