1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_tlreg.h,v 1.15 1999/09/19 22:39:24 wpaul Exp $ 33 * $DragonFly: src/sys/dev/netif/tl/if_tlreg.h,v 1.5 2005/06/14 12:38:04 joerg Exp $ 34 */ 35 36 37 struct tl_type { 38 u_int16_t tl_vid; 39 u_int16_t tl_did; 40 char *tl_name; 41 }; 42 43 /* 44 * ThunderLAN TX/RX list format. The TX and RX lists are pretty much 45 * identical: the list begins with a 32-bit forward pointer which points 46 * at the next list in the chain, followed by 16 bits for the total 47 * frame size, and a 16 bit status field. This is followed by a series 48 * of 10 32-bit data count/data address pairs that point to the fragments 49 * that make up the complete frame. 50 */ 51 52 #define TL_MAXFRAGS 10 53 #define TL_RX_LIST_CNT 64 54 #define TL_TX_LIST_CNT 128 55 #define TL_MIN_FRAMELEN 64 56 57 struct tl_frag { 58 u_int32_t tlist_dcnt; 59 u_int32_t tlist_dadr; 60 }; 61 62 struct tl_list { 63 u_int32_t tlist_fptr; /* phys address of next list */ 64 u_int16_t tlist_cstat; /* status word */ 65 u_int16_t tlist_frsize; /* size of data in frame */ 66 struct tl_frag tl_frag[TL_MAXFRAGS]; 67 }; 68 69 /* 70 * This is a special case of an RX list. By setting the One_Frag 71 * bit in the NETCONFIG register, the driver can force the ThunderLAN 72 * chip to use only one fragment when DMAing RX frames. 73 */ 74 75 struct tl_list_onefrag { 76 u_int32_t tlist_fptr; 77 u_int16_t tlist_cstat; 78 u_int16_t tlist_frsize; 79 struct tl_frag tl_frag; 80 }; 81 82 struct tl_list_data { 83 struct tl_list_onefrag tl_rx_list[TL_RX_LIST_CNT]; 84 struct tl_list tl_tx_list[TL_TX_LIST_CNT]; 85 unsigned char tl_pad[TL_MIN_FRAMELEN]; 86 }; 87 88 struct tl_chain { 89 struct tl_list *tl_ptr; 90 struct mbuf *tl_mbuf; 91 struct tl_chain *tl_next; 92 }; 93 94 struct tl_chain_onefrag { 95 struct tl_list_onefrag *tl_ptr; 96 struct mbuf *tl_mbuf; 97 struct tl_chain_onefrag *tl_next; 98 }; 99 100 struct tl_chain_data { 101 struct tl_chain_onefrag tl_rx_chain[TL_RX_LIST_CNT]; 102 struct tl_chain tl_tx_chain[TL_TX_LIST_CNT]; 103 104 struct tl_chain_onefrag *tl_rx_head; 105 struct tl_chain_onefrag *tl_rx_tail; 106 107 struct tl_chain *tl_tx_head; 108 struct tl_chain *tl_tx_tail; 109 struct tl_chain *tl_tx_free; 110 }; 111 112 struct tl_softc { 113 struct arpcom arpcom; /* interface info */ 114 struct ifmedia ifmedia; /* media info */ 115 bus_space_handle_t tl_bhandle; 116 bus_space_tag_t tl_btag; 117 void *tl_intrhand; 118 struct resource *tl_irq; 119 struct resource *tl_res; 120 device_t tl_miibus; 121 struct tl_type *tl_dinfo; /* ThunderLAN adapter info */ 122 u_int8_t tl_eeaddr; 123 struct tl_list_data *tl_ldata; /* TX/RX lists and mbufs */ 124 struct tl_chain_data tl_cdata; 125 u_int8_t tl_txeoc; 126 u_int8_t tl_bitrate; 127 int tl_if_flags; 128 struct callout tl_stat_timer; 129 }; 130 131 /* 132 * Transmit interrupt threshold. 133 */ 134 #define TX_THR 0x00000004 135 136 /* 137 * General constants that are fun to know. 138 * 139 * The ThunderLAN controller is made by Texas Instruments. The 140 * manual indicates that if the EEPROM checksum fails, the PCI 141 * vendor and device ID registers will be loaded with TI-specific 142 * values. 143 */ 144 #define TI_VENDORID 0x104C 145 #define TI_DEVICEID_THUNDERLAN 0x0500 146 147 /* 148 * These are the PCI vendor and device IDs for Compaq ethernet 149 * adapters based on the ThunderLAN controller. 150 */ 151 #define COMPAQ_VENDORID 0x0E11 152 #define COMPAQ_DEVICEID_NETEL_10_100 0xAE32 153 #define COMPAQ_DEVICEID_NETEL_UNKNOWN 0xAE33 154 #define COMPAQ_DEVICEID_NETEL_10 0xAE34 155 #define COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED 0xAE35 156 #define COMPAQ_DEVICEID_NETEL_10_100_DUAL 0xAE40 157 #define COMPAQ_DEVICEID_NETEL_10_100_PROLIANT 0xAE43 158 #define COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED 0xB011 159 #define COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX 0xB012 160 #define COMPAQ_DEVICEID_NETEL_10_100_TX_UTP 0xB030 161 #define COMPAQ_DEVICEID_NETFLEX_3P 0xF130 162 #define COMPAQ_DEVICEID_NETFLEX_3P_BNC 0xF150 163 164 /* 165 * These are the PCI vendor and device IDs for Olicom 166 * adapters based on the ThunderLAN controller. 167 */ 168 #define OLICOM_VENDORID 0x108D 169 #define OLICOM_DEVICEID_OC2183 0x0013 170 #define OLICOM_DEVICEID_OC2325 0x0012 171 #define OLICOM_DEVICEID_OC2326 0x0014 172 173 /* 174 * PCI low memory base and low I/O base 175 */ 176 #define TL_PCI_LOIO 0x10 177 #define TL_PCI_LOMEM 0x14 178 179 /* 180 * PCI latency timer (it's actually 0x0D, but we want a value 181 * that's longword aligned). 182 */ 183 #define TL_PCI_LATENCY_TIMER 0x0C 184 185 #define TL_DIO_ADDR_INC 0x8000 /* Increment addr on each read */ 186 #define TL_DIO_RAM_SEL 0x4000 /* RAM address select */ 187 #define TL_DIO_ADDR_MASK 0x3FFF /* address bits mask */ 188 189 /* 190 * Interrupt types 191 */ 192 #define TL_INTR_INVALID 0x0 193 #define TL_INTR_TXEOF 0x1 194 #define TL_INTR_STATOFLOW 0x2 195 #define TL_INTR_RXEOF 0x3 196 #define TL_INTR_DUMMY 0x4 197 #define TL_INTR_TXEOC 0x5 198 #define TL_INTR_ADCHK 0x6 199 #define TL_INTR_RXEOC 0x7 200 201 #define TL_INT_MASK 0x001C 202 #define TL_VEC_MASK 0x1FE0 203 /* 204 * Host command register bits 205 */ 206 #define TL_CMD_GO 0x80000000 207 #define TL_CMD_STOP 0x40000000 208 #define TL_CMD_ACK 0x20000000 209 #define TL_CMD_CHSEL7 0x10000000 210 #define TL_CMD_CHSEL6 0x08000000 211 #define TL_CMD_CHSEL5 0x04000000 212 #define TL_CMD_CHSEL4 0x02000000 213 #define TL_CMD_CHSEL3 0x01000000 214 #define TL_CMD_CHSEL2 0x00800000 215 #define TL_CMD_CHSEL1 0x00400000 216 #define TL_CMD_CHSEL0 0x00200000 217 #define TL_CMD_EOC 0x00100000 218 #define TL_CMD_RT 0x00080000 219 #define TL_CMD_NES 0x00040000 220 #define TL_CMD_ZERO0 0x00020000 221 #define TL_CMD_ZERO1 0x00010000 222 #define TL_CMD_ADRST 0x00008000 223 #define TL_CMD_LDTMR 0x00004000 224 #define TL_CMD_LDTHR 0x00002000 225 #define TL_CMD_REQINT 0x00001000 226 #define TL_CMD_INTSOFF 0x00000800 227 #define TL_CMD_INTSON 0x00000400 228 #define TL_CMD_RSVD0 0x00000200 229 #define TL_CMD_RSVD1 0x00000100 230 #define TL_CMD_ACK7 0x00000080 231 #define TL_CMD_ACK6 0x00000040 232 #define TL_CMD_ACK5 0x00000020 233 #define TL_CMD_ACK4 0x00000010 234 #define TL_CMD_ACK3 0x00000008 235 #define TL_CMD_ACK2 0x00000004 236 #define TL_CMD_ACK1 0x00000002 237 #define TL_CMD_ACK0 0x00000001 238 239 #define TL_CMD_CHSEL_MASK 0x01FE0000 240 #define TL_CMD_ACK_MASK 0xFF 241 242 /* 243 * EEPROM address where station address resides. 244 */ 245 #define TL_EEPROM_EADDR 0x83 246 #define TL_EEPROM_EADDR2 0x99 247 #define TL_EEPROM_EADDR3 0xAF 248 #define TL_EEPROM_EADDR_OC 0xF8 /* Olicom cards use a different 249 address than Compaqs. */ 250 /* 251 * ThunderLAN host command register offsets. 252 * (Can be accessed either by IO ports or memory map.) 253 */ 254 #define TL_HOSTCMD 0x00 255 #define TL_CH_PARM 0x04 256 #define TL_DIO_ADDR 0x08 257 #define TL_HOST_INT 0x0A 258 #define TL_DIO_DATA 0x0C 259 260 /* 261 * ThunderLAN internal registers 262 */ 263 #define TL_NETCMD 0x00 264 #define TL_NETSIO 0x01 265 #define TL_NETSTS 0x02 266 #define TL_NETMASK 0x03 267 268 #define TL_NETCONFIG 0x04 269 #define TL_MANTEST 0x06 270 271 #define TL_VENID_LSB 0x08 272 #define TL_VENID_MSB 0x09 273 #define TL_DEVID_LSB 0x0A 274 #define TL_DEVID_MSB 0x0B 275 276 #define TL_REVISION 0x0C 277 #define TL_SUBCLASS 0x0D 278 #define TL_MINLAT 0x0E 279 #define TL_MAXLAT 0x0F 280 281 #define TL_AREG0_B5 0x10 282 #define TL_AREG0_B4 0x11 283 #define TL_AREG0_B3 0x12 284 #define TL_AREG0_B2 0x13 285 286 #define TL_AREG0_B1 0x14 287 #define TL_AREG0_B0 0x15 288 #define TL_AREG1_B5 0x16 289 #define TL_AREG1_B4 0x17 290 291 #define TL_AREG1_B3 0x18 292 #define TL_AREG1_B2 0x19 293 #define TL_AREG1_B1 0x1A 294 #define TL_AREG1_B0 0x1B 295 296 #define TL_AREG2_B5 0x1C 297 #define TL_AREG2_B4 0x1D 298 #define TL_AREG2_B3 0x1E 299 #define TL_AREG2_B2 0x1F 300 301 #define TL_AREG2_B1 0x20 302 #define TL_AREG2_B0 0x21 303 #define TL_AREG3_B5 0x22 304 #define TL_AREG3_B4 0x23 305 306 #define TL_AREG3_B3 0x24 307 #define TL_AREG3_B2 0x25 308 #define TL_AREG3_B1 0x26 309 #define TL_AREG3_B0 0x27 310 311 #define TL_HASH1 0x28 312 #define TL_HASH2 0x2C 313 #define TL_TXGOODFRAMES 0x30 314 #define TL_TXUNDERRUN 0x33 315 #define TL_RXGOODFRAMES 0x34 316 #define TL_RXOVERRUN 0x37 317 #define TL_DEFEREDTX 0x38 318 #define TL_CRCERROR 0x3A 319 #define TL_CODEERROR 0x3B 320 #define TL_MULTICOLTX 0x3C 321 #define TL_SINGLECOLTX 0x3E 322 #define TL_EXCESSIVECOL 0x40 323 #define TL_LATECOL 0x41 324 #define TL_CARRIERLOSS 0x42 325 #define TL_ACOMMIT 0x43 326 #define TL_LDREG 0x44 327 #define TL_BSIZEREG 0x45 328 #define TL_MAXRX 0x46 329 330 /* 331 * ThunderLAN SIO register bits 332 */ 333 #define TL_SIO_MINTEN 0x80 334 #define TL_SIO_ECLOK 0x40 335 #define TL_SIO_ETXEN 0x20 336 #define TL_SIO_EDATA 0x10 337 #define TL_SIO_NMRST 0x08 338 #define TL_SIO_MCLK 0x04 339 #define TL_SIO_MTXEN 0x02 340 #define TL_SIO_MDATA 0x01 341 342 /* 343 * Thunderlan NETCONFIG bits 344 */ 345 #define TL_CFG_RCLKTEST 0x8000 346 #define TL_CFG_TCLKTEST 0x4000 347 #define TL_CFG_BITRATE 0x2000 348 #define TL_CFG_RXCRC 0x1000 349 #define TL_CFG_PEF 0x0800 350 #define TL_CFG_ONEFRAG 0x0400 351 #define TL_CFG_ONECHAN 0x0200 352 #define TL_CFG_MTEST 0x0100 353 #define TL_CFG_PHYEN 0x0080 354 #define TL_CFG_MACSEL6 0x0040 355 #define TL_CFG_MACSEL5 0x0020 356 #define TL_CFG_MACSEL4 0x0010 357 #define TL_CFG_MACSEL3 0x0008 358 #define TL_CFG_MACSEL2 0x0004 359 #define TL_CFG_MACSEL1 0x0002 360 #define TL_CFG_MACSEL0 0x0001 361 362 /* 363 * ThunderLAN NETSTS bits 364 */ 365 #define TL_STS_MIRQ 0x80 366 #define TL_STS_HBEAT 0x40 367 #define TL_STS_TXSTOP 0x20 368 #define TL_STS_RXSTOP 0x10 369 370 /* 371 * ThunderLAN NETCMD bits 372 */ 373 #define TL_CMD_NRESET 0x80 374 #define TL_CMD_NWRAP 0x40 375 #define TL_CMD_CSF 0x20 376 #define TL_CMD_CAF 0x10 377 #define TL_CMD_NOBRX 0x08 378 #define TL_CMD_DUPLEX 0x04 379 #define TL_CMD_TRFRAM 0x02 380 #define TL_CMD_TXPACE 0x01 381 382 /* 383 * ThunderLAN NETMASK bits 384 */ 385 #define TL_MASK_MASK7 0x80 386 #define TL_MASK_MASK6 0x40 387 #define TL_MASK_MASK5 0x20 388 #define TL_MASK_MASK4 0x10 389 390 /* 391 * MII frame format 392 */ 393 #ifdef ANSI_DOESNT_ALLOW_BITFIELDS 394 struct tl_mii_frame { 395 u_int16_t mii_stdelim:2, 396 mii_opcode:2, 397 mii_phyaddr:5, 398 mii_regaddr:5, 399 mii_turnaround:2; 400 u_int16_t mii_data; 401 }; 402 #else 403 struct tl_mii_frame { 404 u_int8_t mii_stdelim; 405 u_int8_t mii_opcode; 406 u_int8_t mii_phyaddr; 407 u_int8_t mii_regaddr; 408 u_int8_t mii_turnaround; 409 u_int16_t mii_data; 410 }; 411 #endif 412 /* 413 * MII constants 414 */ 415 #define TL_MII_STARTDELIM 0x01 416 #define TL_MII_READOP 0x02 417 #define TL_MII_WRITEOP 0x01 418 #define TL_MII_TURNAROUND 0x02 419 420 #define TL_LAST_FRAG 0x80000000 421 #define TL_CSTAT_UNUSED 0x8000 422 #define TL_CSTAT_FRAMECMP 0x4000 423 #define TL_CSTAT_READY 0x3000 424 #define TL_CSTAT_UNUSED13 0x2000 425 #define TL_CSTAT_UNUSED12 0x1000 426 #define TL_CSTAT_EOC 0x0800 427 #define TL_CSTAT_RXERROR 0x0400 428 #define TL_CSTAT_PASSCRC 0x0200 429 #define TL_CSTAT_DPRIO 0x0100 430 431 #define TL_FRAME_MASK 0x00FFFFFF 432 #define tl_tx_goodframes(x) (x.tl_txstat & TL_FRAME_MASK) 433 #define tl_tx_underrun(x) ((x.tl_txstat & ~TL_FRAME_MASK) >> 24) 434 #define tl_rx_goodframes(x) (x.tl_rxstat & TL_FRAME_MASK) 435 #define tl_rx_overrun(x) ((x.tl_rxstat & ~TL_FRAME_MASK) >> 24) 436 437 struct tl_stats { 438 u_int32_t tl_txstat; 439 u_int32_t tl_rxstat; 440 u_int16_t tl_deferred; 441 u_int8_t tl_crc_errors; 442 u_int8_t tl_code_errors; 443 u_int16_t tl_tx_multi_collision; 444 u_int16_t tl_tx_single_collision; 445 u_int8_t tl_excessive_collision; 446 u_int8_t tl_late_collision; 447 u_int8_t tl_carrier_loss; 448 u_int8_t acommit; 449 }; 450 451 /* 452 * ACOMMIT register bits. These are used only when a bitrate 453 * PHY is selected ('bitrate' bit in netconfig register is set). 454 */ 455 #define TL_AC_MTXER 0x01 /* reserved */ 456 #define TL_AC_MTXD1 0x02 /* 0 == 10baseT 1 == AUI */ 457 #define TL_AC_MTXD2 0x04 /* loopback disable */ 458 #define TL_AC_MTXD3 0x08 /* full duplex disable */ 459 460 #define TL_AC_TXTHRESH 0xF0 461 #define TL_AC_TXTHRESH_16LONG 0x00 462 #define TL_AC_TXTHRESH_32LONG 0x10 463 #define TL_AC_TXTHRESH_64LONG 0x20 464 #define TL_AC_TXTHRESH_128LONG 0x30 465 #define TL_AC_TXTHRESH_256LONG 0x40 466 #define TL_AC_TXTHRESH_WHOLEPKT 0x50 467 468 /* 469 * PCI burst size register (TL_BSIZEREG). 470 */ 471 #define TL_RXBURST 0x0F 472 #define TL_TXBURST 0xF0 473 474 #define TL_RXBURST_4LONG 0x00 475 #define TL_RXBURST_8LONG 0x01 476 #define TL_RXBURST_16LONG 0x02 477 #define TL_RXBURST_32LONG 0x03 478 #define TL_RXBURST_64LONG 0x04 479 #define TL_RXBURST_128LONG 0x05 480 481 #define TL_TXBURST_4LONG 0x00 482 #define TL_TXBURST_8LONG 0x10 483 #define TL_TXBURST_16LONG 0x20 484 #define TL_TXBURST_32LONG 0x30 485 #define TL_TXBURST_64LONG 0x40 486 #define TL_TXBURST_128LONG 0x50 487 488 /* 489 * register space access macros 490 */ 491 #define CSR_WRITE_4(sc, reg, val) \ 492 bus_space_write_4(sc->tl_btag, sc->tl_bhandle, reg, val) 493 #define CSR_WRITE_2(sc, reg, val) \ 494 bus_space_write_2(sc->tl_btag, sc->tl_bhandle, reg, val) 495 #define CSR_WRITE_1(sc, reg, val) \ 496 bus_space_write_1(sc->tl_btag, sc->tl_bhandle, reg, val) 497 498 #define CSR_READ_4(sc, reg) \ 499 bus_space_read_4(sc->tl_btag, sc->tl_bhandle, reg) 500 #define CSR_READ_2(sc, reg) \ 501 bus_space_read_2(sc->tl_btag, sc->tl_bhandle, reg) 502 #define CSR_READ_1(sc, reg) \ 503 bus_space_read_1(sc->tl_btag, sc->tl_bhandle, reg) 504 505 #define CMD_PUT(sc, x) CSR_WRITE_4(sc, TL_HOSTCMD, x) 506 #define CMD_SET(sc, x) \ 507 CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) | (x)) 508 #define CMD_CLR(sc, x) \ 509 CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) & ~(x)) 510 511 /* 512 * ThunderLAN adapters typically have a serial EEPROM containing 513 * configuration information. The main reason we're interested in 514 * it is because it also contains the adapters's station address. 515 * 516 * Access to the EEPROM is a bit goofy since it is a serial device: 517 * you have to do reads and writes one bit at a time. The state of 518 * the DATA bit can only change while the CLOCK line is held low. 519 * Transactions work basically like this: 520 * 521 * 1) Send the EEPROM_START sequence to prepare the EEPROM for 522 * accepting commands. This pulls the clock high, sets 523 * the data bit to 0, enables transmission to the EEPROM, 524 * pulls the data bit up to 1, then pulls the clock low. 525 * The idea is to do a 0 to 1 transition of the data bit 526 * while the clock pin is held high. 527 * 528 * 2) To write a bit to the EEPROM, set the TXENABLE bit, then 529 * set the EDATA bit to send a 1 or clear it to send a 0. 530 * Finally, set and then clear ECLOK. Strobing the clock 531 * transmits the bit. After 8 bits have been written, the 532 * EEPROM should respond with an ACK, which should be read. 533 * 534 * 3) To read a bit from the EEPROM, clear the TXENABLE bit, 535 * then set ECLOK. The bit can then be read by reading EDATA. 536 * ECLOCK should then be cleared again. This can be repeated 537 * 8 times to read a whole byte, after which the 538 * 539 * 4) We need to send the address byte to the EEPROM. For this 540 * we have to send the write control byte to the EEPROM to 541 * tell it to accept data. The byte is 0xA0. The EEPROM should 542 * ack this. The address byte can be send after that. 543 * 544 * 5) Now we have to tell the EEPROM to send us data. For that we 545 * have to transmit the read control byte, which is 0xA1. This 546 * byte should also be acked. We can then read the data bits 547 * from the EEPROM. 548 * 549 * 6) When we're all finished, send the EEPROM_STOP sequence. 550 * 551 * Note that we use the ThunderLAN's NetSio register to access the 552 * EEPROM, however there is an alternate method. There is a PCI NVRAM 553 * register at PCI offset 0xB4 which can also be used with minor changes. 554 * The difference is that access to PCI registers via pci_conf_read() 555 * and pci_conf_write() is done using programmed I/O, which we want to 556 * avoid. 557 */ 558 559 /* 560 * Note that EEPROM_START leaves transmission enabled. 561 */ 562 #define EEPROM_START \ 563 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock pin high */\ 564 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Set DATA bit to 1 */ \ 565 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit to write bit */\ 566 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA bit to 0 again */\ 567 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */ 568 569 /* 570 * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so 571 * that no further data can be written to the EEPROM I/O pin. 572 */ 573 #define EEPROM_STOP \ 574 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit */ \ 575 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA to 0 */ \ 576 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock high */ \ 577 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit */ \ 578 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Toggle DATA to 1 */ \ 579 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit. */ \ 580 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */ 581 582 583 /* 584 * Microchip Technology 24Cxx EEPROM control bytes 585 */ 586 #define EEPROM_CTL_READ 0xA1 /* 0101 0001 */ 587 #define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */ 588