1 /* ASSIST.C (c) Copyright Roger Bowler, 1999-2009 */
2 /* ESA/390 MVS Assist Routines */
3
4 /*-------------------------------------------------------------------*/
5 /* This module contains routines which process the MVS Assist */
6 /* instructions described in the manual GA22-7079-01. */
7 /*-------------------------------------------------------------------*/
8
9 /* Instruction decode rework - Jan Jaeger */
10 /* Correct address wraparound - Jan Jaeger */
11 /* z/Architecture support - (c) Copyright Jan Jaeger, 1999-2009 */
12 /* Add dummy assist instruction - Jay Maynard, */
13 /* suggested by Brandon Hill */
14
15 #include "hstdinc.h"
16
17 #if !defined(_HENGINE_DLL_)
18 #define _HENGINE_DLL_
19 #endif
20
21 #if !defined(_ASSIST_C_)
22 #define _ASSIST_C_
23 #endif
24
25 #include "hercules.h"
26
27 #include "opcode.h"
28
29 #include "inline.h"
30
31 #if !defined(_ASSIST_C)
32
33 #define _ASSIST_C
34
35 /*-------------------------------------------------------------------*/
36 /* Control block offsets fixed by architecture */
37 /*-------------------------------------------------------------------*/
38
39 /* Prefixed storage area offsets */
40 #define PSALCPUA 0x2F4 /* Logical CPU address */
41 #define PSAHLHI 0x2F8 /* Locks held indicators */
42
43 /* Bit settings for PSAHLHI */
44 #define PSACMSLI 0x00000002 /* CMS lock held indicator */
45 #define PSALCLLI 0x00000001 /* Local lock held indicator */
46
47 /* Address space control block offsets */
48 #define ASCBLOCK 0x080 /* Local lock */
49 #define ASCBLSWQ 0x084 /* Local lock suspend queue */
50
51 /* Lock interface table offsets */
52 #define LITOLOC (-16) /* Obtain local error exit */
53 #define LITRLOC (-12) /* Release local error exit */
54 #define LITOCMS (-8) /* Obtain CMS error exit */
55 #define LITRCMS (-4) /* Release CMS error exit */
56
57 #endif /*!defined(_ASSIST_C)*/
58
59
60 #if !defined(FEATURE_S390_DAT) && !defined(FEATURE_ESAME)
61 /*-------------------------------------------------------------------*/
62 /* E502 - Page Fix [SSE] */
63 /*-------------------------------------------------------------------*/
DEF_INST(fix_page)64 DEF_INST(fix_page)
65 {
66 int b1, b2; /* Values of base field */
67 VADR effective_addr1,
68 effective_addr2; /* Effective addresses */
69
70 SSE(inst, regs, b1, effective_addr1, b2, effective_addr2);
71
72 PRIV_CHECK(regs);
73
74 PTT(PTT_CL_ERR,"*E502 PGFIX",effective_addr1,effective_addr2,regs->psw.IA_L);
75 /*INCOMPLETE*/
76
77 }
78 #endif /*!defined(FEATURE_S390_DAT) && !defined(FEATURE_ESAME)*/
79
80
81 /*-------------------------------------------------------------------*/
82 /* E503 - SVC assist [SSE] */
83 /*-------------------------------------------------------------------*/
DEF_INST(svc_assist)84 DEF_INST(svc_assist)
85 {
86 int b1, b2; /* Values of base field */
87 VADR effective_addr1,
88 effective_addr2; /* Effective addresses */
89
90 SSE(inst, regs, b1, effective_addr1, b2, effective_addr2);
91
92 PRIV_CHECK(regs);
93
94 PTT(PTT_CL_ERR,"*E503 SVCA",effective_addr1,effective_addr2,regs->psw.IA_L);
95 /*INCOMPLETE: NO ACTION IS TAKEN, THE SVC IS UNASSISTED
96 AND MVS WILL HAVE TO HANDLE THE SITUATION*/
97
98 }
99
100
101 /*-------------------------------------------------------------------*/
102 /* E504 - Obtain Local Lock [SSE] */
103 /*-------------------------------------------------------------------*/
DEF_INST(obtain_local_lock)104 DEF_INST(obtain_local_lock)
105 {
106 int b1, b2; /* Values of base field */
107 VADR effective_addr1,
108 effective_addr2; /* Effective addresses */
109 VADR ascb_addr; /* Virtual address of ASCB */
110 VADR lock_addr; /* Virtual addr of ASCBLOCK */
111 U32 hlhi_word; /* Highest lock held word */
112 VADR lit_addr; /* Virtual address of lock
113 interface table */
114 U32 lock; /* Lock value */
115 U32 lcpa; /* Logical CPU address */
116 VADR newia; /* Unsuccessful branch addr */
117 int acc_mode = 0; /* access mode to use */
118
119 SSE(inst, regs, b1, effective_addr1, b2, effective_addr2);
120
121 PRIV_CHECK(regs);
122
123 /* Specification exception if operands are not on word boundary */
124 if ((effective_addr1 & 0x00000003) || (effective_addr2 & 0x00000003))
125 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
126
127 PERFORM_SERIALIZATION(regs);
128
129 /* Obtain main-storage access lock */
130 OBTAIN_MAINLOCK(regs);
131
132 if (ACCESS_REGISTER_MODE(®s->psw))
133 acc_mode = USE_PRIMARY_SPACE;
134
135 /* Load ASCB address from first operand location */
136 ascb_addr = ARCH_DEP(vfetch4) ( effective_addr1, acc_mode, regs );
137
138 /* Load locks held bits from second operand location */
139 hlhi_word = ARCH_DEP(vfetch4) ( effective_addr2, acc_mode, regs );
140
141 /* Fetch our logical CPU address from PSALCPUA */
142 lcpa = ARCH_DEP(vfetch4) ( effective_addr2 - 4, acc_mode, regs );
143
144 lock_addr = (ascb_addr + ASCBLOCK) & ADDRESS_MAXWRAP(regs);
145
146 /* Fetch the local lock from the ASCB */
147 lock = ARCH_DEP(vfetch4) ( lock_addr, acc_mode, regs );
148
149 /* Obtain the local lock if not already held by any CPU */
150 if (lock == 0
151 && (hlhi_word & PSALCLLI) == 0)
152 {
153 /* Store the unchanged value into the second operand to
154 ensure suppression in the event of an access exception */
155 ARCH_DEP(vstore4) ( hlhi_word, effective_addr2, acc_mode, regs );
156
157 /* Store our logical CPU address in ASCBLOCK */
158 ARCH_DEP(vstore4) ( lcpa, lock_addr, acc_mode, regs );
159
160 /* Set the local lock held bit in the second operand */
161 hlhi_word |= PSALCLLI;
162 ARCH_DEP(vstore4) ( hlhi_word, effective_addr2, acc_mode, regs );
163
164 /* Set register 13 to zero to indicate lock obtained */
165 regs->GR_L(13) = 0;
166 }
167 else
168 {
169 /* Fetch the lock interface table address from the
170 second word of the second operand, and load the
171 new instruction address and amode from LITOLOC */
172 lit_addr = ARCH_DEP(vfetch4) ( effective_addr2 + 4, acc_mode, regs ) + LITOLOC;
173 lit_addr &= ADDRESS_MAXWRAP(regs);
174 newia = ARCH_DEP(vfetch4) ( lit_addr, acc_mode, regs );
175
176 /* Save the link information in register 12 */
177 regs->GR_L(12) = PSW_IA(regs, 0);
178
179 /* Copy LITOLOC into register 13 to signify obtain failure */
180 regs->GR_L(13) = newia;
181
182 /* Update the PSW instruction address */
183 UPD_PSW_IA(regs, newia);
184 }
185
186 /* Release main-storage access lock */
187 RELEASE_MAINLOCK(regs);
188
189 PERFORM_SERIALIZATION(regs);
190
191 } /* end function obtain_local_lock */
192
193
194 /*-------------------------------------------------------------------*/
195 /* E505 - Release Local Lock [SSE] */
196 /*-------------------------------------------------------------------*/
DEF_INST(release_local_lock)197 DEF_INST(release_local_lock)
198 {
199 int b1, b2; /* Values of base field */
200 VADR effective_addr1,
201 effective_addr2; /* Effective addresses */
202 VADR ascb_addr; /* Virtual address of ASCB */
203 VADR lock_addr; /* Virtual addr of ASCBLOCK */
204 VADR susp_addr; /* Virtual addr of ASCBLSWQ */
205 U32 hlhi_word; /* Highest lock held word */
206 VADR lit_addr; /* Virtual address of lock
207 interface table */
208 U32 lock; /* Lock value */
209 U32 susp; /* Lock suspend queue */
210 U32 lcpa; /* Logical CPU address */
211 VADR newia; /* Unsuccessful branch addr */
212 int acc_mode = 0; /* access mode to use */
213
214 SSE(inst, regs, b1, effective_addr1, b2, effective_addr2);
215
216 PRIV_CHECK(regs);
217
218 /* Specification exception if operands are not on word boundary */
219 if ((effective_addr1 & 0x00000003) || (effective_addr2 & 0x00000003))
220 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
221
222 /* Obtain main-storage access lock */
223 OBTAIN_MAINLOCK(regs);
224
225 if (ACCESS_REGISTER_MODE(®s->psw))
226 acc_mode = USE_PRIMARY_SPACE;
227
228 /* Load ASCB address from first operand location */
229 ascb_addr = ARCH_DEP(vfetch4) ( effective_addr1, acc_mode, regs );
230
231 /* Load locks held bits from second operand location */
232 hlhi_word = ARCH_DEP(vfetch4) ( effective_addr2, acc_mode, regs );
233
234 /* Fetch our logical CPU address from PSALCPUA */
235 lcpa = ARCH_DEP(vfetch4) ( effective_addr2 - 4, acc_mode, regs );
236
237 /* Fetch the local lock and the suspend queue from the ASCB */
238 lock_addr = (ascb_addr + ASCBLOCK) & ADDRESS_MAXWRAP(regs);
239 susp_addr = (ascb_addr + ASCBLSWQ) & ADDRESS_MAXWRAP(regs);
240 lock = ARCH_DEP(vfetch4) ( lock_addr, acc_mode, regs );
241 susp = ARCH_DEP(vfetch4) ( susp_addr, acc_mode, regs );
242
243 /* Test if this CPU holds the local lock, and does not hold
244 any CMS lock, and the local lock suspend queue is empty */
245 if (lock == lcpa
246 && (hlhi_word & (PSALCLLI | PSACMSLI)) == PSALCLLI
247 && susp == 0)
248 {
249 /* Store the unchanged value into the second operand to
250 ensure suppression in the event of an access exception */
251 ARCH_DEP(vstore4) ( hlhi_word, effective_addr2, acc_mode, regs );
252
253 /* Set the local lock to zero */
254 ARCH_DEP(vstore4) ( 0, lock_addr, acc_mode, regs );
255
256 /* Clear the local lock held bit in the second operand */
257 hlhi_word &= ~PSALCLLI;
258 ARCH_DEP(vstore4) ( hlhi_word, effective_addr2, acc_mode, regs );
259
260 /* Set register 13 to zero to indicate lock released */
261 regs->GR_L(13) = 0;
262 }
263 else
264 {
265 /* Fetch the lock interface table address from the
266 second word of the second operand, and load the
267 new instruction address and amode from LITRLOC */
268 lit_addr = ARCH_DEP(vfetch4) ( effective_addr2 + 4, acc_mode, regs ) + LITRLOC;
269 lit_addr &= ADDRESS_MAXWRAP(regs);
270 newia = ARCH_DEP(vfetch4) ( lit_addr, acc_mode, regs );
271
272 /* Save the link information in register 12 */
273 regs->GR_L(12) = PSW_IA(regs, 0);
274
275 /* Copy LITRLOC into register 13 to signify release failure */
276 regs->GR_L(13) = newia;
277
278 /* Update the PSW instruction address */
279 UPD_PSW_IA(regs, newia);
280 }
281
282 /* Release main-storage access lock */
283 RELEASE_MAINLOCK(regs);
284
285 } /* end function release_local_lock */
286
287
288 /*-------------------------------------------------------------------*/
289 /* E506 - Obtain CMS Lock [SSE] */
290 /*-------------------------------------------------------------------*/
DEF_INST(obtain_cms_lock)291 DEF_INST(obtain_cms_lock)
292 {
293 int b1, b2; /* Values of base field */
294 VADR effective_addr1,
295 effective_addr2; /* Effective addresses */
296 VADR ascb_addr; /* Virtual address of ASCB */
297 U32 hlhi_word; /* Highest lock held word */
298 VADR lit_addr; /* Virtual address of lock
299 interface table */
300 VADR lock_addr; /* Lock address */
301 int lock_arn; /* Lock access register */
302 U32 lock; /* Lock value */
303 VADR newia; /* Unsuccessful branch addr */
304 int acc_mode = 0; /* access mode to use */
305
306 SSE(inst, regs, b1, effective_addr1, b2, effective_addr2);
307
308 PRIV_CHECK(regs);
309
310 /* Specification exception if operands are not on word boundary */
311 if ((effective_addr1 & 0x00000003) || (effective_addr2 & 0x00000003))
312 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
313
314 PERFORM_SERIALIZATION(regs);
315
316 /* General register 11 contains the lock address */
317 lock_addr = regs->GR_L(11) & ADDRESS_MAXWRAP(regs);
318 lock_arn = 11;
319
320 /* Obtain main-storage access lock */
321 OBTAIN_MAINLOCK(regs);
322
323 if (ACCESS_REGISTER_MODE(®s->psw))
324 acc_mode = USE_PRIMARY_SPACE;
325
326 /* Load ASCB address from first operand location */
327 ascb_addr = ARCH_DEP(vfetch4) ( effective_addr1, acc_mode, regs );
328
329 /* Load locks held bits from second operand location */
330 hlhi_word = ARCH_DEP(vfetch4) ( effective_addr2, acc_mode, regs );
331
332 /* Fetch the lock addressed by general register 11 */
333 lock = ARCH_DEP(vfetch4) ( lock_addr, acc_mode, regs );
334
335 /* Obtain the lock if not held by any ASCB, and if this CPU
336 holds the local lock and does not hold a CMS lock */
337 if (lock == 0
338 && (hlhi_word & (PSALCLLI | PSACMSLI)) == PSALCLLI)
339 {
340 /* Store the unchanged value into the second operand to
341 ensure suppression in the event of an access exception */
342 ARCH_DEP(vstore4) ( hlhi_word, effective_addr2, acc_mode, regs );
343
344 /* Store the ASCB address in the CMS lock */
345 ARCH_DEP(vstore4) ( ascb_addr, lock_addr, acc_mode, regs );
346
347 /* Set the CMS lock held bit in the second operand */
348 hlhi_word |= PSACMSLI;
349 ARCH_DEP(vstore4) ( hlhi_word, effective_addr2, acc_mode, regs );
350
351 /* Set register 13 to zero to indicate lock obtained */
352 regs->GR_L(13) = 0;
353 }
354 else
355 {
356 /* Fetch the lock interface table address from the
357 second word of the second operand, and load the
358 new instruction address and amode from LITOCMS */
359 lit_addr = ARCH_DEP(vfetch4) ( effective_addr2 + 4, acc_mode, regs ) + LITOCMS;
360 lit_addr &= ADDRESS_MAXWRAP(regs);
361 newia = ARCH_DEP(vfetch4) ( lit_addr, acc_mode, regs );
362
363 /* Save the link information in register 12 */
364 regs->GR_L(12) = PSW_IA(regs, 0);
365
366 /* Copy LITOCMS into register 13 to signify obtain failure */
367 regs->GR_L(13) = newia;
368
369 /* Update the PSW instruction address */
370 UPD_PSW_IA(regs, newia);
371 }
372
373 /* Release main-storage access lock */
374 RELEASE_MAINLOCK(regs);
375
376 PERFORM_SERIALIZATION(regs);
377
378 } /* end function obtain_cms_lock */
379
380
381 /*-------------------------------------------------------------------*/
382 /* E507 - Release CMS Lock [SSE] */
383 /*-------------------------------------------------------------------*/
DEF_INST(release_cms_lock)384 DEF_INST(release_cms_lock)
385 {
386 int b1, b2; /* Values of base field */
387 VADR effective_addr1,
388 effective_addr2; /* Effective addresses */
389 VADR ascb_addr; /* Virtual address of ASCB */
390 U32 hlhi_word; /* Highest lock held word */
391 VADR lit_addr; /* Virtual address of lock
392 interface table */
393 VADR lock_addr; /* Lock address */
394 int lock_arn; /* Lock access register */
395 U32 lock; /* Lock value */
396 U32 susp; /* Lock suspend queue */
397 VADR newia; /* Unsuccessful branch addr */
398 int acc_mode = 0; /* access mode to use */
399
400 SSE(inst, regs, b1, effective_addr1, b2, effective_addr2);
401
402 PRIV_CHECK(regs);
403
404 /* Specification exception if operands are not on word boundary */
405 if ((effective_addr1 & 0x00000003) || (effective_addr2 & 0x00000003))
406 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
407
408 /* General register 11 contains the lock address */
409 lock_addr = regs->GR_L(11) & ADDRESS_MAXWRAP(regs);
410 lock_arn = 11;
411
412 /* Obtain main-storage access lock */
413 OBTAIN_MAINLOCK(regs);
414
415 if (ACCESS_REGISTER_MODE(®s->psw))
416 acc_mode = USE_PRIMARY_SPACE;
417
418 /* Load ASCB address from first operand location */
419 ascb_addr = ARCH_DEP(vfetch4) ( effective_addr1, acc_mode, regs );
420
421 /* Load locks held bits from second operand location */
422 hlhi_word = ARCH_DEP(vfetch4) ( effective_addr2, acc_mode, regs );
423
424 /* Fetch the CMS lock and the suspend queue word */
425 lock = ARCH_DEP(vfetch4) ( lock_addr, acc_mode, regs );
426 susp = ARCH_DEP(vfetch4) ( lock_addr + 4, acc_mode, regs );
427
428 /* Test if current ASCB holds this lock, the locks held indicators
429 show a CMS lock is held, and the lock suspend queue is empty */
430 if (lock == ascb_addr
431 && (hlhi_word & PSACMSLI)
432 && susp == 0)
433 {
434 /* Store the unchanged value into the second operand to
435 ensure suppression in the event of an access exception */
436 ARCH_DEP(vstore4) ( hlhi_word, effective_addr2, acc_mode, regs );
437
438 /* Set the CMS lock to zero */
439 ARCH_DEP(vstore4) ( 0, lock_addr, acc_mode, regs );
440
441 /* Clear the CMS lock held bit in the second operand */
442 hlhi_word &= ~PSACMSLI;
443 ARCH_DEP(vstore4) ( hlhi_word, effective_addr2, acc_mode, regs );
444
445 /* Set register 13 to zero to indicate lock released */
446 regs->GR_L(13) = 0;
447 }
448 else
449 {
450 /* Fetch the lock interface table address from the
451 second word of the second operand, and load the
452 new instruction address and amode from LITRCMS */
453 lit_addr = ARCH_DEP(vfetch4) ( effective_addr2 + 4, acc_mode, regs ) + LITRCMS;
454 lit_addr &= ADDRESS_MAXWRAP(regs);
455 newia = ARCH_DEP(vfetch4) ( lit_addr, acc_mode, regs );
456
457 /* Save the link information in register 12 */
458 regs->GR_L(12) = PSW_IA(regs, 0);
459
460 /* Copy LITRCMS into register 13 to signify release failure */
461 regs->GR_L(13) = newia;
462
463 /* Update the PSW instruction address */
464 UPD_PSW_IA(regs, newia);
465 }
466
467 /* Release main-storage access lock */
468 RELEASE_MAINLOCK(regs);
469
470 } /* end function release_cms_lock */
471
472
473 #if !defined(FEATURE_TRACING)
474 /*-------------------------------------------------------------------*/
475 /* E508 - Trace SVC Interruption [SSE] */
476 /*-------------------------------------------------------------------*/
DEF_INST(trace_svc_interruption)477 DEF_INST(trace_svc_interruption)
478 {
479 int b1, b2; /* Values of base field */
480 VADR effective_addr1,
481 effective_addr2; /* Effective addresses */
482
483 SSE(inst, regs, b1, effective_addr1, b2, effective_addr2);
484
485 PRIV_CHECK(regs);
486
487 /* Specification exception if operands are not on word boundary */
488 if ((effective_addr1 & 0x00000003) || (effective_addr2 & 0x00000003))
489 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
490
491 PTT(PTT_CL_ERR,"*E508 TRSVC",effective_addr1,effective_addr2,regs->psw.IA_L);
492 /*INCOMPLETE: NO TRACE ENTRY IS GENERATED*/
493
494 }
495
496
497 /*-------------------------------------------------------------------*/
498 /* E509 - Trace Program Interruption [SSE] */
499 /*-------------------------------------------------------------------*/
DEF_INST(trace_program_interruption)500 DEF_INST(trace_program_interruption)
501 {
502 int b1, b2; /* Values of base field */
503 VADR effective_addr1,
504 effective_addr2; /* Effective addresses */
505
506 SSE(inst, regs, b1, effective_addr1, b2, effective_addr2);
507
508 PRIV_CHECK(regs);
509
510 /* Specification exception if operands are not on word boundary */
511 if ((effective_addr1 & 0x00000003) || (effective_addr2 & 0x00000003))
512 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
513
514 PTT(PTT_CL_ERR,"*E509 TRPGM",effective_addr1,effective_addr2,regs->psw.IA_L);
515 /*INCOMPLETE: NO TRACE ENTRY IS GENERATED*/
516
517 }
518
519
520 /*-------------------------------------------------------------------*/
521 /* E50A - Trace Initial SRB Dispatch [SSE] */
522 /*-------------------------------------------------------------------*/
DEF_INST(trace_initial_srb_dispatch)523 DEF_INST(trace_initial_srb_dispatch)
524 {
525 int b1, b2; /* Values of base field */
526 VADR effective_addr1,
527 effective_addr2; /* Effective addresses */
528
529 SSE(inst, regs, b1, effective_addr1, b2, effective_addr2);
530
531 PRIV_CHECK(regs);
532
533 /* Specification exception if operands are not on word boundary */
534 if ((effective_addr1 & 0x00000003) || (effective_addr2 & 0x00000003))
535 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
536
537 PTT(PTT_CL_ERR,"*E50A TRSRB",effective_addr1,effective_addr2,regs->psw.IA_L);
538 /*INCOMPLETE: NO TRACE ENTRY IS GENERATED*/
539
540 }
541
542
543 /*-------------------------------------------------------------------*/
544 /* E50B - Trace I/O Interruption [SSE] */
545 /*-------------------------------------------------------------------*/
DEF_INST(trace_io_interruption)546 DEF_INST(trace_io_interruption)
547 {
548 int b1, b2; /* Values of base field */
549 VADR effective_addr1,
550 effective_addr2; /* Effective addresses */
551
552 SSE(inst, regs, b1, effective_addr1, b2, effective_addr2);
553
554 PRIV_CHECK(regs);
555
556 /* Specification exception if operands are not on word boundary */
557 if ((effective_addr1 & 0x00000003) || (effective_addr2 & 0x00000003))
558 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
559
560 PTT(PTT_CL_ERR,"*E50B TRIO",effective_addr1,effective_addr2,regs->psw.IA_L);
561 /*INCOMPLETE: NO TRACE ENTRY IS GENERATED*/
562
563 }
564
565
566 /*-------------------------------------------------------------------*/
567 /* E50C - Trace Task Dispatch [SSE] */
568 /*-------------------------------------------------------------------*/
DEF_INST(trace_task_dispatch)569 DEF_INST(trace_task_dispatch)
570 {
571 int b1, b2; /* Values of base field */
572 VADR effective_addr1,
573 effective_addr2; /* Effective addresses */
574
575 SSE(inst, regs, b1, effective_addr1, b2, effective_addr2);
576
577 PRIV_CHECK(regs);
578
579 /* Specification exception if operands are not on word boundary */
580 if ((effective_addr1 & 0x00000003) || (effective_addr2 & 0x00000003))
581 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
582
583 PTT(PTT_CL_ERR,"*E50C TRTSK",effective_addr1,effective_addr2,regs->psw.IA_L);
584 /*INCOMPLETE: NO TRACE ENTRY IS GENERATED*/
585
586 }
587
588
589 /*-------------------------------------------------------------------*/
590 /* E50D - Trace SVC Return [SSE] */
591 /*-------------------------------------------------------------------*/
DEF_INST(trace_svc_return)592 DEF_INST(trace_svc_return)
593 {
594 int b1, b2; /* Values of base field */
595 VADR effective_addr1,
596 effective_addr2; /* Effective addresses */
597
598 SSE(inst, regs, b1, effective_addr1, b2, effective_addr2);
599
600 PRIV_CHECK(regs);
601
602 /* Specification exception if operands are not on word boundary */
603 if ((effective_addr1 & 0x00000003) || (effective_addr2 & 0x00000003))
604 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
605
606 PTT(PTT_CL_ERR,"*E50D TRRTN",effective_addr1,effective_addr2,regs->psw.IA_L);
607 /*INCOMPLETE: NO TRACE ENTRY IS GENERATED*/
608
609 }
610 #endif /*!defined(FEATURE_TRACING)*/
611
612
613 #if !defined(_GEN_ARCH)
614
615 #if defined(_ARCHMODE2)
616 #define _GEN_ARCH _ARCHMODE2
617 #include "assist.c"
618 #endif
619
620 #if defined(_ARCHMODE3)
621 #undef _GEN_ARCH
622 #define _GEN_ARCH _ARCHMODE3
623 #include "assist.c"
624 #endif
625
626 #endif /*!defined(_GEN_ARCH)*/
627