1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 #include "ta_xgmi_if.h" 31 #include "ta_ras_if.h" 32 #include "ta_rap_if.h" 33 #include "ta_secureDisplay_if.h" 34 35 #define PSP_FENCE_BUFFER_SIZE 0x1000 36 #define PSP_CMD_BUFFER_SIZE 0x1000 37 #define PSP_1_MEG 0x100000 38 #define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000) 39 #define PSP_TMR_ALIGNMENT 0x100000 40 #define PSP_FW_NAME_LEN 0x24 41 42 extern const struct attribute_group amdgpu_flash_attr_group; 43 44 enum psp_shared_mem_size { 45 PSP_ASD_SHARED_MEM_SIZE = 0x0, 46 PSP_XGMI_SHARED_MEM_SIZE = 0x4000, 47 PSP_RAS_SHARED_MEM_SIZE = 0x4000, 48 PSP_HDCP_SHARED_MEM_SIZE = 0x4000, 49 PSP_DTM_SHARED_MEM_SIZE = 0x4000, 50 PSP_RAP_SHARED_MEM_SIZE = 0x4000, 51 PSP_SECUREDISPLAY_SHARED_MEM_SIZE = 0x4000, 52 }; 53 54 enum ta_type_id { 55 TA_TYPE_XGMI = 1, 56 TA_TYPE_RAS, 57 TA_TYPE_HDCP, 58 TA_TYPE_DTM, 59 TA_TYPE_RAP, 60 TA_TYPE_SECUREDISPLAY, 61 62 TA_TYPE_MAX_INDEX, 63 }; 64 65 struct psp_context; 66 struct psp_xgmi_node_info; 67 struct psp_xgmi_topology_info; 68 struct psp_bin_desc; 69 70 enum psp_bootloader_cmd { 71 PSP_BL__LOAD_SYSDRV = 0x10000, 72 PSP_BL__LOAD_SOSDRV = 0x20000, 73 PSP_BL__LOAD_KEY_DATABASE = 0x80000, 74 PSP_BL__LOAD_SOCDRV = 0xB0000, 75 PSP_BL__LOAD_DBGDRV = 0xC0000, 76 PSP_BL__LOAD_HADDRV = PSP_BL__LOAD_DBGDRV, 77 PSP_BL__LOAD_INTFDRV = 0xD0000, 78 PSP_BL__LOAD_RASDRV = 0xE0000, 79 PSP_BL__LOAD_IPKEYMGRDRV = 0xF0000, 80 PSP_BL__DRAM_LONG_TRAIN = 0x100000, 81 PSP_BL__DRAM_SHORT_TRAIN = 0x200000, 82 PSP_BL__LOAD_TOS_SPL_TABLE = 0x10000000, 83 }; 84 85 enum psp_ring_type { 86 PSP_RING_TYPE__INVALID = 0, 87 /* 88 * These values map to the way the PSP kernel identifies the 89 * rings. 90 */ 91 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 92 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 93 }; 94 95 struct psp_ring { 96 enum psp_ring_type ring_type; 97 struct psp_gfx_rb_frame *ring_mem; 98 uint64_t ring_mem_mc_addr; 99 void *ring_mem_handle; 100 uint32_t ring_size; 101 uint32_t ring_wptr; 102 }; 103 104 /* More registers may will be supported */ 105 enum psp_reg_prog_id { 106 PSP_REG_IH_RB_CNTL = 0, /* register IH_RB_CNTL */ 107 PSP_REG_IH_RB_CNTL_RING1 = 1, /* register IH_RB_CNTL_RING1 */ 108 PSP_REG_IH_RB_CNTL_RING2 = 2, /* register IH_RB_CNTL_RING2 */ 109 PSP_REG_LAST 110 }; 111 112 struct psp_funcs { 113 int (*init_microcode)(struct psp_context *psp); 114 int (*wait_for_bootloader)(struct psp_context *psp); 115 int (*bootloader_load_kdb)(struct psp_context *psp); 116 int (*bootloader_load_spl)(struct psp_context *psp); 117 int (*bootloader_load_sysdrv)(struct psp_context *psp); 118 int (*bootloader_load_soc_drv)(struct psp_context *psp); 119 int (*bootloader_load_intf_drv)(struct psp_context *psp); 120 int (*bootloader_load_dbg_drv)(struct psp_context *psp); 121 int (*bootloader_load_ras_drv)(struct psp_context *psp); 122 int (*bootloader_load_ipkeymgr_drv)(struct psp_context *psp); 123 int (*bootloader_load_sos)(struct psp_context *psp); 124 int (*ring_create)(struct psp_context *psp, 125 enum psp_ring_type ring_type); 126 int (*ring_stop)(struct psp_context *psp, 127 enum psp_ring_type ring_type); 128 int (*ring_destroy)(struct psp_context *psp, 129 enum psp_ring_type ring_type); 130 bool (*smu_reload_quirk)(struct psp_context *psp); 131 int (*mode1_reset)(struct psp_context *psp); 132 int (*mem_training)(struct psp_context *psp, uint32_t ops); 133 uint32_t (*ring_get_wptr)(struct psp_context *psp); 134 void (*ring_set_wptr)(struct psp_context *psp, uint32_t value); 135 int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 136 int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver); 137 int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr); 138 int (*vbflash_stat)(struct psp_context *psp); 139 int (*fatal_error_recovery_quirk)(struct psp_context *psp); 140 bool (*get_ras_capability)(struct psp_context *psp); 141 }; 142 143 struct ta_funcs { 144 int (*fn_ta_initialize)(struct psp_context *psp); 145 int (*fn_ta_invoke)(struct psp_context *psp, uint32_t ta_cmd_id); 146 int (*fn_ta_terminate)(struct psp_context *psp); 147 }; 148 149 #define AMDGPU_XGMI_MAX_CONNECTED_NODES 64 150 struct psp_xgmi_node_info { 151 uint64_t node_id; 152 uint8_t num_hops; 153 uint8_t is_sharing_enabled; 154 enum ta_xgmi_assigned_sdma_engine sdma_engine; 155 uint8_t num_links; 156 struct xgmi_connected_port_num port_num[TA_XGMI__MAX_PORT_NUM]; 157 }; 158 159 struct psp_xgmi_topology_info { 160 uint32_t num_nodes; 161 struct psp_xgmi_node_info nodes[AMDGPU_XGMI_MAX_CONNECTED_NODES]; 162 }; 163 164 struct psp_bin_desc { 165 uint32_t fw_version; 166 uint32_t feature_version; 167 uint32_t size_bytes; 168 uint8_t *start_addr; 169 }; 170 171 struct ta_mem_context { 172 struct amdgpu_bo *shared_bo; 173 uint64_t shared_mc_addr; 174 void *shared_buf; 175 enum psp_shared_mem_size shared_mem_size; 176 }; 177 178 struct ta_context { 179 bool initialized; 180 uint32_t session_id; 181 uint32_t resp_status; 182 struct ta_mem_context mem_context; 183 struct psp_bin_desc bin_desc; 184 enum psp_gfx_cmd_id ta_load_type; 185 enum ta_type_id ta_type; 186 }; 187 188 struct ta_cp_context { 189 struct ta_context context; 190 struct mutex mutex; 191 }; 192 193 struct psp_xgmi_context { 194 struct ta_context context; 195 struct psp_xgmi_topology_info top_info; 196 bool supports_extended_data; 197 uint8_t xgmi_ta_caps; 198 }; 199 200 struct psp_ras_context { 201 struct ta_context context; 202 struct amdgpu_ras *ras; 203 }; 204 205 #define MEM_TRAIN_SYSTEM_SIGNATURE 0x54534942 206 #define GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES 0x1000 207 #define GDDR6_MEM_TRAINING_OFFSET 0x8000 208 /*Define the VRAM size that will be encroached by BIST training.*/ 209 #define BIST_MEM_TRAINING_ENCROACHED_SIZE 0x2000000 210 211 enum psp_memory_training_init_flag { 212 PSP_MEM_TRAIN_NOT_SUPPORT = 0x0, 213 PSP_MEM_TRAIN_SUPPORT = 0x1, 214 PSP_MEM_TRAIN_INIT_FAILED = 0x2, 215 PSP_MEM_TRAIN_RESERVE_SUCCESS = 0x4, 216 PSP_MEM_TRAIN_INIT_SUCCESS = 0x8, 217 }; 218 219 enum psp_memory_training_ops { 220 PSP_MEM_TRAIN_SEND_LONG_MSG = 0x1, 221 PSP_MEM_TRAIN_SAVE = 0x2, 222 PSP_MEM_TRAIN_RESTORE = 0x4, 223 PSP_MEM_TRAIN_SEND_SHORT_MSG = 0x8, 224 PSP_MEM_TRAIN_COLD_BOOT = PSP_MEM_TRAIN_SEND_LONG_MSG, 225 PSP_MEM_TRAIN_RESUME = PSP_MEM_TRAIN_SEND_SHORT_MSG, 226 }; 227 228 struct psp_memory_training_context { 229 /*training data size*/ 230 u64 train_data_size; 231 /* 232 * sys_cache 233 * cpu virtual address 234 * system memory buffer that used to store the training data. 235 */ 236 void *sys_cache; 237 238 /*vram offset of the p2c training data*/ 239 u64 p2c_train_data_offset; 240 241 /*vram offset of the c2p training data*/ 242 u64 c2p_train_data_offset; 243 struct amdgpu_bo *c2p_bo; 244 245 enum psp_memory_training_init_flag init; 246 u32 training_cnt; 247 bool enable_mem_training; 248 }; 249 250 /** PSP runtime DB **/ 251 #define PSP_RUNTIME_DB_SIZE_IN_BYTES 0x10000 252 #define PSP_RUNTIME_DB_OFFSET 0x100000 253 #define PSP_RUNTIME_DB_COOKIE_ID 0x0ed5 254 #define PSP_RUNTIME_DB_VER_1 0x0100 255 #define PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT 0x40 256 257 enum psp_runtime_entry_type { 258 PSP_RUNTIME_ENTRY_TYPE_INVALID = 0x0, 259 PSP_RUNTIME_ENTRY_TYPE_TEST = 0x1, 260 PSP_RUNTIME_ENTRY_TYPE_MGPU_COMMON = 0x2, /* Common mGPU runtime data */ 261 PSP_RUNTIME_ENTRY_TYPE_MGPU_WAFL = 0x3, /* WAFL runtime data */ 262 PSP_RUNTIME_ENTRY_TYPE_MGPU_XGMI = 0x4, /* XGMI runtime data */ 263 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG = 0x5, /* Boot Config runtime data */ 264 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS = 0x6, /* SCPM validation data */ 265 }; 266 267 /* PSP runtime DB header */ 268 struct psp_runtime_data_header { 269 /* determine the existence of runtime db */ 270 uint16_t cookie; 271 /* version of runtime db */ 272 uint16_t version; 273 }; 274 275 /* PSP runtime DB entry */ 276 struct psp_runtime_entry { 277 /* type of runtime db entry */ 278 uint32_t entry_type; 279 /* offset of entry in bytes */ 280 uint16_t offset; 281 /* size of entry in bytes */ 282 uint16_t size; 283 }; 284 285 /* PSP runtime DB directory */ 286 struct psp_runtime_data_directory { 287 /* number of valid entries */ 288 uint16_t entry_count; 289 /* db entries*/ 290 struct psp_runtime_entry entry_list[PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT]; 291 }; 292 293 /* PSP runtime DB boot config feature bitmask */ 294 enum psp_runtime_boot_cfg_feature { 295 BOOT_CFG_FEATURE_GECC = 0x1, 296 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING = 0x2, 297 }; 298 299 /* PSP run time DB SCPM authentication defines */ 300 enum psp_runtime_scpm_authentication { 301 SCPM_DISABLE = 0x0, 302 SCPM_ENABLE = 0x1, 303 SCPM_ENABLE_WITH_SCPM_ERR = 0x2, 304 }; 305 306 /* PSP runtime DB boot config entry */ 307 struct psp_runtime_boot_cfg_entry { 308 uint32_t boot_cfg_bitmask; 309 uint32_t reserved; 310 }; 311 312 /* PSP runtime DB SCPM entry */ 313 struct psp_runtime_scpm_entry { 314 enum psp_runtime_scpm_authentication scpm_status; 315 }; 316 317 struct psp_context { 318 struct amdgpu_device *adev; 319 struct psp_ring km_ring; 320 struct psp_gfx_cmd_resp *cmd; 321 322 const struct psp_funcs *funcs; 323 const struct ta_funcs *ta_funcs; 324 325 /* firmware buffer */ 326 struct amdgpu_bo *fw_pri_bo; 327 uint64_t fw_pri_mc_addr; 328 void *fw_pri_buf; 329 330 /* sos firmware */ 331 const struct firmware *sos_fw; 332 struct psp_bin_desc sys; 333 struct psp_bin_desc sos; 334 struct psp_bin_desc toc; 335 struct psp_bin_desc kdb; 336 struct psp_bin_desc spl; 337 struct psp_bin_desc rl; 338 struct psp_bin_desc soc_drv; 339 struct psp_bin_desc intf_drv; 340 struct psp_bin_desc dbg_drv; 341 struct psp_bin_desc ras_drv; 342 struct psp_bin_desc ipkeymgr_drv; 343 344 /* tmr buffer */ 345 struct amdgpu_bo *tmr_bo; 346 uint64_t tmr_mc_addr; 347 348 /* asd firmware */ 349 const struct firmware *asd_fw; 350 351 /* toc firmware */ 352 const struct firmware *toc_fw; 353 354 /* cap firmware */ 355 const struct firmware *cap_fw; 356 357 /* fence buffer */ 358 struct amdgpu_bo *fence_buf_bo; 359 uint64_t fence_buf_mc_addr; 360 void *fence_buf; 361 362 /* cmd buffer */ 363 struct amdgpu_bo *cmd_buf_bo; 364 uint64_t cmd_buf_mc_addr; 365 struct psp_gfx_cmd_resp *cmd_buf_mem; 366 367 /* fence value associated with cmd buffer */ 368 atomic_t fence_value; 369 /* flag to mark whether gfx fw autoload is supported or not */ 370 bool autoload_supported; 371 /* flag to mark whether psp use runtime TMR or boottime TMR */ 372 bool boot_time_tmr; 373 /* flag to mark whether df cstate management centralized to PMFW */ 374 bool pmfw_centralized_cstate_management; 375 376 /* xgmi ta firmware and buffer */ 377 const struct firmware *ta_fw; 378 uint32_t ta_fw_version; 379 380 uint32_t cap_fw_version; 381 uint32_t cap_feature_version; 382 uint32_t cap_ucode_size; 383 384 struct ta_context asd_context; 385 struct psp_xgmi_context xgmi_context; 386 struct psp_ras_context ras_context; 387 struct ta_cp_context hdcp_context; 388 struct ta_cp_context dtm_context; 389 struct ta_cp_context rap_context; 390 struct ta_cp_context securedisplay_context; 391 struct mutex mutex; 392 struct psp_memory_training_context mem_train_ctx; 393 394 uint32_t boot_cfg_bitmask; 395 396 /* firmware upgrades supported */ 397 bool sup_pd_fw_up; 398 bool sup_ifwi_up; 399 400 char *vbflash_tmp_buf; 401 size_t vbflash_image_size; 402 bool vbflash_done; 403 }; 404 405 struct amdgpu_psp_funcs { 406 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 407 enum AMDGPU_UCODE_ID); 408 }; 409 410 411 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 412 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 413 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 414 #define psp_init_microcode(psp) \ 415 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 416 #define psp_bootloader_load_kdb(psp) \ 417 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0) 418 #define psp_bootloader_load_spl(psp) \ 419 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0) 420 #define psp_bootloader_load_sysdrv(psp) \ 421 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 422 #define psp_bootloader_load_soc_drv(psp) \ 423 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0) 424 #define psp_bootloader_load_intf_drv(psp) \ 425 ((psp)->funcs->bootloader_load_intf_drv ? (psp)->funcs->bootloader_load_intf_drv((psp)) : 0) 426 #define psp_bootloader_load_dbg_drv(psp) \ 427 ((psp)->funcs->bootloader_load_dbg_drv ? (psp)->funcs->bootloader_load_dbg_drv((psp)) : 0) 428 #define psp_bootloader_load_ras_drv(psp) \ 429 ((psp)->funcs->bootloader_load_ras_drv ? \ 430 (psp)->funcs->bootloader_load_ras_drv((psp)) : 0) 431 #define psp_bootloader_load_ipkeymgr_drv(psp) \ 432 ((psp)->funcs->bootloader_load_ipkeymgr_drv ? \ 433 (psp)->funcs->bootloader_load_ipkeymgr_drv((psp)) : 0) 434 #define psp_bootloader_load_sos(psp) \ 435 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 436 #define psp_smu_reload_quirk(psp) \ 437 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 438 #define psp_mode1_reset(psp) \ 439 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 440 #define psp_mem_training(psp, ops) \ 441 ((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0) 442 443 #define psp_ring_get_wptr(psp) (psp)->funcs->ring_get_wptr((psp)) 444 #define psp_ring_set_wptr(psp, value) (psp)->funcs->ring_set_wptr((psp), (value)) 445 446 #define psp_load_usbc_pd_fw(psp, fw_pri_mc_addr) \ 447 ((psp)->funcs->load_usbc_pd_fw ? \ 448 (psp)->funcs->load_usbc_pd_fw((psp), (fw_pri_mc_addr)) : -EINVAL) 449 450 #define psp_read_usbc_pd_fw(psp, fw_ver) \ 451 ((psp)->funcs->read_usbc_pd_fw ? \ 452 (psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL) 453 454 #define psp_update_spirom(psp, fw_pri_mc_addr) \ 455 ((psp)->funcs->update_spirom ? \ 456 (psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL) 457 458 #define psp_vbflash_status(psp) \ 459 ((psp)->funcs->vbflash_stat ? \ 460 (psp)->funcs->vbflash_stat((psp)) : -EINVAL) 461 462 #define psp_fatal_error_recovery_quirk(psp) \ 463 ((psp)->funcs->fatal_error_recovery_quirk ? \ 464 (psp)->funcs->fatal_error_recovery_quirk((psp)) : 0) 465 466 extern const struct amd_ip_funcs psp_ip_funcs; 467 468 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 469 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 470 extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; 471 extern const struct amdgpu_ip_block_version psp_v11_0_8_ip_block; 472 extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; 473 extern const struct amdgpu_ip_block_version psp_v13_0_ip_block; 474 extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block; 475 extern const struct amdgpu_ip_block_version psp_v14_0_ip_block; 476 477 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 478 uint32_t field_val, uint32_t mask, bool check_changed); 479 extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index, 480 uint32_t field_val, uint32_t mask, uint32_t msec_timeout); 481 482 int psp_execute_ip_fw_load(struct psp_context *psp, 483 struct amdgpu_firmware_info *ucode); 484 485 int psp_gpu_reset(struct amdgpu_device *adev); 486 487 int psp_ta_init_shared_buf(struct psp_context *psp, 488 struct ta_mem_context *mem_ctx); 489 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx); 490 int psp_ta_unload(struct psp_context *psp, struct ta_context *context); 491 int psp_ta_load(struct psp_context *psp, struct ta_context *context); 492 int psp_ta_invoke(struct psp_context *psp, 493 uint32_t ta_cmd_id, 494 struct ta_context *context); 495 496 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta); 497 int psp_xgmi_terminate(struct psp_context *psp); 498 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 499 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id); 500 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id); 501 int psp_xgmi_get_topology_info(struct psp_context *psp, 502 int number_devices, 503 struct psp_xgmi_topology_info *topology, 504 bool get_extended_data); 505 int psp_xgmi_set_topology_info(struct psp_context *psp, 506 int number_devices, 507 struct psp_xgmi_topology_info *topology); 508 int psp_ras_initialize(struct psp_context *psp); 509 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 510 int psp_ras_enable_features(struct psp_context *psp, 511 union ta_ras_cmd_input *info, bool enable); 512 int psp_ras_trigger_error(struct psp_context *psp, 513 struct ta_ras_trigger_error_input *info, uint32_t instance_mask); 514 int psp_ras_terminate(struct psp_context *psp); 515 int psp_ras_query_address(struct psp_context *psp, 516 struct ta_ras_query_address_input *addr_in, 517 struct ta_ras_query_address_output *addr_out); 518 519 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 520 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 521 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status); 522 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id); 523 524 int psp_rlc_autoload_start(struct psp_context *psp); 525 526 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 527 uint32_t value); 528 int psp_ring_cmd_submit(struct psp_context *psp, 529 uint64_t cmd_buf_mc_addr, 530 uint64_t fence_mc_addr, 531 int index); 532 int psp_init_asd_microcode(struct psp_context *psp, 533 const char *chip_name); 534 int psp_init_toc_microcode(struct psp_context *psp, 535 const char *chip_name); 536 int psp_init_sos_microcode(struct psp_context *psp, 537 const char *chip_name); 538 int psp_init_ta_microcode(struct psp_context *psp, 539 const char *chip_name); 540 int psp_init_cap_microcode(struct psp_context *psp, 541 const char *chip_name); 542 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 543 uint64_t *output_ptr); 544 545 int psp_load_fw_list(struct psp_context *psp, 546 struct amdgpu_firmware_info **ucode_list, int ucode_count); 547 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size); 548 549 int psp_spatial_partition(struct psp_context *psp, int mode); 550 551 int is_psp_fw_valid(struct psp_bin_desc bin); 552 553 int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev); 554 bool amdgpu_psp_get_ras_capability(struct psp_context *psp); 555 #endif 556