1 /* BFD support for Infineon's TriCore architecture.
2 Copyright (C) 1998-2003 Free Software Foundation, Inc.
3 Contributed by Michael Schumacher (mike@hightec-rt.com).
4
5 This file is part of BFD, the Binary File Descriptor library.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335 USA */
20
21 #include <stdio.h>
22 #include <string.h>
23 #include <sys/types.h>
24 #include <stdbool.h>
25
26 //#include "bfd.h"
27 #include "sysdep.h"
28 #include "disas-asm.h"
29 //#include "libbfd.h"
30 #include "opcode/tricore.h"
31
32 /* Opcode masks for TriCore's various instruction formats. */
33
34 unsigned long tricore_mask_abs;
35 unsigned long tricore_mask_absb;
36 unsigned long tricore_mask_b;
37 unsigned long tricore_mask_bit;
38 unsigned long tricore_mask_bo;
39 unsigned long tricore_mask_bol;
40 unsigned long tricore_mask_brc;
41 unsigned long tricore_mask_brn;
42 unsigned long tricore_mask_brr;
43 unsigned long tricore_mask_rc;
44 unsigned long tricore_mask_rcpw;
45 unsigned long tricore_mask_rcr;
46 unsigned long tricore_mask_rcrr;
47 unsigned long tricore_mask_rcrw;
48 unsigned long tricore_mask_rlc;
49 unsigned long tricore_mask_rr;
50 unsigned long tricore_mask_rr1;
51 unsigned long tricore_mask_rr2;
52 unsigned long tricore_mask_rrpw;
53 unsigned long tricore_mask_rrr;
54 unsigned long tricore_mask_rrr1;
55 unsigned long tricore_mask_rrr2;
56 unsigned long tricore_mask_rrrr;
57 unsigned long tricore_mask_rrrw;
58 unsigned long tricore_mask_sys;
59 unsigned long tricore_mask_sb;
60 unsigned long tricore_mask_sbc;
61 unsigned long tricore_mask_sbr;
62 unsigned long tricore_mask_sbrn;
63 unsigned long tricore_mask_sc;
64 unsigned long tricore_mask_slr;
65 unsigned long tricore_mask_slro;
66 unsigned long tricore_mask_sr;
67 unsigned long tricore_mask_src;
68 unsigned long tricore_mask_sro;
69 unsigned long tricore_mask_srr;
70 unsigned long tricore_mask_srrs;
71 unsigned long tricore_mask_ssr;
72 unsigned long tricore_mask_ssro;
73 unsigned long tricore_opmask[TRICORE_FMT_MAX];
74
75 int
bfd_default_scan(info,string)76 bfd_default_scan (info, string)
77 const bfd_arch_info_type *info;
78 const char *string;
79 {
80 return true;
81 }
82
83 const bfd_arch_info_type *
bfd_default_compatible(a,b)84 bfd_default_compatible (a, b)
85 const bfd_arch_info_type *a;
86 const bfd_arch_info_type *b;
87 {
88 if (a->arch != b->arch) {
89 return NULL;
90 }
91
92 if (a->bits_per_word != b->bits_per_word) {
93 return NULL;
94 }
95
96 if (a->mach > b->mach) {
97 return a;
98 }
99
100 if (b->mach > a->mach) {
101 return b;
102 }
103
104 return a;
105 }
106
107 void tricore_init_arch_vars PARAMS ((unsigned long));
108
109 /* Describe the various flavours of the TriCore architecture. */
110
111 static const bfd_arch_info_type arch_info_struct[] =
112 {
113 /* Rider-A ISA. */
114 {
115 32, /* 32 bits per word. */
116 32, /* 32 bits per address. */
117 8, /* 8 bits per byte. */
118 bfd_arch_tricore, /* Architecture type. */
119 bfd_mach_rider_a, /* Machine type. */
120 "tricore", /* Name of architecture (internal use). */
121 "TriCore:Rider-A", /* Name of architecture to print. */
122 3, /* Align sections on 8 byte boundaries. */
123 false, /* No, this is ain't the default arch type. */
124 bfd_default_compatible, /* We're compatible with ourselves. */
125 bfd_default_scan, /* Let BFD find the default arch. */
126 &arch_info_struct[1] /* Next TriCore architecture. */
127 },
128
129 /* Rider-D ISA. */
130 {
131 32, /* 32 bits per word. */
132 32, /* 32 bits per address. */
133 8, /* 8 bits per byte. */
134 bfd_arch_tricore, /* Architecture type. */
135 bfd_mach_rider_d, /* Machine type. */
136 "tricore", /* Name of architecture (internal use). */
137 "TriCore:Rider-D", /* Name of architecture to print. */
138 3, /* Align sections on 8 byte boundaries. */
139 false, /* No, this is ain't the default arch type. */
140 bfd_default_compatible, /* We're compatible with ourselves. */
141 bfd_default_scan, /* Let BFD find the default arch. */
142 &arch_info_struct[2] /* Next TriCore architecture. */
143 },
144
145 /* TriCore V2 ISA. */
146 {
147 32, /* 32 bits per word. */
148 32, /* 32 bits per address. */
149 8, /* 8 bits per byte. */
150 bfd_arch_tricore, /* Architecture type. */
151 bfd_mach_rider_2, /* Machine type. */
152 "tricore", /* Name of architecture (internal use). */
153 "TriCore:V2", /* Name of architecture to print. */
154 3, /* Align sections on 8 byte boundaries. */
155 false, /* No, this is ain't the default arch type. */
156 bfd_default_compatible, /* We're compatible with ourselves. */
157 bfd_default_scan, /* Let BFD find the default arch. */
158 (bfd_arch_info_type *) 0 /* No more arch types for TriCore. */
159 }
160 };
161
162 const bfd_arch_info_type bfd_tricore_arch =
163 {
164 /* Rider-B ISA. */
165 32, /* 32 bits per word. */
166 32, /* 32 bits per address. */
167 8, /* 8 bits per byte. */
168 bfd_arch_tricore, /* Architecture type. */
169 bfd_mach_rider_b, /* Machine type. */
170 "tricore", /* Name of architecture (internal use). */
171 "TriCore:Rider-B", /* Name of architecture to print. */
172 3, /* Align sections on 8 byte boundaries. */
173 true, /* Yes, this is the default arch type. */
174 bfd_default_compatible, /* We're compatible with ourselves. */
175 bfd_default_scan, /* Let BFD find the default arch. */
176 &arch_info_struct[0] /* Next arch type for TriCore. */
177 };
178
179 /* Initialize the architecture-specific variables. This must be called
180 by the assembler and disassembler prior to encoding/decoding any
181 TriCore instructions; the linker (or more precisely, the specific
182 back-end, bfd/elf32-tricore.c:tricore_elf32_relocate_section) will
183 also have to call this if it ever accesses the variables below, but
184 it currently doesn't. */
185
186 void
tricore_init_arch_vars(mach)187 tricore_init_arch_vars (mach)
188 unsigned long mach;
189 {
190 switch (mach & bfd_mach_rider_mask)
191 {
192 case bfd_mach_rider_a:
193 tricore_mask_abs = 0x0c0000ff;
194 tricore_mask_absb = 0x0c0000ff;
195 tricore_mask_b = 0x000000ff;
196 tricore_mask_bit = 0x006000ff;
197 tricore_mask_bo = 0x0fc000ff;
198 tricore_mask_bol = 0x000000ff;
199 tricore_mask_brc = 0x800000ff;
200 tricore_mask_brn = 0x8000007f;
201 tricore_mask_brr = 0x800000ff;
202 tricore_mask_rc = 0x0fe000ff;
203 tricore_mask_rcpw = 0x006000ff;
204 tricore_mask_rcr = 0x00e000ff;
205 tricore_mask_rcrr = 0x00e000ff;
206 tricore_mask_rcrw = 0x00e000ff;
207 tricore_mask_rlc = 0x000000ff;
208 tricore_mask_rr = 0x0ff000ff;
209 tricore_mask_rrpw = 0x006000ff;
210 tricore_mask_rrr = 0x00f000ff;
211 tricore_mask_rrr1 = 0x00fc00ff;
212 tricore_mask_rrr2 = 0x00ff00ff;
213 tricore_mask_rrrr = 0x00e000ff;
214 tricore_mask_rrrw = 0x00e000ff;
215 tricore_mask_sys = 0x07c000ff;
216 tricore_mask_sb = 0x00ff;
217 tricore_mask_sbc = 0x00ff;
218 tricore_mask_sbr = 0x00ff;
219 tricore_mask_sbrn = 0x007f;
220 tricore_mask_sc = 0x00ff;
221 tricore_mask_slr = 0x00ff;
222 tricore_mask_slro = 0x00ff;
223 tricore_mask_sr = 0xf0ff;
224 tricore_mask_src = 0x00ff;
225 tricore_mask_sro = 0x00ff;
226 tricore_mask_srr = 0x00ff;
227 tricore_mask_srrs = 0x003f;
228 tricore_mask_ssr = 0x00ff;
229 tricore_mask_ssro = 0x00ff;
230 break;
231
232 case bfd_mach_rider_b: /* Same as bfd_mach_rider_d! */
233 case bfd_mach_rider_2:
234 tricore_mask_abs = 0x0c0000ff;
235 tricore_mask_absb = 0x0c0000ff;
236 tricore_mask_b = 0x000000ff;
237 tricore_mask_bit = 0x006000ff;
238 tricore_mask_bo = 0x0fc000ff;
239 tricore_mask_bol = 0x000000ff;
240 tricore_mask_brc = 0x800000ff;
241 tricore_mask_brn = 0x8000007f;
242 tricore_mask_brr = 0x800000ff;
243 tricore_mask_rc = 0x0fe000ff;
244 tricore_mask_rcpw = 0x006000ff;
245 tricore_mask_rcr = 0x00e000ff;
246 tricore_mask_rcrr = 0x00e000ff;
247 tricore_mask_rcrw = 0x00e000ff;
248 tricore_mask_rlc = 0x000000ff;
249 tricore_mask_rr = 0x0ff300ff;
250 tricore_mask_rr1 = 0x0ffc00ff;
251 tricore_mask_rr2 = 0x0fff00ff;
252 tricore_mask_rrpw = 0x006000ff;
253 tricore_mask_rrr = 0x00f300ff;
254 tricore_mask_rrr1 = 0x00fc00ff;
255 tricore_mask_rrr2 = 0x00ff00ff;
256 tricore_mask_rrrr = 0x00e000ff;
257 tricore_mask_rrrw = 0x00e000ff;
258 if ((mach & bfd_mach_rider_mask) == bfd_mach_rider_2) {
259 tricore_mask_sys = 0x0fc000ff;
260 } else {
261 tricore_mask_sys = 0x07c000ff;
262 }
263 tricore_mask_sb = 0x00ff;
264 tricore_mask_sbc = 0x00ff;
265 tricore_mask_sbr = 0x00ff;
266 tricore_mask_sbrn = 0x00ff;
267 tricore_mask_sc = 0x00ff;
268 tricore_mask_slr = 0x00ff;
269 tricore_mask_slro = 0x00ff;
270 tricore_mask_sr = 0xf0ff;
271 tricore_mask_src = 0x00ff;
272 tricore_mask_sro = 0x00ff;
273 tricore_mask_srr = 0x00ff;
274 tricore_mask_srrs = 0x003f;
275 tricore_mask_ssr = 0x00ff;
276 tricore_mask_ssro = 0x00ff;
277 break;
278 }
279
280 /* Now fill in tricore_opmask[]. */
281
282 tricore_opmask[TRICORE_FMT_ABS] = tricore_mask_abs;
283 tricore_opmask[TRICORE_FMT_ABSB] = tricore_mask_absb;
284 tricore_opmask[TRICORE_FMT_B] = tricore_mask_b;
285 tricore_opmask[TRICORE_FMT_BIT] = tricore_mask_bit;
286 tricore_opmask[TRICORE_FMT_BO] = tricore_mask_bo;
287 tricore_opmask[TRICORE_FMT_BOL] = tricore_mask_bol;
288 tricore_opmask[TRICORE_FMT_BRC] = tricore_mask_brc;
289 tricore_opmask[TRICORE_FMT_BRN] = tricore_mask_brn;
290 tricore_opmask[TRICORE_FMT_BRR] = tricore_mask_brr;
291 tricore_opmask[TRICORE_FMT_RC] = tricore_mask_rc;
292 tricore_opmask[TRICORE_FMT_RCPW] = tricore_mask_rcpw;
293 tricore_opmask[TRICORE_FMT_RCR] = tricore_mask_rcr;
294 tricore_opmask[TRICORE_FMT_RCRR] = tricore_mask_rcrr;
295 tricore_opmask[TRICORE_FMT_RCRW] = tricore_mask_rcrw;
296 tricore_opmask[TRICORE_FMT_RLC] = tricore_mask_rlc;
297 tricore_opmask[TRICORE_FMT_RR] = tricore_mask_rr;
298 tricore_opmask[TRICORE_FMT_RR1] = tricore_mask_rr1;
299 tricore_opmask[TRICORE_FMT_RR2] = tricore_mask_rr2;
300 tricore_opmask[TRICORE_FMT_RRPW] = tricore_mask_rrpw;
301 tricore_opmask[TRICORE_FMT_RRR] = tricore_mask_rrr;
302 tricore_opmask[TRICORE_FMT_RRR1] = tricore_mask_rrr1;
303 tricore_opmask[TRICORE_FMT_RRR2] = tricore_mask_rrr2;
304 tricore_opmask[TRICORE_FMT_RRRR] = tricore_mask_rrrr;
305 tricore_opmask[TRICORE_FMT_RRRW] = tricore_mask_rrrw;
306 tricore_opmask[TRICORE_FMT_SYS] = tricore_mask_sys;
307 tricore_opmask[TRICORE_FMT_SB] = tricore_mask_sb;
308 tricore_opmask[TRICORE_FMT_SBC] = tricore_mask_sbc;
309 tricore_opmask[TRICORE_FMT_SBR] = tricore_mask_sbr;
310 tricore_opmask[TRICORE_FMT_SBRN] = tricore_mask_sbrn;
311 tricore_opmask[TRICORE_FMT_SC] = tricore_mask_sc;
312 tricore_opmask[TRICORE_FMT_SLR] = tricore_mask_slr;
313 tricore_opmask[TRICORE_FMT_SLRO] = tricore_mask_slro;
314 tricore_opmask[TRICORE_FMT_SR] = tricore_mask_sr;
315 tricore_opmask[TRICORE_FMT_SRC] = tricore_mask_src;
316 tricore_opmask[TRICORE_FMT_SRO] = tricore_mask_sro;
317 tricore_opmask[TRICORE_FMT_SRR] = tricore_mask_srr;
318 tricore_opmask[TRICORE_FMT_SRRS] = tricore_mask_srrs;
319 tricore_opmask[TRICORE_FMT_SSR] = tricore_mask_ssr;
320 tricore_opmask[TRICORE_FMT_SSRO] = tricore_mask_ssro;
321 }
322
323 /* End of cpu-tricore.c. */
324