1 /* $OpenBSD: trm.c,v 1.47 2024/09/04 07:54:52 mglocker Exp $
2 * ------------------------------------------------------------
3 * O.S : OpenBSD
4 * File Name : trm.c
5 * Device Driver for Tekram DC395U/UW/F,DC315/U
6 * PCI SCSI Bus Master Host Adapter
7 * (SCSI chip set used Tekram ASIC TRM-S1040)
8 *
9 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd.
10 * (C)Copyright 2001-2002 Ashley R. Martens and Kenneth R Westerback
11 * ------------------------------------------------------------
12 * HISTORY:
13 *
14 * REV# DATE NAME DESCRIPTION
15 * 1.00 05/01/99 ERICH CHEN First released for NetBSD 1.4.x
16 * 1.01 00/00/00 MARTIN AKESSON Port to OpenBSD 2.8
17 * 1.02 09/19/01 ASHLEY MARTENS Cleanup and formatting
18 * 2.00 01/00/02 KENNETH R WESTERBACK Rewrite of the bus and code logic
19 * ------------------------------------------------------------
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions
23 * are met:
24 * 1. Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * 2. Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
29 * 3. The name of the author may not be used to endorse or promote products
30 * derived from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
33 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
34 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
35 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
36 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
37 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
41 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 * ------------------------------------------------------------
44 */
45
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/malloc.h>
50 #include <sys/buf.h>
51 #include <sys/device.h>
52
53 #include <machine/bus.h>
54
55 #include <scsi/scsi_all.h>
56 #include <scsi/scsiconf.h>
57 #include <scsi/scsi_message.h>
58
59 #include <dev/pci/pcidevs.h>
60 #include <dev/ic/trm.h>
61
62 /* #define TRM_DEBUG0 */
63
64 void trm_check_eeprom(struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t);
65 void trm_read_all (struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t);
66 void trm_write_all (struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t);
67
68 void trm_set_data (bus_space_tag_t, bus_space_handle_t, u_int8_t, u_int8_t);
69 void trm_write_cmd(bus_space_tag_t, bus_space_handle_t, u_int8_t, u_int8_t);
70
71 u_int8_t trm_get_data(bus_space_tag_t, bus_space_handle_t, u_int8_t);
72
73 void trm_wait_30us(bus_space_tag_t, bus_space_handle_t);
74
75 void *trm_srb_alloc(void *);
76
77 void trm_DataOutPhase0(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
78 void trm_DataInPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
79 void trm_StatusPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
80 void trm_MsgOutPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
81 void trm_MsgInPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
82 void trm_DataOutPhase1(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
83 void trm_DataInPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
84 void trm_CommandPhase1(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
85 void trm_StatusPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
86 void trm_MsgOutPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
87 void trm_MsgInPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
88 void trm_Nop (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
89
90 void trm_SetXferParams (struct trm_softc *, struct trm_dcb *, int);
91
92 void trm_DataIO_transfer(struct trm_softc *, struct trm_scsi_req_q *, u_int16_t);
93
94 int trm_StartSRB (struct trm_softc *, struct trm_scsi_req_q *);
95 void trm_srb_reinit (struct trm_softc *, struct trm_scsi_req_q *);
96 void trm_srb_free (void *, void *);
97 void trm_RewaitSRB (struct trm_softc *, struct trm_scsi_req_q *);
98 void trm_FinishSRB (struct trm_softc *, struct trm_scsi_req_q *);
99 void trm_RequestSense(struct trm_softc *, struct trm_scsi_req_q *);
100
101 void trm_initAdapter (struct trm_softc *);
102 void trm_Disconnect (struct trm_softc *);
103 void trm_Reselect (struct trm_softc *);
104 void trm_GoingSRB_Done (struct trm_softc *, struct trm_dcb *);
105 void trm_ScsiRstDetect (struct trm_softc *);
106 void trm_ResetSCSIBus (struct trm_softc *);
107 void trm_reset (struct trm_softc *);
108 void trm_StartWaitingSRB (struct trm_softc *);
109 void trm_ResetAllDevParam(struct trm_softc *);
110 void trm_RecoverSRB (struct trm_softc *);
111 void trm_linkSRB (struct trm_softc *);
112
113 void trm_initACB(struct trm_softc *, int);
114
115 void trm_ResetDevParam(struct trm_softc *, struct trm_dcb *, u_int8_t);
116
117 void trm_EnableMsgOut(struct trm_softc *, u_int8_t);
118
119 void trm_timeout(void *);
120
121 void trm_print_info(struct trm_softc *, struct trm_dcb *);
122
123 /*
124 * ------------------------------------------------------------
125 *
126 * stateV = (void *) trm_SCSI_phase0[phase]
127 *
128 * ------------------------------------------------------------
129 */
130 static void *trm_SCSI_phase0[8] = {
131 trm_DataOutPhase0, /* phase:0 */
132 trm_DataInPhase0, /* phase:1 */
133 trm_Nop, /* phase:2 */
134 trm_StatusPhase0, /* phase:3 */
135 trm_Nop, /* phase:4 */
136 trm_Nop, /* phase:5 */
137 trm_MsgOutPhase0, /* phase:6 */
138 trm_MsgInPhase0, /* phase:7 */
139 };
140
141 /*
142 * ------------------------------------------------------------
143 *
144 * stateV = (void *) trm_SCSI_phase1[phase]
145 *
146 * ------------------------------------------------------------
147 */
148 static void *trm_SCSI_phase1[8] = {
149 trm_DataOutPhase1, /* phase:0 */
150 trm_DataInPhase1, /* phase:1 */
151 trm_CommandPhase1, /* phase:2 */
152 trm_StatusPhase1, /* phase:3 */
153 trm_Nop, /* phase:4 */
154 trm_Nop, /* phase:5 */
155 trm_MsgOutPhase1, /* phase:6 */
156 trm_MsgInPhase1, /* phase:7 */
157 };
158
159
160 struct trm_adapter_nvram trm_eepromBuf[TRM_MAX_ADAPTER_NUM];
161 /*
162 *Fast20: 000 50ns, 20.0 Mbytes/s
163 * 001 75ns, 13.3 Mbytes/s
164 * 010 100ns, 10.0 Mbytes/s
165 * 011 125ns, 8.0 Mbytes/s
166 * 100 150ns, 6.6 Mbytes/s
167 * 101 175ns, 5.7 Mbytes/s
168 * 110 200ns, 5.0 Mbytes/s
169 * 111 250ns, 4.0 Mbytes/s
170 *
171 *Fast40: 000 25ns, 40.0 Mbytes/s
172 * 001 50ns, 20.0 Mbytes/s
173 * 010 75ns, 13.3 Mbytes/s
174 * 011 100ns, 10.0 Mbytes/s
175 * 100 125ns, 8.0 Mbytes/s
176 * 101 150ns, 6.6 Mbytes/s
177 * 110 175ns, 5.7 Mbytes/s
178 * 111 200ns, 5.0 Mbytes/s
179 */
180
181 /*
182 * real period:
183 */
184 u_int8_t trm_clock_period[8] = {
185 /* nanosecond divided by 4 */
186 12, /* 48 ns 20 MB/sec */
187 18, /* 72 ns 13.3 MB/sec */
188 25, /* 100 ns 10.0 MB/sec */
189 31, /* 124 ns 8.0 MB/sec */
190 37, /* 148 ns 6.6 MB/sec */
191 43, /* 172 ns 5.7 MB/sec */
192 50, /* 200 ns 5.0 MB/sec */
193 62 /* 248 ns 4.0 MB/sec */
194 };
195
196 /*
197 * ------------------------------------------------------------
198 * Function : trm_srb_alloc
199 * Purpose : Get the first free SRB
200 * Inputs :
201 * Return : NULL or a free SCSI Request block
202 * ------------------------------------------------------------
203 */
204 void *
trm_srb_alloc(void * xsc)205 trm_srb_alloc(void *xsc)
206 {
207 struct trm_softc *sc = xsc;
208 struct trm_scsi_req_q *pSRB;
209
210 mtx_enter(&sc->sc_srb_mtx);
211 pSRB = TAILQ_FIRST(&sc->freeSRB);
212 if (pSRB != NULL)
213 TAILQ_REMOVE(&sc->freeSRB, pSRB, link);
214 mtx_leave(&sc->sc_srb_mtx);
215
216 #ifdef TRM_DEBUG0
217 printf("%s: trm_srb_alloc. pSRB = %p, next pSRB = %p\n",
218 sc->sc_device.dv_xname, pSRB, TAILQ_FIRST(&sc->freeSRB));
219 #endif
220
221 return pSRB;
222 }
223
224 /*
225 * ------------------------------------------------------------
226 * Function : trm_RewaitSRB
227 * Purpose : Q back to pending Q
228 * Inputs : struct trm_dcb * -
229 * struct trm_scsi_req_q * -
230 * ------------------------------------------------------------
231 */
232 void
trm_RewaitSRB(struct trm_softc * sc,struct trm_scsi_req_q * pSRB)233 trm_RewaitSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB)
234 {
235 int intflag;
236
237 intflag = splbio();
238
239 if ((pSRB->SRBFlag & TRM_ON_WAITING_SRB) != 0) {
240 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB;
241 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link);
242 }
243
244 if ((pSRB->SRBFlag & TRM_ON_GOING_SRB) != 0) {
245 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB;
246 TAILQ_REMOVE(&sc->goingSRB, pSRB, link);
247 }
248
249 pSRB->SRBState = TRM_READY;
250 pSRB->TargetStatus = SCSI_OK;
251 pSRB->AdaptStatus = TRM_STATUS_GOOD;
252
253 pSRB->SRBFlag |= TRM_ON_WAITING_SRB;
254 TAILQ_INSERT_HEAD(&sc->waitingSRB, pSRB, link);
255
256 splx(intflag);
257 }
258
259 /*
260 * ------------------------------------------------------------
261 * Function : trm_StartWaitingSRB
262 * Purpose : If there is no active DCB then run robin through
263 * the DCB's to find the next waiting SRB
264 * and move it to the going list.
265 * Inputs : struct trm_softc * -
266 * ------------------------------------------------------------
267 */
268 void
trm_StartWaitingSRB(struct trm_softc * sc)269 trm_StartWaitingSRB(struct trm_softc *sc)
270 {
271 struct trm_scsi_req_q *pSRB, *next;
272 int intflag;
273
274 intflag = splbio();
275
276 if ((sc->pActiveDCB != NULL) ||
277 (TAILQ_EMPTY(&sc->waitingSRB)) ||
278 (sc->sc_Flag & (RESET_DETECT | RESET_DONE | RESET_DEV)) != 0)
279 goto out;
280
281 for (pSRB = TAILQ_FIRST(&sc->waitingSRB); pSRB != NULL; pSRB = next) {
282 next = TAILQ_NEXT(pSRB, link);
283 if (trm_StartSRB(sc, pSRB) == 0) {
284 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB;
285 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link);
286 pSRB->SRBFlag |= TRM_ON_GOING_SRB;
287 TAILQ_INSERT_TAIL(&sc->goingSRB, pSRB, link);
288 break;
289 }
290 }
291
292 out:
293 splx(intflag);
294 }
295
296 /*
297 * ------------------------------------------------------------
298 * Function : trm_scsi_cmd
299 * Purpose : enqueues a SCSI command
300 * Inputs :
301 * Call By : GENERIC SCSI driver
302 * ------------------------------------------------------------
303 */
304 void
trm_scsi_cmd(struct scsi_xfer * xs)305 trm_scsi_cmd(struct scsi_xfer *xs)
306 {
307 struct trm_scsi_req_q *pSRB;
308 bus_space_handle_t ioh;
309 struct trm_softc *sc;
310 bus_space_tag_t iot;
311 struct trm_dcb *pDCB;
312 u_int8_t target, lun;
313 int i, error, intflag, timeout, xferflags;
314
315 target = xs->sc_link->target;
316 lun = xs->sc_link->lun;
317
318 sc = xs->sc_link->bus->sb_adapter_softc;
319 ioh = sc->sc_iohandle;
320 iot = sc->sc_iotag;
321
322 #ifdef TRM_DEBUG0
323 if ((xs->flags & SCSI_POLL) != 0) {
324 sc_print_addr(xs->sc_link);
325 printf("trm_scsi_cmd. sc = %p, xs = %p, opcode = 0x%02x\n",
326 sc, xs, lun, xs->cmd.opcode);
327 }
328 #endif
329
330 if (target >= TRM_MAX_TARGETS) {
331 sc_print_addr(xs->sc_link);
332 printf("target >= %d\n", TRM_MAX_TARGETS);
333 xs->error = XS_DRIVER_STUFFUP;
334 scsi_done(xs);
335 return;
336 }
337 if (lun >= TRM_MAX_LUNS) {
338 sc_print_addr(xs->sc_link);
339 printf("lun >= %d\n", TRM_MAX_LUNS);
340 xs->error = XS_DRIVER_STUFFUP;
341 scsi_done(xs);
342 return;
343 }
344
345 pDCB = sc->pDCB[target][lun];
346 if (pDCB == NULL) {
347 /* Removed as a result of INQUIRY proving no device present */
348 xs->error = XS_DRIVER_STUFFUP;
349 scsi_done(xs);
350 return;
351 }
352
353 xferflags = xs->flags;
354 if (xferflags & SCSI_RESET) {
355 #ifdef TRM_DEBUG0
356 sc_print_addr(xs->sc_link);
357 printf("trm_reset via SCSI_RESET\n");
358 #endif
359 trm_reset(sc);
360 xs->error = XS_NOERROR;
361 scsi_done(xs);
362 return;
363 }
364
365 pSRB = xs->io;
366 trm_srb_reinit(sc, pSRB);
367
368 xs->error = XS_NOERROR;
369 xs->status = SCSI_OK;
370 xs->resid = 0;
371
372 intflag = splbio();
373
374 /*
375 * BuildSRB(pSRB,pDCB);
376 */
377 if (xs->datalen != 0) {
378 #ifdef TRM_DEBUG0
379 sc_print_addr(xs->sc_link);
380 printf("xs->datalen=%x\n", (u_int32_t)&xs->datalen);
381 sc_print_addr(xs->sc_link);
382 printf("sc->sc_dmatag=0x%x\n", (u_int32_t)sc->sc_dmatag);
383 sc_print_addr(xs->sc_link);
384 printf("pSRB->dmamapxfer=0x%x\n", (u_int32_t)pSRB->dmamapxfer);
385 sc_print_addr(xs->sc_link);
386 printf("xs->data=0x%x\n", (u_int32_t)&xs->data);
387 #endif
388 if ((error = bus_dmamap_load(sc->sc_dmatag, pSRB->dmamapxfer,
389 xs->data, xs->datalen, NULL,
390 (xferflags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT :
391 BUS_DMA_WAITOK)) != 0) {
392 sc_print_addr(xs->sc_link);
393 printf("DMA transfer map unable to load, error = %d\n",
394 error);
395 xs->error = XS_DRIVER_STUFFUP;
396 splx(intflag);
397 scsi_done(xs);
398 return;
399 }
400
401 bus_dmamap_sync(sc->sc_dmatag, pSRB->dmamapxfer,
402 0, pSRB->dmamapxfer->dm_mapsize,
403 (xferflags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
404
405 /*
406 * Set up the scatter gather list
407 */
408 for (i = 0; i < pSRB->dmamapxfer->dm_nsegs; i++) {
409 pSRB->SegmentX[i].address = pSRB->dmamapxfer->dm_segs[i].ds_addr;
410 pSRB->SegmentX[i].length = pSRB->dmamapxfer->dm_segs[i].ds_len;
411 }
412 pSRB->SRBTotalXferLength = xs->datalen;
413 pSRB->SRBSGCount = pSRB->dmamapxfer->dm_nsegs;
414 }
415
416 pSRB->pSRBDCB = pDCB;
417 pSRB->xs = xs;
418 pSRB->ScsiCmdLen = xs->cmdlen;
419
420 memcpy(pSRB->CmdBlock, &xs->cmd, xs->cmdlen);
421
422 timeout_set(&xs->stimeout, trm_timeout, pSRB);
423
424 pSRB->SRBFlag |= TRM_ON_WAITING_SRB;
425 TAILQ_INSERT_TAIL(&sc->waitingSRB, pSRB, link);
426 trm_StartWaitingSRB(sc);
427
428 if ((xferflags & SCSI_POLL) == 0) {
429 timeout_add_msec(&xs->stimeout, xs->timeout);
430 splx(intflag);
431 return;
432 }
433
434 splx(intflag);
435 for (timeout = xs->timeout; timeout > 0; timeout--) {
436 intflag = splbio();
437 trm_Interrupt(sc);
438 splx(intflag);
439 if (ISSET(xs->flags, ITSDONE))
440 break;
441 DELAY(1000);
442 }
443
444 if (!ISSET(xs->flags, ITSDONE) && timeout == 0)
445 trm_timeout(pSRB);
446
447 scsi_done(xs);
448 }
449
450 /*
451 * ------------------------------------------------------------
452 * Function : trm_ResetAllDevParam
453 * Purpose :
454 * Inputs : struct trm_softc *
455 * ------------------------------------------------------------
456 */
457 void
trm_ResetAllDevParam(struct trm_softc * sc)458 trm_ResetAllDevParam(struct trm_softc *sc)
459 {
460 struct trm_adapter_nvram *pEEpromBuf;
461 int target, quirks;
462
463 pEEpromBuf = &trm_eepromBuf[sc->sc_AdapterUnit];
464
465 for (target = 0; target < TRM_MAX_TARGETS; target++) {
466 if (target == sc->sc_AdaptSCSIID || sc->pDCB[target][0] == NULL)
467 continue;
468
469 if ((sc->pDCB[target][0]->DCBFlag & TRM_QUIRKS_VALID) == 0)
470 quirks = SDEV_NOWIDE | SDEV_NOSYNC | SDEV_NOTAGS;
471 else if (sc->pDCB[target][0]->sc_link != NULL)
472 quirks = sc->pDCB[target][0]->sc_link->quirks;
473
474 trm_ResetDevParam(sc, sc->pDCB[target][0], quirks);
475 }
476 }
477
478 /*
479 * ------------------------------------------------------------
480 * Function : trm_ResetDevParam
481 * Purpose :
482 * Inputs :
483 * ------------------------------------------------------------
484 */
485 void
trm_ResetDevParam(struct trm_softc * sc,struct trm_dcb * pDCB,u_int8_t quirks)486 trm_ResetDevParam(struct trm_softc *sc, struct trm_dcb *pDCB, u_int8_t quirks)
487 {
488 struct trm_adapter_nvram *pEEpromBuf = &trm_eepromBuf[sc->sc_AdapterUnit];
489 u_int8_t PeriodIndex;
490 const int target = pDCB->target;
491
492 pDCB->DCBFlag &= TRM_QUIRKS_VALID;
493 pDCB->DCBFlag |= (TRM_WIDE_NEGO_ENABLE | TRM_SYNC_NEGO_ENABLE);
494
495 pDCB->SyncPeriod = 0;
496 pDCB->SyncOffset = 0;
497 pDCB->MaxNegoPeriod = 0;
498
499 pDCB->DevMode = pEEpromBuf->NvramTarget[target].NvmTarCfg0;
500
501 pDCB->IdentifyMsg = MSG_IDENTIFY(pDCB->lun, ((pDCB->DevMode & TRM_DISCONNECT) != 0));
502
503 if (((quirks & SDEV_NOWIDE) == 0) &&
504 (pDCB->DevMode & TRM_WIDE) &&
505 ((sc->sc_config & HCC_WIDE_CARD) != 0))
506 pDCB->DCBFlag |= TRM_WIDE_NEGO_16BIT;
507
508 if (((quirks & SDEV_NOSYNC) == 0) &&
509 ((pDCB->DevMode & TRM_SYNC) != 0)) {
510 PeriodIndex = pEEpromBuf->NvramTarget[target].NvmTarPeriod & 0x07;
511 pDCB->MaxNegoPeriod = trm_clock_period[PeriodIndex];
512 }
513
514 if (((quirks & SDEV_NOTAGS) == 0) &&
515 ((pDCB->DevMode & TRM_TAG_QUEUING) != 0) &&
516 ((pDCB->DevMode & TRM_DISCONNECT) != 0))
517 /* TODO XXXX: Every device(lun) gets to queue TagMaxNum commands? */
518 pDCB->DCBFlag |= TRM_USE_TAG_QUEUING;
519
520 trm_SetXferParams(sc, pDCB, 0);
521 }
522
523 /*
524 * ------------------------------------------------------------
525 * Function : trm_RecoverSRB
526 * Purpose : Moves all SRBs from Going to Waiting for all the Link DCBs
527 * Inputs : struct trm_softc * -
528 * ------------------------------------------------------------
529 */
530 void
trm_RecoverSRB(struct trm_softc * sc)531 trm_RecoverSRB(struct trm_softc *sc)
532 {
533 struct trm_scsi_req_q *pSRB;
534
535 /* ASSUME we are inside splbio()/splx() */
536
537 while ((pSRB = TAILQ_FIRST(&sc->goingSRB)) != NULL) {
538 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB;
539 TAILQ_REMOVE(&sc->goingSRB, pSRB, link);
540 pSRB->SRBFlag |= TRM_ON_WAITING_SRB;
541 TAILQ_INSERT_HEAD(&sc->waitingSRB, pSRB, link);
542 }
543 }
544
545 /*
546 * ------------------------------------------------------------
547 * Function : trm_reset
548 * Purpose : perform a hard reset on the SCSI bus (and TRM_S1040 chip).
549 * Inputs :
550 * ------------------------------------------------------------
551 */
552 void
trm_reset(struct trm_softc * sc)553 trm_reset(struct trm_softc *sc)
554 {
555 const bus_space_handle_t ioh = sc->sc_iohandle;
556 const bus_space_tag_t iot = sc->sc_iotag;
557 int i, intflag;
558
559 intflag = splbio();
560
561 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, 0);
562 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 0);
563
564 trm_ResetSCSIBus(sc);
565 for (i = 0; i < 500; i++)
566 DELAY(1000);
567
568 /*
569 * Enable all SCSI interrupts except EN_SCAM
570 */
571 bus_space_write_1(iot, ioh,
572 TRM_S1040_SCSI_INTEN,
573 (EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED |
574 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE));
575 /*
576 * Enable DMA interrupt
577 */
578 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, EN_SCSIINTR);
579 /*
580 * Clear DMA FIFO
581 */
582 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, CLRXFIFO);
583 /*
584 * Clear SCSI FIFO
585 */
586 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO);
587
588 trm_ResetAllDevParam(sc);
589 trm_GoingSRB_Done(sc, NULL);
590 sc->pActiveDCB = NULL;
591
592 /*
593 * RESET_DETECT, RESET_DONE, RESET_DEV
594 */
595 sc->sc_Flag = 0;
596 trm_StartWaitingSRB(sc);
597
598 splx(intflag);
599 }
600
601 /*
602 * ------------------------------------------------------------
603 * Function : trm_timeout
604 * Purpose : Prints a timeout message and aborts the timed out SCSI request
605 * Inputs : void * - A struct trm_scsi_req_q * structure pointer
606 * ------------------------------------------------------------
607 */
608 void
trm_timeout(void * arg1)609 trm_timeout(void *arg1)
610 {
611 struct trm_scsi_req_q *pSRB;
612 struct scsi_xfer *xs;
613 struct trm_softc *sc;
614
615 pSRB = (struct trm_scsi_req_q *)arg1;
616 xs = pSRB->xs;
617
618 if (xs != NULL) {
619 sc = xs->sc_link->bus->sb_adapter_softc;
620 sc_print_addr(xs->sc_link);
621 printf("SCSI OpCode 0x%02x ", xs->cmd.opcode);
622 if (pSRB->SRBFlag & TRM_AUTO_REQSENSE)
623 printf("REQUEST SENSE ");
624 printf("timed out\n");
625 pSRB->SRBFlag |= TRM_SCSI_TIMED_OUT;
626 trm_FinishSRB(sc, pSRB);
627 #ifdef TRM_DEBUG0
628 sc_print_addr(xs->sc_link);
629 printf("trm_reset via trm_timeout()\n");
630 #endif
631 trm_reset(sc);
632 trm_StartWaitingSRB(sc);
633 }
634 }
635
636 /*
637 * ------------------------------------------------------------
638 * Function : trm_StartSRB
639 * Purpose : Send the commands in the SRB to the device
640 * Inputs : struct trm_softc * -
641 * struct trm_scsi_req_q * -
642 * Return : 0 - SCSI processor is unoccupied
643 * 1 - SCSI processor is occupied with an SRB
644 * ------------------------------------------------------------
645 */
646 int
trm_StartSRB(struct trm_softc * sc,struct trm_scsi_req_q * pSRB)647 trm_StartSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB)
648 {
649 const bus_space_handle_t ioh = sc->sc_iohandle;
650 const bus_space_tag_t iot = sc->sc_iotag;
651 struct trm_dcb *pDCB = pSRB->pSRBDCB;
652 u_int32_t tag_mask;
653 u_int8_t tag_id, scsicommand;
654
655 #ifdef TRM_DEBUG0
656 printf("%s: trm_StartSRB. sc = %p, pDCB = %p, pSRB = %p\n",
657 sc->sc_device.dv_xname, sc, pDCB, pSRB);
658 #endif
659 /*
660 * If the queue is full or the SCSI processor has a pending interrupt
661 * then try again later.
662 */
663 if ((pDCB->DCBFlag & TRM_QUEUE_FULL) || (bus_space_read_2(iot, ioh,
664 TRM_S1040_SCSI_STATUS) & SCSIINTERRUPT))
665 return (1);
666
667 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, sc->sc_AdaptSCSIID);
668 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TARGETID, pDCB->target);
669 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod);
670 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset);
671
672 if ((sc->pDCB[pDCB->target][0]->sc_link != NULL) &&
673 ((sc->pDCB[pDCB->target][0]->DCBFlag & TRM_QUIRKS_VALID) == 0)) {
674 sc->pDCB[pDCB->target][0]->DCBFlag |= TRM_QUIRKS_VALID;
675 trm_ResetDevParam(sc, sc->pDCB[pDCB->target][0], sc->pDCB[pDCB->target][0]->sc_link->quirks);
676 }
677
678 /*
679 * Flush FIFO
680 */
681 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO);
682
683 sc->MsgCnt = 1;
684 sc->MsgBuf[0] = pDCB->IdentifyMsg;
685 if (((pSRB->xs->flags & SCSI_POLL) != 0) ||
686 (pSRB->CmdBlock[0] == INQUIRY) ||
687 (pSRB->CmdBlock[0] == REQUEST_SENSE))
688 sc->MsgBuf[0] &= ~MSG_IDENTIFY_DISCFLAG;
689
690 scsicommand = SCMD_SEL_ATN;
691
692 if ((pDCB->DCBFlag & (TRM_WIDE_NEGO_ENABLE | TRM_SYNC_NEGO_ENABLE)) != 0) {
693 scsicommand = SCMD_SEL_ATNSTOP;
694 pSRB->SRBState = TRM_MSGOUT;
695
696 } else if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) == 0) {
697 pDCB->DCBFlag |= TRM_QUEUE_FULL;
698
699 } else if ((sc->MsgBuf[0] & MSG_IDENTIFY_DISCFLAG) != 0) {
700 if (pSRB->TagNumber == TRM_NO_TAG) {
701 for (tag_id=1, tag_mask=2; tag_id < 32; tag_id++, tag_mask <<= 1)
702 if ((tag_mask & pDCB->TagMask) == 0) {
703 pDCB->TagMask |= tag_mask;
704 pSRB->TagNumber = tag_id;
705 break;
706 }
707
708 if (tag_id >= 32) {
709 pDCB->DCBFlag |= TRM_QUEUE_FULL;
710 sc->MsgCnt = 0;
711 return 1;
712 }
713 }
714
715 /* TODO XXXX: Should send ORDERED_Q_TAG if metadata (non-block) i/o!? */
716 sc->MsgBuf[sc->MsgCnt++] = MSG_SIMPLE_Q_TAG;
717 sc->MsgBuf[sc->MsgCnt++] = pSRB->TagNumber;
718
719 scsicommand = SCMD_SEL_ATN3;
720 }
721
722 pSRB->SRBState = TRM_START;
723 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */
724 sc->pActiveDCB = pDCB;
725 pDCB->pActiveSRB = pSRB;
726
727 if (sc->MsgCnt > 0) {
728 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_FIFO, sc->MsgBuf[0]);
729 if (sc->MsgCnt > 1) {
730 DELAY(30);
731 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &sc->MsgBuf[1], sc->MsgCnt - 1);
732 }
733 sc->MsgCnt = 0;
734 }
735
736 /*
737 * it's important for atn stop
738 */
739 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH | DO_HWRESELECT);
740 /*
741 * SCSI command
742 */
743 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, scsicommand);
744
745 return 0;
746 }
747
748 /*
749 * ------------------------------------------------------------
750 * Function : trm_Interrupt
751 * Purpose : Catch an interrupt from the adapter
752 * Process pending device interrupts.
753 * Inputs : void * - struct trm_softc * structure pointer
754 * ------------------------------------------------------------
755 */
756 int
trm_Interrupt(void * vsc)757 trm_Interrupt(void *vsc)
758 {
759 void (*stateV)(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
760 struct trm_scsi_req_q *pSRB;
761 bus_space_handle_t ioh;
762 struct trm_softc *sc = (struct trm_softc *)vsc;
763 bus_space_tag_t iot;
764 u_int16_t phase;
765 u_int8_t scsi_status, scsi_intstatus;
766
767 if (sc == NULL)
768 return 0;
769
770 ioh = sc->sc_iohandle;
771 iot = sc->sc_iotag;
772
773 scsi_status = bus_space_read_2(iot, ioh, TRM_S1040_SCSI_STATUS);
774 if (!(scsi_status & SCSIINTERRUPT))
775 return 0;
776 scsi_intstatus = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_INTSTATUS);
777
778 #ifdef TRM_DEBUG0
779 printf("%s: trm_interrupt - scsi_status=0x%02x, scsi_intstatus=0x%02x\n",
780 sc->sc_device.dv_xname, scsi_status, scsi_intstatus);
781 #endif
782 if ((scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) != 0)
783 trm_Disconnect(sc);
784
785 else if ((scsi_intstatus & INT_RESELECTED) != 0)
786 trm_Reselect(sc);
787
788 else if ((scsi_intstatus & INT_SCSIRESET) != 0)
789 trm_ScsiRstDetect(sc);
790
791 else if ((sc->pActiveDCB != NULL) && ((scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) != 0)) {
792 pSRB = sc->pActiveDCB->pActiveSRB;
793 /*
794 * software sequential machine
795 */
796 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */
797 /*
798 * 62037 or 62137
799 * call trm_SCSI_phase0[]... "phase entry"
800 * handle every phase before start transfer
801 */
802 stateV = trm_SCSI_phase0[phase];
803 stateV(sc, pSRB, &scsi_status);
804 /*
805 * if any exception occurred
806 * scsi_status will be modified to bus free phase
807 * new scsi_status transfer out from previous stateV
808 */
809 /*
810 * phase:0,1,2,3,4,5,6,7
811 */
812 pSRB->ScsiPhase = scsi_status & PHASEMASK;
813 phase = (u_int16_t) scsi_status & PHASEMASK;
814 /*
815 * call trm_SCSI_phase1[]... "phase entry"
816 * handle every phase do transfer
817 */
818 stateV = trm_SCSI_phase1[phase];
819 stateV(sc, pSRB, &scsi_status);
820
821 } else {
822 return 0;
823 }
824
825 return 1;
826 }
827
828 /*
829 * ------------------------------------------------------------
830 * Function : trm_MsgOutPhase0
831 * Purpose : Check the state machine before sending a message out
832 * Inputs : struct trm_softc * -
833 * struct trm_scsi_req_q * -
834 * u_int8_t * - scsi status, set to PH_BUS_FREE if not ready
835 * ------------------------------------------------------------
836 */
837 void
trm_MsgOutPhase0(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)838 trm_MsgOutPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
839 {
840 switch (pSRB->SRBState) {
841 case TRM_UNEXPECT_RESEL:
842 case TRM_ABORT_SENT:
843 *pscsi_status = PH_BUS_FREE; /* initial phase */
844 break;
845
846 default:
847 break;
848 }
849 }
850
851 /*
852 * ------------------------------------------------------------
853 * Function : trm_MsgOutPhase1
854 * Purpose : Write the message out to the bus
855 * Inputs : struct trm_softc * -
856 * struct trm_scsi_req_q * -
857 * u_int8_t * - unused
858 * ------------------------------------------------------------
859 */
860 void
trm_MsgOutPhase1(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)861 trm_MsgOutPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
862 {
863 const bus_space_handle_t ioh = sc->sc_iohandle;
864 const bus_space_tag_t iot = sc->sc_iotag;
865 struct trm_dcb *pDCB = sc->pActiveDCB;
866
867 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO);
868
869 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_ENABLE) != 0) {
870 /*
871 * WIDE DATA TRANSFER REQUEST code (03h)
872 */
873 pDCB->DCBFlag &= ~TRM_WIDE_NEGO_ENABLE;
874 pDCB->DCBFlag |= TRM_DOING_WIDE_NEGO;
875
876 sc->MsgBuf[0] = pDCB->IdentifyMsg & ~MSG_IDENTIFY_DISCFLAG;
877 sc->MsgBuf[1] = MSG_EXTENDED;
878 sc->MsgBuf[2] = MSG_EXT_WDTR_LEN;
879 sc->MsgBuf[3] = MSG_EXT_WDTR;
880
881 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0)
882 sc->MsgBuf[4] = MSG_EXT_WDTR_BUS_8_BIT;
883 else
884 sc->MsgBuf[4] = MSG_EXT_WDTR_BUS_16_BIT;
885
886 sc->MsgCnt = 5;
887
888 } else if ((pDCB->DCBFlag & TRM_SYNC_NEGO_ENABLE) != 0) {
889
890 pDCB->DCBFlag &= ~TRM_SYNC_NEGO_ENABLE;
891 pDCB->DCBFlag |= TRM_DOING_SYNC_NEGO;
892
893 sc->MsgCnt = 0;
894
895 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_DONE) == 0)
896 sc->MsgBuf[sc->MsgCnt++] = pDCB->IdentifyMsg & ~MSG_IDENTIFY_DISCFLAG;
897
898 sc->MsgBuf[sc->MsgCnt++] = MSG_EXTENDED;
899 sc->MsgBuf[sc->MsgCnt++] = MSG_EXT_SDTR_LEN;
900 sc->MsgBuf[sc->MsgCnt++] = MSG_EXT_SDTR;
901 sc->MsgBuf[sc->MsgCnt++] = pDCB->MaxNegoPeriod;
902
903 if (pDCB->MaxNegoPeriod > 0)
904 sc->MsgBuf[sc->MsgCnt++] = TRM_MAX_SYNC_OFFSET;
905 else
906 sc->MsgBuf[sc->MsgCnt++] = 0;
907 }
908
909 if (sc->MsgCnt > 0) {
910 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &sc->MsgBuf[0], sc->MsgCnt);
911 if (sc->MsgBuf[0] == MSG_ABORT)
912 pSRB->SRBState = TRM_ABORT_SENT;
913 sc->MsgCnt = 0;
914 }
915 /*
916 * it's important for atn stop
917 */
918 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH);
919 /*
920 * Transfer information out
921 */
922 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_OUT);
923 }
924
925 /*
926 * ------------------------------------------------------------
927 * Function : trm_CommandPhase1
928 * Purpose : Send commands to bus
929 * Inputs :
930 * ------------------------------------------------------------
931 */
932 void
trm_CommandPhase1(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)933 trm_CommandPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
934 {
935 const bus_space_handle_t ioh = sc->sc_iohandle;
936 const bus_space_tag_t iot = sc->sc_iotag;
937
938 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO);
939
940 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &pSRB->CmdBlock[0], pSRB->ScsiCmdLen);
941
942 pSRB->SRBState = TRM_COMMAND;
943 /*
944 * it's important for atn stop
945 */
946 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH);
947 /*
948 * Transfer information out
949 */
950 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_OUT);
951 }
952
953 /*
954 * ------------------------------------------------------------
955 * Function : trm_DataOutPhase0
956 * Purpose : Ready for Data Out, clear FIFO
957 * Inputs : u_int8_t * - SCSI status, used but not set
958 * ------------------------------------------------------------
959 */
960 void
trm_DataOutPhase0(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)961 trm_DataOutPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
962 {
963 const bus_space_handle_t ioh = sc->sc_iohandle;
964 const bus_space_tag_t iot = sc->sc_iotag;
965 struct SGentry *pseg;
966 struct trm_dcb *pDCB;
967 u_int32_t dLeftCounter, TempSRBXferredLength;
968 u_int16_t scsi_status;
969 u_int8_t TempDMAstatus, SGIndexTemp;
970
971 dLeftCounter = 0;
972
973 pDCB = pSRB->pSRBDCB;
974 scsi_status = *pscsi_status;
975
976 if (pSRB->SRBState != TRM_XFERPAD) {
977 if ((scsi_status & PARITYERROR) != 0)
978 pSRB->SRBFlag |= TRM_PARITY_ERROR;
979 if ((scsi_status & SCSIXFERDONE) == 0) {
980 /*
981 * when data transfer from DMA FIFO to SCSI FIFO
982 * if there was some data left in SCSI FIFO
983 */
984 dLeftCounter = (u_int32_t)(bus_space_read_1(
985 iot, ioh, TRM_S1040_SCSI_FIFOCNT) & 0x1F);
986 if (pDCB->SyncPeriod & WIDE_SYNC) {
987 /*
988 * if WIDE scsi SCSI FIFOCNT unit is word
989 * so need to * 2
990 */
991 dLeftCounter <<= 1;
992 }
993 }
994 /*
995 * calculate all the residue data that not yet transferred
996 * SCSI transfer counter + left in SCSI FIFO data
997 *
998 * .....TRM_S1040_SCSI_COUNTER (24bits)
999 * The counter always decrement by one for every SCSI byte
1000 * transfer.
1001 * .....TRM_S1040_SCSI_FIFOCNT ( 5bits)
1002 * The counter is SCSI FIFO offset counter
1003 */
1004 dLeftCounter += bus_space_read_4(iot, ioh,
1005 TRM_S1040_SCSI_COUNTER);
1006 if (dLeftCounter == 1) {
1007 dLeftCounter = 0;
1008 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL,
1009 DO_CLRFIFO);
1010 }
1011 if (dLeftCounter == 0 ||
1012 (scsi_status & SCSIXFERCNT_2_ZERO) != 0) {
1013 TempDMAstatus = bus_space_read_1(iot,
1014 ioh, TRM_S1040_DMA_STATUS);
1015 while ((TempDMAstatus & DMAXFERCOMP) == 0) {
1016 TempDMAstatus = bus_space_read_1(iot,
1017 ioh, TRM_S1040_DMA_STATUS);
1018 }
1019 pSRB->SRBTotalXferLength = 0;
1020 } else {
1021 /*
1022 * Update SG list
1023 */
1024 /*
1025 * if transfer not yet complete
1026 * there were some data residue in SCSI FIFO or
1027 * SCSI transfer counter not empty
1028 */
1029 if (pSRB->SRBTotalXferLength != dLeftCounter) {
1030 /*
1031 * data that had transferred length
1032 */
1033 TempSRBXferredLength = pSRB->SRBTotalXferLength
1034 - dLeftCounter;
1035 /*
1036 * next time to be transferred length
1037 */
1038 pSRB->SRBTotalXferLength = dLeftCounter;
1039 /*
1040 * parsing from last time disconnect SRBSGIndex
1041 */
1042 pseg = &pSRB->SegmentX[pSRB->SRBSGIndex];
1043 for (SGIndexTemp = pSRB->SRBSGIndex;
1044 SGIndexTemp < pSRB->SRBSGCount;
1045 SGIndexTemp++) {
1046 /*
1047 * find last time which SG transfer be
1048 * disconnect
1049 */
1050 if (TempSRBXferredLength >= pseg->length)
1051 TempSRBXferredLength -= pseg->length;
1052 else {
1053 /*
1054 * update last time disconnected
1055 * SG list
1056 */
1057 /*
1058 * residue data length
1059 */
1060 pseg->length -=
1061 TempSRBXferredLength;
1062 /*
1063 * residue data pointer
1064 */
1065 pseg->address +=
1066 TempSRBXferredLength;
1067 pSRB->SRBSGIndex = SGIndexTemp;
1068 break;
1069 }
1070 pseg++;
1071 }
1072 }
1073 }
1074 }
1075 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, STOPDMAXFER);
1076 }
1077
1078 /*
1079 * ------------------------------------------------------------
1080 * Function : trm_DataOutPhase1
1081 * Purpose : Transfers data out, calls trm_DataIO_transfer
1082 * Inputs :
1083 * ------------------------------------------------------------
1084 */
1085 void
trm_DataOutPhase1(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)1086 trm_DataOutPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
1087 {
1088 trm_DataIO_transfer(sc, pSRB, XFERDATAOUT);
1089 }
1090
1091 /*
1092 * ------------------------------------------------------------
1093 * Function : trm_DataInPhase0
1094 * Purpose : Prepare for reading data in from bus
1095 * Inputs :
1096 * ------------------------------------------------------------
1097 */
1098 void
trm_DataInPhase0(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)1099 trm_DataInPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
1100 {
1101 const bus_space_handle_t ioh = sc->sc_iohandle;
1102 const bus_space_tag_t iot = sc->sc_iotag;
1103 struct SGentry *pseg;
1104 u_int32_t TempSRBXferredLength, dLeftCounter;
1105 u_int16_t scsi_status;
1106 u_int8_t SGIndexTemp;
1107
1108 dLeftCounter = 0;
1109
1110 scsi_status = *pscsi_status;
1111 if (pSRB->SRBState != TRM_XFERPAD) {
1112 if ((scsi_status & PARITYERROR) != 0)
1113 pSRB->SRBFlag |= TRM_PARITY_ERROR;
1114 dLeftCounter += bus_space_read_4(iot, ioh,
1115 TRM_S1040_SCSI_COUNTER);
1116 if (dLeftCounter == 0 ||
1117 (scsi_status & SCSIXFERCNT_2_ZERO) != 0) {
1118 while ((bus_space_read_1(iot, ioh, TRM_S1040_DMA_STATUS) & DMAXFERCOMP) == 0)
1119 ;
1120 pSRB->SRBTotalXferLength = 0;
1121 } else {
1122 /*
1123 * phase changed
1124 *
1125 * parsing the case:
1126 * when a transfer not yet complete
1127 * but be disconnected by upper layer
1128 * if transfer not yet complete
1129 * there were some data residue in SCSI FIFO or
1130 * SCSI transfer counter not empty
1131 */
1132 if (pSRB->SRBTotalXferLength != dLeftCounter) {
1133 /*
1134 * data that had transferred length
1135 */
1136 TempSRBXferredLength = pSRB->SRBTotalXferLength
1137 - dLeftCounter;
1138 /*
1139 * next time to be transferred length
1140 */
1141 pSRB->SRBTotalXferLength = dLeftCounter;
1142 /*
1143 * parsing from last time disconnect SRBSGIndex
1144 */
1145 pseg = &pSRB->SegmentX[pSRB->SRBSGIndex];
1146 for (SGIndexTemp = pSRB->SRBSGIndex;
1147 SGIndexTemp < pSRB->SRBSGCount;
1148 SGIndexTemp++) {
1149 /*
1150 * find last time which SG transfer be
1151 * disconnect
1152 */
1153 if (TempSRBXferredLength >=
1154 pseg->length) {
1155 TempSRBXferredLength -= pseg->length;
1156 } else {
1157 /*
1158 * update last time disconnected
1159 * SG list
1160 *
1161 * residue data length
1162 */
1163 pseg->length -= TempSRBXferredLength;
1164 /*
1165 * residue data pointer
1166 */
1167 pseg->address += TempSRBXferredLength;
1168 pSRB->SRBSGIndex = SGIndexTemp;
1169 break;
1170 }
1171 pseg++;
1172 }
1173 }
1174 }
1175 }
1176 }
1177
1178 /*
1179 * ------------------------------------------------------------
1180 * Function : trm_DataInPhase1
1181 * Purpose : Transfer data in from bus, calls trm_DataIO_transfer
1182 * Inputs :
1183 * ------------------------------------------------------------
1184 */
1185 void
trm_DataInPhase1(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)1186 trm_DataInPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
1187 {
1188 trm_DataIO_transfer(sc, pSRB, XFERDATAIN);
1189 }
1190
1191 /*
1192 * ------------------------------------------------------------
1193 * Function : trm_DataIO_transfer
1194 * Purpose :
1195 * Inputs :
1196 * ------------------------------------------------------------
1197 */
1198 void
trm_DataIO_transfer(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int16_t ioDir)1199 trm_DataIO_transfer(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int16_t ioDir)
1200 {
1201 const bus_space_handle_t ioh = sc->sc_iohandle;
1202 const bus_space_tag_t iot = sc->sc_iotag;
1203 struct trm_dcb *pDCB = pSRB->pSRBDCB;
1204 u_int8_t bval;
1205
1206 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) {
1207 if (pSRB->SRBTotalXferLength != 0) {
1208 /*
1209 * load what physical address of Scatter/Gather list
1210 * table want to be transfer
1211 */
1212 pSRB->SRBState = TRM_DATA_XFER;
1213 bus_space_write_4(iot, ioh, TRM_S1040_DMA_XHIGHADDR, 0);
1214 bus_space_write_4(iot, ioh,
1215 TRM_S1040_DMA_XLOWADDR, (pSRB->SRBSGPhyAddr +
1216 ((u_int32_t)pSRB->SRBSGIndex << 3)));
1217 /*
1218 * load how many bytes in the Scatter/Gather list table
1219 */
1220 bus_space_write_4(iot, ioh, TRM_S1040_DMA_XCNT,
1221 ((u_int32_t)(pSRB->SRBSGCount -
1222 pSRB->SRBSGIndex) << 3));
1223 /*
1224 * load total transfer length (24bits,
1225 * pSRB->SRBTotalXferLength) max value 16Mbyte
1226 */
1227 bus_space_write_4(iot, ioh,
1228 TRM_S1040_SCSI_COUNTER, pSRB->SRBTotalXferLength);
1229 /*
1230 * Start DMA transfer
1231 */
1232 bus_space_write_2(iot,ioh,TRM_S1040_DMA_COMMAND, ioDir);
1233 /* bus_space_write_2(iot, ioh,
1234 TRM_S1040_DMA_CONTROL, STARTDMAXFER);*/
1235 /*
1236 * Set the transfer bus and direction
1237 */
1238 bval = ioDir == XFERDATAOUT ? SCMD_DMA_OUT :SCMD_DMA_IN;
1239 } else {
1240 /*
1241 * xfer pad
1242 */
1243 if (pSRB->SRBSGCount)
1244 pSRB->AdaptStatus = TRM_OVER_UNDER_RUN;
1245
1246 if (pDCB->SyncPeriod & WIDE_SYNC) {
1247 bus_space_write_4(iot, ioh,
1248 TRM_S1040_SCSI_COUNTER, 2);
1249 } else {
1250 bus_space_write_4(iot, ioh,
1251 TRM_S1040_SCSI_COUNTER, 1);
1252 }
1253
1254 if (ioDir == XFERDATAOUT) {
1255 bus_space_write_2(iot,
1256 ioh, TRM_S1040_SCSI_FIFO, 0);
1257 } else {
1258 bus_space_read_2(iot,
1259 ioh, TRM_S1040_SCSI_FIFO);
1260 }
1261 pSRB->SRBState = TRM_XFERPAD;
1262 /*
1263 * Set the transfer bus and direction
1264 */
1265 bval = ioDir == XFERDATAOUT ? SCMD_FIFO_OUT : SCMD_FIFO_IN;
1266 }
1267 /*
1268 * it's important for atn stop
1269 */
1270 bus_space_write_2(iot,ioh,TRM_S1040_SCSI_CONTROL, DO_DATALATCH);
1271 /*
1272 * Tell the bus to do the transfer
1273 */
1274 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, bval);
1275 }
1276 }
1277
1278 /*
1279 * ------------------------------------------------------------
1280 * Function : trm_StatusPhase0
1281 * Purpose : Update Target Status with data from SCSI FIFO
1282 * Inputs : u_int8_t * - Set to PH_BUS_FREE
1283 * ------------------------------------------------------------
1284 */
1285 void
trm_StatusPhase0(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)1286 trm_StatusPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
1287 {
1288 const bus_space_handle_t ioh = sc->sc_iohandle;
1289 const bus_space_tag_t iot = sc->sc_iotag;
1290
1291 pSRB->TargetStatus = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO);
1292
1293 pSRB->SRBState = TRM_COMPLETED;
1294 /*
1295 * initial phase
1296 */
1297 *pscsi_status = PH_BUS_FREE;
1298 /*
1299 * it's important for atn stop
1300 */
1301 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH);
1302 /*
1303 * Tell bus that the message was accepted
1304 */
1305 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT);
1306 }
1307
1308 /*
1309 * ------------------------------------------------------------
1310 * Function : trm_StatusPhase1
1311 * Purpose : Clear FIFO of DMA and SCSI
1312 * Inputs :
1313 * ------------------------------------------------------------
1314 */
1315 void
trm_StatusPhase1(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)1316 trm_StatusPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
1317 {
1318 const bus_space_handle_t ioh = sc->sc_iohandle;
1319 const bus_space_tag_t iot = sc->sc_iotag;
1320
1321 if ((bus_space_read_2(iot, ioh, TRM_S1040_DMA_COMMAND) & 0x0001) != 0) {
1322 if ((bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFOCNT) & 0x40)
1323 == 0) {
1324 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL,
1325 DO_CLRFIFO);
1326 }
1327 if ((bus_space_read_2(iot, ioh,
1328 TRM_S1040_DMA_FIFOCNT) & 0x8000) == 0) {
1329 bus_space_write_1(iot, ioh,
1330 TRM_S1040_DMA_CONTROL, CLRXFIFO);
1331 }
1332 } else {
1333 if ((bus_space_read_2(iot, ioh,
1334 TRM_S1040_DMA_FIFOCNT) & 0x8000) == 0) {
1335 bus_space_write_1(iot, ioh,
1336 TRM_S1040_DMA_CONTROL, CLRXFIFO);
1337 }
1338 if ((bus_space_read_1(iot, ioh,
1339 TRM_S1040_SCSI_FIFOCNT) & 0x40) == 0) {
1340 bus_space_write_2(iot, ioh,
1341 TRM_S1040_SCSI_CONTROL, DO_CLRFIFO);
1342 }
1343 }
1344 pSRB->SRBState = TRM_STATUS;
1345 /*
1346 * it's important for atn stop
1347 */
1348 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH);
1349 /*
1350 * Tell the bus that the command is complete
1351 */
1352 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_COMP);
1353 }
1354
1355 /*
1356 * ------------------------------------------------------------
1357 * Function : trm_MsgInPhase0
1358 * Purpose :
1359 * Inputs :
1360 *
1361 * extended message codes:
1362 * code description
1363 * ---- -----------
1364 * 02h Reserved
1365 * 00h MODIFY DATA POINTER
1366 * 01h SYNCHRONOUS DATA TRANSFER REQUEST
1367 * 03h WIDE DATA TRANSFER REQUEST
1368 * 04h - 7Fh Reserved
1369 * 80h - FFh Vendor specific
1370 *
1371 * ------------------------------------------------------------
1372 */
1373 void
trm_MsgInPhase0(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)1374 trm_MsgInPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
1375 {
1376 const bus_space_handle_t ioh = sc->sc_iohandle;
1377 const bus_space_tag_t iot = sc->sc_iotag;
1378 struct trm_dcb *pDCB;
1379 u_int8_t message_in_code, bIndex, message_in_tag_id;
1380
1381 pDCB = sc->pActiveDCB;
1382
1383 message_in_code = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO);
1384
1385 if (pSRB->SRBState != TRM_EXTEND_MSGIN) {
1386 switch (message_in_code) {
1387 case MSG_DISCONNECT:
1388 pSRB->SRBState = TRM_DISCONNECTED;
1389 break;
1390
1391 case MSG_EXTENDED:
1392 case MSG_SIMPLE_Q_TAG:
1393 case MSG_HEAD_OF_Q_TAG:
1394 case MSG_ORDERED_Q_TAG:
1395 pSRB->SRBState = TRM_EXTEND_MSGIN;
1396 /*
1397 * extended message (01h)
1398 */
1399 bzero(&sc->MsgBuf[0], sizeof(sc->MsgBuf));
1400 sc->MsgBuf[0] = message_in_code;
1401 sc->MsgCnt = 1;
1402 /*
1403 * extended message length (n)
1404 */
1405 break;
1406
1407 case MSG_MESSAGE_REJECT:
1408 /*
1409 * Reject message
1410 */
1411 if ((pDCB->DCBFlag & TRM_DOING_WIDE_NEGO) != 0) {
1412 /*
1413 * do wide nego reject
1414 */
1415 pDCB = pSRB->pSRBDCB;
1416
1417 pDCB->DCBFlag &= ~TRM_DOING_WIDE_NEGO;
1418 pDCB->DCBFlag |= TRM_WIDE_NEGO_DONE;
1419
1420 if ((pDCB->DCBFlag & TRM_SYNC_NEGO_ENABLE) != 0) {
1421 /*
1422 * Set ATN, in case ATN was clear
1423 */
1424 pSRB->SRBState = TRM_MSGOUT;
1425 bus_space_write_2(iot, ioh,
1426 TRM_S1040_SCSI_CONTROL, DO_SETATN);
1427 } else {
1428 /*
1429 * Clear ATN
1430 */
1431 bus_space_write_2(iot, ioh,
1432 TRM_S1040_SCSI_CONTROL, DO_CLRATN);
1433 }
1434
1435 } else if ((pDCB->DCBFlag & TRM_DOING_SYNC_NEGO) != 0) {
1436 /*
1437 * do sync nego reject
1438 */
1439 pDCB = pSRB->pSRBDCB;
1440
1441 pDCB->DCBFlag &= ~TRM_DOING_SYNC_NEGO;
1442
1443 pDCB->SyncPeriod = 0;
1444 pDCB->SyncOffset = 0;
1445
1446 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRATN);
1447 goto re_prog;
1448 }
1449 break;
1450
1451 case MSG_IGN_WIDE_RESIDUE:
1452 bus_space_write_4(iot, ioh, TRM_S1040_SCSI_COUNTER, 1);
1453 bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO);
1454 break;
1455
1456 default:
1457 break;
1458 }
1459
1460 } else {
1461
1462 /*
1463 * We are collecting an extended message. Save the latest byte and then
1464 * check to see if the message is complete. If so, process it.
1465 */
1466 sc->MsgBuf[sc->MsgCnt++] = message_in_code;
1467 #ifdef TRM_DEBUG0
1468 printf("%s: sc->MsgBuf = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n",
1469 sc->sc_device.dv_xname,
1470 sc->MsgBuf[0], sc->MsgBuf[1], sc->MsgBuf[2], sc->MsgBuf[3], sc->MsgBuf[4], sc->MsgBuf[5] );
1471 #endif
1472 switch (sc->MsgBuf[0]) {
1473 case MSG_SIMPLE_Q_TAG:
1474 case MSG_HEAD_OF_Q_TAG:
1475 case MSG_ORDERED_Q_TAG:
1476 if (sc->MsgCnt == 2) {
1477 pSRB->SRBState = TRM_FREE;
1478 message_in_tag_id = sc->MsgBuf[1];
1479 sc->MsgCnt = 0;
1480 TAILQ_FOREACH(pSRB, &sc->goingSRB, link) {
1481 if ((pSRB->pSRBDCB == pDCB) && (pSRB->TagNumber == message_in_tag_id))
1482 break;
1483 }
1484 if ((pSRB != NULL) && (pSRB->SRBState == TRM_DISCONNECTED)) {
1485 pDCB->pActiveSRB = pSRB;
1486 pSRB->SRBState = TRM_DATA_XFER;
1487 } else {
1488 #ifdef TRM_DEBUG0
1489 printf("%s: TRM_UNEXPECT_RESEL!\n",
1490 sc->sc_device.dv_xname);
1491 #endif
1492 pSRB = &sc->SRB[0];
1493 trm_srb_reinit(sc, pSRB);
1494 pSRB->SRBState = TRM_UNEXPECT_RESEL;
1495 pDCB->pActiveSRB = pSRB;
1496 trm_EnableMsgOut(sc, MSG_ABORT_TAG);
1497 }
1498 }
1499 break;
1500
1501 case MSG_EXTENDED:
1502 /* TODO XXXX: Correctly handling target initiated negotiations? */
1503 if ((sc->MsgBuf[2] == MSG_EXT_WDTR) && (sc->MsgCnt == 4)) {
1504 /*
1505 * ======================================
1506 * WIDE DATA TRANSFER REQUEST
1507 * ======================================
1508 * byte 0 : Extended message (01h)
1509 * byte 1 : Extended message length (02h)
1510 * byte 2 : WIDE DATA TRANSFER code (03h)
1511 * byte 3 : Transfer width exponent
1512 */
1513
1514 pSRB->SRBState = TRM_FREE;
1515 pDCB->DCBFlag &= ~(TRM_WIDE_NEGO_ENABLE | TRM_DOING_WIDE_NEGO);
1516
1517 if (sc->MsgBuf[1] != MSG_EXT_WDTR_LEN)
1518 goto reject_offer;
1519
1520 switch (sc->MsgBuf[3]) {
1521 case MSG_EXT_WDTR_BUS_32_BIT:
1522 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0)
1523 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_8_BIT;
1524 else
1525 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_16_BIT;
1526 break;
1527
1528 case MSG_EXT_WDTR_BUS_16_BIT:
1529 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0) {
1530 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_8_BIT;
1531 break;
1532 }
1533 pDCB->SyncPeriod |= WIDE_SYNC;
1534 /* FALL THROUGH == ACCEPT OFFER */
1535
1536 case MSG_EXT_WDTR_BUS_8_BIT:
1537 pSRB->SRBState = TRM_MSGOUT;
1538 pDCB->DCBFlag |= (TRM_SYNC_NEGO_ENABLE | TRM_WIDE_NEGO_DONE);
1539
1540 if (pDCB->MaxNegoPeriod == 0) {
1541 pDCB->SyncPeriod = 0;
1542 pDCB->SyncOffset = 0;
1543 goto re_prog;
1544 }
1545 break;
1546
1547 default:
1548 pDCB->DCBFlag &= ~TRM_WIDE_NEGO_ENABLE;
1549 pDCB->DCBFlag |= TRM_WIDE_NEGO_DONE;
1550 reject_offer:
1551 sc->MsgCnt = 1;
1552 sc->MsgBuf[0] = MSG_MESSAGE_REJECT;
1553 break;
1554 }
1555
1556 /* Echo accepted offer, or send revised offer */
1557 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_SETATN);
1558
1559 } else if ((sc->MsgBuf[2] == MSG_EXT_SDTR) && (sc->MsgCnt == 5)) {
1560 /*
1561 * =================================
1562 * SYNCHRONOUS DATA TRANSFER REQUEST
1563 * =================================
1564 * byte 0 : Extended message (01h)
1565 * byte 1 : Extended message length (03)
1566 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h)
1567 * byte 3 : Transfer period factor
1568 * byte 4 : REQ/ACK offset
1569 */
1570
1571 pSRB->SRBState = TRM_FREE;
1572 pDCB->DCBFlag &= ~(TRM_SYNC_NEGO_ENABLE | TRM_DOING_SYNC_NEGO);
1573
1574 if (sc->MsgBuf[1] != MSG_EXT_SDTR_LEN)
1575 goto reject_offer;
1576
1577 if ((sc->MsgBuf[3] == 0) || (sc->MsgBuf[4] == 0)) {
1578 /*
1579 * Asynchronous transfers
1580 */
1581 pDCB->SyncPeriod = 0;
1582 pDCB->SyncOffset = 0;
1583
1584 } else {
1585 /*
1586 * Synchronous transfers
1587 */
1588 /*
1589 * REQ/ACK offset
1590 */
1591 pDCB->SyncOffset = sc->MsgBuf[4];
1592
1593 for (bIndex = 0; bIndex < 7; bIndex++)
1594 if (sc->MsgBuf[3] <= trm_clock_period[bIndex])
1595 break;
1596
1597 pDCB->SyncPeriod |= (bIndex | ALT_SYNC);
1598 }
1599
1600 re_prog: /*
1601 * program SCSI control register
1602 */
1603 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod);
1604 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset);
1605
1606 trm_SetXferParams(sc, pDCB, (pDCB->DCBFlag & TRM_QUIRKS_VALID));
1607 }
1608 break;
1609
1610 default:
1611 break;
1612 }
1613 }
1614
1615 /*
1616 * initial phase
1617 */
1618 *pscsi_status = PH_BUS_FREE;
1619 /*
1620 * it's important for atn stop
1621 */
1622 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH);
1623 /*
1624 * Tell bus that the message was accepted
1625 */
1626 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT);
1627 }
1628
1629 /*
1630 * ------------------------------------------------------------
1631 * Function : trm_MsgInPhase1
1632 * Purpose : Clear the FIFO
1633 * Inputs :
1634 * ------------------------------------------------------------
1635 */
1636 void
trm_MsgInPhase1(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)1637 trm_MsgInPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
1638 {
1639 const bus_space_handle_t ioh = sc->sc_iohandle;
1640 const bus_space_tag_t iot = sc->sc_iotag;
1641
1642 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO);
1643 bus_space_write_4(iot, ioh, TRM_S1040_SCSI_COUNTER, 1);
1644
1645 /*
1646 * it's important for atn stop
1647 */
1648 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH);
1649 /*
1650 * SCSI command
1651 */
1652 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_IN);
1653 }
1654
1655 /*
1656 * ------------------------------------------------------------
1657 * Function : trm_Nop
1658 * Purpose : EMPTY
1659 * Inputs :
1660 * ------------------------------------------------------------
1661 */
1662 void
trm_Nop(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)1663 trm_Nop(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
1664 {
1665 }
1666
1667 /*
1668 * ------------------------------------------------------------
1669 * Function : trm_SetXferParams
1670 * Purpose : Set the Sync period, offset and mode for each device that has
1671 * the same target as the given one (struct trm_dcb *)
1672 * Inputs :
1673 * ------------------------------------------------------------
1674 */
1675 void
trm_SetXferParams(struct trm_softc * sc,struct trm_dcb * pDCB,int print_info)1676 trm_SetXferParams(struct trm_softc *sc, struct trm_dcb *pDCB, int print_info)
1677 {
1678 struct trm_dcb *pDCBTemp;
1679 int lun, target;
1680
1681 /*
1682 * set all lun device's period, offset
1683 */
1684 #ifdef TRM_DEBUG0
1685 printf("%s: trm_SetXferParams\n", sc->sc_device.dv_xname);
1686 #endif
1687
1688 target = pDCB->target;
1689 for(lun = 0; lun < TRM_MAX_LUNS; lun++) {
1690 pDCBTemp = sc->pDCB[target][lun];
1691 if (pDCBTemp != NULL) {
1692 pDCBTemp->DevMode = pDCB->DevMode;
1693 pDCBTemp->MaxNegoPeriod = pDCB->MaxNegoPeriod;
1694 pDCBTemp->SyncPeriod = pDCB->SyncPeriod;
1695 pDCBTemp->SyncOffset = pDCB->SyncOffset;
1696 pDCBTemp->DCBFlag = pDCB->DCBFlag;
1697 }
1698 }
1699
1700 if (print_info)
1701 trm_print_info(sc, pDCB);
1702 }
1703
1704 /*
1705 * ------------------------------------------------------------
1706 * Function : trm_Disconnect
1707 * Purpose :
1708 * Inputs :
1709 *
1710 * ---SCSI bus phase
1711 * PH_DATA_OUT 0x00 Data out phase
1712 * PH_DATA_IN 0x01 Data in phase
1713 * PH_COMMAND 0x02 Command phase
1714 * PH_STATUS 0x03 Status phase
1715 * PH_BUS_FREE 0x04 Invalid phase used as bus free
1716 * PH_BUS_FREE 0x05 Invalid phase used as bus free
1717 * PH_MSG_OUT 0x06 Message out phase
1718 * PH_MSG_IN 0x07 Message in phase
1719 * ------------------------------------------------------------
1720 */
1721 void
trm_Disconnect(struct trm_softc * sc)1722 trm_Disconnect(struct trm_softc *sc)
1723 {
1724 const bus_space_handle_t ioh = sc->sc_iohandle;
1725 struct trm_scsi_req_q *pSRB;
1726 const bus_space_tag_t iot = sc->sc_iotag;
1727 struct trm_dcb *pDCB;
1728 int j;
1729
1730 #ifdef TRM_DEBUG0
1731 printf("%s: trm_Disconnect\n", sc->sc_device.dv_xname);
1732 #endif
1733
1734 pDCB = sc->pActiveDCB;
1735 if (pDCB == NULL) {
1736 /* TODO: Why use a loop? Why not use DELAY(400)? */
1737 for(j = 400; j > 0; --j)
1738 DELAY(1); /* 1 msec */
1739 bus_space_write_2(iot, ioh,
1740 TRM_S1040_SCSI_CONTROL, (DO_CLRFIFO | DO_HWRESELECT));
1741 return;
1742 }
1743
1744 pSRB = pDCB->pActiveSRB;
1745 sc->pActiveDCB = NULL;
1746 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */
1747 bus_space_write_2(iot, ioh,
1748 TRM_S1040_SCSI_CONTROL, (DO_CLRFIFO | DO_HWRESELECT));
1749 DELAY(100);
1750
1751 switch (pSRB->SRBState) {
1752 case TRM_UNEXPECT_RESEL:
1753 pSRB->SRBState = TRM_FREE;
1754 break;
1755
1756 case TRM_ABORT_SENT:
1757 trm_GoingSRB_Done(sc, pDCB);
1758 break;
1759
1760 case TRM_START:
1761 case TRM_MSGOUT:
1762 /*
1763 * Selection time out
1764 */
1765 /* If not polling just keep trying until xs->stimeout expires */
1766 if ((pSRB->xs->flags & SCSI_POLL) == 0) {
1767 trm_RewaitSRB(sc, pSRB);
1768 } else {
1769 pSRB->TargetStatus = TRM_SCSI_SELECT_TIMEOUT;
1770 goto disc1;
1771 }
1772 break;
1773
1774 case TRM_COMPLETED:
1775 disc1:
1776 /*
1777 * TRM_COMPLETED - remove id from mask of active tags
1778 */
1779 pDCB->pActiveSRB = NULL;
1780 trm_FinishSRB(sc, pSRB);
1781 break;
1782
1783 default:
1784 break;
1785 }
1786
1787 trm_StartWaitingSRB(sc);
1788 }
1789
1790 /*
1791 * ------------------------------------------------------------
1792 * Function : trm_Reselect
1793 * Purpose :
1794 * Inputs :
1795 * ------------------------------------------------------------
1796 */
1797 void
trm_Reselect(struct trm_softc * sc)1798 trm_Reselect(struct trm_softc *sc)
1799 {
1800 const bus_space_handle_t ioh = sc->sc_iohandle;
1801 const bus_space_tag_t iot = sc->sc_iotag;
1802 struct trm_scsi_req_q *pSRB;
1803 struct trm_dcb *pDCB;
1804 u_int16_t RselTarLunId;
1805 u_int8_t target, lun;
1806
1807 #ifdef TRM_DEBUG0
1808 printf("%s: trm_Reselect\n", sc->sc_device.dv_xname);
1809 #endif
1810
1811 pDCB = sc->pActiveDCB;
1812 if (pDCB != NULL) {
1813 /*
1814 * Arbitration lost but Reselection win
1815 */
1816 pSRB = pDCB->pActiveSRB;
1817 trm_RewaitSRB(sc, pSRB);
1818 }
1819
1820 /*
1821 * Read Reselected Target Id and LUN
1822 */
1823 RselTarLunId = bus_space_read_2(iot, ioh, TRM_S1040_SCSI_TARGETID) & 0x1FFF;
1824 /* TODO XXXX: Make endian independent! */
1825 target = RselTarLunId & 0xff;
1826 lun = (RselTarLunId >> 8) & 0xff;
1827
1828 #ifdef TRM_DEBUG0
1829 printf("%s: reselect - target = %d, lun = %d\n",
1830 sc->sc_device.dv_xname, target, lun);
1831 #endif
1832
1833 if ((target < TRM_MAX_TARGETS) && (lun < TRM_MAX_LUNS))
1834 pDCB = sc->pDCB[target][lun];
1835 else
1836 pDCB = NULL;
1837
1838 if (pDCB == NULL)
1839 printf("%s: reselect - target = %d, lun = %d not found\n",
1840 sc->sc_device.dv_xname, target, lun);
1841
1842 sc->pActiveDCB = pDCB;
1843
1844 /* TODO XXXX: This will crash if pDCB is ever NULL */
1845 if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) != 0) {
1846 pSRB = &sc->SRB[0];
1847 pDCB->pActiveSRB = pSRB;
1848 } else {
1849 pSRB = pDCB->pActiveSRB;
1850 if (pSRB == NULL || (pSRB->SRBState != TRM_DISCONNECTED)) {
1851 /*
1852 * abort command
1853 */
1854 pSRB = &sc->SRB[0];
1855 pSRB->SRBState = TRM_UNEXPECT_RESEL;
1856 pDCB->pActiveSRB = pSRB;
1857 trm_EnableMsgOut(sc, MSG_ABORT);
1858 } else
1859 pSRB->SRBState = TRM_DATA_XFER;
1860 }
1861 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */
1862
1863 /*
1864 * Program HA ID, target ID, period and offset
1865 */
1866 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TARGETID, target);
1867 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, sc->sc_AdaptSCSIID);
1868 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod);
1869 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset);
1870
1871 /*
1872 * it's important for atn stop
1873 */
1874 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH);
1875 DELAY(30);
1876
1877 /*
1878 * SCSI command
1879 * to rls the /ACK signal
1880 */
1881 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT);
1882 }
1883
1884 /*
1885 * ------------------------------------------------------------
1886 * Function : trm_FinishSRB
1887 * Purpose : Complete execution of a SCSI command
1888 * Inputs :
1889 * ------------------------------------------------------------
1890 */
1891 void
trm_FinishSRB(struct trm_softc * sc,struct trm_scsi_req_q * pSRB)1892 trm_FinishSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB)
1893 {
1894 struct scsi_inquiry_data *ptr;
1895 struct scsi_sense_data *s1, *s2;
1896 struct scsi_xfer *xs = pSRB->xs;
1897 struct trm_dcb *pDCB = pSRB->pSRBDCB;
1898 int target, lun, intflag;
1899
1900 #ifdef TRM_DEBUG0
1901 printf("%s: trm_FinishSRB. sc = %p, pSRB = %p\n",
1902 sc->sc_device.dv_xname, sc, pSRB);
1903 #endif
1904 pDCB->DCBFlag &= ~TRM_QUEUE_FULL;
1905
1906 intflag = splbio();
1907 if (pSRB->TagNumber != TRM_NO_TAG) {
1908 pSRB->pSRBDCB->TagMask &= ~(1 << pSRB->TagNumber);
1909 pSRB->TagNumber = TRM_NO_TAG;
1910 }
1911 /* SRB may have started & finished, or be waiting and timed out */
1912 if ((pSRB->SRBFlag & TRM_ON_WAITING_SRB) != 0) {
1913 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB;
1914 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link);
1915 }
1916 if ((pSRB->SRBFlag & TRM_ON_GOING_SRB) != 0) {
1917 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB;
1918 TAILQ_REMOVE(&sc->goingSRB, pSRB, link);
1919 }
1920 splx(intflag);
1921
1922 if (xs == NULL) {
1923 return;
1924 }
1925
1926 timeout_del(&xs->stimeout);
1927
1928 xs->status = pSRB->TargetStatus;
1929 if (xs->datalen != 0) {
1930 bus_dmamap_sync(sc->sc_dmatag, pSRB->dmamapxfer,
1931 0, pSRB->dmamapxfer->dm_mapsize,
1932 (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_POSTREAD :
1933 BUS_DMASYNC_POSTWRITE);
1934 bus_dmamap_unload(sc->sc_dmatag, pSRB->dmamapxfer);
1935 }
1936
1937 switch (xs->status) {
1938 case SCSI_INTERM_COND_MET:
1939 case SCSI_COND_MET:
1940 case SCSI_INTERM:
1941 case SCSI_OK:
1942 switch (pSRB->AdaptStatus) {
1943 case TRM_STATUS_GOOD:
1944 if ((pSRB->SRBFlag & TRM_PARITY_ERROR) != 0) {
1945 #ifdef TRM_DEBUG0
1946 sc_print_addr(xs->sc_link);
1947 printf(" trm_FinishSRB. TRM_PARITY_ERROR\n");
1948 #endif
1949 xs->error = XS_DRIVER_STUFFUP;
1950
1951 } else if ((pSRB->SRBFlag & TRM_SCSI_TIMED_OUT) != 0) {
1952 if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) == 0)
1953 xs->error = XS_TIMEOUT;
1954 else {
1955 bzero(&xs->sense, sizeof(xs->sense));
1956 xs->status = SCSI_CHECK;
1957 xs->error = XS_SENSE;
1958 }
1959
1960 } else if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) != 0) {
1961 s1 = &pSRB->scsisense;
1962 s2 = &xs->sense;
1963
1964 *s2 = *s1;
1965
1966 xs->status = SCSI_CHECK;
1967 xs->error = XS_SENSE;
1968
1969 } else
1970 xs->error = XS_NOERROR;
1971 break;
1972
1973 case TRM_OVER_UNDER_RUN:
1974 #ifdef TRM_DEBUG0
1975 sc_print_addr(xs->sc_link);
1976 printf("trm_FinishSRB. TRM_OVER_UNDER_RUN\n");
1977 #endif
1978 xs->error = XS_DRIVER_STUFFUP;
1979 break;
1980
1981 default:
1982 #ifdef TRM_DEBUG0
1983 sc_print_addr(xs->sc_link);
1984 printf("trm_FinishSRB. AdaptStatus Error = 0x%02x\n",
1985 pSRB->AdaptStatus);
1986 #endif
1987 xs->error = XS_DRIVER_STUFFUP;
1988 break;
1989 }
1990 break;
1991
1992 case SCSI_TERMINATED:
1993 case SCSI_ACA_ACTIVE:
1994 case SCSI_CHECK:
1995 if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) != 0)
1996 xs->error = XS_DRIVER_STUFFUP;
1997 else {
1998 trm_RequestSense(sc, pSRB);
1999 return;
2000 }
2001 break;
2002
2003 case SCSI_QUEUE_FULL:
2004 /* this says no more until someone completes */
2005 pDCB->DCBFlag |= TRM_QUEUE_FULL;
2006 trm_RewaitSRB(sc, pSRB);
2007 return;
2008
2009 case SCSI_RESV_CONFLICT:
2010 case SCSI_BUSY:
2011 xs->error = XS_BUSY;
2012 break;
2013
2014 case TRM_SCSI_UNEXP_BUS_FREE:
2015 xs->status = SCSI_OK;
2016 xs->error = XS_DRIVER_STUFFUP;
2017 break;
2018
2019 case TRM_SCSI_BUS_RST_DETECTED:
2020 xs->status = SCSI_OK;
2021 xs->error = XS_RESET;
2022 break;
2023
2024 case TRM_SCSI_SELECT_TIMEOUT:
2025 xs->status = SCSI_OK;
2026 xs->error = XS_SELTIMEOUT;
2027 break;
2028
2029 default:
2030 xs->error = XS_DRIVER_STUFFUP;
2031 break;
2032 }
2033
2034 target = xs->sc_link->target;
2035 lun = xs->sc_link->lun;
2036
2037 if ((xs->flags & SCSI_POLL) != 0) {
2038
2039 if (xs->cmd.opcode == INQUIRY && pDCB->sc_link == NULL) {
2040
2041 ptr = (struct scsi_inquiry_data *) xs->data;
2042
2043 if ((xs->error != XS_NOERROR) ||
2044 ((ptr->device & SID_QUAL_BAD_LU) == SID_QUAL_BAD_LU)) {
2045 #ifdef TRM_DEBUG0
2046 sc_print_addr(xs->sc_link);
2047 printf("trm_FinishSRB NO Device\n");
2048 #endif
2049 free(pDCB, M_DEVBUF, 0);
2050 sc->pDCB[target][lun] = NULL;
2051 pDCB = NULL;
2052
2053 } else
2054 pDCB->sc_link = xs->sc_link;
2055 }
2056 }
2057
2058 /*
2059 * Notify cmd done
2060 */
2061 #ifdef TRM_DEBUG0
2062 if ((xs->error != 0) || (xs->status != 0) ||
2063 ((xs->flags & SCSI_POLL) != 0)) {
2064 sc_print_addr(xs->sc_link);
2065 printf("trm_FinishSRB. xs->cmd.opcode = 0x%02x, xs->error = %d, xs->status = %d\n",
2066 xs->cmd.opcode, xs->error, xs->status);
2067 }
2068 #endif
2069
2070 if (ISSET(xs->flags, SCSI_POLL))
2071 SET(xs->flags, ITSDONE);
2072 else
2073 scsi_done(xs);
2074 }
2075
2076 /*
2077 * ------------------------------------------------------------
2078 * Function : trm_srb_reinit
2079 * Purpose :
2080 * Inputs :
2081 * ------------------------------------------------------------
2082 */
2083 void
trm_srb_reinit(struct trm_softc * sc,struct trm_scsi_req_q * pSRB)2084 trm_srb_reinit(struct trm_softc *sc, struct trm_scsi_req_q *pSRB)
2085 {
2086 bzero(&pSRB->SegmentX[0], sizeof(pSRB->SegmentX));
2087 bzero(&pSRB->CmdBlock[0], sizeof(pSRB->CmdBlock));
2088 bzero(&pSRB->scsisense, sizeof(pSRB->scsisense));
2089
2090 pSRB->SRBTotalXferLength = 0;
2091 pSRB->SRBSGCount = 0;
2092 pSRB->SRBSGIndex = 0;
2093 pSRB->SRBFlag = 0;
2094
2095 pSRB->SRBState = TRM_FREE;
2096 pSRB->AdaptStatus = TRM_STATUS_GOOD;
2097 pSRB->TargetStatus = SCSI_OK;
2098 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */
2099
2100 pSRB->xs = NULL;
2101 pSRB->pSRBDCB = NULL;
2102 }
2103
2104 /*
2105 * ------------------------------------------------------------
2106 * Function : trm_srb_free
2107 * Purpose :
2108 * Inputs :
2109 * ------------------------------------------------------------
2110 */
2111 void
trm_srb_free(void * xsc,void * xpSRB)2112 trm_srb_free(void *xsc, void *xpSRB)
2113 {
2114 struct trm_softc *sc = xsc;
2115 struct trm_scsi_req_q *pSRB = xpSRB;
2116
2117 trm_srb_reinit(sc, pSRB);
2118
2119 if (pSRB != &sc->SRB[0]) {
2120 mtx_enter(&sc->sc_srb_mtx);
2121 TAILQ_INSERT_TAIL(&sc->freeSRB, pSRB, link);
2122 mtx_leave(&sc->sc_srb_mtx);
2123 }
2124 }
2125
2126 /*
2127 * ------------------------------------------------------------
2128 * Function : trm_GoingSRB_Done
2129 * Purpose :
2130 * Inputs :
2131 * ------------------------------------------------------------
2132 */
2133 void
trm_GoingSRB_Done(struct trm_softc * sc,struct trm_dcb * pDCB)2134 trm_GoingSRB_Done(struct trm_softc *sc, struct trm_dcb *pDCB)
2135 {
2136 struct trm_scsi_req_q *pSRB, *pNextSRB;
2137
2138 /* ASSUME we are inside a splbio()/splx() pair */
2139
2140 pSRB = TAILQ_FIRST(&sc->goingSRB);
2141 while (pSRB != NULL) {
2142 /*
2143 * Need to save pNextSRB because trm_FinishSRB() puts
2144 * pSRB in freeSRB queue, and thus its links no longer
2145 * point to members of the goingSRB queue. This is why
2146 * TAILQ_FOREACH() will not work for this traversal.
2147 */
2148 pNextSRB = TAILQ_NEXT(pSRB, link);
2149 if (pDCB == NULL || pSRB->pSRBDCB == pDCB) {
2150 /* TODO XXXX: Is TIMED_OUT the best state to report? */
2151 pSRB->SRBFlag |= TRM_SCSI_TIMED_OUT;
2152 trm_FinishSRB(sc, pSRB);
2153 }
2154 pSRB = pNextSRB;
2155 }
2156 }
2157
2158 /*
2159 * ------------------------------------------------------------
2160 * Function : trm_ResetSCSIBus
2161 * Purpose : Reset the SCSI bus
2162 * Inputs : struct trm_softc * -
2163 * ------------------------------------------------------------
2164 */
2165 void
trm_ResetSCSIBus(struct trm_softc * sc)2166 trm_ResetSCSIBus(struct trm_softc *sc)
2167 {
2168 const bus_space_handle_t ioh = sc->sc_iohandle;
2169 const bus_space_tag_t iot = sc->sc_iotag;
2170 int intflag;
2171
2172 intflag = splbio();
2173
2174 sc->sc_Flag |= RESET_DEV;
2175
2176 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_RSTSCSI);
2177 while ((bus_space_read_2(iot, ioh,
2178 TRM_S1040_SCSI_INTSTATUS) & INT_SCSIRESET) == 0);
2179
2180 splx(intflag);
2181 }
2182
2183 /*
2184 * ------------------------------------------------------------
2185 * Function : trm_ScsiRstDetect
2186 * Purpose :
2187 * Inputs :
2188 * ------------------------------------------------------------
2189 */
2190 void
trm_ScsiRstDetect(struct trm_softc * sc)2191 trm_ScsiRstDetect(struct trm_softc *sc)
2192 {
2193 const bus_space_handle_t ioh = sc->sc_iohandle;
2194 const bus_space_tag_t iot = sc->sc_iotag;
2195 int wlval;
2196
2197 #ifdef TRM_DEBUG0
2198 printf("%s: trm_ScsiRstDetect\n", sc->sc_device.dv_xname);
2199 #endif
2200
2201 wlval = 1000;
2202 /*
2203 * delay 1 sec
2204 */
2205 while (--wlval != 0)
2206 DELAY(1000);
2207
2208 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, STOPDMAXFER);
2209 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO);
2210
2211 if ((sc->sc_Flag & RESET_DEV) != 0)
2212 sc->sc_Flag |= RESET_DONE;
2213 else {
2214 sc->sc_Flag |= RESET_DETECT;
2215 trm_ResetAllDevParam(sc);
2216 trm_RecoverSRB(sc);
2217 sc->pActiveDCB = NULL;
2218 sc->sc_Flag = 0;
2219 trm_StartWaitingSRB(sc);
2220 }
2221 }
2222
2223 /*
2224 * ------------------------------------------------------------
2225 * Function : trm_RequestSense
2226 * Purpose :
2227 * Inputs :
2228 * ------------------------------------------------------------
2229 */
2230 void
trm_RequestSense(struct trm_softc * sc,struct trm_scsi_req_q * pSRB)2231 trm_RequestSense(struct trm_softc *sc, struct trm_scsi_req_q *pSRB)
2232 {
2233 pSRB->SRBFlag |= TRM_AUTO_REQSENSE;
2234
2235 /*
2236 * Status of initiator/target
2237 */
2238 pSRB->AdaptStatus = TRM_STATUS_GOOD;
2239 pSRB->TargetStatus = SCSI_OK;
2240 /*
2241 * Status of initiator/target
2242 */
2243
2244 pSRB->SegmentX[0].address = pSRB->scsisensePhyAddr;
2245 pSRB->SegmentX[0].length = sizeof(struct scsi_sense_data);
2246 pSRB->SRBTotalXferLength = sizeof(struct scsi_sense_data);
2247 pSRB->SRBSGCount = 1;
2248 pSRB->SRBSGIndex = 0;
2249
2250 bzero(&pSRB->CmdBlock[0], sizeof(pSRB->CmdBlock));
2251
2252 pSRB->CmdBlock[0] = REQUEST_SENSE;
2253 pSRB->CmdBlock[1] = (pSRB->xs->sc_link->lun) << 5;
2254 pSRB->CmdBlock[4] = sizeof(struct scsi_sense_data);
2255
2256 pSRB->ScsiCmdLen = 6;
2257
2258 if ((pSRB->xs != NULL) && ((pSRB->xs->flags & SCSI_POLL) == 0))
2259 timeout_add_msec(&pSRB->xs->stimeout, pSRB->xs->timeout);
2260
2261 if (trm_StartSRB(sc, pSRB) != 0)
2262 trm_RewaitSRB(sc, pSRB);
2263 }
2264
2265 /*
2266 * ------------------------------------------------------------
2267 * Function : trm_EnableMsgOut
2268 * Purpose : set up MsgBuf to send out a single byte message
2269 * Inputs :
2270 * ------------------------------------------------------------
2271 */
2272 void
trm_EnableMsgOut(struct trm_softc * sc,u_int8_t msg)2273 trm_EnableMsgOut(struct trm_softc *sc, u_int8_t msg)
2274 {
2275 sc->MsgBuf[0] = msg;
2276 sc->MsgCnt = 1;
2277
2278 bus_space_write_2(sc->sc_iotag, sc->sc_iohandle, TRM_S1040_SCSI_CONTROL, DO_SETATN);
2279 }
2280
2281 /*
2282 * ------------------------------------------------------------
2283 * Function : trm_linkSRB
2284 * Purpose :
2285 * Inputs :
2286 * ------------------------------------------------------------
2287 */
2288 void
trm_linkSRB(struct trm_softc * sc)2289 trm_linkSRB(struct trm_softc *sc)
2290 {
2291 struct trm_scsi_req_q *pSRB;
2292 int i, intflag;
2293
2294 intflag = splbio();
2295
2296 for (i = 0; i < TRM_MAX_SRB_CNT; i++) {
2297 pSRB = &sc->SRB[i];
2298
2299 pSRB->PhysSRB = sc->sc_dmamap_control->dm_segs[0].ds_addr
2300 + i * sizeof(struct trm_scsi_req_q);
2301
2302 pSRB->SRBSGPhyAddr = sc->sc_dmamap_control->dm_segs[0].ds_addr
2303 + i * sizeof(struct trm_scsi_req_q)
2304 + offsetof(struct trm_scsi_req_q, SegmentX);
2305
2306 pSRB->scsisensePhyAddr = sc->sc_dmamap_control->dm_segs[0].ds_addr
2307 + i * sizeof(struct trm_scsi_req_q)
2308 + offsetof(struct trm_scsi_req_q, scsisense);
2309
2310 /*
2311 * map all SRB space
2312 */
2313 if (bus_dmamap_create(sc->sc_dmatag, TRM_MAX_PHYSG_BYTE,
2314 TRM_MAX_SG_LISTENTRY, TRM_MAX_PHYSG_BYTE, 0,
2315 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
2316 &pSRB->dmamapxfer) != 0) {
2317 printf("%s: unable to create DMA transfer map\n",
2318 sc->sc_device.dv_xname);
2319 splx(intflag);
2320 return;
2321 }
2322
2323 if (i > 0)
2324 /* We use sc->SRB[0] directly, so *don't* link it */
2325 TAILQ_INSERT_TAIL(&sc->freeSRB, pSRB, link);
2326 #ifdef TRM_DEBUG0
2327 printf("pSRB = %p ", pSRB);
2328 #endif
2329 }
2330 #ifdef TRM_DEBUG0
2331 printf("\n ");
2332 #endif
2333 splx(intflag);
2334 }
2335
2336 /*
2337 * ------------------------------------------------------------
2338 * Function : trm_initACB
2339 * Purpose : initialize the internal structures for a given SCSI host
2340 * Inputs :
2341 * ------------------------------------------------------------
2342 */
2343 void
trm_initACB(struct trm_softc * sc,int unit)2344 trm_initACB(struct trm_softc *sc, int unit)
2345 {
2346 const bus_space_handle_t ioh = sc->sc_iohandle;
2347 const bus_space_tag_t iot = sc->sc_iotag;
2348 struct trm_adapter_nvram *pEEpromBuf;
2349 struct trm_dcb *pDCB;
2350 int target, lun;
2351
2352 pEEpromBuf = &trm_eepromBuf[unit];
2353 sc->sc_config = HCC_AUTOTERM | HCC_PARITY;
2354
2355 if ((bus_space_read_1(iot, ioh, TRM_S1040_GEN_STATUS) & WIDESCSI) != 0)
2356 sc->sc_config |= HCC_WIDE_CARD;
2357
2358 if ((pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) != 0)
2359 sc->sc_config |= HCC_SCSI_RESET;
2360
2361 TAILQ_INIT(&sc->freeSRB);
2362 TAILQ_INIT(&sc->waitingSRB);
2363 TAILQ_INIT(&sc->goingSRB);
2364
2365 mtx_init(&sc->sc_srb_mtx, IPL_BIO);
2366 scsi_iopool_init(&sc->sc_iopool, sc, trm_srb_alloc, trm_srb_free);
2367
2368 sc->pActiveDCB = NULL;
2369 sc->sc_AdapterUnit = unit;
2370 sc->sc_AdaptSCSIID = pEEpromBuf->NvramScsiId;
2371 sc->sc_TagMaxNum = 2 << pEEpromBuf->NvramMaxTag;
2372 sc->sc_Flag = 0;
2373
2374 /*
2375 * put all SRB's (except [0]) onto the freeSRB list
2376 */
2377 trm_linkSRB(sc);
2378
2379 /*
2380 * allocate DCB array
2381 */
2382 for (target = 0; target < TRM_MAX_TARGETS; target++) {
2383 if (target == sc->sc_AdaptSCSIID)
2384 continue;
2385
2386 for (lun = 0; lun < TRM_MAX_LUNS; lun++) {
2387 pDCB = (struct trm_dcb *)malloc(sizeof(struct trm_dcb),
2388 M_DEVBUF, M_NOWAIT | M_ZERO);
2389 sc->pDCB[target][lun] = pDCB;
2390
2391 if (pDCB == NULL)
2392 continue;
2393
2394 pDCB->target = target;
2395 pDCB->lun = lun;
2396 pDCB->pActiveSRB = NULL;
2397 }
2398 }
2399
2400 trm_reset(sc);
2401 }
2402
2403 /*
2404 * ------------------------------------------------------------
2405 * Function : trm_write_all
2406 * Description : write pEEpromBuf 128 bytes to seeprom
2407 * Input : iot, ioh - chip's base address
2408 * Output : none
2409 * ------------------------------------------------------------
2410 */
2411 void
trm_write_all(struct trm_adapter_nvram * pEEpromBuf,bus_space_tag_t iot,bus_space_handle_t ioh)2412 trm_write_all(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot,
2413 bus_space_handle_t ioh)
2414 {
2415 u_int8_t *bpEeprom = (u_int8_t *)pEEpromBuf;
2416 u_int8_t bAddr;
2417
2418 /*
2419 * Enable SEEPROM
2420 */
2421 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL,
2422 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) | EN_EEPROM));
2423 /*
2424 * Write enable
2425 */
2426 trm_write_cmd(iot, ioh, 0x04, 0xFF);
2427 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0);
2428 trm_wait_30us(iot, ioh);
2429 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++)
2430 trm_set_data(iot, ioh, bAddr, *bpEeprom);
2431 /*
2432 * Write disable
2433 */
2434 trm_write_cmd(iot, ioh, 0x04, 0x00);
2435 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0);
2436 trm_wait_30us(iot, ioh);
2437 /*
2438 * Disable SEEPROM
2439 */
2440 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL,
2441 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) & ~EN_EEPROM));
2442 }
2443
2444 /*
2445 * ------------------------------------------------------------
2446 * Function : trm_set_data
2447 * Description : write one byte to seeprom
2448 * Input : iot, ioh - chip's base address
2449 * bAddr - address of SEEPROM
2450 * bData - data of SEEPROM
2451 * Output : none
2452 * ------------------------------------------------------------
2453 */
2454 void
trm_set_data(bus_space_tag_t iot,bus_space_handle_t ioh,u_int8_t bAddr,u_int8_t bData)2455 trm_set_data(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bAddr,
2456 u_int8_t bData)
2457 {
2458 u_int8_t bSendData;
2459 int i;
2460
2461 /*
2462 * Send write command & address
2463 */
2464 trm_write_cmd(iot, ioh, 0x05, bAddr);
2465 /*
2466 * Write data
2467 */
2468 for (i = 0; i < 8; i++, bData <<= 1) {
2469 bSendData = NVR_SELECT;
2470 if ((bData & 0x80) != 0) { /* Start from bit 7 */
2471 bSendData |= NVR_BITOUT;
2472 }
2473 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData);
2474 trm_wait_30us(iot, ioh);
2475 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM,
2476 (bSendData | NVR_CLOCK));
2477 trm_wait_30us(iot, ioh);
2478 }
2479 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT);
2480 trm_wait_30us(iot, ioh);
2481 /*
2482 * Disable chip select
2483 */
2484 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0);
2485 trm_wait_30us(iot, ioh);
2486 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT);
2487 trm_wait_30us(iot, ioh);
2488 /*
2489 * Wait for write ready
2490 */
2491 for (;;) {
2492 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM,
2493 (NVR_SELECT | NVR_CLOCK));
2494 trm_wait_30us(iot, ioh);
2495 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT);
2496 trm_wait_30us(iot, ioh);
2497 if (bus_space_read_1(iot, ioh, TRM_S1040_GEN_NVRAM) & NVR_BITIN)
2498 break;
2499 }
2500 /*
2501 * Disable chip select
2502 */
2503 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0);
2504 }
2505
2506 /*
2507 * ------------------------------------------------------------
2508 * Function : trm_read_all
2509 * Description : read seeprom 128 bytes to pEEpromBuf
2510 * Input : pEEpromBuf, iot, ioh - chip's base address
2511 * Output : none
2512 * ------------------------------------------------------------
2513 */
2514 void
trm_read_all(struct trm_adapter_nvram * pEEpromBuf,bus_space_tag_t iot,bus_space_handle_t ioh)2515 trm_read_all(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot,
2516 bus_space_handle_t ioh)
2517 {
2518 u_int8_t *bpEeprom = (u_int8_t *)pEEpromBuf;
2519 u_int8_t bAddr;
2520
2521 /*
2522 * Enable SEEPROM
2523 */
2524 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL,
2525 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) | EN_EEPROM));
2526
2527 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++)
2528 *bpEeprom = trm_get_data(iot, ioh, bAddr);
2529
2530 /*
2531 * Disable SEEPROM
2532 */
2533 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL,
2534 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) & ~EN_EEPROM));
2535 }
2536
2537 /*
2538 * ------------------------------------------------------------
2539 * Function : trm_get_data
2540 * Description : read one byte from seeprom
2541 * Input : iot, ioh - chip's base address
2542 * bAddr - address of SEEPROM
2543 * Output : bData - data of SEEPROM
2544 * ------------------------------------------------------------
2545 */
2546 u_int8_t
trm_get_data(bus_space_tag_t iot,bus_space_handle_t ioh,u_int8_t bAddr)2547 trm_get_data( bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bAddr)
2548 {
2549 u_int8_t bReadData, bData;
2550 int i;
2551
2552 bData = 0;
2553
2554 /*
2555 * Send read command & address
2556 */
2557 trm_write_cmd(iot, ioh, 0x06, bAddr);
2558
2559 for (i = 0; i < 8; i++) {
2560 /*
2561 * Read data
2562 */
2563 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM,
2564 (NVR_SELECT | NVR_CLOCK));
2565 trm_wait_30us(iot, ioh);
2566 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT);
2567 /*
2568 * Get data bit while falling edge
2569 */
2570 bReadData = bus_space_read_1(iot, ioh, TRM_S1040_GEN_NVRAM);
2571 bData <<= 1;
2572 if ((bReadData & NVR_BITIN) != 0)
2573 bData |= 1;
2574 trm_wait_30us(iot, ioh);
2575 }
2576 /*
2577 * Disable chip select
2578 */
2579 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0);
2580
2581 return bData;
2582 }
2583
2584 /*
2585 * ------------------------------------------------------------
2586 * Function : trm_wait_30us
2587 * Description : wait 30 us
2588 * Input : iot, ioh - chip's base address
2589 * Output : none
2590 * ------------------------------------------------------------
2591 */
2592 void
trm_wait_30us(bus_space_tag_t iot,bus_space_handle_t ioh)2593 trm_wait_30us(bus_space_tag_t iot, bus_space_handle_t ioh)
2594 {
2595 bus_space_write_1(iot, ioh, TRM_S1040_GEN_TIMER, 5);
2596
2597 while ((bus_space_read_1(iot, ioh, TRM_S1040_GEN_STATUS) & GTIMEOUT)
2598 == 0);
2599 }
2600
2601 /*
2602 * ------------------------------------------------------------
2603 * Function : trm_write_cmd
2604 * Description : write SB and Op Code into seeprom
2605 * Input : iot, ioh - chip's base address
2606 * bCmd - SB + Op Code
2607 * bAddr - address of SEEPROM
2608 * Output : none
2609 * ------------------------------------------------------------
2610 */
2611 void
trm_write_cmd(bus_space_tag_t iot,bus_space_handle_t ioh,u_int8_t bCmd,u_int8_t bAddr)2612 trm_write_cmd( bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bCmd,
2613 u_int8_t bAddr)
2614 {
2615 u_int8_t bSendData;
2616 int i;
2617
2618 for (i = 0; i < 3; i++, bCmd <<= 1) {
2619 /*
2620 * Program SB + OP code
2621 */
2622 bSendData = NVR_SELECT;
2623 if (bCmd & 0x04) /* Start from bit 2 */
2624 bSendData |= NVR_BITOUT;
2625 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData);
2626 trm_wait_30us(iot, ioh);
2627 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM,
2628 (bSendData | NVR_CLOCK));
2629 trm_wait_30us(iot, ioh);
2630 }
2631
2632 for (i = 0; i < 7; i++, bAddr <<= 1) {
2633 /*
2634 * Program address
2635 */
2636 bSendData = NVR_SELECT;
2637 if (bAddr & 0x40) { /* Start from bit 6 */
2638 bSendData |= NVR_BITOUT;
2639 }
2640 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData);
2641 trm_wait_30us(iot, ioh);
2642 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM,
2643 (bSendData | NVR_CLOCK));
2644 trm_wait_30us(iot, ioh);
2645 }
2646 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT);
2647 trm_wait_30us(iot, ioh);
2648 }
2649
2650 /*
2651 * ------------------------------------------------------------
2652 * Function : trm_check_eeprom
2653 * Description : read eeprom 128 bytes to pEEpromBuf and check
2654 * checksum. If it is wrong, updated with default value.
2655 * Input : eeprom, iot, ioh - chip's base address
2656 * Output : none
2657 * ------------------------------------------------------------
2658 */
2659 void
trm_check_eeprom(struct trm_adapter_nvram * pEEpromBuf,bus_space_tag_t iot,bus_space_handle_t ioh)2660 trm_check_eeprom(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot,
2661 bus_space_handle_t ioh)
2662 {
2663 u_int32_t *dpEeprom = (u_int32_t *)pEEpromBuf->NvramTarget;
2664 u_int32_t dAddr;
2665 u_int16_t *wpEeprom = (u_int16_t *)pEEpromBuf;
2666 u_int16_t wAddr, wCheckSum;
2667
2668 #ifdef TRM_DEBUG0
2669 printf("\ntrm_check_eeprom\n");
2670 #endif
2671 trm_read_all(pEEpromBuf, iot, ioh);
2672 wCheckSum = 0;
2673 for (wAddr = 0; wAddr < 64; wAddr++, wpEeprom++)
2674 wCheckSum += *wpEeprom;
2675
2676 if (wCheckSum != 0x1234) {
2677 #ifdef TRM_DEBUG0
2678 printf("TRM_S1040 EEPROM Check Sum ERROR (load default)\n");
2679 #endif
2680 /*
2681 * Checksum error, load default
2682 */
2683 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t)PCI_VENDOR_TEKRAM2;
2684 pEEpromBuf->NvramSubVendorID[1] = (u_int8_t)(PCI_VENDOR_TEKRAM2
2685 >> 8);
2686 pEEpromBuf->NvramSubSysID[0] = (u_int8_t)
2687 PCI_PRODUCT_TEKRAM2_DC3X5U;
2688 pEEpromBuf->NvramSubSysID[1] = (u_int8_t)
2689 (PCI_PRODUCT_TEKRAM2_DC3X5U >> 8);
2690 pEEpromBuf->NvramSubClass = 0;
2691 pEEpromBuf->NvramVendorID[0] = (u_int8_t)PCI_VENDOR_TEKRAM2;
2692 pEEpromBuf->NvramVendorID[1] = (u_int8_t)(PCI_VENDOR_TEKRAM2
2693 >> 8);
2694 pEEpromBuf->NvramDeviceID[0] = (u_int8_t)
2695 PCI_PRODUCT_TEKRAM2_DC3X5U;
2696 pEEpromBuf->NvramDeviceID[1] = (u_int8_t)
2697 (PCI_PRODUCT_TEKRAM2_DC3X5U >> 8);
2698 pEEpromBuf->NvramReserved = 0;
2699
2700 for (dAddr = 0; dAddr < 16; dAddr++, dpEeprom++)
2701 /*
2702 * NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0
2703 */
2704 *dpEeprom = 0x00000077;
2705
2706 /*
2707 * NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId
2708 */
2709 *dpEeprom++ = 0x04000F07;
2710
2711 /*
2712 * NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0
2713 */
2714 *dpEeprom++ = 0x00000015;
2715 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++)
2716 *dpEeprom = 0;
2717
2718 pEEpromBuf->NvramCheckSum = 0;
2719 for (wAddr = 0, wCheckSum =0; wAddr < 63; wAddr++, wpEeprom++)
2720 wCheckSum += *wpEeprom;
2721
2722 *wpEeprom = 0x1234 - wCheckSum;
2723 trm_write_all(pEEpromBuf, iot, ioh);
2724 }
2725 }
2726
2727 /*
2728 * ------------------------------------------------------------
2729 * Function : trm_initAdapter
2730 * Purpose : initialize the SCSI chip ctrl registers
2731 * Inputs : psh - pointer to this host adapter's structure
2732 * ------------------------------------------------------------
2733 */
2734 void
trm_initAdapter(struct trm_softc * sc)2735 trm_initAdapter(struct trm_softc *sc)
2736 {
2737 const bus_space_handle_t ioh = sc->sc_iohandle;
2738 const bus_space_tag_t iot = sc->sc_iotag;
2739 u_int16_t wval;
2740 u_int8_t bval;
2741
2742 /*
2743 * program configuration 0
2744 */
2745 if ((sc->sc_config & HCC_PARITY) != 0) {
2746 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK;
2747 } else {
2748 bval = PHASELATCH | INITIATOR | BLOCKRST;
2749 }
2750 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_CONFIG0, bval);
2751 /*
2752 * program configuration 1
2753 */
2754 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_CONFIG1, 0x13);
2755 /*
2756 * 250ms selection timeout
2757 */
2758 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TIMEOUT, TRM_SEL_TIMEOUT);
2759 /*
2760 * Mask all the interrupt
2761 */
2762 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, 0);
2763 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 0);
2764 /*
2765 * Reset SCSI module
2766 */
2767 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_RSTMODULE);
2768 /*
2769 * program Host ID
2770 */
2771 bval = sc->sc_AdaptSCSIID;
2772 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, bval);
2773 /*
2774 * set asynchronous transfer
2775 */
2776 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, 0);
2777 /*
2778 * Turn LED control off
2779 */
2780 wval = bus_space_read_2(iot, ioh, TRM_S1040_GEN_CONTROL) & 0x7F;
2781 bus_space_write_2(iot, ioh, TRM_S1040_GEN_CONTROL, wval);
2782 /*
2783 * DMA config
2784 */
2785 wval = bus_space_read_2(iot, ioh, TRM_S1040_DMA_CONFIG) | DMA_ENHANCE;
2786 bus_space_write_2(iot, ioh, TRM_S1040_DMA_CONFIG, wval);
2787 /*
2788 * Clear pending interrupt status
2789 */
2790 bus_space_read_1(iot, ioh, TRM_S1040_SCSI_INTSTATUS);
2791 /*
2792 * Enable SCSI interrupts
2793 */
2794 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN,
2795 (EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED |
2796 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE));
2797 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, EN_SCSIINTR);
2798 }
2799
2800 /*
2801 * ------------------------------------------------------------
2802 * Function : trm_init
2803 * Purpose : initialize the internal structures for a given SCSI host
2804 * Inputs : host - pointer to this host adapter's structure
2805 * Preconditions : when this function is called, the chip_type field of
2806 * the ACB structure MUST have been set.
2807 * ------------------------------------------------------------
2808 */
2809 int
trm_init(struct trm_softc * sc,int unit)2810 trm_init(struct trm_softc *sc, int unit)
2811 {
2812 const bus_space_handle_t ioh = sc->sc_iohandle;
2813 const bus_space_tag_t iot = sc->sc_iotag;
2814 bus_dma_segment_t seg;
2815 int error, rseg, all_srbs_size;
2816
2817 /*
2818 * EEPROM CHECKSUM
2819 */
2820 trm_check_eeprom(&trm_eepromBuf[unit], iot, ioh);
2821
2822 /*
2823 * MEMORY ALLOCATE FOR ADAPTER CONTROL BLOCK
2824 */
2825 /*
2826 * allocate the space for all SCSI control blocks (SRB) for DMA memory.
2827 */
2828 all_srbs_size = TRM_MAX_SRB_CNT * sizeof(struct trm_scsi_req_q);
2829
2830 error = bus_dmamem_alloc(sc->sc_dmatag, all_srbs_size, NBPG, 0, &seg,
2831 1, &rseg, BUS_DMA_NOWAIT | BUS_DMA_ZERO);
2832 if (error != 0) {
2833 printf("%s: unable to allocate SCSI REQUEST BLOCKS, error = %d\n",
2834 sc->sc_device.dv_xname, error);
2835 /*errx(error, "%s: unable to allocate SCSI request blocks",
2836 sc->sc_device.dv_xname);*/
2837 return -1;
2838 }
2839
2840 error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, all_srbs_size,
2841 (caddr_t *)&sc->SRB, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
2842 if (error != 0) {
2843 printf("%s: unable to map SCSI REQUEST BLOCKS, error = %d\n",
2844 sc->sc_device.dv_xname, error);
2845 /*errx(error, "unable to map SCSI request blocks");*/
2846 return -1;
2847 }
2848
2849 error = bus_dmamap_create(sc->sc_dmatag, all_srbs_size, 1,
2850 all_srbs_size, 0, BUS_DMA_NOWAIT,&sc->sc_dmamap_control);
2851 if (error != 0) {
2852 printf("%s: unable to create SRB DMA maps, error = %d\n",
2853 sc->sc_device.dv_xname, error);
2854 /*errx(error, "unable to create SRB DMA maps");*/
2855 return -1;
2856 }
2857
2858 error = bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap_control,
2859 sc->SRB, all_srbs_size, NULL, BUS_DMA_NOWAIT);
2860 if (error != 0) {
2861 printf("%s: unable to load SRB DMA maps, error = %d\n",
2862 sc->sc_device.dv_xname, error);
2863 /*errx(error, "unable to load SRB DMA maps");*/
2864 return -1;
2865 }
2866 #ifdef TRM_DEBUG0
2867 printf("\n\n%s: all_srbs_size=%x\n",
2868 sc->sc_device.dv_xname, all_srbs_size);
2869 #endif
2870 trm_initACB(sc, unit);
2871 trm_initAdapter(sc);
2872
2873 return 0;
2874 }
2875
2876 /* ------------------------------------------------------------
2877 * Function : trm_print_info
2878 * Purpose : Print the DCB negotiation information
2879 * Inputs :
2880 * ------------------------------------------------------------
2881 */
2882 void
trm_print_info(struct trm_softc * sc,struct trm_dcb * pDCB)2883 trm_print_info(struct trm_softc *sc, struct trm_dcb *pDCB)
2884 {
2885 int syncXfer, index;
2886
2887 index = pDCB->SyncPeriod & ~(WIDE_SYNC | ALT_SYNC);
2888
2889 printf("%s: target %d using ", sc->sc_device.dv_xname, pDCB->target);
2890 if ((pDCB->SyncPeriod & WIDE_SYNC) != 0)
2891 printf("16 bit ");
2892 else
2893 printf("8 bit ");
2894
2895 if (pDCB->SyncOffset == 0)
2896 printf("Asynchronous ");
2897 else {
2898 syncXfer = 100000 / (trm_clock_period[index] * 4);
2899 printf("%d.%01d MHz, Offset %d ",
2900 syncXfer / 100, syncXfer % 100, pDCB->SyncOffset);
2901 }
2902 printf("data transfers ");
2903
2904 if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) != 0)
2905 printf("with Tag Queuing");
2906
2907 printf("\n");
2908 }
2909