1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2001 Wind River Systems
5 * Copyright (c) 1997, 1998, 1999, 2000, 2001
6 * Bill Paul <william.paul@windriver.com>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36 #include <sys/cdefs.h>
37 /*
38 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
39 * documentation not available, but ask me nicely.
40 *
41 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
42 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
43 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
44 * are three supported methods for data transfer between host and
45 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
46 * Propulsion Technology (tm) DMA. The latter mechanism is a form
47 * of double buffer DMA where the packet data is copied to a
48 * pre-allocated DMA buffer who's physical address has been loaded
49 * into a table at device initialization time. The rationale is that
50 * the virtual to physical address translation needed for normal
51 * scatter/gather DMA is more expensive than the data copy needed
52 * for double buffering. This may be true in Windows NT and the like,
53 * but it isn't true for us, at least on the x86 arch. This driver
54 * uses the scatter/gather I/O method for both TX and RX.
55 *
56 * The LXT1001 only supports TCP/IP checksum offload on receive.
57 * Also, the VLAN tagging is done using a 16-entry table which allows
58 * the chip to perform hardware filtering based on VLAN tags. Sadly,
59 * our vlan support doesn't currently play well with this kind of
60 * hardware support.
61 *
62 * Special thanks to:
63 * - Jeff James at Intel, for arranging to have the LXT1001 manual
64 * released (at long last)
65 * - Beny Chen at D-Link, for actually sending it to me
66 * - Brad Short and Keith Alexis at SMC, for sending me sample
67 * SMC9462SX and SMC9462TX adapters for testing
68 * - Paul Saab at Y!, for not killing me (though it remains to be seen
69 * if in fact he did me much of a favor)
70 */
71
72 #include <sys/param.h>
73 #include <sys/systm.h>
74 #include <sys/sockio.h>
75 #include <sys/mbuf.h>
76 #include <sys/malloc.h>
77 #include <sys/kernel.h>
78 #include <sys/module.h>
79 #include <sys/socket.h>
80
81 #include <net/if.h>
82 #include <net/if_var.h>
83 #include <net/if_arp.h>
84 #include <net/ethernet.h>
85 #include <net/if_dl.h>
86 #include <net/if_media.h>
87 #include <net/if_types.h>
88
89 #include <net/bpf.h>
90
91 #include <vm/vm.h> /* for vtophys */
92 #include <vm/pmap.h> /* for vtophys */
93 #include <machine/bus.h>
94 #include <machine/resource.h>
95 #include <sys/bus.h>
96 #include <sys/rman.h>
97
98 #include <dev/mii/mii.h>
99 #include <dev/mii/miivar.h>
100
101 #include <dev/pci/pcireg.h>
102 #include <dev/pci/pcivar.h>
103
104 #define LGE_USEIOSPACE
105
106 #include <dev/lge/if_lgereg.h>
107
108 /* "device miibus" required. See GENERIC if you get errors here. */
109 #include "miibus_if.h"
110
111 /*
112 * Various supported device vendors/types and their names.
113 */
114 static const struct lge_type lge_devs[] = {
115 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" },
116 { 0, 0, NULL }
117 };
118
119 static int lge_probe(device_t);
120 static int lge_attach(device_t);
121 static int lge_detach(device_t);
122
123 static int lge_alloc_jumbo_mem(struct lge_softc *);
124 static void lge_free_jumbo_mem(struct lge_softc *);
125 static void *lge_jalloc(struct lge_softc *);
126 static void lge_jfree(struct mbuf *);
127
128 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *);
129 static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *);
130 static void lge_rxeof(struct lge_softc *, int);
131 static void lge_rxeoc(struct lge_softc *);
132 static void lge_txeof(struct lge_softc *);
133 static void lge_intr(void *);
134 static void lge_tick(void *);
135 static void lge_start(if_t);
136 static void lge_start_locked(if_t);
137 static int lge_ioctl(if_t, u_long, caddr_t);
138 static void lge_init(void *);
139 static void lge_init_locked(struct lge_softc *);
140 static void lge_stop(struct lge_softc *);
141 static void lge_watchdog(struct lge_softc *);
142 static int lge_shutdown(device_t);
143 static int lge_ifmedia_upd(if_t);
144 static void lge_ifmedia_upd_locked(if_t);
145 static void lge_ifmedia_sts(if_t, struct ifmediareq *);
146
147 static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *);
148 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int);
149
150 static int lge_miibus_readreg(device_t, int, int);
151 static int lge_miibus_writereg(device_t, int, int, int);
152 static void lge_miibus_statchg(device_t);
153
154 static void lge_setmulti(struct lge_softc *);
155 static void lge_reset(struct lge_softc *);
156 static int lge_list_rx_init(struct lge_softc *);
157 static int lge_list_tx_init(struct lge_softc *);
158
159 #ifdef LGE_USEIOSPACE
160 #define LGE_RES SYS_RES_IOPORT
161 #define LGE_RID LGE_PCI_LOIO
162 #else
163 #define LGE_RES SYS_RES_MEMORY
164 #define LGE_RID LGE_PCI_LOMEM
165 #endif
166
167 static device_method_t lge_methods[] = {
168 /* Device interface */
169 DEVMETHOD(device_probe, lge_probe),
170 DEVMETHOD(device_attach, lge_attach),
171 DEVMETHOD(device_detach, lge_detach),
172 DEVMETHOD(device_shutdown, lge_shutdown),
173
174 /* MII interface */
175 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
176 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
177 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
178
179 DEVMETHOD_END
180 };
181
182 static driver_t lge_driver = {
183 "lge",
184 lge_methods,
185 sizeof(struct lge_softc)
186 };
187
188 DRIVER_MODULE(lge, pci, lge_driver, 0, 0);
189 DRIVER_MODULE(miibus, lge, miibus_driver, 0, 0);
190 MODULE_DEPEND(lge, pci, 1, 1, 1);
191 MODULE_DEPEND(lge, ether, 1, 1, 1);
192 MODULE_DEPEND(lge, miibus, 1, 1, 1);
193
194 #define LGE_SETBIT(sc, reg, x) \
195 CSR_WRITE_4(sc, reg, \
196 CSR_READ_4(sc, reg) | (x))
197
198 #define LGE_CLRBIT(sc, reg, x) \
199 CSR_WRITE_4(sc, reg, \
200 CSR_READ_4(sc, reg) & ~(x))
201
202 #define SIO_SET(x) \
203 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
204
205 #define SIO_CLR(x) \
206 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
207
208 /*
209 * Read a word of data stored in the EEPROM at address 'addr.'
210 */
211 static void
lge_eeprom_getword(struct lge_softc * sc,int addr,u_int16_t * dest)212 lge_eeprom_getword(struct lge_softc *sc, int addr, u_int16_t *dest)
213 {
214 int i;
215 u_int32_t val;
216
217 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
218 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8));
219
220 for (i = 0; i < LGE_TIMEOUT; i++)
221 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
222 break;
223
224 if (i == LGE_TIMEOUT) {
225 device_printf(sc->lge_dev, "EEPROM read timed out\n");
226 return;
227 }
228
229 val = CSR_READ_4(sc, LGE_EEDATA);
230
231 if (addr & 1)
232 *dest = (val >> 16) & 0xFFFF;
233 else
234 *dest = val & 0xFFFF;
235
236 return;
237 }
238
239 /*
240 * Read a sequence of words from the EEPROM.
241 */
242 static void
lge_read_eeprom(struct lge_softc * sc,caddr_t dest,int off,int cnt,int swap)243 lge_read_eeprom(struct lge_softc *sc, caddr_t dest, int off, int cnt, int swap)
244 {
245 int i;
246 u_int16_t word = 0, *ptr;
247
248 for (i = 0; i < cnt; i++) {
249 lge_eeprom_getword(sc, off + i, &word);
250 ptr = (u_int16_t *)(dest + (i * 2));
251 if (swap)
252 *ptr = ntohs(word);
253 else
254 *ptr = word;
255 }
256
257 return;
258 }
259
260 static int
lge_miibus_readreg(device_t dev,int phy,int reg)261 lge_miibus_readreg(device_t dev, int phy, int reg)
262 {
263 struct lge_softc *sc;
264 int i;
265
266 sc = device_get_softc(dev);
267
268 /*
269 * If we have a non-PCS PHY, pretend that the internal
270 * autoneg stuff at PHY address 0 isn't there so that
271 * the miibus code will find only the GMII PHY.
272 */
273 if (sc->lge_pcs == 0 && phy == 0)
274 return(0);
275
276 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
277
278 for (i = 0; i < LGE_TIMEOUT; i++)
279 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
280 break;
281
282 if (i == LGE_TIMEOUT) {
283 device_printf(sc->lge_dev, "PHY read timed out\n");
284 return(0);
285 }
286
287 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
288 }
289
290 static int
lge_miibus_writereg(device_t dev,int phy,int reg,int data)291 lge_miibus_writereg(device_t dev, int phy, int reg, int data)
292 {
293 struct lge_softc *sc;
294 int i;
295
296 sc = device_get_softc(dev);
297
298 CSR_WRITE_4(sc, LGE_GMIICTL,
299 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
300
301 for (i = 0; i < LGE_TIMEOUT; i++)
302 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
303 break;
304
305 if (i == LGE_TIMEOUT) {
306 device_printf(sc->lge_dev, "PHY write timed out\n");
307 return(0);
308 }
309
310 return(0);
311 }
312
313 static void
lge_miibus_statchg(device_t dev)314 lge_miibus_statchg(device_t dev)
315 {
316 struct lge_softc *sc;
317 struct mii_data *mii;
318
319 sc = device_get_softc(dev);
320 mii = device_get_softc(sc->lge_miibus);
321
322 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
323 switch (IFM_SUBTYPE(mii->mii_media_active)) {
324 case IFM_1000_T:
325 case IFM_1000_SX:
326 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
327 break;
328 case IFM_100_TX:
329 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
330 break;
331 case IFM_10_T:
332 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
333 break;
334 default:
335 /*
336 * Choose something, even if it's wrong. Clearing
337 * all the bits will hose autoneg on the internal
338 * PHY.
339 */
340 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
341 break;
342 }
343
344 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
345 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
346 } else {
347 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
348 }
349
350 return;
351 }
352
353 static u_int
lge_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int count)354 lge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int count)
355 {
356 uint32_t h, *hashes = arg;
357
358 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
359 if (h < 32)
360 hashes[0] |= (1 << h);
361 else
362 hashes[1] |= (1 << (h - 32));
363 return (1);
364 }
365
366 static void
lge_setmulti(struct lge_softc * sc)367 lge_setmulti(struct lge_softc *sc)
368 {
369 if_t ifp;
370 uint32_t hashes[2] = { 0, 0 };
371
372 ifp = sc->lge_ifp;
373 LGE_LOCK_ASSERT(sc);
374
375 /* Make sure multicast hash table is enabled. */
376 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);
377
378 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) {
379 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
380 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
381 return;
382 }
383
384 /* first, zot all the existing hash bits */
385 CSR_WRITE_4(sc, LGE_MAR0, 0);
386 CSR_WRITE_4(sc, LGE_MAR1, 0);
387
388 /* now program new ones */
389 if_foreach_llmaddr(ifp, lge_hash_maddr, hashes);
390
391 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
392 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
393
394 return;
395 }
396
397 static void
lge_reset(struct lge_softc * sc)398 lge_reset(struct lge_softc *sc)
399 {
400 int i;
401
402 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST);
403
404 for (i = 0; i < LGE_TIMEOUT; i++) {
405 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))
406 break;
407 }
408
409 if (i == LGE_TIMEOUT)
410 device_printf(sc->lge_dev, "reset never completed\n");
411
412 /* Wait a little while for the chip to get its brains in order. */
413 DELAY(1000);
414
415 return;
416 }
417
418 /*
419 * Probe for a Level 1 chip. Check the PCI vendor and device
420 * IDs against our list and return a device name if we find a match.
421 */
422 static int
lge_probe(device_t dev)423 lge_probe(device_t dev)
424 {
425 const struct lge_type *t;
426
427 t = lge_devs;
428
429 while(t->lge_name != NULL) {
430 if ((pci_get_vendor(dev) == t->lge_vid) &&
431 (pci_get_device(dev) == t->lge_did)) {
432 device_set_desc(dev, t->lge_name);
433 return(BUS_PROBE_DEFAULT);
434 }
435 t++;
436 }
437
438 return(ENXIO);
439 }
440
441 /*
442 * Attach the interface. Allocate softc structures, do ifmedia
443 * setup and ethernet/BPF attach.
444 */
445 static int
lge_attach(device_t dev)446 lge_attach(device_t dev)
447 {
448 u_char eaddr[ETHER_ADDR_LEN];
449 struct lge_softc *sc;
450 if_t ifp = NULL;
451 int error = 0, rid;
452
453 sc = device_get_softc(dev);
454 sc->lge_dev = dev;
455
456 mtx_init(&sc->lge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
457 MTX_DEF);
458 callout_init_mtx(&sc->lge_stat_callout, &sc->lge_mtx, 0);
459
460 /*
461 * Map control/status registers.
462 */
463 pci_enable_busmaster(dev);
464
465 rid = LGE_RID;
466 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE);
467
468 if (sc->lge_res == NULL) {
469 device_printf(dev, "couldn't map ports/memory\n");
470 error = ENXIO;
471 goto fail;
472 }
473
474 sc->lge_btag = rman_get_bustag(sc->lge_res);
475 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
476
477 /* Allocate interrupt */
478 rid = 0;
479 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
480 RF_SHAREABLE | RF_ACTIVE);
481
482 if (sc->lge_irq == NULL) {
483 device_printf(dev, "couldn't map interrupt\n");
484 error = ENXIO;
485 goto fail;
486 }
487
488 /* Reset the adapter. */
489 lge_reset(sc);
490
491 /*
492 * Get station address from the EEPROM.
493 */
494 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0);
495 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0);
496 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0);
497
498 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
499 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
500
501 if (sc->lge_ldata == NULL) {
502 device_printf(dev, "no memory for list buffers!\n");
503 error = ENXIO;
504 goto fail;
505 }
506
507 /* Try to allocate memory for jumbo buffers. */
508 if (lge_alloc_jumbo_mem(sc)) {
509 device_printf(dev, "jumbo buffer allocation failed\n");
510 error = ENXIO;
511 goto fail;
512 }
513
514 ifp = sc->lge_ifp = if_alloc(IFT_ETHER);
515 if (ifp == NULL) {
516 device_printf(dev, "can not if_alloc()\n");
517 error = ENOSPC;
518 goto fail;
519 }
520 if_setsoftc(ifp, sc);
521 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
522 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
523 if_setioctlfn(ifp, lge_ioctl);
524 if_setstartfn(ifp, lge_start);
525 if_setinitfn(ifp, lge_init);
526 if_setsendqlen(ifp, LGE_TX_LIST_CNT - 1);
527 if_setcapabilities(ifp, IFCAP_RXCSUM);
528 if_setcapenable(ifp, if_getcapabilities(ifp));
529
530 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
531 sc->lge_pcs = 1;
532 else
533 sc->lge_pcs = 0;
534
535 /*
536 * Do MII setup.
537 */
538 error = mii_attach(dev, &sc->lge_miibus, ifp, lge_ifmedia_upd,
539 lge_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
540 if (error != 0) {
541 device_printf(dev, "attaching PHYs failed\n");
542 goto fail;
543 }
544
545 /*
546 * Call MI attach routine.
547 */
548 ether_ifattach(ifp, eaddr);
549
550 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET | INTR_MPSAFE,
551 NULL, lge_intr, sc, &sc->lge_intrhand);
552
553 if (error) {
554 ether_ifdetach(ifp);
555 device_printf(dev, "couldn't set up irq\n");
556 goto fail;
557 }
558 return (0);
559
560 fail:
561 lge_free_jumbo_mem(sc);
562 if (sc->lge_ldata)
563 contigfree(sc->lge_ldata,
564 sizeof(struct lge_list_data), M_DEVBUF);
565 if (ifp)
566 if_free(ifp);
567 if (sc->lge_irq)
568 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
569 if (sc->lge_res)
570 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
571 mtx_destroy(&sc->lge_mtx);
572 return(error);
573 }
574
575 static int
lge_detach(device_t dev)576 lge_detach(device_t dev)
577 {
578 struct lge_softc *sc;
579 if_t ifp;
580
581 sc = device_get_softc(dev);
582 ifp = sc->lge_ifp;
583
584 LGE_LOCK(sc);
585 lge_reset(sc);
586 lge_stop(sc);
587 LGE_UNLOCK(sc);
588 callout_drain(&sc->lge_stat_callout);
589 ether_ifdetach(ifp);
590
591 bus_generic_detach(dev);
592 device_delete_child(dev, sc->lge_miibus);
593
594 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
595 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
596 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
597
598 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF);
599 if_free(ifp);
600 lge_free_jumbo_mem(sc);
601 mtx_destroy(&sc->lge_mtx);
602
603 return(0);
604 }
605
606 /*
607 * Initialize the transmit descriptors.
608 */
609 static int
lge_list_tx_init(struct lge_softc * sc)610 lge_list_tx_init(struct lge_softc *sc)
611 {
612 struct lge_list_data *ld;
613 struct lge_ring_data *cd;
614 int i;
615
616 cd = &sc->lge_cdata;
617 ld = sc->lge_ldata;
618 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
619 ld->lge_tx_list[i].lge_mbuf = NULL;
620 ld->lge_tx_list[i].lge_ctl = 0;
621 }
622
623 cd->lge_tx_prod = cd->lge_tx_cons = 0;
624
625 return(0);
626 }
627
628
629 /*
630 * Initialize the RX descriptors and allocate mbufs for them. Note that
631 * we arralge the descriptors in a closed ring, so that the last descriptor
632 * points back to the first.
633 */
634 static int
lge_list_rx_init(struct lge_softc * sc)635 lge_list_rx_init(struct lge_softc *sc)
636 {
637 struct lge_list_data *ld;
638 struct lge_ring_data *cd;
639 int i;
640
641 ld = sc->lge_ldata;
642 cd = &sc->lge_cdata;
643
644 cd->lge_rx_prod = cd->lge_rx_cons = 0;
645
646 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
647
648 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
649 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
650 break;
651 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
652 return(ENOBUFS);
653 }
654
655 /* Clear possible 'rx command queue empty' interrupt. */
656 CSR_READ_4(sc, LGE_ISR);
657
658 return(0);
659 }
660
661 /*
662 * Initialize an RX descriptor and attach an MBUF cluster.
663 */
664 static int
lge_newbuf(struct lge_softc * sc,struct lge_rx_desc * c,struct mbuf * m)665 lge_newbuf(struct lge_softc *sc, struct lge_rx_desc *c, struct mbuf *m)
666 {
667 struct mbuf *m_new = NULL;
668 char *buf = NULL;
669
670 if (m == NULL) {
671 MGETHDR(m_new, M_NOWAIT, MT_DATA);
672 if (m_new == NULL) {
673 device_printf(sc->lge_dev, "no memory for rx list "
674 "-- packet dropped!\n");
675 return(ENOBUFS);
676 }
677
678 /* Allocate the jumbo buffer */
679 buf = lge_jalloc(sc);
680 if (buf == NULL) {
681 #ifdef LGE_VERBOSE
682 device_printf(sc->lge_dev, "jumbo allocation failed "
683 "-- packet dropped!\n");
684 #endif
685 m_freem(m_new);
686 return(ENOBUFS);
687 }
688 /* Attach the buffer to the mbuf */
689 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
690 m_extadd(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, sc, NULL,
691 0, EXT_NET_DRV);
692 } else {
693 m_new = m;
694 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN;
695 m_new->m_data = m_new->m_ext.ext_buf;
696 }
697
698 /*
699 * Adjust alignment so packet payload begins on a
700 * longword boundary. Mandatory for Alpha, useful on
701 * x86 too.
702 */
703 m_adj(m_new, ETHER_ALIGN);
704
705 c->lge_mbuf = m_new;
706 c->lge_fragptr_hi = 0;
707 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
708 c->lge_fraglen = m_new->m_len;
709 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
710 c->lge_sts = 0;
711
712 /*
713 * Put this buffer in the RX command FIFO. To do this,
714 * we just write the physical address of the descriptor
715 * into the RX descriptor address registers. Note that
716 * there are two registers, one high DWORD and one low
717 * DWORD, which lets us specify a 64-bit address if
718 * desired. We only use a 32-bit address for now.
719 * Writing to the low DWORD register is what actually
720 * causes the command to be issued, so we do that
721 * last.
722 */
723 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
724 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
725
726 return(0);
727 }
728
729 static int
lge_alloc_jumbo_mem(struct lge_softc * sc)730 lge_alloc_jumbo_mem(struct lge_softc *sc)
731 {
732 caddr_t ptr;
733 int i;
734 struct lge_jpool_entry *entry;
735
736 /* Grab a big chunk o' storage. */
737 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
738 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
739
740 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
741 device_printf(sc->lge_dev, "no memory for jumbo buffers!\n");
742 return(ENOBUFS);
743 }
744
745 SLIST_INIT(&sc->lge_jfree_listhead);
746 SLIST_INIT(&sc->lge_jinuse_listhead);
747
748 /*
749 * Now divide it up into 9K pieces and save the addresses
750 * in an array.
751 */
752 ptr = sc->lge_cdata.lge_jumbo_buf;
753 for (i = 0; i < LGE_JSLOTS; i++) {
754 sc->lge_cdata.lge_jslots[i] = ptr;
755 ptr += LGE_JLEN;
756 entry = malloc(sizeof(struct lge_jpool_entry),
757 M_DEVBUF, M_NOWAIT);
758 if (entry == NULL) {
759 device_printf(sc->lge_dev, "no memory for jumbo "
760 "buffer queue!\n");
761 return(ENOBUFS);
762 }
763 entry->slot = i;
764 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
765 entry, jpool_entries);
766 }
767
768 return(0);
769 }
770
771 static void
lge_free_jumbo_mem(struct lge_softc * sc)772 lge_free_jumbo_mem(struct lge_softc *sc)
773 {
774 struct lge_jpool_entry *entry;
775
776 if (sc->lge_cdata.lge_jumbo_buf == NULL)
777 return;
778
779 while ((entry = SLIST_FIRST(&sc->lge_jinuse_listhead))) {
780 device_printf(sc->lge_dev,
781 "asked to free buffer that is in use!\n");
782 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries);
783 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry,
784 jpool_entries);
785 }
786 while (!SLIST_EMPTY(&sc->lge_jfree_listhead)) {
787 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
788 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
789 free(entry, M_DEVBUF);
790 }
791
792 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
793
794 return;
795 }
796
797 /*
798 * Allocate a jumbo buffer.
799 */
800 static void *
lge_jalloc(struct lge_softc * sc)801 lge_jalloc(struct lge_softc *sc)
802 {
803 struct lge_jpool_entry *entry;
804
805 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
806
807 if (entry == NULL) {
808 #ifdef LGE_VERBOSE
809 device_printf(sc->lge_dev, "no free jumbo buffers\n");
810 #endif
811 return(NULL);
812 }
813
814 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
815 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries);
816 return(sc->lge_cdata.lge_jslots[entry->slot]);
817 }
818
819 /*
820 * Release a jumbo buffer.
821 */
822 static void
lge_jfree(struct mbuf * m)823 lge_jfree(struct mbuf *m)
824 {
825 struct lge_softc *sc;
826 int i;
827 struct lge_jpool_entry *entry;
828
829 /* Extract the softc struct pointer. */
830 sc = m->m_ext.ext_arg1;
831
832 if (sc == NULL)
833 panic("lge_jfree: can't find softc pointer!");
834
835 /* calculate the slot this buffer belongs to */
836 i = ((vm_offset_t)m->m_ext.ext_buf
837 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
838
839 if ((i < 0) || (i >= LGE_JSLOTS))
840 panic("lge_jfree: asked to free buffer that we don't manage!");
841
842 entry = SLIST_FIRST(&sc->lge_jinuse_listhead);
843 if (entry == NULL)
844 panic("lge_jfree: buffer not in use!");
845 entry->slot = i;
846 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries);
847 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries);
848 }
849
850 /*
851 * A frame has been uploaded: pass the resulting mbuf chain up to
852 * the higher level protocols.
853 */
854 static void
lge_rxeof(struct lge_softc * sc,int cnt)855 lge_rxeof(struct lge_softc *sc, int cnt)
856 {
857 struct mbuf *m;
858 if_t ifp;
859 struct lge_rx_desc *cur_rx;
860 int c, i, total_len = 0;
861 u_int32_t rxsts, rxctl;
862
863 ifp = sc->lge_ifp;
864
865 /* Find out how many frames were processed. */
866 c = cnt;
867 i = sc->lge_cdata.lge_rx_cons;
868
869 /* Suck them in. */
870 while(c) {
871 struct mbuf *m0 = NULL;
872
873 cur_rx = &sc->lge_ldata->lge_rx_list[i];
874 rxctl = cur_rx->lge_ctl;
875 rxsts = cur_rx->lge_sts;
876 m = cur_rx->lge_mbuf;
877 cur_rx->lge_mbuf = NULL;
878 total_len = LGE_RXBYTES(cur_rx);
879 LGE_INC(i, LGE_RX_LIST_CNT);
880 c--;
881
882 /*
883 * If an error occurs, update stats, clear the
884 * status word and leave the mbuf cluster in place:
885 * it should simply get re-used next time this descriptor
886 * comes up in the ring.
887 */
888 if (rxctl & LGE_RXCTL_ERRMASK) {
889 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
890 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
891 continue;
892 }
893
894 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
895 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN,
896 ifp, NULL);
897 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
898 if (m0 == NULL) {
899 device_printf(sc->lge_dev, "no receive buffers "
900 "available -- packet dropped!\n");
901 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
902 continue;
903 }
904 m = m0;
905 } else {
906 m->m_pkthdr.rcvif = ifp;
907 m->m_pkthdr.len = m->m_len = total_len;
908 }
909
910 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
911
912 /* Do IP checksum checking. */
913 if (rxsts & LGE_RXSTS_ISIP)
914 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
915 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
916 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
917 if ((rxsts & LGE_RXSTS_ISTCP &&
918 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
919 (rxsts & LGE_RXSTS_ISUDP &&
920 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
921 m->m_pkthdr.csum_flags |=
922 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
923 m->m_pkthdr.csum_data = 0xffff;
924 }
925
926 LGE_UNLOCK(sc);
927 if_input(ifp, m);
928 LGE_LOCK(sc);
929 }
930
931 sc->lge_cdata.lge_rx_cons = i;
932
933 return;
934 }
935
936 static void
lge_rxeoc(struct lge_softc * sc)937 lge_rxeoc(struct lge_softc *sc)
938 {
939 if_t ifp;
940
941 ifp = sc->lge_ifp;
942 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
943 lge_init_locked(sc);
944 return;
945 }
946
947 /*
948 * A frame was downloaded to the chip. It's safe for us to clean up
949 * the list buffers.
950 */
951
952 static void
lge_txeof(struct lge_softc * sc)953 lge_txeof(struct lge_softc *sc)
954 {
955 struct lge_tx_desc *cur_tx = NULL;
956 if_t ifp;
957 u_int32_t idx, txdone;
958
959 ifp = sc->lge_ifp;
960
961 /* Clear the timeout timer. */
962 sc->lge_timer = 0;
963
964 /*
965 * Go through our tx list and free mbufs for those
966 * frames that have been transmitted.
967 */
968 idx = sc->lge_cdata.lge_tx_cons;
969 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
970
971 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
972 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
973
974 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
975 if (cur_tx->lge_mbuf != NULL) {
976 m_freem(cur_tx->lge_mbuf);
977 cur_tx->lge_mbuf = NULL;
978 }
979 cur_tx->lge_ctl = 0;
980
981 txdone--;
982 LGE_INC(idx, LGE_TX_LIST_CNT);
983 sc->lge_timer = 0;
984 }
985
986 sc->lge_cdata.lge_tx_cons = idx;
987
988 if (cur_tx != NULL)
989 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
990
991 return;
992 }
993
994 static void
lge_tick(void * xsc)995 lge_tick(void *xsc)
996 {
997 struct lge_softc *sc;
998 struct mii_data *mii;
999 if_t ifp;
1000
1001 sc = xsc;
1002 ifp = sc->lge_ifp;
1003 LGE_LOCK_ASSERT(sc);
1004
1005 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
1006 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL));
1007 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1008 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, CSR_READ_4(sc, LGE_STATSVAL));
1009
1010 if (!sc->lge_link) {
1011 mii = device_get_softc(sc->lge_miibus);
1012 mii_tick(mii);
1013 if (mii->mii_media_status & IFM_ACTIVE &&
1014 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1015 sc->lge_link++;
1016 if (bootverbose &&
1017 (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
1018 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T))
1019 device_printf(sc->lge_dev, "gigabit link up\n");
1020 if (!if_sendq_empty(ifp))
1021 lge_start_locked(ifp);
1022 }
1023 }
1024
1025 if (sc->lge_timer != 0 && --sc->lge_timer == 0)
1026 lge_watchdog(sc);
1027 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc);
1028
1029 return;
1030 }
1031
1032 static void
lge_intr(void * arg)1033 lge_intr(void *arg)
1034 {
1035 struct lge_softc *sc;
1036 if_t ifp;
1037 u_int32_t status;
1038
1039 sc = arg;
1040 ifp = sc->lge_ifp;
1041 LGE_LOCK(sc);
1042
1043 /* Suppress unwanted interrupts */
1044 if (!(if_getflags(ifp) & IFF_UP)) {
1045 lge_stop(sc);
1046 LGE_UNLOCK(sc);
1047 return;
1048 }
1049
1050 for (;;) {
1051 /*
1052 * Reading the ISR register clears all interrupts, and
1053 * clears the 'interrupts enabled' bit in the IMR
1054 * register.
1055 */
1056 status = CSR_READ_4(sc, LGE_ISR);
1057
1058 if ((status & LGE_INTRS) == 0)
1059 break;
1060
1061 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1062 lge_txeof(sc);
1063
1064 if (status & LGE_ISR_RXDMA_DONE)
1065 lge_rxeof(sc, LGE_RX_DMACNT(status));
1066
1067 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1068 lge_rxeoc(sc);
1069
1070 if (status & LGE_ISR_PHY_INTR) {
1071 sc->lge_link = 0;
1072 callout_stop(&sc->lge_stat_callout);
1073 lge_tick(sc);
1074 }
1075 }
1076
1077 /* Re-enable interrupts. */
1078 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1079
1080 if (!if_sendq_empty(ifp))
1081 lge_start_locked(ifp);
1082
1083 LGE_UNLOCK(sc);
1084 return;
1085 }
1086
1087 /*
1088 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1089 * pointers to the fragment pointers.
1090 */
1091 static int
lge_encap(struct lge_softc * sc,struct mbuf * m_head,u_int32_t * txidx)1092 lge_encap(struct lge_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
1093 {
1094 struct lge_frag *f = NULL;
1095 struct lge_tx_desc *cur_tx;
1096 struct mbuf *m;
1097 int frag = 0, tot_len = 0;
1098
1099 /*
1100 * Start packing the mbufs in this chain into
1101 * the fragment pointers. Stop when we run out
1102 * of fragments or hit the end of the mbuf chain.
1103 */
1104 m = m_head;
1105 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1106 frag = 0;
1107
1108 for (m = m_head; m != NULL; m = m->m_next) {
1109 if (m->m_len != 0) {
1110 tot_len += m->m_len;
1111 f = &cur_tx->lge_frags[frag];
1112 f->lge_fraglen = m->m_len;
1113 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1114 f->lge_fragptr_hi = 0;
1115 frag++;
1116 }
1117 }
1118
1119 if (m != NULL)
1120 return(ENOBUFS);
1121
1122 cur_tx->lge_mbuf = m_head;
1123 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1124 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1125
1126 /* Queue for transmit */
1127 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1128
1129 return(0);
1130 }
1131
1132 /*
1133 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1134 * to the mbuf data regions directly in the transmit lists. We also save a
1135 * copy of the pointers since the transmit list fragment pointers are
1136 * physical addresses.
1137 */
1138
1139 static void
lge_start(if_t ifp)1140 lge_start(if_t ifp)
1141 {
1142 struct lge_softc *sc;
1143
1144 sc = if_getsoftc(ifp);
1145 LGE_LOCK(sc);
1146 lge_start_locked(ifp);
1147 LGE_UNLOCK(sc);
1148 }
1149
1150 static void
lge_start_locked(if_t ifp)1151 lge_start_locked(if_t ifp)
1152 {
1153 struct lge_softc *sc;
1154 struct mbuf *m_head = NULL;
1155 u_int32_t idx;
1156
1157 sc = if_getsoftc(ifp);
1158
1159 if (!sc->lge_link)
1160 return;
1161
1162 idx = sc->lge_cdata.lge_tx_prod;
1163
1164 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE)
1165 return;
1166
1167 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1168 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
1169 break;
1170
1171 m_head = if_dequeue(ifp);
1172 if (m_head == NULL)
1173 break;
1174
1175 if (lge_encap(sc, m_head, &idx)) {
1176 if_sendq_prepend(ifp, m_head);
1177 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1178 break;
1179 }
1180
1181 /*
1182 * If there's a BPF listener, bounce a copy of this frame
1183 * to him.
1184 */
1185 BPF_MTAP(ifp, m_head);
1186 }
1187
1188 sc->lge_cdata.lge_tx_prod = idx;
1189
1190 /*
1191 * Set a timeout in case the chip goes out to lunch.
1192 */
1193 sc->lge_timer = 5;
1194
1195 return;
1196 }
1197
1198 static void
lge_init(void * xsc)1199 lge_init(void *xsc)
1200 {
1201 struct lge_softc *sc = xsc;
1202
1203 LGE_LOCK(sc);
1204 lge_init_locked(sc);
1205 LGE_UNLOCK(sc);
1206 }
1207
1208 static void
lge_init_locked(struct lge_softc * sc)1209 lge_init_locked(struct lge_softc *sc)
1210 {
1211 if_t ifp = sc->lge_ifp;
1212
1213 LGE_LOCK_ASSERT(sc);
1214 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1215 return;
1216
1217 /*
1218 * Cancel pending I/O and free all RX/TX buffers.
1219 */
1220 lge_stop(sc);
1221 lge_reset(sc);
1222
1223 /* Set MAC address */
1224 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&if_getlladdr(sc->lge_ifp)[0]));
1225 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&if_getlladdr(sc->lge_ifp)[4]));
1226
1227 /* Init circular RX list. */
1228 if (lge_list_rx_init(sc) == ENOBUFS) {
1229 device_printf(sc->lge_dev, "initialization failed: no "
1230 "memory for rx buffers\n");
1231 lge_stop(sc);
1232 return;
1233 }
1234
1235 /*
1236 * Init tx descriptors.
1237 */
1238 lge_list_tx_init(sc);
1239
1240 /* Set initial value for MODE1 register. */
1241 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST|
1242 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD|
1243 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0|
1244 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2);
1245
1246 /* If we want promiscuous mode, set the allframes bit. */
1247 if (if_getflags(ifp) & IFF_PROMISC) {
1248 CSR_WRITE_4(sc, LGE_MODE1,
1249 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC);
1250 } else {
1251 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1252 }
1253
1254 /*
1255 * Set the capture broadcast bit to capture broadcast frames.
1256 */
1257 if (if_getflags(ifp) & IFF_BROADCAST) {
1258 CSR_WRITE_4(sc, LGE_MODE1,
1259 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST);
1260 } else {
1261 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1262 }
1263
1264 /* Packet padding workaround? */
1265 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1266
1267 /* No error frames */
1268 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1269
1270 /* Receive large frames */
1271 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS);
1272
1273 /* Workaround: disable RX/TX flow control */
1274 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1275 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1276
1277 /* Make sure to strip CRC from received frames */
1278 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1279
1280 /* Turn off magic packet mode */
1281 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1282
1283 /* Turn off all VLAN stuff */
1284 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
1285 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT);
1286
1287 /* Workarond: FIFO overflow */
1288 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1289 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1290
1291 /*
1292 * Load the multicast filter.
1293 */
1294 lge_setmulti(sc);
1295
1296 /*
1297 * Enable hardware checksum validation for all received IPv4
1298 * packets, do not reject packets with bad checksums.
1299 */
1300 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM|
1301 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM|
1302 LGE_MODE2_RX_ERRCSUM);
1303
1304 /*
1305 * Enable the delivery of PHY interrupts based on
1306 * link/speed/duplex status chalges.
1307 */
1308 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL);
1309
1310 /* Enable receiver and transmitter. */
1311 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1312 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB);
1313
1314 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1315 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB);
1316
1317 /*
1318 * Enable interrupts.
1319 */
1320 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|
1321 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS);
1322
1323 lge_ifmedia_upd_locked(ifp);
1324
1325 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
1326 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1327
1328 callout_reset(&sc->lge_stat_callout, hz, lge_tick, sc);
1329
1330 return;
1331 }
1332
1333 /*
1334 * Set media options.
1335 */
1336 static int
lge_ifmedia_upd(if_t ifp)1337 lge_ifmedia_upd(if_t ifp)
1338 {
1339 struct lge_softc *sc;
1340
1341 sc = if_getsoftc(ifp);
1342 LGE_LOCK(sc);
1343 lge_ifmedia_upd_locked(ifp);
1344 LGE_UNLOCK(sc);
1345
1346 return(0);
1347 }
1348
1349 static void
lge_ifmedia_upd_locked(if_t ifp)1350 lge_ifmedia_upd_locked(if_t ifp)
1351 {
1352 struct lge_softc *sc;
1353 struct mii_data *mii;
1354 struct mii_softc *miisc;
1355
1356 sc = if_getsoftc(ifp);
1357
1358 LGE_LOCK_ASSERT(sc);
1359 mii = device_get_softc(sc->lge_miibus);
1360 sc->lge_link = 0;
1361 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1362 PHY_RESET(miisc);
1363 mii_mediachg(mii);
1364 }
1365
1366 /*
1367 * Report current media status.
1368 */
1369 static void
lge_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)1370 lge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1371 {
1372 struct lge_softc *sc;
1373 struct mii_data *mii;
1374
1375 sc = if_getsoftc(ifp);
1376
1377 LGE_LOCK(sc);
1378 mii = device_get_softc(sc->lge_miibus);
1379 mii_pollstat(mii);
1380 ifmr->ifm_active = mii->mii_media_active;
1381 ifmr->ifm_status = mii->mii_media_status;
1382 LGE_UNLOCK(sc);
1383
1384 return;
1385 }
1386
1387 static int
lge_ioctl(if_t ifp,u_long command,caddr_t data)1388 lge_ioctl(if_t ifp, u_long command, caddr_t data)
1389 {
1390 struct lge_softc *sc = if_getsoftc(ifp);
1391 struct ifreq *ifr = (struct ifreq *) data;
1392 struct mii_data *mii;
1393 int error = 0;
1394
1395 switch(command) {
1396 case SIOCSIFMTU:
1397 LGE_LOCK(sc);
1398 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1399 error = EINVAL;
1400 else
1401 if_setmtu(ifp, ifr->ifr_mtu);
1402 LGE_UNLOCK(sc);
1403 break;
1404 case SIOCSIFFLAGS:
1405 LGE_LOCK(sc);
1406 if (if_getflags(ifp) & IFF_UP) {
1407 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
1408 if_getflags(ifp) & IFF_PROMISC &&
1409 !(sc->lge_if_flags & IFF_PROMISC)) {
1410 CSR_WRITE_4(sc, LGE_MODE1,
1411 LGE_MODE1_SETRST_CTL1|
1412 LGE_MODE1_RX_PROMISC);
1413 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
1414 !(if_getflags(ifp) & IFF_PROMISC) &&
1415 sc->lge_if_flags & IFF_PROMISC) {
1416 CSR_WRITE_4(sc, LGE_MODE1,
1417 LGE_MODE1_RX_PROMISC);
1418 } else {
1419 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1420 lge_init_locked(sc);
1421 }
1422 } else {
1423 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1424 lge_stop(sc);
1425 }
1426 sc->lge_if_flags = if_getflags(ifp);
1427 LGE_UNLOCK(sc);
1428 error = 0;
1429 break;
1430 case SIOCADDMULTI:
1431 case SIOCDELMULTI:
1432 LGE_LOCK(sc);
1433 lge_setmulti(sc);
1434 LGE_UNLOCK(sc);
1435 error = 0;
1436 break;
1437 case SIOCGIFMEDIA:
1438 case SIOCSIFMEDIA:
1439 mii = device_get_softc(sc->lge_miibus);
1440 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1441 break;
1442 default:
1443 error = ether_ioctl(ifp, command, data);
1444 break;
1445 }
1446
1447 return(error);
1448 }
1449
1450 static void
lge_watchdog(struct lge_softc * sc)1451 lge_watchdog(struct lge_softc *sc)
1452 {
1453 if_t ifp;
1454
1455 LGE_LOCK_ASSERT(sc);
1456 ifp = sc->lge_ifp;
1457
1458 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1459 if_printf(ifp, "watchdog timeout\n");
1460
1461 lge_stop(sc);
1462 lge_reset(sc);
1463 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1464 lge_init_locked(sc);
1465
1466 if (!if_sendq_empty(ifp))
1467 lge_start_locked(ifp);
1468 }
1469
1470 /*
1471 * Stop the adapter and free any mbufs allocated to the
1472 * RX and TX lists.
1473 */
1474 static void
lge_stop(struct lge_softc * sc)1475 lge_stop(struct lge_softc *sc)
1476 {
1477 int i;
1478 if_t ifp;
1479
1480 LGE_LOCK_ASSERT(sc);
1481 ifp = sc->lge_ifp;
1482 sc->lge_timer = 0;
1483 callout_stop(&sc->lge_stat_callout);
1484 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1485
1486 /* Disable receiver and transmitter. */
1487 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1488 sc->lge_link = 0;
1489
1490 /*
1491 * Free data in the RX lists.
1492 */
1493 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1494 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1495 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1496 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1497 }
1498 }
1499 bzero((char *)&sc->lge_ldata->lge_rx_list,
1500 sizeof(sc->lge_ldata->lge_rx_list));
1501
1502 /*
1503 * Free the TX list buffers.
1504 */
1505 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1506 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1507 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1508 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1509 }
1510 }
1511
1512 bzero((char *)&sc->lge_ldata->lge_tx_list,
1513 sizeof(sc->lge_ldata->lge_tx_list));
1514
1515 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
1516
1517 return;
1518 }
1519
1520 /*
1521 * Stop all chip I/O so that the kernel's probe routines don't
1522 * get confused by errant DMAs when rebooting.
1523 */
1524 static int
lge_shutdown(device_t dev)1525 lge_shutdown(device_t dev)
1526 {
1527 struct lge_softc *sc;
1528
1529 sc = device_get_softc(dev);
1530
1531 LGE_LOCK(sc);
1532 lge_reset(sc);
1533 lge_stop(sc);
1534 LGE_UNLOCK(sc);
1535
1536 return (0);
1537 }
1538