xref: /dragonfly/sys/dev/netif/txp/if_txp.c (revision 05d02a38)
1 /*	$OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $	*/
2 /*	$FreeBSD: src/sys/dev/txp/if_txp.c,v 1.4.2.4 2001/12/14 19:50:43 jlemon Exp $ */
3 
4 /*
5  * Copyright (c) 2001
6  *	Jason L. Wright <jason@thought.net>, Theo de Raadt, and
7  *	Aaron Campbell <aaron@monkey.org>.  All rights reserved.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. All advertising materials mentioning features or use of this software
18  *    must display the following acknowledgement:
19  *	This product includes software developed by Jason L. Wright,
20  *	Theo de Raadt and Aaron Campbell.
21  * 4. Neither the name of the author nor the names of any co-contributors
22  *    may be used to endorse or promote products derived from this software
23  *    without specific prior written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
26  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
35  * THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 /*
39  * Driver for 3c990 (Typhoon) Ethernet ASIC
40  */
41 
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/sockio.h>
45 #include <sys/mbuf.h>
46 #include <sys/malloc.h>
47 #include <sys/kernel.h>
48 #include <sys/socket.h>
49 #include <sys/serialize.h>
50 #include <sys/bus.h>
51 #include <sys/rman.h>
52 #include <sys/interrupt.h>
53 
54 #include <net/if.h>
55 #include <net/ifq_var.h>
56 #include <net/if_arp.h>
57 #include <net/ethernet.h>
58 #include <net/if_dl.h>
59 #include <net/if_types.h>
60 #include <net/vlan/if_vlan_var.h>
61 #include <net/vlan/if_vlan_ether.h>
62 
63 #include <netinet/in.h>
64 #include <netinet/in_systm.h>
65 #include <netinet/in_var.h>
66 #include <netinet/ip.h>
67 #include <netinet/if_ether.h>
68 #include <sys/in_cksum.h>
69 
70 #include <net/if_media.h>
71 
72 #include <net/bpf.h>
73 
74 #include <vm/vm.h>              /* for vtophys */
75 #include <vm/pmap.h>            /* for vtophys */
76 
77 #include "../mii_layer/mii.h"
78 #include "../mii_layer/miivar.h"
79 
80 #include "pcidevs.h"
81 #include <bus/pci/pcireg.h>
82 #include <bus/pci/pcivar.h>
83 
84 #define TXP_USEIOSPACE
85 #define __STRICT_ALIGNMENT
86 
87 #include "if_txpreg.h"
88 #include "3c990img.h"
89 
90 /*
91  * Various supported device vendors/types and their names.
92  */
93 static struct txp_type txp_devs[] = {
94 	{ PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX95,
95 	    "3Com 3cR990-TX-95 Etherlink with 3XP Processor" },
96 	{ PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990TX97,
97 	    "3Com 3cR990-TX-97 Etherlink with 3XP Processor" },
98 	{ PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990B,
99 	    "3Com 3cR990B-TXM Etherlink with 3XP Processor" },
100 	{ PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR95,
101 	    "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" },
102 	{ PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CR990SVR97,
103 	    "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" },
104 	{ PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C990BSVR,
105 	    "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" },
106 	{ 0, 0, NULL }
107 };
108 
109 static int txp_probe	(device_t);
110 static int txp_attach	(device_t);
111 static int txp_detach	(device_t);
112 static void txp_intr	(void *);
113 static void txp_tick	(void *);
114 static int txp_shutdown	(device_t);
115 static int txp_ioctl	(struct ifnet *, u_long, caddr_t, struct ucred *);
116 static void txp_start	(struct ifnet *, struct ifaltq_subque *);
117 static void txp_stop	(struct txp_softc *);
118 static void txp_init	(void *);
119 static void txp_watchdog	(struct ifnet *);
120 
121 static void txp_release_resources (device_t);
122 static int txp_chip_init (struct txp_softc *);
123 static int txp_reset_adapter (struct txp_softc *);
124 static int txp_download_fw (struct txp_softc *);
125 static int txp_download_fw_wait (struct txp_softc *);
126 static int txp_download_fw_section (struct txp_softc *,
127     struct txp_fw_section_header *, int);
128 static int txp_alloc_rings (struct txp_softc *);
129 static int txp_rxring_fill (struct txp_softc *);
130 static void txp_rxring_empty (struct txp_softc *);
131 static void txp_set_filter (struct txp_softc *);
132 
133 static int txp_cmd_desc_numfree (struct txp_softc *);
134 static int txp_command (struct txp_softc *, u_int16_t, u_int16_t, u_int32_t,
135     u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int);
136 static int txp_command2 (struct txp_softc *, u_int16_t, u_int16_t,
137     u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t,
138     struct txp_rsp_desc **, int);
139 static int txp_response (struct txp_softc *, u_int32_t, u_int16_t, u_int16_t,
140     struct txp_rsp_desc **);
141 static void txp_rsp_fixup (struct txp_softc *, struct txp_rsp_desc *,
142     struct txp_rsp_desc *);
143 static void txp_capabilities (struct txp_softc *);
144 
145 static void txp_ifmedia_sts (struct ifnet *, struct ifmediareq *);
146 static int txp_ifmedia_upd (struct ifnet *);
147 #ifdef TXP_DEBUG
148 static void txp_show_descriptor (void *);
149 #endif
150 static void txp_tx_reclaim (struct txp_softc *, struct txp_tx_ring *);
151 static void txp_rxbuf_reclaim (struct txp_softc *);
152 static void txp_rx_reclaim (struct txp_softc *, struct txp_rx_ring *);
153 
154 #ifdef TXP_USEIOSPACE
155 #define TXP_RES			SYS_RES_IOPORT
156 #define TXP_RID			TXP_PCI_LOIO
157 #else
158 #define TXP_RES			SYS_RES_MEMORY
159 #define TXP_RID			TXP_PCI_LOMEM
160 #endif
161 
162 static device_method_t txp_methods[] = {
163         /* Device interface */
164 	DEVMETHOD(device_probe,		txp_probe),
165 	DEVMETHOD(device_attach,	txp_attach),
166 	DEVMETHOD(device_detach,	txp_detach),
167 	DEVMETHOD(device_shutdown,	txp_shutdown),
168 	DEVMETHOD_END
169 };
170 
171 static driver_t txp_driver = {
172 	"txp",
173 	txp_methods,
174 	sizeof(struct txp_softc)
175 };
176 
177 static devclass_t txp_devclass;
178 
179 DECLARE_DUMMY_MODULE(if_txp);
180 DRIVER_MODULE(if_txp, pci, txp_driver, txp_devclass, NULL, NULL);
181 
182 static int
txp_probe(device_t dev)183 txp_probe(device_t dev)
184 {
185 	struct txp_type *t;
186 	uint16_t vid, did;
187 
188 	vid = pci_get_vendor(dev);
189 	did = pci_get_device(dev);
190 
191 	for (t = txp_devs; t->txp_name != NULL; ++t) {
192 		if ((vid == t->txp_vid) && (did == t->txp_did)) {
193 			device_set_desc(dev, t->txp_name);
194 			return(0);
195 		}
196 	}
197 
198 	return(ENXIO);
199 }
200 
201 static int
txp_attach(device_t dev)202 txp_attach(device_t dev)
203 {
204 	struct txp_softc *sc;
205 	struct ifnet *ifp;
206 	uint16_t p1;
207 	uint32_t p2;
208 	uint8_t enaddr[ETHER_ADDR_LEN];
209 	int error = 0, rid;
210 
211 	sc = device_get_softc(dev);
212 	callout_init(&sc->txp_stat_timer);
213 
214 	ifp = &sc->sc_arpcom.ac_if;
215 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
216 
217 	pci_enable_busmaster(dev);
218 
219 	rid = TXP_RID;
220 	sc->sc_res = bus_alloc_resource_any(dev, TXP_RES, &rid, RF_ACTIVE);
221 
222 	if (sc->sc_res == NULL) {
223 		device_printf(dev, "couldn't map ports/memory\n");
224 		return(ENXIO);
225 	}
226 
227 	sc->sc_bt = rman_get_bustag(sc->sc_res);
228 	sc->sc_bh = rman_get_bushandle(sc->sc_res);
229 
230 	/* Allocate interrupt */
231 	rid = 0;
232 	sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
233 	    RF_SHAREABLE | RF_ACTIVE);
234 
235 	if (sc->sc_irq == NULL) {
236 		device_printf(dev, "couldn't map interrupt\n");
237 		error = ENXIO;
238 		goto fail;
239 	}
240 
241 	if (txp_chip_init(sc)) {
242 		error = ENXIO;
243 		goto fail;
244 	}
245 
246 	sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF,
247 	    M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
248 	error = txp_download_fw(sc);
249 	contigfree(sc->sc_fwbuf, 32768, M_DEVBUF);
250 	sc->sc_fwbuf = NULL;
251 
252 	if (error)
253 		goto fail;
254 
255 	sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF,
256 	    M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
257 
258 	if (txp_alloc_rings(sc)) {
259 		error = ENXIO;
260 		goto fail;
261 	}
262 
263 	if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0,
264 	    NULL, NULL, NULL, 1)) {
265 		error = ENXIO;
266 		goto fail;
267 	}
268 
269 	if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0,
270 	    &p1, &p2, NULL, 1)) {
271 		error = ENXIO;
272 		goto fail;
273 	}
274 
275 	txp_set_filter(sc);
276 
277 	enaddr[0] = ((uint8_t *)&p1)[1];
278 	enaddr[1] = ((uint8_t *)&p1)[0];
279 	enaddr[2] = ((uint8_t *)&p2)[3];
280 	enaddr[3] = ((uint8_t *)&p2)[2];
281 	enaddr[4] = ((uint8_t *)&p2)[1];
282 	enaddr[5] = ((uint8_t *)&p2)[0];
283 
284 	ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts);
285 	ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
286 	ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
287 	ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
288 	ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
289 	ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL);
290 	ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
291 	ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
292 
293 	sc->sc_xcvr = TXP_XCVR_AUTO;
294 	txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0,
295 	    NULL, NULL, NULL, 0);
296 	ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO);
297 
298 	ifp->if_softc = sc;
299 	ifp->if_mtu = ETHERMTU;
300 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
301 	ifp->if_ioctl = txp_ioctl;
302 	ifp->if_start = txp_start;
303 	ifp->if_watchdog = txp_watchdog;
304 	ifp->if_init = txp_init;
305 	ifp->if_baudrate = 100000000;
306 	ifq_set_maxlen(&ifp->if_snd, TX_ENTRIES);
307 	ifq_set_ready(&ifp->if_snd);
308 	ifp->if_hwassist = 0;
309 	txp_capabilities(sc);
310 
311 	ether_ifattach(ifp, enaddr, NULL);
312 
313 	ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sc_irq));
314 
315 	error = bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE,
316 			       txp_intr, sc, &sc->sc_intrhand,
317 			       ifp->if_serializer);
318 	if (error) {
319 		device_printf(dev, "couldn't set up irq\n");
320 		ether_ifdetach(ifp);
321 		goto fail;
322 	}
323 
324 	return(0);
325 
326 fail:
327 	txp_release_resources(dev);
328 	return(error);
329 }
330 
331 static int
txp_detach(device_t dev)332 txp_detach(device_t dev)
333 {
334 	struct txp_softc *sc = device_get_softc(dev);
335 	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
336 	int i;
337 
338 	lwkt_serialize_enter(ifp->if_serializer);
339 
340 	txp_stop(sc);
341 	txp_shutdown(dev);
342 	bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
343 
344 	lwkt_serialize_exit(ifp->if_serializer);
345 
346 	ifmedia_removeall(&sc->sc_ifmedia);
347 	ether_ifdetach(ifp);
348 
349 	for (i = 0; i < RXBUF_ENTRIES; i++)
350 		kfree(sc->sc_rxbufs[i].rb_sd, M_DEVBUF);
351 
352 	txp_release_resources(dev);
353 
354 	return(0);
355 }
356 
357 static void
txp_release_resources(device_t dev)358 txp_release_resources(device_t dev)
359 {
360 	struct txp_softc *sc;
361 
362 	sc = device_get_softc(dev);
363 
364 	if (sc->sc_irq != NULL)
365 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
366 
367 	if (sc->sc_res != NULL)
368 		bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res);
369 
370 	if (sc->sc_ldata != NULL)
371 		contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF);
372 
373 	return;
374 }
375 
376 static int
txp_chip_init(struct txp_softc * sc)377 txp_chip_init(struct txp_softc *sc)
378 {
379 	/* disable interrupts */
380 	WRITE_REG(sc, TXP_IER, 0);
381 	WRITE_REG(sc, TXP_IMR,
382 	    TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
383 	    TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
384 	    TXP_INT_LATCH);
385 
386 	/* ack all interrupts */
387 	WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
388 	    TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
389 	    TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
390 	    TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
391 	    TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
392 
393 	if (txp_reset_adapter(sc))
394 		return (-1);
395 
396 	/* disable interrupts */
397 	WRITE_REG(sc, TXP_IER, 0);
398 	WRITE_REG(sc, TXP_IMR,
399 	    TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
400 	    TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
401 	    TXP_INT_LATCH);
402 
403 	/* ack all interrupts */
404 	WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH |
405 	    TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
406 	    TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
407 	    TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
408 	    TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0);
409 
410 	return (0);
411 }
412 
413 static int
txp_reset_adapter(struct txp_softc * sc)414 txp_reset_adapter(struct txp_softc *sc)
415 {
416 	u_int32_t r;
417 	int i;
418 
419 	WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL);
420 	DELAY(1000);
421 	WRITE_REG(sc, TXP_SRR, 0);
422 
423 	/* Should wait max 6 seconds */
424 	for (i = 0; i < 6000; i++) {
425 		r = READ_REG(sc, TXP_A2H_0);
426 		if (r == STAT_WAITING_FOR_HOST_REQUEST)
427 			break;
428 		DELAY(1000);
429 	}
430 
431 	if (r != STAT_WAITING_FOR_HOST_REQUEST) {
432 		if_printf(&sc->sc_arpcom.ac_if, "reset hung\n");
433 		return (-1);
434 	}
435 
436 	return (0);
437 }
438 
439 static int
txp_download_fw(struct txp_softc * sc)440 txp_download_fw(struct txp_softc *sc)
441 {
442 	struct txp_fw_file_header *fileheader;
443 	struct txp_fw_section_header *secthead;
444 	int sect;
445 	u_int32_t r, i, ier, imr;
446 
447 	ier = READ_REG(sc, TXP_IER);
448 	WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0);
449 
450 	imr = READ_REG(sc, TXP_IMR);
451 	WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0);
452 
453 	for (i = 0; i < 10000; i++) {
454 		r = READ_REG(sc, TXP_A2H_0);
455 		if (r == STAT_WAITING_FOR_HOST_REQUEST)
456 			break;
457 		DELAY(50);
458 	}
459 	if (r != STAT_WAITING_FOR_HOST_REQUEST) {
460 		if_printf(&sc->sc_arpcom.ac_if,
461 			  "not waiting for host request\n");
462 		return (-1);
463 	}
464 
465 	/* Ack the status */
466 	WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
467 
468 	fileheader = (struct txp_fw_file_header *)tc990image;
469 	if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) {
470 		if_printf(&sc->sc_arpcom.ac_if, "fw invalid magic\n");
471 		return (-1);
472 	}
473 
474 	/* Tell boot firmware to get ready for image */
475 	WRITE_REG(sc, TXP_H2A_1, fileheader->addr);
476 	WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE);
477 
478 	if (txp_download_fw_wait(sc)) {
479 		if_printf(&sc->sc_arpcom.ac_if, "fw wait failed, initial\n");
480 		return (-1);
481 	}
482 
483 	secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) +
484 	    sizeof(struct txp_fw_file_header));
485 
486 	for (sect = 0; sect < fileheader->nsections; sect++) {
487 		if (txp_download_fw_section(sc, secthead, sect))
488 			return (-1);
489 		secthead = (struct txp_fw_section_header *)
490 		    (((u_int8_t *)secthead) + secthead->nbytes +
491 		    sizeof(*secthead));
492 	}
493 
494 	WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE);
495 
496 	for (i = 0; i < 10000; i++) {
497 		r = READ_REG(sc, TXP_A2H_0);
498 		if (r == STAT_WAITING_FOR_BOOT)
499 			break;
500 		DELAY(50);
501 	}
502 	if (r != STAT_WAITING_FOR_BOOT) {
503 		if_printf(&sc->sc_arpcom.ac_if, "not waiting for boot\n");
504 		return (-1);
505 	}
506 
507 	WRITE_REG(sc, TXP_IER, ier);
508 	WRITE_REG(sc, TXP_IMR, imr);
509 
510 	return (0);
511 }
512 
513 static int
txp_download_fw_wait(struct txp_softc * sc)514 txp_download_fw_wait(struct txp_softc *sc)
515 {
516 	u_int32_t i, r;
517 
518 	for (i = 0; i < 10000; i++) {
519 		r = READ_REG(sc, TXP_ISR);
520 		if (r & TXP_INT_A2H_0)
521 			break;
522 		DELAY(50);
523 	}
524 
525 	if (!(r & TXP_INT_A2H_0)) {
526 		if_printf(&sc->sc_arpcom.ac_if, "fw wait failed comm0\n");
527 		return (-1);
528 	}
529 
530 	WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0);
531 
532 	r = READ_REG(sc, TXP_A2H_0);
533 	if (r != STAT_WAITING_FOR_SEGMENT) {
534 		if_printf(&sc->sc_arpcom.ac_if, "fw not waiting for segment\n");
535 		return (-1);
536 	}
537 	return (0);
538 }
539 
540 static int
txp_download_fw_section(struct txp_softc * sc,struct txp_fw_section_header * sect,int sectnum)541 txp_download_fw_section(struct txp_softc *sc,
542 			struct txp_fw_section_header *sect, int sectnum)
543 {
544 	vm_offset_t dma;
545 	int rseg, err = 0;
546 	struct mbuf m;
547 	u_int16_t csum;
548 
549 	/* Skip zero length sections */
550 	if (sect->nbytes == 0)
551 		return (0);
552 
553 	/* Make sure we aren't past the end of the image */
554 	rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image);
555 	if (rseg >= sizeof(tc990image)) {
556 		if_printf(&sc->sc_arpcom.ac_if, "fw invalid section address, "
557 		    "section %d\n", sectnum);
558 		return (-1);
559 	}
560 
561 	/* Make sure this section doesn't go past the end */
562 	rseg += sect->nbytes;
563 	if (rseg >= sizeof(tc990image)) {
564 		if_printf(&sc->sc_arpcom.ac_if, "fw truncated section %d\n",
565 		    sectnum);
566 		return (-1);
567 	}
568 
569 	bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes);
570 	dma = vtophys(sc->sc_fwbuf);
571 
572 	/*
573 	 * dummy up mbuf and verify section checksum
574 	 */
575 	m.m_type = MT_DATA;
576 	m.m_next = m.m_nextpkt = NULL;
577 	m.m_len = sect->nbytes;
578 	m.m_data = sc->sc_fwbuf;
579 	m.m_flags = 0;
580 	csum = in_cksum(&m, sect->nbytes);
581 	if (csum != sect->cksum) {
582 		if_printf(&sc->sc_arpcom.ac_if, "fw section %d, bad "
583 		    "cksum (expected 0x%x got 0x%x)\n",
584 		    sectnum, sect->cksum, csum);
585 		err = -1;
586 		goto bail;
587 	}
588 
589 	WRITE_REG(sc, TXP_H2A_1, sect->nbytes);
590 	WRITE_REG(sc, TXP_H2A_2, sect->cksum);
591 	WRITE_REG(sc, TXP_H2A_3, sect->addr);
592 	WRITE_REG(sc, TXP_H2A_4, 0);
593 	WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff);
594 	WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE);
595 
596 	if (txp_download_fw_wait(sc)) {
597 		if_printf(&sc->sc_arpcom.ac_if, "fw wait failed, "
598 		    "section %d\n", sectnum);
599 		err = -1;
600 	}
601 
602 bail:
603 	return (err);
604 }
605 
606 static void
txp_intr(void * vsc)607 txp_intr(void *vsc)
608 {
609 	struct txp_softc *sc = vsc;
610 	struct txp_hostvar *hv = sc->sc_hostvar;
611 	u_int32_t isr;
612 
613 	/* mask all interrupts */
614 	WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF |
615 	    TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
616 	    TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 |
617 	    TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
618 	    TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |  TXP_INT_LATCH);
619 
620 	isr = READ_REG(sc, TXP_ISR);
621 	while (isr) {
622 		WRITE_REG(sc, TXP_ISR, isr);
623 
624 		if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff))
625 			txp_rx_reclaim(sc, &sc->sc_rxhir);
626 		if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff))
627 			txp_rx_reclaim(sc, &sc->sc_rxlor);
628 
629 		if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx)
630 			txp_rxbuf_reclaim(sc);
631 
632 		if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons !=
633 		    TXP_OFFSET2IDX(*(sc->sc_txhir.r_off))))
634 			txp_tx_reclaim(sc, &sc->sc_txhir);
635 
636 		if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons !=
637 		    TXP_OFFSET2IDX(*(sc->sc_txlor.r_off))))
638 			txp_tx_reclaim(sc, &sc->sc_txlor);
639 
640 		isr = READ_REG(sc, TXP_ISR);
641 	}
642 
643 	/* unmask all interrupts */
644 	WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
645 
646 	if_devstart(&sc->sc_arpcom.ac_if);
647 }
648 
649 static void
txp_rx_reclaim(struct txp_softc * sc,struct txp_rx_ring * r)650 txp_rx_reclaim(struct txp_softc *sc, struct txp_rx_ring *r)
651 {
652 	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
653 	struct txp_rx_desc *rxd;
654 	struct mbuf *m;
655 	struct txp_swdesc *sd = NULL;
656 	u_int32_t roff, woff;
657 
658 	roff = *r->r_roff;
659 	woff = *r->r_woff;
660 	rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc));
661 
662 	while (roff != woff) {
663 
664 		if (rxd->rx_flags & RX_FLAGS_ERROR) {
665 			if_printf(ifp, "error 0x%x\n", rxd->rx_stat);
666 			IFNET_STAT_INC(ifp, ierrors, 1);
667 			goto next;
668 		}
669 
670 		/* retrieve stashed pointer */
671 		sd = rxd->rx_sd;
672 
673 		m = sd->sd_mbuf;
674 		sd->sd_mbuf = NULL;
675 
676 		m->m_pkthdr.len = m->m_len = rxd->rx_len;
677 
678 #ifdef __STRICT_ALIGNMENT
679 		{
680 			/*
681 			 * XXX Nice chip, except it won't accept "off by 2"
682 			 * buffers, so we're force to copy.  Supposedly
683 			 * this will be fixed in a newer firmware rev
684 			 * and this will be temporary.
685 			 */
686 			struct mbuf *mnew;
687 
688 			MGETHDR(mnew, M_NOWAIT, MT_DATA);
689 			if (mnew == NULL) {
690 				m_freem(m);
691 				goto next;
692 			}
693 			if (m->m_len > (MHLEN - 2)) {
694 				MCLGET(mnew, M_NOWAIT);
695 				if (!(mnew->m_flags & M_EXT)) {
696 					m_freem(mnew);
697 					m_freem(m);
698 					goto next;
699 				}
700 			}
701 			mnew->m_pkthdr.rcvif = ifp;
702 			m_adj(mnew, 2);
703 			mnew->m_pkthdr.len = mnew->m_len = m->m_len;
704 			m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, void *));
705 			m_freem(m);
706 			m = mnew;
707 		}
708 #endif
709 
710 		if (rxd->rx_stat & RX_STAT_IPCKSUMBAD)
711 			m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
712 		else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD)
713 		 	m->m_pkthdr.csum_flags |=
714 			    CSUM_IP_CHECKED|CSUM_IP_VALID;
715 
716 		if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) ||
717 		    (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) {
718 			m->m_pkthdr.csum_flags |=
719 			    CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
720 			    CSUM_FRAG_NOT_CHECKED;
721 			m->m_pkthdr.csum_data = 0xffff;
722 		}
723 
724 		if (rxd->rx_stat & RX_STAT_VLAN) {
725 			m->m_flags |= M_VLANTAG;
726 			m->m_pkthdr.ether_vlantag = htons(rxd->rx_vlan >> 16);
727 		}
728 		ifp->if_input(ifp, m, NULL, -1);
729 
730 next:
731 
732 		roff += sizeof(struct txp_rx_desc);
733 		if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) {
734 			roff = 0;
735 			rxd = r->r_desc;
736 		} else
737 			rxd++;
738 		woff = *r->r_woff;
739 	}
740 
741 	*r->r_roff = woff;
742 
743 	return;
744 }
745 
746 static void
txp_rxbuf_reclaim(struct txp_softc * sc)747 txp_rxbuf_reclaim(struct txp_softc *sc)
748 {
749 	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
750 	struct txp_hostvar *hv = sc->sc_hostvar;
751 	struct txp_rxbuf_desc *rbd;
752 	struct txp_swdesc *sd;
753 	u_int32_t i;
754 
755 	if (!(ifp->if_flags & IFF_RUNNING))
756 		return;
757 
758 	i = sc->sc_rxbufprod;
759 	rbd = sc->sc_rxbufs + i;
760 
761 	while (1) {
762 		sd = rbd->rb_sd;
763 		if (sd->sd_mbuf != NULL)
764 			break;
765 
766 		MGETHDR(sd->sd_mbuf, M_NOWAIT, MT_DATA);
767 		if (sd->sd_mbuf == NULL)
768 			goto err_sd;
769 
770 		MCLGET(sd->sd_mbuf, M_NOWAIT);
771 		if ((sd->sd_mbuf->m_flags & M_EXT) == 0)
772 			goto err_mbuf;
773 		sd->sd_mbuf->m_pkthdr.rcvif = ifp;
774 		sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES;
775 
776 		rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t))
777 		    & 0xffffffff;
778 		rbd->rb_paddrhi = 0;
779 
780 		hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i);
781 
782 		if (++i == RXBUF_ENTRIES) {
783 			i = 0;
784 			rbd = sc->sc_rxbufs;
785 		} else
786 			rbd++;
787 	}
788 
789 	sc->sc_rxbufprod = i;
790 
791 	return;
792 
793 err_mbuf:
794 	m_freem(sd->sd_mbuf);
795 err_sd:
796 	kfree(sd, M_DEVBUF);
797 }
798 
799 /*
800  * Reclaim mbufs and entries from a transmit ring.
801  */
802 static void
txp_tx_reclaim(struct txp_softc * sc,struct txp_tx_ring * r)803 txp_tx_reclaim(struct txp_softc *sc, struct txp_tx_ring *r)
804 {
805 	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
806 	u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off));
807 	u_int32_t cons = r->r_cons, cnt = r->r_cnt;
808 	struct txp_tx_desc *txd = r->r_desc + cons;
809 	struct txp_swdesc *sd = sc->sc_txd + cons;
810 	struct mbuf *m;
811 
812 	while (cons != idx) {
813 		if (cnt == 0)
814 			break;
815 
816 		if ((txd->tx_flags & TX_FLAGS_TYPE_M) ==
817 		    TX_FLAGS_TYPE_DATA) {
818 			m = sd->sd_mbuf;
819 			if (m != NULL) {
820 				m_freem(m);
821 				txd->tx_addrlo = 0;
822 				txd->tx_addrhi = 0;
823 				IFNET_STAT_INC(ifp, opackets, 1);
824 			}
825 		}
826 		ifq_clr_oactive(&ifp->if_snd);
827 
828 		if (++cons == TX_ENTRIES) {
829 			txd = r->r_desc;
830 			cons = 0;
831 			sd = sc->sc_txd;
832 		} else {
833 			txd++;
834 			sd++;
835 		}
836 
837 		cnt--;
838 	}
839 
840 	r->r_cons = cons;
841 	r->r_cnt = cnt;
842 	if (cnt == 0)
843 		ifp->if_timer = 0;
844 }
845 
846 static int
txp_shutdown(device_t dev)847 txp_shutdown(device_t dev)
848 {
849 	struct txp_softc *sc;
850 	struct ifnet *ifp;
851 
852 	sc = device_get_softc(dev);
853 	ifp = &sc->sc_arpcom.ac_if;
854 	lwkt_serialize_enter(ifp->if_serializer);
855 
856 	/* mask all interrupts */
857 	WRITE_REG(sc, TXP_IMR,
858 	    TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |
859 	    TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
860 	    TXP_INT_LATCH);
861 
862 	txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0);
863 	txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0);
864 	txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0);
865 
866 	lwkt_serialize_exit(ifp->if_serializer);
867 	return(0);
868 }
869 
870 static int
txp_alloc_rings(struct txp_softc * sc)871 txp_alloc_rings(struct txp_softc *sc)
872 {
873 	struct txp_boot_record *boot;
874 	struct txp_ldata *ld;
875 	u_int32_t r;
876 	int i;
877 
878 	ld = sc->sc_ldata;
879 	boot = &ld->txp_boot;
880 
881 	/* boot record */
882 	sc->sc_boot = boot;
883 
884 	/* host variables */
885 	bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar));
886 	boot->br_hostvar_lo = vtophys(&ld->txp_hostvar);
887 	boot->br_hostvar_hi = 0;
888 	sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar;
889 
890 	/* hi priority tx ring */
891 	boot->br_txhipri_lo = vtophys(&ld->txp_txhiring);
892 	boot->br_txhipri_hi = 0;
893 	boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc);
894 	sc->sc_txhir.r_reg = TXP_H2A_1;
895 	sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring;
896 	sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0;
897 	sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx;
898 
899 	/* lo priority tx ring */
900 	boot->br_txlopri_lo = vtophys(&ld->txp_txloring);
901 	boot->br_txlopri_hi = 0;
902 	boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc);
903 	sc->sc_txlor.r_reg = TXP_H2A_3;
904 	sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring;
905 	sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0;
906 	sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx;
907 
908 	/* high priority rx ring */
909 	boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring);
910 	boot->br_rxhipri_hi = 0;
911 	boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc);
912 	sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring;
913 	sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx;
914 	sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx;
915 
916 	/* low priority rx ring */
917 	boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring);
918 	boot->br_rxlopri_hi = 0;
919 	boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc);
920 	sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring;
921 	sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx;
922 	sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx;
923 
924 	/* command ring */
925 	bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES);
926 	boot->br_cmd_lo = vtophys(&ld->txp_cmdring);
927 	boot->br_cmd_hi = 0;
928 	boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc);
929 	sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring;
930 	sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc);
931 	sc->sc_cmdring.lastwrite = 0;
932 
933 	/* response ring */
934 	bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES);
935 	boot->br_resp_lo = vtophys(&ld->txp_rspring);
936 	boot->br_resp_hi = 0;
937 	boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc);
938 	sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring;
939 	sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc);
940 	sc->sc_rspring.lastwrite = 0;
941 
942 	/* receive buffer ring */
943 	boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs);
944 	boot->br_rxbuf_hi = 0;
945 	boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc);
946 	sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs;
947 
948 	for (i = 0; i < RXBUF_ENTRIES; i++) {
949 		struct txp_swdesc *sd;
950 		if (sc->sc_rxbufs[i].rb_sd != NULL)
951 			continue;
952 		sc->sc_rxbufs[i].rb_sd = kmalloc(sizeof(struct txp_swdesc),
953 		    M_DEVBUF, M_WAITOK);
954 		sd = sc->sc_rxbufs[i].rb_sd;
955 		sd->sd_mbuf = NULL;
956 	}
957 	sc->sc_rxbufprod = 0;
958 
959 	/* zero dma */
960 	bzero(&ld->txp_zero, sizeof(u_int32_t));
961 	boot->br_zero_lo = vtophys(&ld->txp_zero);
962 	boot->br_zero_hi = 0;
963 
964 	/* See if it's waiting for boot, and try to boot it */
965 	for (i = 0; i < 10000; i++) {
966 		r = READ_REG(sc, TXP_A2H_0);
967 		if (r == STAT_WAITING_FOR_BOOT)
968 			break;
969 		DELAY(50);
970 	}
971 
972 	if (r != STAT_WAITING_FOR_BOOT) {
973 		if_printf(&sc->sc_arpcom.ac_if, "not waiting for boot\n");
974 		return(ENXIO);
975 	}
976 
977 	WRITE_REG(sc, TXP_H2A_2, 0);
978 	WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot));
979 	WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD);
980 
981 	/* See if it booted */
982 	for (i = 0; i < 10000; i++) {
983 		r = READ_REG(sc, TXP_A2H_0);
984 		if (r == STAT_RUNNING)
985 			break;
986 		DELAY(50);
987 	}
988 	if (r != STAT_RUNNING) {
989 		if_printf(&sc->sc_arpcom.ac_if, "fw not running\n");
990 		return(ENXIO);
991 	}
992 
993 	/* Clear TX and CMD ring write registers */
994 	WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL);
995 	WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL);
996 	WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL);
997 	WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL);
998 
999 	return (0);
1000 }
1001 
1002 static int
txp_ioctl(struct ifnet * ifp,u_long command,caddr_t data,struct ucred * cr)1003 txp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1004 {
1005 	struct txp_softc *sc = ifp->if_softc;
1006 	struct ifreq *ifr = (struct ifreq *)data;
1007 	int error = 0;
1008 
1009 	switch(command) {
1010 	case SIOCSIFFLAGS:
1011 		if (ifp->if_flags & IFF_UP) {
1012 			txp_init(sc);
1013 		} else {
1014 			if (ifp->if_flags & IFF_RUNNING)
1015 				txp_stop(sc);
1016 		}
1017 		break;
1018 	case SIOCADDMULTI:
1019 	case SIOCDELMULTI:
1020 		/*
1021 		 * Multicast list has changed; set the hardware
1022 		 * filter accordingly.
1023 		 */
1024 		txp_set_filter(sc);
1025 		error = 0;
1026 		break;
1027 	case SIOCGIFMEDIA:
1028 	case SIOCSIFMEDIA:
1029 		error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command);
1030 		break;
1031 	default:
1032 		error = ether_ioctl(ifp, command, data);
1033 		break;
1034 	}
1035 	return(error);
1036 }
1037 
1038 static int
txp_rxring_fill(struct txp_softc * sc)1039 txp_rxring_fill(struct txp_softc *sc)
1040 {
1041 	int i;
1042 	struct ifnet *ifp;
1043 	struct txp_swdesc *sd;
1044 
1045 	ifp = &sc->sc_arpcom.ac_if;
1046 
1047 	for (i = 0; i < RXBUF_ENTRIES; i++) {
1048 		sd = sc->sc_rxbufs[i].rb_sd;
1049 		MGETHDR(sd->sd_mbuf, M_NOWAIT, MT_DATA);
1050 		if (sd->sd_mbuf == NULL)
1051 			return(ENOBUFS);
1052 
1053 		MCLGET(sd->sd_mbuf, M_NOWAIT);
1054 		if ((sd->sd_mbuf->m_flags & M_EXT) == 0) {
1055 			m_freem(sd->sd_mbuf);
1056 			return(ENOBUFS);
1057 		}
1058 		sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES;
1059 		sd->sd_mbuf->m_pkthdr.rcvif = ifp;
1060 
1061 		sc->sc_rxbufs[i].rb_paddrlo =
1062 		    vtophys(mtod(sd->sd_mbuf, vm_offset_t));
1063 		sc->sc_rxbufs[i].rb_paddrhi = 0;
1064 	}
1065 
1066 	sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) *
1067 	    sizeof(struct txp_rxbuf_desc);
1068 
1069 	return(0);
1070 }
1071 
1072 static void
txp_rxring_empty(struct txp_softc * sc)1073 txp_rxring_empty(struct txp_softc *sc)
1074 {
1075 	int i;
1076 	struct txp_swdesc *sd;
1077 
1078 	if (sc->sc_rxbufs == NULL)
1079 		return;
1080 
1081 	for (i = 0; i < RXBUF_ENTRIES; i++) {
1082 		if (&sc->sc_rxbufs[i] == NULL)
1083 			continue;
1084 		sd = sc->sc_rxbufs[i].rb_sd;
1085 		if (sd == NULL)
1086 			continue;
1087 		if (sd->sd_mbuf != NULL) {
1088 			m_freem(sd->sd_mbuf);
1089 			sd->sd_mbuf = NULL;
1090 		}
1091 	}
1092 
1093 	return;
1094 }
1095 
1096 static void
txp_init(void * xsc)1097 txp_init(void *xsc)
1098 {
1099 	struct txp_softc *sc;
1100 	struct ifnet *ifp;
1101 	u_int16_t p1;
1102 	u_int32_t p2;
1103 
1104 	sc = xsc;
1105 	ifp = &sc->sc_arpcom.ac_if;
1106 
1107 	if (ifp->if_flags & IFF_RUNNING)
1108 		return;
1109 
1110 	txp_stop(sc);
1111 
1112 	txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0,
1113 	    NULL, NULL, NULL, 1);
1114 
1115 	/* Set station address. */
1116 	((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0];
1117 	((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1];
1118 	((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2];
1119 	((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3];
1120 	((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4];
1121 	((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5];
1122 	txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0,
1123 	    NULL, NULL, NULL, 1);
1124 
1125 	txp_set_filter(sc);
1126 
1127 	txp_rxring_fill(sc);
1128 
1129 	txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1130 	txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1131 
1132 	WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF |
1133 	    TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 |
1134 	    TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 |
1135 	    TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 |
1136 	    TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT |  TXP_INT_LATCH);
1137 	WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3);
1138 
1139 	ifp->if_flags |= IFF_RUNNING;
1140 	ifq_clr_oactive(&ifp->if_snd);
1141 	ifp->if_timer = 0;
1142 
1143 	callout_reset(&sc->txp_stat_timer, hz, txp_tick, sc);
1144 }
1145 
1146 static void
txp_tick(void * vsc)1147 txp_tick(void *vsc)
1148 {
1149 	struct txp_softc *sc = vsc;
1150 	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1151 	struct txp_rsp_desc *rsp = NULL;
1152 	struct txp_ext_desc *ext;
1153 
1154 	lwkt_serialize_enter(ifp->if_serializer);
1155 	txp_rxbuf_reclaim(sc);
1156 
1157 	if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0,
1158 	    &rsp, 1))
1159 		goto out;
1160 	if (rsp->rsp_numdesc != 6)
1161 		goto out;
1162 	if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0,
1163 	    NULL, NULL, NULL, 1))
1164 		goto out;
1165 	ext = (struct txp_ext_desc *)(rsp + 1);
1166 
1167 	IFNET_STAT_INC(ifp, ierrors,
1168 	    ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 +
1169 	    ext[4].ext_1 + ext[4].ext_4);
1170 	IFNET_STAT_INC(ifp, oerrors,
1171 	    ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + ext[2].ext_1);
1172 	IFNET_STAT_INC(ifp, collisions,
1173 	    ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + ext[1].ext_3);
1174 	IFNET_STAT_INC(ifp, opackets, rsp->rsp_par2);
1175 	IFNET_STAT_INC(ifp, ipackets, ext[2].ext_3);
1176 
1177 out:
1178 	if (rsp != NULL)
1179 		kfree(rsp, M_DEVBUF);
1180 
1181 	callout_reset(&sc->txp_stat_timer, hz, txp_tick, sc);
1182 	lwkt_serialize_exit(ifp->if_serializer);
1183 }
1184 
1185 static void
txp_start(struct ifnet * ifp,struct ifaltq_subque * ifsq)1186 txp_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1187 {
1188 	struct txp_softc *sc = ifp->if_softc;
1189 	struct txp_tx_ring *r = &sc->sc_txhir;
1190 	struct txp_tx_desc *txd;
1191 	struct txp_frag_desc *fxd;
1192 	struct mbuf *m, *m0, *m_defragged;
1193 	struct txp_swdesc *sd;
1194 	u_int32_t firstprod, firstcnt, prod, cnt;
1195 
1196 	ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1197 
1198 	if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1199 		return;
1200 
1201 	prod = r->r_prod;
1202 	cnt = r->r_cnt;
1203 
1204 	while (1) {
1205 		int frag;
1206 
1207 		firstprod = prod;
1208 		firstcnt = cnt;
1209 
1210 		if ((TX_ENTRIES - cnt) < 4)
1211 			goto oactive;
1212 
1213 		m_defragged = NULL;
1214 		m = ifq_dequeue(&ifp->if_snd);
1215 		if (m == NULL)
1216 			break;
1217 again:
1218 		frag = 1;	/* Extra desc */
1219 		for (m0 = m; m0 != NULL; m0 = m0->m_next)
1220 			++frag;
1221 		if ((cnt + frag) >= (TX_ENTRIES - 4)) {
1222 			if (m_defragged != NULL) {
1223 				/*
1224 				 * Even after defragmentation, there
1225 				 * are still too many fragments, so
1226 				 * drop this packet.
1227 				 */
1228 				m_freem(m);
1229 				goto oactive;
1230 			}
1231 
1232 			m_defragged = m_defrag(m, M_NOWAIT);
1233 			if (m_defragged == NULL) {
1234 				m_freem(m);
1235 				continue;
1236 			}
1237 			m = m_defragged;
1238 
1239 			/* Recount # of fragments */
1240 			goto again;
1241 		}
1242 
1243 		sd = sc->sc_txd + prod;
1244 		sd->sd_mbuf = m;
1245 
1246 		txd = r->r_desc + prod;
1247 		txd->tx_flags = TX_FLAGS_TYPE_DATA;
1248 		txd->tx_numdesc = 0;
1249 		txd->tx_addrlo = 0;
1250 		txd->tx_addrhi = 0;
1251 		txd->tx_totlen = 0;
1252 		txd->tx_pflags = 0;
1253 
1254 		if (++prod == TX_ENTRIES)
1255 			prod = 0;
1256 
1257 		++cnt;
1258 		KASSERT(cnt < (TX_ENTRIES - 4), ("too many frag"));
1259 
1260 		if (m->m_flags & M_VLANTAG) {
1261 			txd->tx_pflags = TX_PFLAGS_VLAN |
1262 			    (htons(m->m_pkthdr.ether_vlantag) <<
1263 			     TX_PFLAGS_VLANTAG_S);
1264 		}
1265 
1266 		if (m->m_pkthdr.csum_flags & CSUM_IP)
1267 			txd->tx_pflags |= TX_PFLAGS_IPCKSUM;
1268 
1269 #if 0
1270 		if (m->m_pkthdr.csum_flags & CSUM_TCP)
1271 			txd->tx_pflags |= TX_PFLAGS_TCPCKSUM;
1272 		if (m->m_pkthdr.csum_flags & CSUM_UDP)
1273 			txd->tx_pflags |= TX_PFLAGS_UDPCKSUM;
1274 #endif
1275 
1276 		fxd = (struct txp_frag_desc *)(r->r_desc + prod);
1277 		for (m0 = m; m0 != NULL; m0 = m0->m_next) {
1278 			if (m0->m_len == 0)
1279 				continue;
1280 
1281 			++cnt;
1282 			KASSERT(cnt < (TX_ENTRIES - 4), ("too many frag"));
1283 
1284 			txd->tx_numdesc++;
1285 
1286 			fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG;
1287 			fxd->frag_rsvd1 = 0;
1288 			fxd->frag_len = m0->m_len;
1289 			fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t));
1290 			fxd->frag_addrhi = 0;
1291 			fxd->frag_rsvd2 = 0;
1292 
1293 			if (++prod == TX_ENTRIES) {
1294 				fxd = (struct txp_frag_desc *)r->r_desc;
1295 				prod = 0;
1296 			} else
1297 				fxd++;
1298 		}
1299 
1300 		ifp->if_timer = 5;
1301 
1302 		ETHER_BPF_MTAP(ifp, m);
1303 		WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod));
1304 	}
1305 
1306 	r->r_prod = prod;
1307 	r->r_cnt = cnt;
1308 	return;
1309 
1310 oactive:
1311 	ifq_set_oactive(&ifp->if_snd);
1312 	r->r_prod = firstprod;
1313 	r->r_cnt = firstcnt;
1314 	return;
1315 }
1316 
1317 /*
1318  * Handle simple commands sent to the typhoon
1319  */
1320 static int
txp_command(struct txp_softc * sc,u_int16_t id,u_int16_t in1,u_int32_t in2,u_int32_t in3,u_int16_t * out1,u_int32_t * out2,u_int32_t * out3,int wait)1321 txp_command(struct txp_softc *sc, u_int16_t id, u_int16_t in1, u_int32_t in2,
1322 	    u_int32_t in3, u_int16_t *out1, u_int32_t *out2, u_int32_t *out3,
1323 	    int wait)
1324 {
1325 	struct txp_rsp_desc *rsp = NULL;
1326 
1327 	if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait))
1328 		return (-1);
1329 
1330 	if (!wait)
1331 		return (0);
1332 
1333 	if (out1 != NULL)
1334 		*out1 = rsp->rsp_par1;
1335 	if (out2 != NULL)
1336 		*out2 = rsp->rsp_par2;
1337 	if (out3 != NULL)
1338 		*out3 = rsp->rsp_par3;
1339 	kfree(rsp, M_DEVBUF);
1340 	return (0);
1341 }
1342 
1343 static int
txp_command2(struct txp_softc * sc,u_int16_t id,u_int16_t in1,u_int32_t in2,u_int32_t in3,struct txp_ext_desc * in_extp,u_int8_t in_extn,struct txp_rsp_desc ** rspp,int wait)1344 txp_command2(struct txp_softc *sc, u_int16_t id, u_int16_t in1, u_int32_t in2,
1345 	     u_int32_t in3, struct txp_ext_desc *in_extp, u_int8_t in_extn,
1346 	     struct txp_rsp_desc **rspp, int wait)
1347 {
1348 	struct txp_hostvar *hv = sc->sc_hostvar;
1349 	struct txp_cmd_desc *cmd;
1350 	struct txp_ext_desc *ext;
1351 	u_int32_t idx, i;
1352 	u_int16_t seq;
1353 
1354 	if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) {
1355 		if_printf(&sc->sc_arpcom.ac_if, "no free cmd descriptors\n");
1356 		return (-1);
1357 	}
1358 
1359 	idx = sc->sc_cmdring.lastwrite;
1360 	cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx);
1361 	bzero(cmd, sizeof(*cmd));
1362 
1363 	cmd->cmd_numdesc = in_extn;
1364 	cmd->cmd_seq = seq = sc->sc_seq++;
1365 	cmd->cmd_id = id;
1366 	cmd->cmd_par1 = in1;
1367 	cmd->cmd_par2 = in2;
1368 	cmd->cmd_par3 = in3;
1369 	cmd->cmd_flags = CMD_FLAGS_TYPE_CMD |
1370 	    (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID;
1371 
1372 	idx += sizeof(struct txp_cmd_desc);
1373 	if (idx == sc->sc_cmdring.size)
1374 		idx = 0;
1375 
1376 	for (i = 0; i < in_extn; i++) {
1377 		ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx);
1378 		bcopy(in_extp, ext, sizeof(struct txp_ext_desc));
1379 		in_extp++;
1380 		idx += sizeof(struct txp_cmd_desc);
1381 		if (idx == sc->sc_cmdring.size)
1382 			idx = 0;
1383 	}
1384 
1385 	sc->sc_cmdring.lastwrite = idx;
1386 
1387 	WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite);
1388 
1389 	if (!wait)
1390 		return (0);
1391 
1392 	for (i = 0; i < 10000; i++) {
1393 		idx = hv->hv_resp_read_idx;
1394 		if (idx != hv->hv_resp_write_idx) {
1395 			*rspp = NULL;
1396 			if (txp_response(sc, idx, id, seq, rspp))
1397 				return (-1);
1398 			if (*rspp != NULL)
1399 				break;
1400 		}
1401 		DELAY(50);
1402 	}
1403 	if (i == 1000 || (*rspp) == NULL) {
1404 		if_printf(&sc->sc_arpcom.ac_if, "0x%x command failed\n", id);
1405 		return (-1);
1406 	}
1407 
1408 	return (0);
1409 }
1410 
1411 static int
txp_response(struct txp_softc * sc,u_int32_t ridx,u_int16_t id,u_int16_t seq,struct txp_rsp_desc ** rspp)1412 txp_response(struct txp_softc *sc, u_int32_t ridx, u_int16_t id, u_int16_t seq,
1413 	     struct txp_rsp_desc **rspp)
1414 {
1415 	struct txp_hostvar *hv = sc->sc_hostvar;
1416 	struct txp_rsp_desc *rsp;
1417 
1418 	while (ridx != hv->hv_resp_write_idx) {
1419 		rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx);
1420 
1421 		if (id == rsp->rsp_id && rsp->rsp_seq == seq) {
1422 			*rspp = (struct txp_rsp_desc *)kmalloc(
1423 			    sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1),
1424 			    M_DEVBUF, M_INTWAIT);
1425 			if ((*rspp) == NULL)
1426 				return (-1);
1427 			txp_rsp_fixup(sc, rsp, *rspp);
1428 			return (0);
1429 		}
1430 
1431 		if (rsp->rsp_flags & RSP_FLAGS_ERROR) {
1432 			if_printf(&sc->sc_arpcom.ac_if, "response error!\n");
1433 			txp_rsp_fixup(sc, rsp, NULL);
1434 			ridx = hv->hv_resp_read_idx;
1435 			continue;
1436 		}
1437 
1438 		switch (rsp->rsp_id) {
1439 		case TXP_CMD_CYCLE_STATISTICS:
1440 		case TXP_CMD_MEDIA_STATUS_READ:
1441 			break;
1442 		case TXP_CMD_HELLO_RESPONSE:
1443 			if_printf(&sc->sc_arpcom.ac_if, "hello\n");
1444 			break;
1445 		default:
1446 			if_printf(&sc->sc_arpcom.ac_if, "unknown id(0x%x)\n",
1447 			    rsp->rsp_id);
1448 		}
1449 
1450 		txp_rsp_fixup(sc, rsp, NULL);
1451 		ridx = hv->hv_resp_read_idx;
1452 		hv->hv_resp_read_idx = ridx;
1453 	}
1454 
1455 	return (0);
1456 }
1457 
1458 static void
txp_rsp_fixup(struct txp_softc * sc,struct txp_rsp_desc * rsp,struct txp_rsp_desc * dst)1459 txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp,
1460 	      struct txp_rsp_desc *dst)
1461 {
1462 	struct txp_rsp_desc *src = rsp;
1463 	struct txp_hostvar *hv = sc->sc_hostvar;
1464 	u_int32_t i, ridx;
1465 
1466 	ridx = hv->hv_resp_read_idx;
1467 
1468 	for (i = 0; i < rsp->rsp_numdesc + 1; i++) {
1469 		if (dst != NULL)
1470 			bcopy(src, dst++, sizeof(struct txp_rsp_desc));
1471 		ridx += sizeof(struct txp_rsp_desc);
1472 		if (ridx == sc->sc_rspring.size) {
1473 			src = sc->sc_rspring.base;
1474 			ridx = 0;
1475 		} else
1476 			src++;
1477 		sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx;
1478 	}
1479 
1480 	hv->hv_resp_read_idx = ridx;
1481 }
1482 
1483 static int
txp_cmd_desc_numfree(struct txp_softc * sc)1484 txp_cmd_desc_numfree(struct txp_softc *sc)
1485 {
1486 	struct txp_hostvar *hv = sc->sc_hostvar;
1487 	struct txp_boot_record *br = sc->sc_boot;
1488 	u_int32_t widx, ridx, nfree;
1489 
1490 	widx = sc->sc_cmdring.lastwrite;
1491 	ridx = hv->hv_cmd_read_idx;
1492 
1493 	if (widx == ridx) {
1494 		/* Ring is completely free */
1495 		nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc);
1496 	} else {
1497 		if (widx > ridx)
1498 			nfree = br->br_cmd_siz -
1499 			    (widx - ridx + sizeof(struct txp_cmd_desc));
1500 		else
1501 			nfree = ridx - widx - sizeof(struct txp_cmd_desc);
1502 	}
1503 
1504 	return (nfree / sizeof(struct txp_cmd_desc));
1505 }
1506 
1507 static void
txp_stop(struct txp_softc * sc)1508 txp_stop(struct txp_softc *sc)
1509 {
1510 	struct ifnet *ifp;
1511 
1512 	ifp = &sc->sc_arpcom.ac_if;
1513 
1514 	ifp->if_flags &= ~IFF_RUNNING;
1515 	ifq_clr_oactive(&ifp->if_snd);
1516 
1517 	callout_stop(&sc->txp_stat_timer);
1518 
1519 	txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1520 	txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1);
1521 
1522 	txp_rxring_empty(sc);
1523 
1524 	return;
1525 }
1526 
1527 static void
txp_watchdog(struct ifnet * ifp)1528 txp_watchdog(struct ifnet *ifp)
1529 {
1530 	return;
1531 }
1532 
1533 static int
txp_ifmedia_upd(struct ifnet * ifp)1534 txp_ifmedia_upd(struct ifnet *ifp)
1535 {
1536 	struct txp_softc *sc = ifp->if_softc;
1537 	struct ifmedia *ifm = &sc->sc_ifmedia;
1538 	u_int16_t new_xcvr;
1539 
1540 	if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1541 		return (EINVAL);
1542 
1543 	if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) {
1544 		if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1545 			new_xcvr = TXP_XCVR_10_FDX;
1546 		else
1547 			new_xcvr = TXP_XCVR_10_HDX;
1548 	} else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
1549 		if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1550 			new_xcvr = TXP_XCVR_100_FDX;
1551 		else
1552 			new_xcvr = TXP_XCVR_100_HDX;
1553 	} else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
1554 		new_xcvr = TXP_XCVR_AUTO;
1555 	} else
1556 		return (EINVAL);
1557 
1558 	/* nothing to do */
1559 	if (sc->sc_xcvr == new_xcvr)
1560 		return (0);
1561 
1562 	txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0,
1563 	    NULL, NULL, NULL, 0);
1564 	sc->sc_xcvr = new_xcvr;
1565 
1566 	return (0);
1567 }
1568 
1569 static void
txp_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)1570 txp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1571 {
1572 	struct txp_softc *sc = ifp->if_softc;
1573 	struct ifmedia *ifm = &sc->sc_ifmedia;
1574 	u_int16_t bmsr, bmcr, anlpar;
1575 
1576 	ifmr->ifm_status = IFM_AVALID;
1577 	ifmr->ifm_active = IFM_ETHER;
1578 
1579 	if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0,
1580 	    &bmsr, NULL, NULL, 1))
1581 		goto bail;
1582 	if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0,
1583 	    &bmsr, NULL, NULL, 1))
1584 		goto bail;
1585 
1586 	if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0,
1587 	    &bmcr, NULL, NULL, 1))
1588 		goto bail;
1589 
1590 	if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0,
1591 	    &anlpar, NULL, NULL, 1))
1592 		goto bail;
1593 
1594 	if (bmsr & BMSR_LINK)
1595 		ifmr->ifm_status |= IFM_ACTIVE;
1596 
1597 	if (bmcr & BMCR_ISO) {
1598 		ifmr->ifm_active |= IFM_NONE;
1599 		ifmr->ifm_status = 0;
1600 		return;
1601 	}
1602 
1603 	if (bmcr & BMCR_LOOP)
1604 		ifmr->ifm_active |= IFM_LOOP;
1605 
1606 	if (bmcr & BMCR_AUTOEN) {
1607 		if ((bmsr & BMSR_ACOMP) == 0) {
1608 			ifmr->ifm_active |= IFM_NONE;
1609 			return;
1610 		}
1611 
1612 		if (anlpar & ANLPAR_T4)
1613 			ifmr->ifm_active |= IFM_100_T4;
1614 		else if (anlpar & ANLPAR_TX_FD)
1615 			ifmr->ifm_active |= IFM_100_TX|IFM_FDX;
1616 		else if (anlpar & ANLPAR_TX)
1617 			ifmr->ifm_active |= IFM_100_TX;
1618 		else if (anlpar & ANLPAR_10_FD)
1619 			ifmr->ifm_active |= IFM_10_T|IFM_FDX;
1620 		else if (anlpar & ANLPAR_10)
1621 			ifmr->ifm_active |= IFM_10_T;
1622 		else
1623 			ifmr->ifm_active |= IFM_NONE;
1624 	} else
1625 		ifmr->ifm_active = ifm->ifm_cur->ifm_media;
1626 	return;
1627 
1628 bail:
1629 	ifmr->ifm_active |= IFM_NONE;
1630 	ifmr->ifm_status &= ~IFM_AVALID;
1631 }
1632 
1633 #ifdef TXP_DEBUG
1634 static void
txp_show_descriptor(void * d)1635 txp_show_descriptor(void *d)
1636 {
1637 	struct txp_cmd_desc *cmd = d;
1638 	struct txp_rsp_desc *rsp = d;
1639 	struct txp_tx_desc *txd = d;
1640 	struct txp_frag_desc *frgd = d;
1641 
1642 	switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) {
1643 	case CMD_FLAGS_TYPE_CMD:
1644 		/* command descriptor */
1645 		kprintf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1646 		    cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq,
1647 		    cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3);
1648 		break;
1649 	case CMD_FLAGS_TYPE_RESP:
1650 		/* response descriptor */
1651 		kprintf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1652 		    rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq,
1653 		    rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3);
1654 		break;
1655 	case CMD_FLAGS_TYPE_DATA:
1656 		/* data header (assuming tx for now) */
1657 		kprintf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]",
1658 		    txd->tx_flags, txd->tx_numdesc, txd->tx_totlen,
1659 		    txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags);
1660 		break;
1661 	case CMD_FLAGS_TYPE_FRAG:
1662 		/* fragment descriptor */
1663 		kprintf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]",
1664 		    frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len,
1665 		    frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2);
1666 		break;
1667 	default:
1668 		kprintf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n",
1669 		    cmd->cmd_flags & CMD_FLAGS_TYPE_M,
1670 		    cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq,
1671 		    cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3);
1672 		break;
1673 	}
1674 }
1675 #endif
1676 
1677 static void
txp_set_filter(struct txp_softc * sc)1678 txp_set_filter(struct txp_softc *sc)
1679 {
1680 	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1681 	uint16_t filter;
1682 	struct ifmultiaddr *ifma;
1683 
1684 	if (ifp->if_flags & IFF_PROMISC) {
1685 		filter = TXP_RXFILT_PROMISC;
1686 		goto setit;
1687 	}
1688 
1689 	filter = TXP_RXFILT_DIRECT;
1690 
1691 	if (ifp->if_flags & IFF_BROADCAST)
1692 		filter |= TXP_RXFILT_BROADCAST;
1693 
1694 	if (ifp->if_flags & IFF_ALLMULTI) {
1695 		filter |= TXP_RXFILT_ALLMULTI;
1696 	} else {
1697 		uint32_t hashbit, hash[2];
1698 		int mcnt = 0;
1699 
1700 		hash[0] = hash[1] = 0;
1701 
1702 		TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1703 			if (ifma->ifma_addr->sa_family != AF_LINK)
1704 				continue;
1705 
1706 			mcnt++;
1707 			hashbit = (uint16_t)(ether_crc32_be(
1708 			    LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1709 			    ETHER_ADDR_LEN) & (64 - 1));
1710 			hash[hashbit / 32] |= (1 << hashbit % 32);
1711 		}
1712 
1713 		if (mcnt > 0) {
1714 			filter |= TXP_RXFILT_HASHMULTI;
1715 			txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE,
1716 			    2, hash[0], hash[1], NULL, NULL, NULL, 0);
1717 		}
1718 	}
1719 
1720 setit:
1721 	txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0,
1722 	    NULL, NULL, NULL, 1);
1723 }
1724 
1725 static void
txp_capabilities(struct txp_softc * sc)1726 txp_capabilities(struct txp_softc *sc)
1727 {
1728 	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1729 	struct txp_rsp_desc *rsp = NULL;
1730 	struct txp_ext_desc *ext;
1731 
1732 	if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1))
1733 		goto out;
1734 
1735 	if (rsp->rsp_numdesc != 1)
1736 		goto out;
1737 	ext = (struct txp_ext_desc *)(rsp + 1);
1738 
1739 	sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK;
1740 	sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK;
1741 	ifp->if_capabilities = 0;
1742 
1743 	if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) {
1744 		sc->sc_tx_capability |= OFFLOAD_VLAN;
1745 		sc->sc_rx_capability |= OFFLOAD_VLAN;
1746 		ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
1747 	}
1748 
1749 #if 0
1750 	/* not ready yet */
1751 	if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) {
1752 		sc->sc_tx_capability |= OFFLOAD_IPSEC;
1753 		sc->sc_rx_capability |= OFFLOAD_IPSEC;
1754 		ifp->if_capabilities |= IFCAP_IPSEC;
1755 	}
1756 #endif
1757 
1758 	if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) {
1759 		sc->sc_tx_capability |= OFFLOAD_IPCKSUM;
1760 		sc->sc_rx_capability |= OFFLOAD_IPCKSUM;
1761 		ifp->if_capabilities |= IFCAP_HWCSUM;
1762 		ifp->if_hwassist |= CSUM_IP;
1763 	}
1764 
1765 	if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) {
1766 #if 0
1767 		sc->sc_tx_capability |= OFFLOAD_TCPCKSUM;
1768 #endif
1769 		sc->sc_rx_capability |= OFFLOAD_TCPCKSUM;
1770 		ifp->if_capabilities |= IFCAP_HWCSUM;
1771 	}
1772 
1773 	if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) {
1774 #if 0
1775 		sc->sc_tx_capability |= OFFLOAD_UDPCKSUM;
1776 #endif
1777 		sc->sc_rx_capability |= OFFLOAD_UDPCKSUM;
1778 		ifp->if_capabilities |= IFCAP_HWCSUM;
1779 	}
1780 	ifp->if_capenable = ifp->if_capabilities;
1781 
1782 	if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0,
1783 	    sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1))
1784 		goto out;
1785 
1786 out:
1787 	if (rsp != NULL)
1788 		kfree(rsp, M_DEVBUF);
1789 
1790 	return;
1791 }
1792