1 /*-
2 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/param.h>
28 #include <sys/systm.h>
29 #include <sys/bus.h>
30 #include <sys/condvar.h>
31 #include <sys/kernel.h>
32 #include <sys/lock.h>
33 #include <sys/module.h>
34 #include <sys/mutex.h>
35 #include <sys/sbuf.h>
36 #include <sys/socket.h>
37 #include <sys/sysctl.h>
38 #include <sys/unistd.h>
39
40 #include <net/if.h>
41 #include <net/if_var.h>
42 #include <net/if_media.h>
43
44 /* needed for checksum offload */
45 #include <netinet/in.h>
46 #include <netinet/ip.h>
47
48 #include <dev/mii/mii.h>
49 #include <dev/mii/miivar.h>
50
51 #include <dev/usb/usb.h>
52 #include <dev/usb/usbdi.h>
53 #include <dev/usb/usbdi_util.h>
54 #include "usbdevs.h"
55
56 #define USB_DEBUG_VAR ure_debug
57 #include <dev/usb/usb_debug.h>
58 #include <dev/usb/usb_process.h>
59
60 #include <dev/usb/net/usb_ethernet.h>
61 #include <dev/usb/net/if_urereg.h>
62
63 #include "miibus_if.h"
64
65 #include "opt_inet6.h"
66
67 #ifdef USB_DEBUG
68 static int ure_debug = 0;
69
70 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
71 "USB ure");
72 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0,
73 "Debug level");
74 #endif
75
76 #ifdef USB_DEBUG_VAR
77 #ifdef USB_DEBUG
78 #define DEVPRINTFN(n,dev,fmt,...) do { \
79 if ((USB_DEBUG_VAR) >= (n)) { \
80 device_printf((dev), "%s: " fmt, \
81 __FUNCTION__ ,##__VA_ARGS__); \
82 } \
83 } while (0)
84 #define DEVPRINTF(...) DEVPRINTFN(1, __VA_ARGS__)
85 #else
86 #define DEVPRINTF(...) do { } while (0)
87 #define DEVPRINTFN(...) do { } while (0)
88 #endif
89 #endif
90
91 /*
92 * Various supported device vendors/products.
93 */
94 static const STRUCT_USB_HOST_ID ure_devs[] = {
95 #define URE_DEV(v,p,i) { \
96 USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i), \
97 USB_IFACE_CLASS(UICLASS_VENDOR), \
98 USB_IFACE_SUBCLASS(UISUBCLASS_VENDOR) }
99 URE_DEV(LENOVO, RTL8153, URE_FLAG_8153),
100 URE_DEV(LENOVO, TBT3LANGEN2, 0),
101 URE_DEV(LENOVO, ONELINK, 0),
102 URE_DEV(LENOVO, RTL8153_04, URE_FLAG_8153),
103 URE_DEV(LENOVO, USBCLAN, 0),
104 URE_DEV(LENOVO, USBCLANGEN2, 0),
105 URE_DEV(LENOVO, USBCLANHYBRID, 0),
106 URE_DEV(MICROSOFT, WINDEVETH, 0),
107 URE_DEV(NVIDIA, RTL8153, URE_FLAG_8153),
108 URE_DEV(REALTEK, RTL8152, URE_FLAG_8152),
109 URE_DEV(REALTEK, RTL8153, URE_FLAG_8153),
110 URE_DEV(TPLINK, RTL8153, URE_FLAG_8153),
111 URE_DEV(REALTEK, RTL8156, URE_FLAG_8156),
112 #undef URE_DEV
113 };
114
115 static device_probe_t ure_probe;
116 static device_attach_t ure_attach;
117 static device_detach_t ure_detach;
118
119 static usb_callback_t ure_bulk_read_callback;
120 static usb_callback_t ure_bulk_write_callback;
121
122 static miibus_readreg_t ure_miibus_readreg;
123 static miibus_writereg_t ure_miibus_writereg;
124 static miibus_statchg_t ure_miibus_statchg;
125
126 static uether_fn_t ure_attach_post;
127 static uether_fn_t ure_init;
128 static uether_fn_t ure_stop;
129 static uether_fn_t ure_start;
130 static uether_fn_t ure_tick;
131 static uether_fn_t ure_rxfilter;
132
133 static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t,
134 void *, int);
135 static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *,
136 int);
137 static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *,
138 int);
139 static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t);
140 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t);
141 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t);
142 static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t);
143 static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t);
144 static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t);
145 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t);
146 static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t);
147 static void ure_sram_write(struct ure_softc *, uint16_t, uint16_t);
148
149 static int ure_sysctl_chipver(SYSCTL_HANDLER_ARGS);
150
151 static void ure_read_chipver(struct ure_softc *);
152 static int ure_attach_post_sub(struct usb_ether *);
153 static void ure_reset(struct ure_softc *);
154 static int ure_ifmedia_upd(if_t);
155 static void ure_ifmedia_sts(if_t, struct ifmediareq *);
156 static void ure_add_media_types(struct ure_softc *);
157 static void ure_link_state(struct ure_softc *sc);
158 static int ure_get_link_status(struct ure_softc *);
159 static int ure_ioctl(if_t, u_long, caddr_t);
160 static void ure_rtl8152_init(struct ure_softc *);
161 static void ure_rtl8152_nic_reset(struct ure_softc *);
162 static void ure_rtl8153_init(struct ure_softc *);
163 static void ure_rtl8153b_init(struct ure_softc *);
164 static void ure_rtl8153b_nic_reset(struct ure_softc *);
165 static void ure_disable_teredo(struct ure_softc *);
166 static void ure_enable_aldps(struct ure_softc *, bool);
167 static uint16_t ure_phy_status(struct ure_softc *, uint16_t);
168 static void ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m);
169 static int ure_txcsum(struct mbuf *m, int caps, uint32_t *regout);
170
171 static device_method_t ure_methods[] = {
172 /* Device interface. */
173 DEVMETHOD(device_probe, ure_probe),
174 DEVMETHOD(device_attach, ure_attach),
175 DEVMETHOD(device_detach, ure_detach),
176
177 /* MII interface. */
178 DEVMETHOD(miibus_readreg, ure_miibus_readreg),
179 DEVMETHOD(miibus_writereg, ure_miibus_writereg),
180 DEVMETHOD(miibus_statchg, ure_miibus_statchg),
181
182 DEVMETHOD_END
183 };
184
185 static driver_t ure_driver = {
186 .name = "ure",
187 .methods = ure_methods,
188 .size = sizeof(struct ure_softc),
189 };
190
191 DRIVER_MODULE(ure, uhub, ure_driver, NULL, NULL);
192 DRIVER_MODULE(miibus, ure, miibus_driver, NULL, NULL);
193 MODULE_DEPEND(ure, uether, 1, 1, 1);
194 MODULE_DEPEND(ure, usb, 1, 1, 1);
195 MODULE_DEPEND(ure, ether, 1, 1, 1);
196 MODULE_DEPEND(ure, miibus, 1, 1, 1);
197 MODULE_VERSION(ure, 1);
198 USB_PNP_HOST_INFO(ure_devs);
199
200 static const struct usb_ether_methods ure_ue_methods = {
201 .ue_attach_post = ure_attach_post,
202 .ue_attach_post_sub = ure_attach_post_sub,
203 .ue_start = ure_start,
204 .ue_init = ure_init,
205 .ue_stop = ure_stop,
206 .ue_tick = ure_tick,
207 .ue_setmulti = ure_rxfilter,
208 .ue_setpromisc = ure_rxfilter,
209 .ue_mii_upd = ure_ifmedia_upd,
210 .ue_mii_sts = ure_ifmedia_sts,
211 };
212
213 #define URE_SETBIT_1(sc, reg, index, x) \
214 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x))
215 #define URE_SETBIT_2(sc, reg, index, x) \
216 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x))
217 #define URE_SETBIT_4(sc, reg, index, x) \
218 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x))
219
220 #define URE_CLRBIT_1(sc, reg, index, x) \
221 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x))
222 #define URE_CLRBIT_2(sc, reg, index, x) \
223 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x))
224 #define URE_CLRBIT_4(sc, reg, index, x) \
225 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x))
226
227 static int
ure_ctl(struct ure_softc * sc,uint8_t rw,uint16_t val,uint16_t index,void * buf,int len)228 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index,
229 void *buf, int len)
230 {
231 struct usb_device_request req;
232
233 URE_LOCK_ASSERT(sc, MA_OWNED);
234
235 if (rw == URE_CTL_WRITE)
236 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
237 else
238 req.bmRequestType = UT_READ_VENDOR_DEVICE;
239 req.bRequest = UR_SET_ADDRESS;
240 USETW(req.wValue, val);
241 USETW(req.wIndex, index);
242 USETW(req.wLength, len);
243
244 return (uether_do_request(&sc->sc_ue, &req, buf, 1000));
245 }
246
247 static int
ure_read_mem(struct ure_softc * sc,uint16_t addr,uint16_t index,void * buf,int len)248 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
249 void *buf, int len)
250 {
251
252 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len));
253 }
254
255 static int
ure_write_mem(struct ure_softc * sc,uint16_t addr,uint16_t index,void * buf,int len)256 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
257 void *buf, int len)
258 {
259
260 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len));
261 }
262
263 static uint8_t
ure_read_1(struct ure_softc * sc,uint16_t reg,uint16_t index)264 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index)
265 {
266 uint32_t val;
267 uint8_t temp[4];
268 uint8_t shift;
269
270 shift = (reg & 3) << 3;
271 reg &= ~3;
272
273 ure_read_mem(sc, reg, index, &temp, 4);
274 val = UGETDW(temp);
275 val >>= shift;
276
277 return (val & 0xff);
278 }
279
280 static uint16_t
ure_read_2(struct ure_softc * sc,uint16_t reg,uint16_t index)281 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index)
282 {
283 uint32_t val;
284 uint8_t temp[4];
285 uint8_t shift;
286
287 shift = (reg & 2) << 3;
288 reg &= ~3;
289
290 ure_read_mem(sc, reg, index, &temp, 4);
291 val = UGETDW(temp);
292 val >>= shift;
293
294 return (val & 0xffff);
295 }
296
297 static uint32_t
ure_read_4(struct ure_softc * sc,uint16_t reg,uint16_t index)298 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index)
299 {
300 uint8_t temp[4];
301
302 ure_read_mem(sc, reg, index, &temp, 4);
303 return (UGETDW(temp));
304 }
305
306 static int
ure_write_1(struct ure_softc * sc,uint16_t reg,uint16_t index,uint32_t val)307 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
308 {
309 uint16_t byen;
310 uint8_t temp[4];
311 uint8_t shift;
312
313 byen = URE_BYTE_EN_BYTE;
314 shift = reg & 3;
315 val &= 0xff;
316
317 if (reg & 3) {
318 byen <<= shift;
319 val <<= (shift << 3);
320 reg &= ~3;
321 }
322
323 USETDW(temp, val);
324 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
325 }
326
327 static int
ure_write_2(struct ure_softc * sc,uint16_t reg,uint16_t index,uint32_t val)328 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
329 {
330 uint16_t byen;
331 uint8_t temp[4];
332 uint8_t shift;
333
334 byen = URE_BYTE_EN_WORD;
335 shift = reg & 2;
336 val &= 0xffff;
337
338 if (reg & 2) {
339 byen <<= shift;
340 val <<= (shift << 3);
341 reg &= ~3;
342 }
343
344 USETDW(temp, val);
345 return (ure_write_mem(sc, reg, index | byen, &temp, 4));
346 }
347
348 static int
ure_write_4(struct ure_softc * sc,uint16_t reg,uint16_t index,uint32_t val)349 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
350 {
351 uint8_t temp[4];
352
353 USETDW(temp, val);
354 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4));
355 }
356
357 static uint16_t
ure_ocp_reg_read(struct ure_softc * sc,uint16_t addr)358 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr)
359 {
360 uint16_t reg;
361
362 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
363 reg = (addr & 0x0fff) | 0xb000;
364
365 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA));
366 }
367
368 static void
ure_ocp_reg_write(struct ure_softc * sc,uint16_t addr,uint16_t data)369 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
370 {
371 uint16_t reg;
372
373 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000);
374 reg = (addr & 0x0fff) | 0xb000;
375
376 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data);
377 }
378
379 static void
ure_sram_write(struct ure_softc * sc,uint16_t addr,uint16_t data)380 ure_sram_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
381 {
382 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, addr);
383 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, data);
384 }
385
386 static int
ure_miibus_readreg(device_t dev,int phy,int reg)387 ure_miibus_readreg(device_t dev, int phy, int reg)
388 {
389 struct ure_softc *sc;
390 uint16_t val;
391 int locked;
392
393 sc = device_get_softc(dev);
394 locked = mtx_owned(&sc->sc_mtx);
395 if (!locked)
396 URE_LOCK(sc);
397
398 /* Let the rgephy driver read the URE_GMEDIASTAT register. */
399 if (reg == URE_GMEDIASTAT) {
400 if (!locked)
401 URE_UNLOCK(sc);
402 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA));
403 }
404
405 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2);
406
407 if (!locked)
408 URE_UNLOCK(sc);
409 return (val);
410 }
411
412 static int
ure_miibus_writereg(device_t dev,int phy,int reg,int val)413 ure_miibus_writereg(device_t dev, int phy, int reg, int val)
414 {
415 struct ure_softc *sc;
416 int locked;
417
418 sc = device_get_softc(dev);
419 if (sc->sc_phyno != phy)
420 return (0);
421
422 locked = mtx_owned(&sc->sc_mtx);
423 if (!locked)
424 URE_LOCK(sc);
425
426 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val);
427
428 if (!locked)
429 URE_UNLOCK(sc);
430 return (0);
431 }
432
433 static void
ure_miibus_statchg(device_t dev)434 ure_miibus_statchg(device_t dev)
435 {
436 struct ure_softc *sc;
437 struct mii_data *mii;
438 if_t ifp;
439 int locked;
440
441 sc = device_get_softc(dev);
442 mii = GET_MII(sc);
443 locked = mtx_owned(&sc->sc_mtx);
444 if (!locked)
445 URE_LOCK(sc);
446
447 ifp = uether_getifp(&sc->sc_ue);
448 if (mii == NULL || ifp == NULL ||
449 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
450 goto done;
451
452 sc->sc_flags &= ~URE_FLAG_LINK;
453 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
454 (IFM_ACTIVE | IFM_AVALID)) {
455 switch (IFM_SUBTYPE(mii->mii_media_active)) {
456 case IFM_10_T:
457 case IFM_100_TX:
458 sc->sc_flags |= URE_FLAG_LINK;
459 sc->sc_rxstarted = 0;
460 break;
461 case IFM_1000_T:
462 if ((sc->sc_flags & URE_FLAG_8152) != 0)
463 break;
464 sc->sc_flags |= URE_FLAG_LINK;
465 sc->sc_rxstarted = 0;
466 break;
467 default:
468 break;
469 }
470 }
471
472 /* Lost link, do nothing. */
473 if ((sc->sc_flags & URE_FLAG_LINK) == 0)
474 goto done;
475 done:
476 if (!locked)
477 URE_UNLOCK(sc);
478 }
479
480 /*
481 * Probe for a RTL8152/RTL8153 chip.
482 */
483 static int
ure_probe(device_t dev)484 ure_probe(device_t dev)
485 {
486 struct usb_attach_arg *uaa;
487
488 uaa = device_get_ivars(dev);
489 if (uaa->usb_mode != USB_MODE_HOST)
490 return (ENXIO);
491 if (uaa->info.bIfaceIndex != URE_IFACE_IDX)
492 return (ENXIO);
493
494 return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa));
495 }
496
497 /*
498 * Attach the interface. Allocate softc structures, do ifmedia
499 * setup and ethernet/BPF attach.
500 */
501 static int
ure_attach(device_t dev)502 ure_attach(device_t dev)
503 {
504 struct usb_attach_arg *uaa = device_get_ivars(dev);
505 struct ure_softc *sc = device_get_softc(dev);
506 struct usb_ether *ue = &sc->sc_ue;
507 struct usb_config ure_config_rx[URE_MAX_RX];
508 struct usb_config ure_config_tx[URE_MAX_TX];
509 uint8_t iface_index;
510 int error;
511 int i;
512
513 sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
514 device_set_usb_desc(dev);
515 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
516
517 iface_index = URE_IFACE_IDX;
518
519 if (sc->sc_flags & (URE_FLAG_8153 | URE_FLAG_8153B))
520 sc->sc_rxbufsz = URE_8153_RX_BUFSZ;
521 else if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))
522 sc->sc_rxbufsz = URE_8156_RX_BUFSZ;
523 else
524 sc->sc_rxbufsz = URE_8152_RX_BUFSZ;
525
526 for (i = 0; i < URE_MAX_RX; i++) {
527 ure_config_rx[i] = (struct usb_config) {
528 .type = UE_BULK,
529 .endpoint = UE_ADDR_ANY,
530 .direction = UE_DIR_IN,
531 .bufsize = sc->sc_rxbufsz,
532 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
533 .callback = ure_bulk_read_callback,
534 .timeout = 0, /* no timeout */
535 };
536 }
537 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_rx_xfer,
538 ure_config_rx, URE_MAX_RX, sc, &sc->sc_mtx);
539 if (error != 0) {
540 device_printf(dev, "allocating USB RX transfers failed\n");
541 goto detach;
542 }
543
544 for (i = 0; i < URE_MAX_TX; i++) {
545 ure_config_tx[i] = (struct usb_config) {
546 .type = UE_BULK,
547 .endpoint = UE_ADDR_ANY,
548 .direction = UE_DIR_OUT,
549 .bufsize = URE_TX_BUFSZ,
550 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
551 .callback = ure_bulk_write_callback,
552 .timeout = 10000, /* 10 seconds */
553 };
554 }
555 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_tx_xfer,
556 ure_config_tx, URE_MAX_TX, sc, &sc->sc_mtx);
557 if (error != 0) {
558 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_MAX_RX);
559 device_printf(dev, "allocating USB TX transfers failed\n");
560 goto detach;
561 }
562
563 ue->ue_sc = sc;
564 ue->ue_dev = dev;
565 ue->ue_udev = uaa->device;
566 ue->ue_mtx = &sc->sc_mtx;
567 ue->ue_methods = &ure_ue_methods;
568
569 error = uether_ifattach(ue);
570 if (error != 0) {
571 device_printf(dev, "could not attach interface\n");
572 goto detach;
573 }
574 return (0); /* success */
575
576 detach:
577 ure_detach(dev);
578 return (ENXIO); /* failure */
579 }
580
581 static int
ure_detach(device_t dev)582 ure_detach(device_t dev)
583 {
584 struct ure_softc *sc = device_get_softc(dev);
585 struct usb_ether *ue = &sc->sc_ue;
586
587 usbd_transfer_unsetup(sc->sc_tx_xfer, URE_MAX_TX);
588 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_MAX_RX);
589 uether_ifdetach(ue);
590 mtx_destroy(&sc->sc_mtx);
591
592 return (0);
593 }
594
595 /*
596 * Copy from USB buffers to a new mbuf chain with pkt header.
597 *
598 * This will use m_getm2 to get a mbuf chain w/ properly sized mbuf
599 * clusters as necessary.
600 */
601 static struct mbuf *
ure_makembuf(struct usb_page_cache * pc,usb_frlength_t offset,usb_frlength_t len)602 ure_makembuf(struct usb_page_cache *pc, usb_frlength_t offset,
603 usb_frlength_t len)
604 {
605 struct usb_page_search_res;
606 struct mbuf *m, *mb;
607 usb_frlength_t tlen;
608
609 m = m_getm2(NULL, len + ETHER_ALIGN, M_NOWAIT, MT_DATA, M_PKTHDR);
610 if (m == NULL)
611 return (m);
612
613 /* uether_newbuf does this. */
614 m_adj(m, ETHER_ALIGN);
615
616 m->m_pkthdr.len = len;
617
618 for (mb = m; len > 0; mb = mb->m_next) {
619 tlen = MIN(len, M_TRAILINGSPACE(mb));
620
621 usbd_copy_out(pc, offset, mtod(mb, uint8_t *), tlen);
622 mb->m_len = tlen;
623
624 offset += tlen;
625 len -= tlen;
626 }
627
628 return (m);
629 }
630
631 static void
ure_bulk_read_callback(struct usb_xfer * xfer,usb_error_t error)632 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
633 {
634 struct ure_softc *sc = usbd_xfer_softc(xfer);
635 struct usb_ether *ue = &sc->sc_ue;
636 if_t ifp = uether_getifp(ue);
637 struct usb_page_cache *pc;
638 struct mbuf *m;
639 struct ure_rxpkt pkt;
640 int actlen, off, len;
641 int caps;
642 uint32_t pktcsum;
643
644 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
645
646 switch (USB_GET_STATE(xfer)) {
647 case USB_ST_TRANSFERRED:
648 off = 0;
649 pc = usbd_xfer_get_frame(xfer, 0);
650 caps = if_getcapenable(ifp);
651 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb start\n");
652 while (actlen > 0) {
653 if (actlen < (int)(sizeof(pkt))) {
654 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
655 goto tr_setup;
656 }
657 usbd_copy_out(pc, off, &pkt, sizeof(pkt));
658
659 off += sizeof(pkt);
660 actlen -= sizeof(pkt);
661
662 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK;
663
664 DEVPRINTFN(13, sc->sc_ue.ue_dev,
665 "rxpkt: %#x, %#x, %#x, %#x, %#x, %#x\n",
666 pkt.ure_pktlen, pkt.ure_csum, pkt.ure_misc,
667 pkt.ure_rsvd2, pkt.ure_rsvd3, pkt.ure_rsvd4);
668 DEVPRINTFN(13, sc->sc_ue.ue_dev, "len: %d\n", len);
669
670 if (len >= URE_RXPKT_LEN_MASK) {
671 /*
672 * drop the rest of this segment. With out
673 * more information, we cannot know where next
674 * packet starts. Blindly continuing would
675 * cause a packet in packet attack, allowing
676 * one VLAN to inject packets w/o a VLAN tag,
677 * or injecting packets into other VLANs.
678 */
679 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
680 goto tr_setup;
681 }
682
683 if (actlen < len) {
684 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
685 goto tr_setup;
686 }
687
688 if (len >= (ETHER_HDR_LEN + ETHER_CRC_LEN))
689 m = ure_makembuf(pc, off, len - ETHER_CRC_LEN);
690 else
691 m = NULL;
692 if (m == NULL) {
693 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
694 } else {
695 /* make mbuf and queue */
696 pktcsum = le32toh(pkt.ure_csum);
697 if (caps & IFCAP_VLAN_HWTAGGING &&
698 pktcsum & URE_RXPKT_RX_VLAN_TAG) {
699 m->m_pkthdr.ether_vtag =
700 bswap16(pktcsum &
701 URE_RXPKT_VLAN_MASK);
702 m->m_flags |= M_VLANTAG;
703 }
704
705 /* set the necessary flags for rx checksum */
706 ure_rxcsum(caps, &pkt, m);
707
708 uether_rxmbuf(ue, m, len - ETHER_CRC_LEN);
709 }
710
711 off += roundup(len, URE_RXPKT_ALIGN);
712 actlen -= roundup(len, URE_RXPKT_ALIGN);
713 }
714 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb end\n");
715
716 /* FALLTHROUGH */
717 case USB_ST_SETUP:
718 tr_setup:
719 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
720 usbd_transfer_submit(xfer);
721 uether_rxflush(ue);
722 return;
723
724 default: /* Error */
725 DPRINTF("bulk read error, %s\n",
726 usbd_errstr(error));
727
728 if (error != USB_ERR_CANCELLED) {
729 /* try to clear stall first */
730 usbd_xfer_set_stall(xfer);
731 goto tr_setup;
732 }
733 return;
734 }
735 }
736
737 static void
ure_bulk_write_callback(struct usb_xfer * xfer,usb_error_t error)738 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
739 {
740 struct ure_softc *sc = usbd_xfer_softc(xfer);
741 if_t ifp = uether_getifp(&sc->sc_ue);
742 struct usb_page_cache *pc;
743 struct mbuf *m;
744 struct ure_txpkt txpkt;
745 uint32_t regtmp;
746 int len, pos;
747 int rem;
748 int caps;
749
750 switch (USB_GET_STATE(xfer)) {
751 case USB_ST_TRANSFERRED:
752 DPRINTFN(11, "transfer complete\n");
753 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
754
755 /* FALLTHROUGH */
756 case USB_ST_SETUP:
757 tr_setup:
758 if ((sc->sc_flags & URE_FLAG_LINK) == 0) {
759 /* don't send anything if there is no link! */
760 break;
761 }
762
763 pc = usbd_xfer_get_frame(xfer, 0);
764 caps = if_getcapenable(ifp);
765
766 pos = 0;
767 rem = URE_TX_BUFSZ;
768 while (rem > sizeof(txpkt)) {
769 m = if_dequeue(ifp);
770 if (m == NULL)
771 break;
772
773 /*
774 * make sure we don't ever send too large of a
775 * packet
776 */
777 len = m->m_pkthdr.len;
778 if ((len & URE_TXPKT_LEN_MASK) != len) {
779 device_printf(sc->sc_ue.ue_dev,
780 "pkt len too large: %#x", len);
781 pkterror:
782 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
783 m_freem(m);
784 continue;
785 }
786
787 if (sizeof(txpkt) +
788 roundup(len, URE_TXPKT_ALIGN) > rem) {
789 /* out of space */
790 if_sendq_prepend(ifp, m);
791 m = NULL;
792 break;
793 }
794
795 txpkt = (struct ure_txpkt){};
796 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) |
797 URE_TKPKT_TX_FS | URE_TKPKT_TX_LS);
798 if (m->m_flags & M_VLANTAG) {
799 txpkt.ure_csum = htole32(
800 bswap16(m->m_pkthdr.ether_vtag &
801 URE_TXPKT_VLAN_MASK) | URE_TXPKT_VLAN);
802 }
803 if (ure_txcsum(m, caps, ®tmp)) {
804 device_printf(sc->sc_ue.ue_dev,
805 "pkt l4 off too large");
806 goto pkterror;
807 }
808 txpkt.ure_csum |= htole32(regtmp);
809
810 DEVPRINTFN(13, sc->sc_ue.ue_dev,
811 "txpkt: mbflg: %#x, %#x, %#x\n",
812 m->m_pkthdr.csum_flags, le32toh(txpkt.ure_pktlen),
813 le32toh(txpkt.ure_csum));
814
815 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt));
816
817 pos += sizeof(txpkt);
818 rem -= sizeof(txpkt);
819
820 usbd_m_copy_in(pc, pos, m, 0, len);
821
822 pos += roundup(len, URE_TXPKT_ALIGN);
823 rem -= roundup(len, URE_TXPKT_ALIGN);
824
825 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
826
827 /*
828 * If there's a BPF listener, bounce a copy
829 * of this frame to him.
830 */
831 BPF_MTAP(ifp, m);
832
833 m_freem(m);
834 }
835
836 /* no packets to send */
837 if (pos == 0)
838 break;
839
840 /* Set frame length. */
841 usbd_xfer_set_frame_len(xfer, 0, pos);
842
843 usbd_transfer_submit(xfer);
844
845 return;
846
847 default: /* Error */
848 DPRINTFN(11, "transfer error, %s\n",
849 usbd_errstr(error));
850
851 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
852 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
853
854 if (error == USB_ERR_TIMEOUT) {
855 DEVPRINTFN(12, sc->sc_ue.ue_dev,
856 "pkt tx timeout\n");
857 }
858
859 if (error != USB_ERR_CANCELLED) {
860 /* try to clear stall first */
861 usbd_xfer_set_stall(xfer);
862 goto tr_setup;
863 }
864 }
865 }
866
867 static void
ure_read_chipver(struct ure_softc * sc)868 ure_read_chipver(struct ure_softc *sc)
869 {
870 uint16_t ver;
871
872 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK;
873 sc->sc_ver = ver;
874 switch (ver) {
875 case 0x4c00:
876 sc->sc_chip |= URE_CHIP_VER_4C00;
877 sc->sc_flags = URE_FLAG_8152;
878 break;
879 case 0x4c10:
880 sc->sc_chip |= URE_CHIP_VER_4C10;
881 sc->sc_flags = URE_FLAG_8152;
882 break;
883 case 0x5c00:
884 sc->sc_chip |= URE_CHIP_VER_5C00;
885 sc->sc_flags = URE_FLAG_8153;
886 break;
887 case 0x5c10:
888 sc->sc_chip |= URE_CHIP_VER_5C10;
889 sc->sc_flags = URE_FLAG_8153;
890 break;
891 case 0x5c20:
892 sc->sc_chip |= URE_CHIP_VER_5C20;
893 sc->sc_flags = URE_FLAG_8153;
894 break;
895 case 0x5c30:
896 sc->sc_chip |= URE_CHIP_VER_5C30;
897 sc->sc_flags = URE_FLAG_8153;
898 break;
899 case 0x6000:
900 sc->sc_flags = URE_FLAG_8153B;
901 sc->sc_chip |= URE_CHIP_VER_6000;
902 break;
903 case 0x6010:
904 sc->sc_flags = URE_FLAG_8153B;
905 sc->sc_chip |= URE_CHIP_VER_6010;
906 break;
907 case 0x7020:
908 sc->sc_flags = URE_FLAG_8156;
909 sc->sc_chip |= URE_CHIP_VER_7020;
910 break;
911 case 0x7030:
912 sc->sc_flags = URE_FLAG_8156;
913 sc->sc_chip |= URE_CHIP_VER_7030;
914 break;
915 case 0x7400:
916 sc->sc_flags = URE_FLAG_8156B;
917 sc->sc_chip |= URE_CHIP_VER_7400;
918 break;
919 case 0x7410:
920 sc->sc_flags = URE_FLAG_8156B;
921 sc->sc_chip |= URE_CHIP_VER_7410;
922 break;
923 default:
924 device_printf(sc->sc_ue.ue_dev,
925 "unknown version 0x%04x\n", ver);
926 break;
927 }
928 }
929
930 static int
ure_sysctl_chipver(SYSCTL_HANDLER_ARGS)931 ure_sysctl_chipver(SYSCTL_HANDLER_ARGS)
932 {
933 struct sbuf sb;
934 struct ure_softc *sc = arg1;
935 int error;
936
937 sbuf_new_for_sysctl(&sb, NULL, 0, req);
938
939 sbuf_printf(&sb, "%04x", sc->sc_ver);
940
941 error = sbuf_finish(&sb);
942 sbuf_delete(&sb);
943
944 return (error);
945 }
946
947 static void
ure_attach_post(struct usb_ether * ue)948 ure_attach_post(struct usb_ether *ue)
949 {
950 struct ure_softc *sc = uether_getsc(ue);
951
952 sc->sc_rxstarted = 0;
953 sc->sc_phyno = 0;
954
955 /* Determine the chip version. */
956 ure_read_chipver(sc);
957
958 /* Initialize controller and get station address. */
959 if (sc->sc_flags & URE_FLAG_8152)
960 ure_rtl8152_init(sc);
961 else if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B))
962 ure_rtl8153b_init(sc);
963 else
964 ure_rtl8153_init(sc);
965
966 if ((sc->sc_chip & URE_CHIP_VER_4C00) ||
967 (sc->sc_chip & URE_CHIP_VER_4C10))
968 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA,
969 ue->ue_eaddr, 8);
970 else
971 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA,
972 ue->ue_eaddr, 8);
973
974 if (ETHER_IS_ZERO(sc->sc_ue.ue_eaddr)) {
975 device_printf(sc->sc_ue.ue_dev, "MAC assigned randomly\n");
976 arc4rand(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN, 0);
977 sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */
978 sc->sc_ue.ue_eaddr[0] |= 0x02; /* locally administered */
979 }
980 }
981
982 static int
ure_attach_post_sub(struct usb_ether * ue)983 ure_attach_post_sub(struct usb_ether *ue)
984 {
985 struct sysctl_ctx_list *sctx;
986 struct sysctl_oid *soid;
987 struct ure_softc *sc;
988 if_t ifp;
989 int error;
990
991 sc = uether_getsc(ue);
992 ifp = ue->ue_ifp;
993 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
994 if_setstartfn(ifp, uether_start);
995 if_setioctlfn(ifp, ure_ioctl);
996 if_setinitfn(ifp, uether_init);
997 /*
998 * Try to keep two transfers full at a time.
999 * ~(TRANSFER_SIZE / 80 bytes/pkt * 2 buffers in flight)
1000 */
1001 if_setsendqlen(ifp, 512);
1002 if_setsendqready(ifp);
1003
1004 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0);
1005 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING, 0);
1006 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM|IFCAP_HWCSUM, 0);
1007 if_sethwassist(ifp, CSUM_IP|CSUM_IP_UDP|CSUM_IP_TCP);
1008 #ifdef INET6
1009 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM_IPV6, 0);
1010 #endif
1011 if_setcapenable(ifp, if_getcapabilities(ifp));
1012
1013 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1014 ifmedia_init(&sc->sc_ifmedia, IFM_IMASK, ure_ifmedia_upd,
1015 ure_ifmedia_sts);
1016 ure_add_media_types(sc);
1017 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
1018 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO);
1019 sc->sc_ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
1020 error = 0;
1021 } else {
1022 bus_topo_lock();
1023 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
1024 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
1025 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0);
1026 bus_topo_unlock();
1027 }
1028
1029 sctx = device_get_sysctl_ctx(sc->sc_ue.ue_dev);
1030 soid = device_get_sysctl_tree(sc->sc_ue.ue_dev);
1031 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "chipver",
1032 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0,
1033 ure_sysctl_chipver, "A",
1034 "Return string with chip version.");
1035
1036 return (error);
1037 }
1038
1039 static void
ure_init(struct usb_ether * ue)1040 ure_init(struct usb_ether *ue)
1041 {
1042 struct ure_softc *sc = uether_getsc(ue);
1043 if_t ifp = uether_getifp(ue);
1044 uint16_t cpcr;
1045 uint32_t reg;
1046
1047 URE_LOCK_ASSERT(sc, MA_OWNED);
1048
1049 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1050 return;
1051
1052 /* Cancel pending I/O. */
1053 ure_stop(ue);
1054
1055 if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B))
1056 ure_rtl8153b_nic_reset(sc);
1057 else
1058 ure_reset(sc);
1059
1060 /* Set MAC address. */
1061 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG);
1062 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES,
1063 if_getlladdr(ifp), 8);
1064 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML);
1065
1066 /* Set RX EARLY timeout and size */
1067 if (sc->sc_flags & URE_FLAG_8153) {
1068 switch (usbd_get_speed(sc->sc_ue.ue_udev)) {
1069 case USB_SPEED_SUPER:
1070 reg = URE_COALESCE_SUPER / 8;
1071 break;
1072 case USB_SPEED_HIGH:
1073 reg = URE_COALESCE_HIGH / 8;
1074 break;
1075 default:
1076 reg = URE_COALESCE_SLOW / 8;
1077 break;
1078 }
1079 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, reg);
1080 reg = URE_8153_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) +
1081 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN);
1082 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 4);
1083 } else if (sc->sc_flags & URE_FLAG_8153B) {
1084 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 158);
1085 ure_write_2(sc, URE_USB_RX_EXTRA_AGG_TMR, URE_MCU_TYPE_USB, 1875);
1086 reg = URE_8153_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) +
1087 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN);
1088 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 8);
1089 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB,
1090 URE_OWN_UPDATE | URE_OWN_CLEAR);
1091 } else if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1092 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 80);
1093 ure_write_2(sc, URE_USB_RX_EXTRA_AGG_TMR, URE_MCU_TYPE_USB, 1875);
1094 reg = URE_8156_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) +
1095 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN);
1096 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 8);
1097 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB,
1098 URE_OWN_UPDATE | URE_OWN_CLEAR);
1099 }
1100
1101 if (sc->sc_flags & URE_FLAG_8156B) {
1102 URE_CLRBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK);
1103 uether_pause(&sc->sc_ue, hz / 500);
1104 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK);
1105 }
1106
1107 /* Reset the packet filter. */
1108 URE_CLRBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN);
1109 URE_SETBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN);
1110
1111 /* Enable RX VLANs if enabled */
1112 cpcr = ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA);
1113 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) {
1114 DEVPRINTFN(12, sc->sc_ue.ue_dev, "enabled hw vlan tag\n");
1115 cpcr |= URE_CPCR_RX_VLAN;
1116 } else {
1117 DEVPRINTFN(12, sc->sc_ue.ue_dev, "disabled hw vlan tag\n");
1118 cpcr &= ~URE_CPCR_RX_VLAN;
1119 }
1120 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, cpcr);
1121
1122 /* Enable transmit and receive. */
1123 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE);
1124
1125 URE_CLRBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN);
1126
1127 /* Configure RX filters. */
1128 ure_rxfilter(ue);
1129
1130 usbd_xfer_set_stall(sc->sc_tx_xfer[0]);
1131
1132 /* Indicate we are up and running. */
1133 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
1134
1135 /* Switch to selected media. */
1136 ure_ifmedia_upd(ifp);
1137 }
1138
1139 static void
ure_tick(struct usb_ether * ue)1140 ure_tick(struct usb_ether *ue)
1141 {
1142 struct ure_softc *sc = uether_getsc(ue);
1143 if_t ifp = uether_getifp(ue);
1144 struct mii_data *mii;
1145
1146 URE_LOCK_ASSERT(sc, MA_OWNED);
1147
1148 (void)ifp;
1149 for (int i = 0; i < URE_MAX_RX; i++)
1150 DEVPRINTFN(13, sc->sc_ue.ue_dev,
1151 "rx[%d] = %d\n", i, USB_GET_STATE(sc->sc_rx_xfer[i]));
1152
1153 for (int i = 0; i < URE_MAX_TX; i++)
1154 DEVPRINTFN(13, sc->sc_ue.ue_dev,
1155 "tx[%d] = %d\n", i, USB_GET_STATE(sc->sc_tx_xfer[i]));
1156
1157 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1158 ure_link_state(sc);
1159 } else {
1160 mii = GET_MII(sc);
1161 mii_tick(mii);
1162 if ((sc->sc_flags & URE_FLAG_LINK) == 0
1163 && mii->mii_media_status & IFM_ACTIVE &&
1164 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1165 sc->sc_flags |= URE_FLAG_LINK;
1166 sc->sc_rxstarted = 0;
1167 ure_start(ue);
1168 }
1169 }
1170 }
1171
1172 static u_int
ure_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)1173 ure_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1174 {
1175 uint32_t h, *hashes = arg;
1176
1177 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
1178 if (h < 32)
1179 hashes[0] |= (1 << h);
1180 else
1181 hashes[1] |= (1 << (h - 32));
1182 return (1);
1183 }
1184
1185 /*
1186 * Program the 64-bit multicast hash filter.
1187 */
1188 static void
ure_rxfilter(struct usb_ether * ue)1189 ure_rxfilter(struct usb_ether *ue)
1190 {
1191 struct ure_softc *sc = uether_getsc(ue);
1192 if_t ifp = uether_getifp(ue);
1193 uint32_t rxmode;
1194 uint32_t h, hashes[2] = { 0, 0 };
1195
1196 URE_LOCK_ASSERT(sc, MA_OWNED);
1197
1198 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA);
1199 rxmode &= ~(URE_RCR_AAP | URE_RCR_AM);
1200 rxmode |= URE_RCR_APM; /* accept physical match packets */
1201 rxmode |= URE_RCR_AB; /* always accept broadcasts */
1202 if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) {
1203 if (if_getflags(ifp) & IFF_PROMISC)
1204 rxmode |= URE_RCR_AAP;
1205 rxmode |= URE_RCR_AM;
1206 hashes[0] = hashes[1] = 0xffffffff;
1207 goto done;
1208 }
1209
1210 /* calculate multicast masks */
1211 if_foreach_llmaddr(ifp, ure_hash_maddr, &hashes);
1212
1213 h = bswap32(hashes[0]);
1214 hashes[0] = bswap32(hashes[1]);
1215 hashes[1] = h;
1216 rxmode |= URE_RCR_AM; /* accept multicast packets */
1217
1218 done:
1219 DEVPRINTFN(14, ue->ue_dev, "rxfilt: RCR: %#x\n",
1220 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA));
1221 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]);
1222 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]);
1223 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode);
1224 }
1225
1226 static void
ure_start(struct usb_ether * ue)1227 ure_start(struct usb_ether *ue)
1228 {
1229 struct ure_softc *sc = uether_getsc(ue);
1230 unsigned i;
1231
1232 URE_LOCK_ASSERT(sc, MA_OWNED);
1233
1234 if (!sc->sc_rxstarted) {
1235 sc->sc_rxstarted = 1;
1236 for (i = 0; i != URE_MAX_RX; i++)
1237 usbd_transfer_start(sc->sc_rx_xfer[i]);
1238 }
1239
1240 for (i = 0; i != URE_MAX_TX; i++)
1241 usbd_transfer_start(sc->sc_tx_xfer[i]);
1242 }
1243
1244 static void
ure_reset(struct ure_softc * sc)1245 ure_reset(struct ure_softc *sc)
1246 {
1247 int i;
1248
1249 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST);
1250
1251 for (i = 0; i < URE_TIMEOUT; i++) {
1252 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) &
1253 URE_CR_RST))
1254 break;
1255 uether_pause(&sc->sc_ue, hz / 100);
1256 }
1257 if (i == URE_TIMEOUT)
1258 device_printf(sc->sc_ue.ue_dev, "reset never completed\n");
1259 }
1260
1261 /*
1262 * Set media options.
1263 */
1264 static int
ure_ifmedia_upd(if_t ifp)1265 ure_ifmedia_upd(if_t ifp)
1266 {
1267 struct ure_softc *sc = if_getsoftc(ifp);
1268 struct ifmedia *ifm;
1269 struct mii_data *mii;
1270 struct mii_softc *miisc;
1271 int gig;
1272 int reg;
1273 int anar;
1274 int locked;
1275 int error;
1276
1277 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1278 ifm = &sc->sc_ifmedia;
1279 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1280 return (EINVAL);
1281
1282 locked = mtx_owned(&sc->sc_mtx);
1283 if (!locked)
1284 URE_LOCK(sc);
1285 reg = ure_ocp_reg_read(sc, 0xa5d4);
1286 reg &= ~URE_ADV_2500TFDX;
1287
1288 anar = gig = 0;
1289 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1290 case IFM_AUTO:
1291 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
1292 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
1293 reg |= URE_ADV_2500TFDX;
1294 break;
1295 case IFM_2500_T:
1296 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
1297 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
1298 reg |= URE_ADV_2500TFDX;
1299 if_setbaudrate(ifp, IF_Mbps(2500));
1300 break;
1301 case IFM_1000_T:
1302 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
1303 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
1304 if_setbaudrate(ifp, IF_Gbps(1));
1305 break;
1306 case IFM_100_TX:
1307 anar |= ANAR_TX | ANAR_TX_FD;
1308 if_setbaudrate(ifp, IF_Mbps(100));
1309 break;
1310 case IFM_10_T:
1311 anar |= ANAR_10 | ANAR_10_FD;
1312 if_setbaudrate(ifp, IF_Mbps(10));
1313 break;
1314 default:
1315 device_printf(sc->sc_ue.ue_dev, "unsupported media type\n");
1316 if (!locked)
1317 URE_UNLOCK(sc);
1318 return (EINVAL);
1319 }
1320
1321 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_ANAR * 2,
1322 anar | ANAR_PAUSE_ASYM | ANAR_FC);
1323 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_100T2CR * 2, gig);
1324 ure_ocp_reg_write(sc, 0xa5d4, reg);
1325 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR,
1326 BMCR_AUTOEN | BMCR_STARTNEG);
1327 if (!locked)
1328 URE_UNLOCK(sc);
1329 return (0);
1330 }
1331
1332 mii = GET_MII(sc);
1333
1334 URE_LOCK_ASSERT(sc, MA_OWNED);
1335 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1336 PHY_RESET(miisc);
1337 error = mii_mediachg(mii);
1338 return (error);
1339 }
1340
1341 /*
1342 * Report current media status.
1343 */
1344 static void
ure_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)1345 ure_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1346 {
1347 struct ure_softc *sc;
1348 struct mii_data *mii;
1349 uint16_t status;
1350
1351 sc = if_getsoftc(ifp);
1352 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1353 URE_LOCK(sc);
1354 ifmr->ifm_status = IFM_AVALID;
1355 if (ure_get_link_status(sc)) {
1356 ifmr->ifm_status |= IFM_ACTIVE;
1357 status = ure_read_2(sc, URE_PLA_PHYSTATUS,
1358 URE_MCU_TYPE_PLA);
1359 if ((status & URE_PHYSTATUS_FDX) ||
1360 (status & URE_PHYSTATUS_2500MBPS))
1361 ifmr->ifm_active |= IFM_FDX;
1362 else
1363 ifmr->ifm_active |= IFM_HDX;
1364 if (status & URE_PHYSTATUS_10MBPS)
1365 ifmr->ifm_active |= IFM_10_T;
1366 else if (status & URE_PHYSTATUS_100MBPS)
1367 ifmr->ifm_active |= IFM_100_TX;
1368 else if (status & URE_PHYSTATUS_1000MBPS)
1369 ifmr->ifm_active |= IFM_1000_T;
1370 else if (status & URE_PHYSTATUS_2500MBPS)
1371 ifmr->ifm_active |= IFM_2500_T;
1372 }
1373 URE_UNLOCK(sc);
1374 return;
1375 }
1376
1377 mii = GET_MII(sc);
1378
1379 URE_LOCK(sc);
1380 mii_pollstat(mii);
1381 ifmr->ifm_active = mii->mii_media_active;
1382 ifmr->ifm_status = mii->mii_media_status;
1383 URE_UNLOCK(sc);
1384 }
1385
1386 static void
ure_add_media_types(struct ure_softc * sc)1387 ure_add_media_types(struct ure_softc *sc)
1388 {
1389 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
1390 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
1391 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
1392 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
1393 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1394 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, NULL);
1395 }
1396
1397 static void
ure_link_state(struct ure_softc * sc)1398 ure_link_state(struct ure_softc *sc)
1399 {
1400 if_t ifp = uether_getifp(&sc->sc_ue);
1401
1402 if (ure_get_link_status(sc)) {
1403 if (if_getlinkstate(ifp) != LINK_STATE_UP) {
1404 if_link_state_change(ifp, LINK_STATE_UP);
1405 /* Enable transmit and receive. */
1406 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE);
1407
1408 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) &
1409 URE_PHYSTATUS_2500MBPS)
1410 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40);
1411 else
1412 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40);
1413 }
1414 } else {
1415 if (if_getlinkstate(ifp) != LINK_STATE_DOWN) {
1416 if_link_state_change(ifp, LINK_STATE_DOWN);
1417 }
1418 }
1419 }
1420
1421 static int
ure_get_link_status(struct ure_softc * sc)1422 ure_get_link_status(struct ure_softc *sc)
1423 {
1424 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) &
1425 URE_PHYSTATUS_LINK) {
1426 sc->sc_flags |= URE_FLAG_LINK;
1427 return (1);
1428 } else {
1429 sc->sc_flags &= ~URE_FLAG_LINK;
1430 return (0);
1431 }
1432 }
1433
1434 static int
ure_ioctl(if_t ifp,u_long cmd,caddr_t data)1435 ure_ioctl(if_t ifp, u_long cmd, caddr_t data)
1436 {
1437 struct usb_ether *ue = if_getsoftc(ifp);
1438 struct ure_softc *sc;
1439 struct ifreq *ifr;
1440 int error, mask, reinit;
1441
1442 sc = uether_getsc(ue);
1443 ifr = (struct ifreq *)data;
1444 error = 0;
1445 reinit = 0;
1446 switch (cmd) {
1447 case SIOCSIFCAP:
1448 URE_LOCK(sc);
1449 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1450 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1451 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
1452 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
1453 reinit++;
1454 }
1455 if ((mask & IFCAP_TXCSUM) != 0 &&
1456 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
1457 if_togglecapenable(ifp, IFCAP_TXCSUM);
1458 }
1459 if ((mask & IFCAP_RXCSUM) != 0 &&
1460 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) {
1461 if_togglecapenable(ifp, IFCAP_RXCSUM);
1462 }
1463 if ((mask & IFCAP_TXCSUM_IPV6) != 0 &&
1464 (if_getcapabilities(ifp) & IFCAP_TXCSUM_IPV6) != 0) {
1465 if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6);
1466 }
1467 if ((mask & IFCAP_RXCSUM_IPV6) != 0 &&
1468 (if_getcapabilities(ifp) & IFCAP_RXCSUM_IPV6) != 0) {
1469 if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6);
1470 }
1471 if (reinit > 0 && if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1472 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1473 else
1474 reinit = 0;
1475 URE_UNLOCK(sc);
1476 if (reinit > 0)
1477 uether_init(ue);
1478 break;
1479
1480 case SIOCSIFMTU:
1481 /*
1482 * in testing large MTUs "crashes" the device, it
1483 * leaves the device w/ a broken state where link
1484 * is in a bad state.
1485 */
1486 if (ifr->ifr_mtu < ETHERMIN ||
1487 ifr->ifr_mtu > (4096 - ETHER_HDR_LEN -
1488 ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)) {
1489 error = EINVAL;
1490 break;
1491 }
1492 URE_LOCK(sc);
1493 if (if_getmtu(ifp) != ifr->ifr_mtu)
1494 if_setmtu(ifp, ifr->ifr_mtu);
1495 URE_UNLOCK(sc);
1496 break;
1497
1498 case SIOCGIFMEDIA:
1499 case SIOCSIFMEDIA:
1500 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))
1501 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd);
1502 else
1503 error = uether_ioctl(ifp, cmd, data);
1504 break;
1505
1506 default:
1507 error = uether_ioctl(ifp, cmd, data);
1508 break;
1509 }
1510
1511 return (error);
1512 }
1513
1514 static void
ure_rtl8152_init(struct ure_softc * sc)1515 ure_rtl8152_init(struct ure_softc *sc)
1516 {
1517 uint32_t pwrctrl;
1518
1519 ure_enable_aldps(sc, false);
1520
1521 if (sc->sc_chip & URE_CHIP_VER_4C00) {
1522 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, URE_LED_MODE_MASK);
1523 }
1524
1525 URE_CLRBIT_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, URE_POWER_CUT);
1526
1527 URE_CLRBIT_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, URE_RESUME_INDICATE);
1528
1529 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH);
1530
1531 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA);
1532 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK;
1533 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN;
1534 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl);
1535 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA,
1536 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK |
1537 URE_SPDWN_LINKCHG_MSK);
1538
1539 /* Enable Rx aggregation. */
1540 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN);
1541
1542 ure_enable_aldps(sc, false);
1543
1544 ure_rtl8152_nic_reset(sc);
1545
1546 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB,
1547 URE_TX_AGG_MAX_THRESHOLD);
1548 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH);
1549 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB,
1550 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1);
1551 }
1552
1553 static void
ure_rtl8153_init(struct ure_softc * sc)1554 ure_rtl8153_init(struct ure_softc *sc)
1555 {
1556 uint16_t val;
1557 uint8_t u1u2[8];
1558 int i;
1559
1560 ure_enable_aldps(sc, false);
1561
1562 memset(u1u2, 0x00, sizeof(u1u2));
1563 ure_write_mem(sc, URE_USB_TOLERANCE,
1564 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1565
1566 for (i = 0; i < URE_TIMEOUT; i++) {
1567 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) &
1568 URE_AUTOLOAD_DONE)
1569 break;
1570 uether_pause(&sc->sc_ue, hz / 100);
1571 }
1572 if (i == URE_TIMEOUT)
1573 device_printf(sc->sc_ue.ue_dev,
1574 "timeout waiting for chip autoload\n");
1575
1576 for (i = 0; i < URE_TIMEOUT; i++) {
1577 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) &
1578 URE_PHY_STAT_MASK;
1579 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN)
1580 break;
1581 uether_pause(&sc->sc_ue, hz / 100);
1582 }
1583 if (i == URE_TIMEOUT)
1584 device_printf(sc->sc_ue.ue_dev,
1585 "timeout waiting for phy to stabilize\n");
1586
1587 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
1588
1589 if (sc->sc_chip & URE_CHIP_VER_5C10) {
1590 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB);
1591 val &= ~URE_PWD_DN_SCALE_MASK;
1592 val |= URE_PWD_DN_SCALE(96);
1593 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val);
1594
1595 URE_SETBIT_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND);
1596 } else if (sc->sc_chip & URE_CHIP_VER_5C20)
1597 URE_CLRBIT_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, URE_ECM_ALDPS);
1598
1599 if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) {
1600 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB);
1601 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) ==
1602 0)
1603 val &= ~URE_DYNAMIC_BURST;
1604 else
1605 val |= URE_DYNAMIC_BURST;
1606 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val);
1607 }
1608
1609 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, URE_EP4_FULL_FC);
1610
1611 URE_CLRBIT_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, URE_TIMER11_EN);
1612
1613 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, URE_LED_MODE_MASK);
1614
1615 if ((sc->sc_chip & URE_CHIP_VER_5C10) &&
1616 usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER)
1617 val = URE_LPM_TIMER_500MS;
1618 else
1619 val = URE_LPM_TIMER_500US;
1620 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB,
1621 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM);
1622
1623 val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB);
1624 val &= ~URE_SEN_VAL_MASK;
1625 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE;
1626 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val);
1627
1628 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001);
1629
1630 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN | URE_PHASE2_EN);
1631
1632 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS);
1633
1634 memset(u1u2, 0xff, sizeof(u1u2));
1635 ure_write_mem(sc, URE_USB_TOLERANCE,
1636 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1637
1638 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA,
1639 URE_ALDPS_SPDWN_RATIO);
1640 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA,
1641 URE_EEE_SPDWN_RATIO);
1642 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA,
1643 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN |
1644 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN);
1645 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA,
1646 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN |
1647 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN |
1648 URE_EEE_SPDWN_EN);
1649
1650 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1651 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1652 val |= URE_U2P3_ENABLE;
1653 else
1654 val &= ~URE_U2P3_ENABLE;
1655 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1656
1657 memset(u1u2, 0x00, sizeof(u1u2));
1658 ure_write_mem(sc, URE_USB_TOLERANCE,
1659 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1660
1661 ure_enable_aldps(sc, false);
1662
1663 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 |
1664 URE_CHIP_VER_5C20)) {
1665 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG,
1666 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L);
1667 }
1668 if (sc->sc_chip & URE_CHIP_VER_5C00) {
1669 ure_ocp_reg_write(sc, URE_OCP_EEE_CFG,
1670 ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) &
1671 ~URE_CTAP_SHORT_EN);
1672 }
1673 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1674 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1675 URE_EEE_CLKDIV_EN);
1676 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED,
1677 ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) |
1678 URE_EN_10M_BGOFF);
1679 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
1680 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
1681 URE_EN_10M_PLLOFF);
1682 ure_sram_write(sc, URE_SRAM_IMPEDANCE, 0x0b13);
1683 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, URE_PFM_PWM_SWITCH);
1684
1685 /* Enable LPF corner auto tune. */
1686 ure_sram_write(sc, URE_SRAM_LPF_CFG, 0xf70f);
1687
1688 /* Adjust 10M amplitude. */
1689 ure_sram_write(sc, URE_SRAM_10M_AMP1, 0x00af);
1690 ure_sram_write(sc, URE_SRAM_10M_AMP2, 0x0208);
1691
1692 ure_rtl8152_nic_reset(sc);
1693
1694 /* Enable Rx aggregation. */
1695 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN);
1696
1697 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
1698 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
1699 val |= URE_U2P3_ENABLE;
1700 else
1701 val &= ~URE_U2P3_ENABLE;
1702 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
1703
1704 memset(u1u2, 0xff, sizeof(u1u2));
1705 ure_write_mem(sc, URE_USB_TOLERANCE,
1706 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
1707 }
1708
1709 static void
ure_rtl8153b_init(struct ure_softc * sc)1710 ure_rtl8153b_init(struct ure_softc *sc)
1711 {
1712 uint16_t val;
1713 int i;
1714
1715 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1716 URE_CLRBIT_1(sc, 0xd26b, URE_MCU_TYPE_USB, 0x01);
1717 ure_write_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0);
1718 URE_SETBIT_2(sc, 0xcfee, URE_MCU_TYPE_USB, 0x0020);
1719 }
1720
1721 if (sc->sc_flags & URE_FLAG_8156B) {
1722 URE_SETBIT_2(sc, 0xb460, URE_MCU_TYPE_USB, 0x08);
1723 }
1724
1725 ure_enable_aldps(sc, false);
1726
1727 /* Disable U1U2 */
1728 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN);
1729
1730 /* Wait loading flash */
1731 if (sc->sc_chip == URE_CHIP_VER_7410) {
1732 if ((ure_read_2(sc, 0xd3ae, URE_MCU_TYPE_PLA) & 0x0002) &&
1733 !(ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0020)) {
1734 for (i=0; i < 100; i++) {
1735 if (ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0004)
1736 break;
1737 uether_pause(&sc->sc_ue, hz / 1000);
1738 }
1739 }
1740 }
1741
1742 for (i = 0; i < URE_TIMEOUT; i++) {
1743 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) &
1744 URE_AUTOLOAD_DONE)
1745 break;
1746 uether_pause(&sc->sc_ue, hz / 100);
1747 }
1748 if (i == URE_TIMEOUT)
1749 device_printf(sc->sc_ue.ue_dev,
1750 "timeout waiting for chip autoload\n");
1751
1752 val = ure_phy_status(sc, 0);
1753 if ((val == URE_PHY_STAT_EXT_INIT) &
1754 (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) {
1755 ure_ocp_reg_write(sc, 0xa468,
1756 ure_ocp_reg_read(sc, 0xa468) & ~0x0a);
1757 if (sc->sc_flags & URE_FLAG_8156B)
1758 ure_ocp_reg_write(sc, 0xa466,
1759 ure_ocp_reg_read(sc, 0xa466) & ~0x01);
1760 }
1761
1762 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + MII_BMCR);
1763 if (val & BMCR_PDOWN) {
1764 val &= ~BMCR_PDOWN;
1765 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR, val);
1766 }
1767
1768 ure_phy_status(sc, URE_PHY_STAT_LAN_ON);
1769
1770 /* Disable U2P3 */
1771 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
1772
1773 /* MSC timer, 32760 ms. */
1774 ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 0x0fff);
1775
1776 /* U1/U2/L1 idle timer, 500 us. */
1777 ure_write_2(sc, URE_USB_U1U2_TIMER, URE_MCU_TYPE_USB, 500);
1778
1779 /* Disable power cut */
1780 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN);
1781 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS);
1782
1783 /* Disable ups */
1784 URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_UPS_EN | URE_USP_PREWAKE);
1785 URE_CLRBIT_1(sc, 0xcfff, URE_MCU_TYPE_USB, 0x01);
1786
1787 /* Disable queue wake */
1788 URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_USB, URE_UPCOMING_RUNTIME_D3);
1789 URE_CLRBIT_1(sc, URE_PLA_SUSPEND_FLAG, URE_MCU_TYPE_USB, URE_LINK_CHG_EVENT);
1790 URE_CLRBIT_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_USB, URE_LINK_CHANGE_FLAG);
1791
1792 /* Disable runtime suspend */
1793 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG);
1794 URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_USB, URE_LINK_OFF_WAKE_EN);
1795 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML);
1796
1797 /* Enable U1U2 */
1798 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_SUPER)
1799 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN);
1800
1801 if (sc->sc_flags & URE_FLAG_8156B) {
1802 URE_CLRBIT_2(sc, 0xc010, URE_MCU_TYPE_PLA, 0x0800);
1803 URE_SETBIT_2(sc, 0xe854, URE_MCU_TYPE_PLA, 0x0001);
1804
1805 /* enable fc timer and set timer to 600 ms. */
1806 ure_write_2(sc, URE_USB_FC_TIMER, URE_MCU_TYPE_USB, URE_CTRL_TIMER_EN | (600 / 8));
1807
1808 if (!(ure_read_1(sc, 0xdc6b, URE_MCU_TYPE_PLA) & 0x80)) {
1809 val = ure_read_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB);
1810 val |= URE_FLOW_CTRL_PATCH_OPT | 0x0100;
1811 val &= ~0x08;
1812 ure_write_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB, val);
1813 }
1814
1815 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK);
1816 }
1817
1818 val = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA);
1819 if (ure_get_link_status(sc))
1820 val |= URE_CUR_LINK_OK;
1821 else
1822 val &= ~URE_CUR_LINK_OK;
1823 val |= URE_POLL_LINK_CHG;
1824 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, val);
1825
1826 /* MAC clock speed down */
1827 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1828 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0x0403);
1829 val = ure_read_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA);
1830 val &= ~0xff;
1831 val |= URE_MAC_CLK_SPDWN_EN | 0x03;
1832 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, val);
1833 } else {
1834 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_USB, URE_MAC_CLK_SPDWN_EN);
1835 }
1836 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN);
1837
1838 /* Enable Rx aggregation. */
1839 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN);
1840
1841 if (sc->sc_flags & URE_FLAG_8156)
1842 URE_SETBIT_1(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x02);
1843
1844 /* Reset tally */
1845 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_USB, URE_TALLY_RESET);
1846 }
1847
1848 static void
ure_rtl8153b_nic_reset(struct ure_softc * sc)1849 ure_rtl8153b_nic_reset(struct ure_softc *sc)
1850 {
1851 if_t ifp = uether_getifp(&sc->sc_ue);
1852 uint16_t val;
1853 int i;
1854
1855 /* Disable U1U2 */
1856 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN);
1857
1858 /* Disable U2P3 */
1859 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
1860
1861 ure_enable_aldps(sc, false);
1862
1863 /* Enable rxdy_gated */
1864 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN);
1865
1866 /* Disable teredo */
1867 ure_disable_teredo(sc);
1868
1869 DEVPRINTFN(14, sc->sc_ue.ue_dev, "rtl8153b_nic_reset: RCR: %#x\n", ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA));
1870 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL);
1871
1872 ure_reset(sc);
1873
1874 /* Reset BMU */
1875 URE_CLRBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, URE_BMU_RESET_EP_IN | URE_BMU_RESET_EP_OUT);
1876 URE_SETBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, URE_BMU_RESET_EP_IN | URE_BMU_RESET_EP_OUT);
1877
1878 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB);
1879 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN);
1880 if (sc->sc_flags & URE_FLAG_8153B) {
1881 for (i = 0; i < URE_TIMEOUT; i++) {
1882 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1883 URE_LINK_LIST_READY)
1884 break;
1885 uether_pause(&sc->sc_ue, hz / 100);
1886 }
1887 if (i == URE_TIMEOUT)
1888 device_printf(sc->sc_ue.ue_dev,
1889 "timeout waiting for OOB control\n");
1890
1891 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL);
1892 for (i = 0; i < URE_TIMEOUT; i++) {
1893 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
1894 URE_LINK_LIST_READY)
1895 break;
1896 uether_pause(&sc->sc_ue, hz / 100);
1897 }
1898 if (i == URE_TIMEOUT)
1899 device_printf(sc->sc_ue.ue_dev,
1900 "timeout waiting for OOB control\n");
1901 }
1902
1903 /* Configure rxvlan */
1904 val = ure_read_2(sc, 0xc012, URE_MCU_TYPE_PLA);
1905 val &= ~0x00c0;
1906 if (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING)
1907 val |= 0x00c0;
1908 ure_write_2(sc, 0xc012, URE_MCU_TYPE_PLA, val);
1909
1910 val = if_getmtu(ifp);
1911 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, URE_FRAMELEN(val));
1912 ure_write_1(sc, URE_PLA_MTPS, URE_MCU_TYPE_PLA, URE_MTPS_JUMBO);
1913
1914 if (sc->sc_flags & URE_FLAG_8153B) {
1915 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO);
1916 ure_reset(sc);
1917 }
1918
1919 /* Configure fc parameter */
1920 if (sc->sc_flags & URE_FLAG_8156) {
1921 ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0400);
1922 ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0800);
1923 } else if (sc->sc_flags & URE_FLAG_8156B) {
1924 ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0200);
1925 ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0400);
1926 }
1927
1928 /* Configure Rx FIFO threshold. */
1929 if (sc->sc_flags & URE_FLAG_8153B) {
1930 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, URE_RXFIFO_THR1_NORMAL);
1931 ure_write_2(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, URE_RXFIFO_THR2_NORMAL);
1932 ure_write_2(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, URE_RXFIFO_THR3_NORMAL);
1933 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_B);
1934 } else {
1935 ure_write_2(sc, 0xc0a2, URE_MCU_TYPE_PLA,
1936 (ure_read_2(sc, 0xc0a2, URE_MCU_TYPE_PLA) & ~0xfff) | 0x08);
1937 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 0x00600400);
1938 }
1939
1940 /* Configure Tx FIFO threshold. */
1941 if (sc->sc_flags & URE_FLAG_8153B) {
1942 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, URE_TXFIFO_THR_NORMAL2);
1943 } else if (sc->sc_flags & URE_FLAG_8156) {
1944 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, URE_TXFIFO_THR_NORMAL2);
1945 URE_SETBIT_2(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x0002);
1946 } else if (sc->sc_flags & URE_FLAG_8156B) {
1947 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 0x0008);
1948 ure_write_2(sc, 0xe61a, URE_MCU_TYPE_PLA,
1949 (URE_FRAMELEN(val) + 0x100) / 16 );
1950 }
1951
1952 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN);
1953
1954 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))
1955 URE_CLRBIT_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0x300);
1956
1957 ure_enable_aldps(sc, true);
1958
1959 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
1960 /* Enable U2P3 */
1961 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE);
1962 }
1963
1964 /* Enable U1U2 */
1965 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_SUPER)
1966 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN);
1967 }
1968
1969 static void
ure_stop(struct usb_ether * ue)1970 ure_stop(struct usb_ether *ue)
1971 {
1972 struct ure_softc *sc = uether_getsc(ue);
1973 if_t ifp = uether_getifp(ue);
1974
1975 URE_LOCK_ASSERT(sc, MA_OWNED);
1976
1977 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
1978 sc->sc_flags &= ~URE_FLAG_LINK;
1979 sc->sc_rxstarted = 0;
1980
1981 /*
1982 * stop all the transfers, if not already stopped:
1983 */
1984 for (int i = 0; i < URE_MAX_RX; i++)
1985 usbd_transfer_stop(sc->sc_rx_xfer[i]);
1986 for (int i = 0; i < URE_MAX_TX; i++)
1987 usbd_transfer_stop(sc->sc_tx_xfer[i]);
1988 }
1989
1990 static void
ure_disable_teredo(struct ure_softc * sc)1991 ure_disable_teredo(struct ure_softc *sc)
1992 {
1993
1994 if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B))
1995 ure_write_1(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 0xff);
1996 else {
1997 URE_CLRBIT_2(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA,
1998 (URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN));
1999 }
2000 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, URE_WDT6_SET_MODE);
2001 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0);
2002 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0);
2003 }
2004
2005 static void
ure_enable_aldps(struct ure_softc * sc,bool enable)2006 ure_enable_aldps(struct ure_softc *sc, bool enable)
2007 {
2008 int i;
2009
2010 if (enable) {
2011 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
2012 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | URE_EN_ALDPS);
2013 } else {
2014 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA |
2015 URE_DIS_SDSAVE);
2016 for (i = 0; i < 20; i++) {
2017 uether_pause(&sc->sc_ue, hz / 1000);
2018 if (ure_ocp_reg_read(sc, 0xe000) & 0x0100)
2019 break;
2020 }
2021 }
2022 }
2023
2024 static uint16_t
ure_phy_status(struct ure_softc * sc,uint16_t desired)2025 ure_phy_status(struct ure_softc *sc, uint16_t desired)
2026 {
2027 uint16_t val;
2028 int i;
2029
2030 for (i = 0; i < URE_TIMEOUT; i++) {
2031 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) &
2032 URE_PHY_STAT_MASK;
2033 if (desired) {
2034 if (val == desired)
2035 break;
2036 } else {
2037 if (val == URE_PHY_STAT_LAN_ON ||
2038 val == URE_PHY_STAT_PWRDN ||
2039 val == URE_PHY_STAT_EXT_INIT)
2040 break;
2041 }
2042 uether_pause(&sc->sc_ue, hz / 100);
2043 }
2044 if (i == URE_TIMEOUT)
2045 device_printf(sc->sc_ue.ue_dev,
2046 "timeout waiting for phy to stabilize\n");
2047
2048 return (val);
2049 }
2050
2051 static void
ure_rtl8152_nic_reset(struct ure_softc * sc)2052 ure_rtl8152_nic_reset(struct ure_softc *sc)
2053 {
2054 uint32_t rx_fifo1, rx_fifo2;
2055 int i;
2056
2057 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN);
2058
2059 ure_disable_teredo(sc);
2060
2061 DEVPRINTFN(14, sc->sc_ue.ue_dev, "rtl8152_nic_reset: RCR: %#x\n", ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA));
2062 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL);
2063
2064 ure_reset(sc);
2065
2066 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0);
2067
2068 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB);
2069
2070 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN);
2071 for (i = 0; i < URE_TIMEOUT; i++) {
2072 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
2073 URE_LINK_LIST_READY)
2074 break;
2075 uether_pause(&sc->sc_ue, hz / 100);
2076 }
2077 if (i == URE_TIMEOUT)
2078 device_printf(sc->sc_ue.ue_dev,
2079 "timeout waiting for OOB control\n");
2080 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL);
2081 for (i = 0; i < URE_TIMEOUT; i++) {
2082 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) &
2083 URE_LINK_LIST_READY)
2084 break;
2085 uether_pause(&sc->sc_ue, hz / 100);
2086 }
2087 if (i == URE_TIMEOUT)
2088 device_printf(sc->sc_ue.ue_dev,
2089 "timeout waiting for OOB control\n");
2090
2091 URE_CLRBIT_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, URE_CPCR_RX_VLAN);
2092
2093 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO);
2094
2095 /* Configure Rx FIFO threshold. */
2096 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA,
2097 URE_RXFIFO_THR1_NORMAL);
2098 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) {
2099 rx_fifo1 = URE_RXFIFO_THR2_FULL;
2100 rx_fifo2 = URE_RXFIFO_THR3_FULL;
2101 } else {
2102 rx_fifo1 = URE_RXFIFO_THR2_HIGH;
2103 rx_fifo2 = URE_RXFIFO_THR3_HIGH;
2104 }
2105 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1);
2106 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2);
2107
2108 /* Configure Tx FIFO threshold. */
2109 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA,
2110 URE_TXFIFO_THR_NORMAL);
2111 }
2112
2113 /*
2114 * Update mbuf for rx checksum from hardware
2115 */
2116 static void
ure_rxcsum(int capenb,struct ure_rxpkt * rp,struct mbuf * m)2117 ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m)
2118 {
2119 int flags;
2120 uint32_t csum, misc;
2121 int tcp, udp;
2122
2123 m->m_pkthdr.csum_flags = 0;
2124
2125 if (!(capenb & IFCAP_RXCSUM))
2126 return;
2127
2128 csum = le32toh(rp->ure_csum);
2129 misc = le32toh(rp->ure_misc);
2130
2131 tcp = udp = 0;
2132
2133 flags = 0;
2134 if (csum & URE_RXPKT_IPV4_CS)
2135 flags |= CSUM_IP_CHECKED;
2136 else if (csum & URE_RXPKT_IPV6_CS)
2137 flags = 0;
2138
2139 tcp = rp->ure_csum & URE_RXPKT_TCP_CS;
2140 udp = rp->ure_csum & URE_RXPKT_UDP_CS;
2141
2142 if (__predict_true((flags & CSUM_IP_CHECKED) &&
2143 !(misc & URE_RXPKT_IP_F))) {
2144 flags |= CSUM_IP_VALID;
2145 }
2146 if (__predict_true(
2147 (tcp && !(misc & URE_RXPKT_TCP_F)) ||
2148 (udp && !(misc & URE_RXPKT_UDP_F)))) {
2149 flags |= CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2150 m->m_pkthdr.csum_data = 0xFFFF;
2151 }
2152
2153 m->m_pkthdr.csum_flags = flags;
2154 }
2155
2156 /*
2157 * If the L4 checksum offset is larger than 0x7ff (2047), return failure.
2158 * We currently restrict MTU such that it can't happen, and even if we
2159 * did have a large enough MTU, only a very specially crafted IPv6 packet
2160 * with MANY headers could possibly come close.
2161 *
2162 * Returns 0 for success, and 1 if the packet cannot be checksummed and
2163 * should be dropped.
2164 */
2165 static int
ure_txcsum(struct mbuf * m,int caps,uint32_t * regout)2166 ure_txcsum(struct mbuf *m, int caps, uint32_t *regout)
2167 {
2168 struct ip ip;
2169 struct ether_header *eh;
2170 int flags;
2171 uint32_t data;
2172 uint32_t reg;
2173 int l3off, l4off;
2174 uint16_t type;
2175
2176 *regout = 0;
2177 flags = m->m_pkthdr.csum_flags;
2178 if (flags == 0)
2179 return (0);
2180
2181 if (__predict_true(m->m_len >= (int)sizeof(*eh))) {
2182 eh = mtod(m, struct ether_header *);
2183 type = eh->ether_type;
2184 } else
2185 m_copydata(m, offsetof(struct ether_header, ether_type),
2186 sizeof(type), (caddr_t)&type);
2187
2188 switch (type = htons(type)) {
2189 case ETHERTYPE_IP:
2190 case ETHERTYPE_IPV6:
2191 l3off = ETHER_HDR_LEN;
2192 break;
2193 case ETHERTYPE_VLAN:
2194 /* XXX - what about QinQ? */
2195 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2196 break;
2197 default:
2198 return (0);
2199 }
2200
2201 reg = 0;
2202
2203 if (flags & CSUM_IP)
2204 reg |= URE_TXPKT_IPV4_CS;
2205
2206 data = m->m_pkthdr.csum_data;
2207 if (flags & (CSUM_IP_TCP | CSUM_IP_UDP)) {
2208 m_copydata(m, l3off, sizeof ip, (caddr_t)&ip);
2209 l4off = l3off + (ip.ip_hl << 2) + data;
2210 if (__predict_false(l4off > URE_L4_OFFSET_MAX))
2211 return (1);
2212
2213 reg |= URE_TXPKT_IPV4_CS;
2214 if (flags & CSUM_IP_TCP)
2215 reg |= URE_TXPKT_TCP_CS;
2216 else if (flags & CSUM_IP_UDP)
2217 reg |= URE_TXPKT_UDP_CS;
2218 reg |= l4off << URE_L4_OFFSET_SHIFT;
2219 }
2220 #ifdef INET6
2221 else if (flags & (CSUM_IP6_TCP | CSUM_IP6_UDP)) {
2222 l4off = l3off + data;
2223 if (__predict_false(l4off > URE_L4_OFFSET_MAX))
2224 return (1);
2225
2226 reg |= URE_TXPKT_IPV6_CS;
2227 if (flags & CSUM_IP6_TCP)
2228 reg |= URE_TXPKT_TCP_CS;
2229 else if (flags & CSUM_IP6_UDP)
2230 reg |= URE_TXPKT_UDP_CS;
2231 reg |= l4off << URE_L4_OFFSET_SHIFT;
2232 }
2233 #endif
2234 *regout = reg;
2235 return 0;
2236 }
2237