1 #ifndef _G_UVM_NVOC_H_
2 #define _G_UVM_NVOC_H_
3 #include "nvoc/runtime.h"
4
5 #ifdef __cplusplus
6 extern "C" {
7 #endif
8
9 /*
10 * SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
11 * SPDX-License-Identifier: MIT
12 *
13 * Permission is hereby granted, free of charge, to any person obtaining a
14 * copy of this software and associated documentation files (the "Software"),
15 * to deal in the Software without restriction, including without limitation
16 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
17 * and/or sell copies of the Software, and to permit persons to whom the
18 * Software is furnished to do so, subject to the following conditions:
19 *
20 * The above copyright notice and this permission notice shall be included in
21 * all copies or substantial portions of the Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
27 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
28 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
29 * DEALINGS IN THE SOFTWARE.
30 */
31
32 #include "g_uvm_nvoc.h"
33
34 #ifndef UVM_H
35 #define UVM_H
36
37 /*!
38 * @file
39 * @brief Provides definitions for all OBJUVM data structures and interfaces.
40 */
41
42 #include "core/core.h"
43 #include "rmapi/control.h"
44 #include "rmapi/rmapi_utils.h"
45 #include "gpu/mem_mgr/mem_desc.h"
46 #include "gpu/gpu.h"
47 #include "nvoc/utility.h"
48 #include "kernel/gpu/intr/intr_service.h"
49
50 #include "gpu/eng_state.h"
51
52 typedef enum
53 {
54 MIMC,
55 MOMC
56 } ACCESS_CNTR_TYPE;
57
58 /*!
59 * Defines the structure used to contain all generic information related to
60 * the OBJUVM.
61 * Contains the Unified Virtual Memory (UVM) feature related data.
62 */
63
64 struct AccessCounterBuffer;
65
66 #ifndef __NVOC_CLASS_AccessCounterBuffer_TYPEDEF__
67 #define __NVOC_CLASS_AccessCounterBuffer_TYPEDEF__
68 typedef struct AccessCounterBuffer AccessCounterBuffer;
69 #endif /* __NVOC_CLASS_AccessCounterBuffer_TYPEDEF__ */
70
71 #ifndef __nvoc_class_id_AccessCounterBuffer
72 #define __nvoc_class_id_AccessCounterBuffer 0x1f0074
73 #endif /* __nvoc_class_id_AccessCounterBuffer */
74
75
76
77 /*
78 * This structure is used to store all the necessary information concerning the access counter buffer.
79 * It is contained within the UVM object.
80 */
81 typedef struct
82 {
83 // kernel fields
84 struct AccessCounterBuffer *pAccessCounterBuffer; // AccessCounterBuffer object
85
86 // physical fields
87 NvU64 bar2UvmAccessCntrBufferAddr; //This is the bar2 VA that is used by the gpu in
88 // order to access the buffer
89 MEMORY_DESCRIPTOR *pUvmAccessCntrMemDesc; // Memory descriptor of the reconstructed access counter buffer
90 } ACCESS_CNTR_BUFFER;
91
92 typedef enum
93 {
94 intr_notify,
95 intr_error,
96 intr_all
97 } ACCESS_CNTR_INTR_TYPE;
98
99 typedef struct OBJUVM *POBJUVM;
100
101
102 // Private field names are wrapped in PRIVATE_FIELD, which does nothing for
103 // the matching C source file, but causes diagnostics to be issued if another
104 // source file references the field.
105 #ifdef NVOC_UVM_H_PRIVATE_ACCESS_ALLOWED
106 #define PRIVATE_FIELD(x) x
107 #else
108 #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x)
109 #endif
110
111 struct OBJUVM {
112 const struct NVOC_RTTI *__nvoc_rtti;
113 struct OBJENGSTATE __nvoc_base_OBJENGSTATE;
114 struct IntrService __nvoc_base_IntrService;
115 struct Object *__nvoc_pbase_Object;
116 struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE;
117 struct IntrService *__nvoc_pbase_IntrService;
118 struct OBJUVM *__nvoc_pbase_OBJUVM;
119 void (*__uvmStateDestroy__)(OBJGPU *, struct OBJUVM *);
120 NV_STATUS (*__uvmStateInitUnlocked__)(OBJGPU *, struct OBJUVM *);
121 NV_STATUS (*__uvmAccessCntrBufferUnregister__)(OBJGPU *, struct OBJUVM *, NvU32);
122 NV_STATUS (*__uvmAccessCntrBufferRegister__)(OBJGPU *, struct OBJUVM *, NvU32, NvU32, RmPhysAddr *);
123 void (*__uvmRegisterIntrService__)(OBJGPU *, struct OBJUVM *, IntrServiceRecord *);
124 NvU32 (*__uvmServiceInterrupt__)(OBJGPU *, struct OBJUVM *, IntrServiceServiceInterruptArguments *);
125 NV_STATUS (*__uvmStateLoad__)(POBJGPU, struct OBJUVM *, NvU32);
126 NV_STATUS (*__uvmStateUnload__)(POBJGPU, struct OBJUVM *, NvU32);
127 NV_STATUS (*__uvmServiceNotificationInterrupt__)(OBJGPU *, struct OBJUVM *, IntrServiceServiceNotificationInterruptArguments *);
128 NV_STATUS (*__uvmStateInitLocked__)(POBJGPU, struct OBJUVM *);
129 NV_STATUS (*__uvmStatePreLoad__)(POBJGPU, struct OBJUVM *, NvU32);
130 NV_STATUS (*__uvmStatePostUnload__)(POBJGPU, struct OBJUVM *, NvU32);
131 NV_STATUS (*__uvmStatePreUnload__)(POBJGPU, struct OBJUVM *, NvU32);
132 void (*__uvmInitMissing__)(POBJGPU, struct OBJUVM *);
133 NV_STATUS (*__uvmStatePreInitLocked__)(POBJGPU, struct OBJUVM *);
134 NV_STATUS (*__uvmStatePreInitUnlocked__)(POBJGPU, struct OBJUVM *);
135 NvBool (*__uvmClearInterrupt__)(OBJGPU *, struct OBJUVM *, IntrServiceClearInterruptArguments *);
136 NV_STATUS (*__uvmStatePostLoad__)(POBJGPU, struct OBJUVM *, NvU32);
137 NV_STATUS (*__uvmConstructEngine__)(POBJGPU, struct OBJUVM *, ENGDESCRIPTOR);
138 NvBool (*__uvmIsPresent__)(POBJGPU, struct OBJUVM *);
139 ACCESS_CNTR_BUFFER *pAccessCounterBuffers;
140 NvU32 accessCounterBufferCount;
141 NvHandle hClient;
142 NvHandle hSubdevice;
143 RM_API *pRmApi;
144 };
145
146 #ifndef __NVOC_CLASS_OBJUVM_TYPEDEF__
147 #define __NVOC_CLASS_OBJUVM_TYPEDEF__
148 typedef struct OBJUVM OBJUVM;
149 #endif /* __NVOC_CLASS_OBJUVM_TYPEDEF__ */
150
151 #ifndef __nvoc_class_id_OBJUVM
152 #define __nvoc_class_id_OBJUVM 0xf9a17d
153 #endif /* __nvoc_class_id_OBJUVM */
154
155 extern const struct NVOC_CLASS_DEF __nvoc_class_def_OBJUVM;
156
157 #define __staticCast_OBJUVM(pThis) \
158 ((pThis)->__nvoc_pbase_OBJUVM)
159
160 #ifdef __nvoc_uvm_h_disabled
161 #define __dynamicCast_OBJUVM(pThis) ((OBJUVM*)NULL)
162 #else //__nvoc_uvm_h_disabled
163 #define __dynamicCast_OBJUVM(pThis) \
164 ((OBJUVM*)__nvoc_dynamicCast(staticCast((pThis), Dynamic), classInfo(OBJUVM)))
165 #endif //__nvoc_uvm_h_disabled
166
167 #define PDB_PROP_UVM_IS_MISSING_BASE_CAST __nvoc_base_OBJENGSTATE.
168 #define PDB_PROP_UVM_IS_MISSING_BASE_NAME PDB_PROP_ENGSTATE_IS_MISSING
169
170 NV_STATUS __nvoc_objCreateDynamic_OBJUVM(OBJUVM**, Dynamic*, NvU32, va_list);
171
172 NV_STATUS __nvoc_objCreate_OBJUVM(OBJUVM**, Dynamic*, NvU32);
173 #define __objCreate_OBJUVM(ppNewObj, pParent, createFlags) \
174 __nvoc_objCreate_OBJUVM((ppNewObj), staticCast((pParent), Dynamic), (createFlags))
175
176 #define uvmStateDestroy(pGpu, pUvm) uvmStateDestroy_DISPATCH(pGpu, pUvm)
177 #define uvmStateInitUnlocked(pGpu, pUvm) uvmStateInitUnlocked_DISPATCH(pGpu, pUvm)
178 #define uvmAccessCntrBufferUnregister(arg0, arg1, accessCounterIndex) uvmAccessCntrBufferUnregister_DISPATCH(arg0, arg1, accessCounterIndex)
179 #define uvmAccessCntrBufferUnregister_HAL(arg0, arg1, accessCounterIndex) uvmAccessCntrBufferUnregister_DISPATCH(arg0, arg1, accessCounterIndex)
180 #define uvmAccessCntrBufferRegister(arg0, arg1, accessCounterIndex, arg2, arg3) uvmAccessCntrBufferRegister_DISPATCH(arg0, arg1, accessCounterIndex, arg2, arg3)
181 #define uvmAccessCntrBufferRegister_HAL(arg0, arg1, accessCounterIndex, arg2, arg3) uvmAccessCntrBufferRegister_DISPATCH(arg0, arg1, accessCounterIndex, arg2, arg3)
182 #define uvmRegisterIntrService(arg0, pUvm, arg1) uvmRegisterIntrService_DISPATCH(arg0, pUvm, arg1)
183 #define uvmServiceInterrupt(arg0, pUvm, arg1) uvmServiceInterrupt_DISPATCH(arg0, pUvm, arg1)
184 #define uvmStateLoad(pGpu, pEngstate, arg0) uvmStateLoad_DISPATCH(pGpu, pEngstate, arg0)
185 #define uvmStateUnload(pGpu, pEngstate, arg0) uvmStateUnload_DISPATCH(pGpu, pEngstate, arg0)
186 #define uvmServiceNotificationInterrupt(pGpu, pIntrService, pParams) uvmServiceNotificationInterrupt_DISPATCH(pGpu, pIntrService, pParams)
187 #define uvmStateInitLocked(pGpu, pEngstate) uvmStateInitLocked_DISPATCH(pGpu, pEngstate)
188 #define uvmStatePreLoad(pGpu, pEngstate, arg0) uvmStatePreLoad_DISPATCH(pGpu, pEngstate, arg0)
189 #define uvmStatePostUnload(pGpu, pEngstate, arg0) uvmStatePostUnload_DISPATCH(pGpu, pEngstate, arg0)
190 #define uvmStatePreUnload(pGpu, pEngstate, arg0) uvmStatePreUnload_DISPATCH(pGpu, pEngstate, arg0)
191 #define uvmInitMissing(pGpu, pEngstate) uvmInitMissing_DISPATCH(pGpu, pEngstate)
192 #define uvmStatePreInitLocked(pGpu, pEngstate) uvmStatePreInitLocked_DISPATCH(pGpu, pEngstate)
193 #define uvmStatePreInitUnlocked(pGpu, pEngstate) uvmStatePreInitUnlocked_DISPATCH(pGpu, pEngstate)
194 #define uvmClearInterrupt(pGpu, pIntrService, pParams) uvmClearInterrupt_DISPATCH(pGpu, pIntrService, pParams)
195 #define uvmStatePostLoad(pGpu, pEngstate, arg0) uvmStatePostLoad_DISPATCH(pGpu, pEngstate, arg0)
196 #define uvmConstructEngine(pGpu, pEngstate, arg0) uvmConstructEngine_DISPATCH(pGpu, pEngstate, arg0)
197 #define uvmIsPresent(pGpu, pEngstate) uvmIsPresent_DISPATCH(pGpu, pEngstate)
198 NV_STATUS uvmInitializeAccessCntrBuffer_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer);
199
200
201 #ifdef __nvoc_uvm_h_disabled
uvmInitializeAccessCntrBuffer(OBJGPU * pGpu,struct OBJUVM * pUvm,struct AccessCounterBuffer * pAccessCounterBuffer)202 static inline NV_STATUS uvmInitializeAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer) {
203 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
204 return NV_ERR_NOT_SUPPORTED;
205 }
206 #else //__nvoc_uvm_h_disabled
207 #define uvmInitializeAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) uvmInitializeAccessCntrBuffer_IMPL(pGpu, pUvm, pAccessCounterBuffer)
208 #endif //__nvoc_uvm_h_disabled
209
210 #define uvmInitializeAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer) uvmInitializeAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer)
211
212 NV_STATUS uvmTerminateAccessCntrBuffer_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer);
213
214
215 #ifdef __nvoc_uvm_h_disabled
uvmTerminateAccessCntrBuffer(OBJGPU * pGpu,struct OBJUVM * pUvm,struct AccessCounterBuffer * pAccessCounterBuffer)216 static inline NV_STATUS uvmTerminateAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer) {
217 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
218 return NV_ERR_NOT_SUPPORTED;
219 }
220 #else //__nvoc_uvm_h_disabled
221 #define uvmTerminateAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) uvmTerminateAccessCntrBuffer_IMPL(pGpu, pUvm, pAccessCounterBuffer)
222 #endif //__nvoc_uvm_h_disabled
223
224 #define uvmTerminateAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer) uvmTerminateAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer)
225
226 NV_STATUS uvmInitAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer);
227
228
229 #ifdef __nvoc_uvm_h_disabled
uvmInitAccessCntrBuffer(OBJGPU * pGpu,struct OBJUVM * pUvm,struct AccessCounterBuffer * pAccessCounterBuffer)230 static inline NV_STATUS uvmInitAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer) {
231 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
232 return NV_ERR_NOT_SUPPORTED;
233 }
234 #else //__nvoc_uvm_h_disabled
235 #define uvmInitAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) uvmInitAccessCntrBuffer_GV100(pGpu, pUvm, pAccessCounterBuffer)
236 #endif //__nvoc_uvm_h_disabled
237
238 #define uvmInitAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer) uvmInitAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer)
239
240 NV_STATUS uvmDestroyAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer);
241
242
243 #ifdef __nvoc_uvm_h_disabled
uvmDestroyAccessCntrBuffer(OBJGPU * pGpu,struct OBJUVM * pUvm,struct AccessCounterBuffer * pAccessCounterBuffer)244 static inline NV_STATUS uvmDestroyAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, struct AccessCounterBuffer *pAccessCounterBuffer) {
245 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
246 return NV_ERR_NOT_SUPPORTED;
247 }
248 #else //__nvoc_uvm_h_disabled
249 #define uvmDestroyAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer) uvmDestroyAccessCntrBuffer_GV100(pGpu, pUvm, pAccessCounterBuffer)
250 #endif //__nvoc_uvm_h_disabled
251
252 #define uvmDestroyAccessCntrBuffer_HAL(pGpu, pUvm, pAccessCounterBuffer) uvmDestroyAccessCntrBuffer(pGpu, pUvm, pAccessCounterBuffer)
253
254 NV_STATUS uvmUnloadAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex);
255
256
257 #ifdef __nvoc_uvm_h_disabled
uvmUnloadAccessCntrBuffer(OBJGPU * pGpu,struct OBJUVM * pUvm,NvU32 accessCounterIndex)258 static inline NV_STATUS uvmUnloadAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex) {
259 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
260 return NV_ERR_NOT_SUPPORTED;
261 }
262 #else //__nvoc_uvm_h_disabled
263 #define uvmUnloadAccessCntrBuffer(pGpu, pUvm, accessCounterIndex) uvmUnloadAccessCntrBuffer_GV100(pGpu, pUvm, accessCounterIndex)
264 #endif //__nvoc_uvm_h_disabled
265
266 #define uvmUnloadAccessCntrBuffer_HAL(pGpu, pUvm, accessCounterIndex) uvmUnloadAccessCntrBuffer(pGpu, pUvm, accessCounterIndex)
267
268 NV_STATUS uvmSetupAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex);
269
270
271 #ifdef __nvoc_uvm_h_disabled
uvmSetupAccessCntrBuffer(OBJGPU * pGpu,struct OBJUVM * pUvm,NvU32 accessCounterIndex)272 static inline NV_STATUS uvmSetupAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex) {
273 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
274 return NV_ERR_NOT_SUPPORTED;
275 }
276 #else //__nvoc_uvm_h_disabled
277 #define uvmSetupAccessCntrBuffer(pGpu, pUvm, accessCounterIndex) uvmSetupAccessCntrBuffer_GV100(pGpu, pUvm, accessCounterIndex)
278 #endif //__nvoc_uvm_h_disabled
279
280 #define uvmSetupAccessCntrBuffer_HAL(pGpu, pUvm, accessCounterIndex) uvmSetupAccessCntrBuffer(pGpu, pUvm, accessCounterIndex)
281
282 NV_STATUS uvmReadAccessCntrBufferPutPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 *arg0);
283
284
285 #ifdef __nvoc_uvm_h_disabled
uvmReadAccessCntrBufferPutPtr(OBJGPU * pGpu,struct OBJUVM * pUvm,NvU32 accessCounterIndex,NvU32 * arg0)286 static inline NV_STATUS uvmReadAccessCntrBufferPutPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 *arg0) {
287 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
288 return NV_ERR_NOT_SUPPORTED;
289 }
290 #else //__nvoc_uvm_h_disabled
291 #define uvmReadAccessCntrBufferPutPtr(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferPutPtr_TU102(pGpu, pUvm, accessCounterIndex, arg0)
292 #endif //__nvoc_uvm_h_disabled
293
294 #define uvmReadAccessCntrBufferPutPtr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferPutPtr(pGpu, pUvm, accessCounterIndex, arg0)
295
296 NV_STATUS uvmReadAccessCntrBufferGetPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 *arg0);
297
298
299 #ifdef __nvoc_uvm_h_disabled
uvmReadAccessCntrBufferGetPtr(OBJGPU * pGpu,struct OBJUVM * pUvm,NvU32 accessCounterIndex,NvU32 * arg0)300 static inline NV_STATUS uvmReadAccessCntrBufferGetPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 *arg0) {
301 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
302 return NV_ERR_NOT_SUPPORTED;
303 }
304 #else //__nvoc_uvm_h_disabled
305 #define uvmReadAccessCntrBufferGetPtr(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferGetPtr_TU102(pGpu, pUvm, accessCounterIndex, arg0)
306 #endif //__nvoc_uvm_h_disabled
307
308 #define uvmReadAccessCntrBufferGetPtr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferGetPtr(pGpu, pUvm, accessCounterIndex, arg0)
309
310 NV_STATUS uvmReadAccessCntrBufferFullPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool *arg0);
311
312
313 #ifdef __nvoc_uvm_h_disabled
uvmReadAccessCntrBufferFullPtr(OBJGPU * pGpu,struct OBJUVM * pUvm,NvU32 accessCounterIndex,NvBool * arg0)314 static inline NV_STATUS uvmReadAccessCntrBufferFullPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool *arg0) {
315 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
316 return NV_ERR_NOT_SUPPORTED;
317 }
318 #else //__nvoc_uvm_h_disabled
319 #define uvmReadAccessCntrBufferFullPtr(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferFullPtr_TU102(pGpu, pUvm, accessCounterIndex, arg0)
320 #endif //__nvoc_uvm_h_disabled
321
322 #define uvmReadAccessCntrBufferFullPtr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmReadAccessCntrBufferFullPtr(pGpu, pUvm, accessCounterIndex, arg0)
323
324 NV_STATUS uvmResetAccessCntrBuffer_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0);
325
326
327 #ifdef __nvoc_uvm_h_disabled
uvmResetAccessCntrBuffer(OBJGPU * pGpu,struct OBJUVM * pUvm,NvU32 accessCounterIndex,NvU32 arg0)328 static inline NV_STATUS uvmResetAccessCntrBuffer(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0) {
329 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
330 return NV_ERR_NOT_SUPPORTED;
331 }
332 #else //__nvoc_uvm_h_disabled
333 #define uvmResetAccessCntrBuffer(pGpu, pUvm, accessCounterIndex, arg0) uvmResetAccessCntrBuffer_GV100(pGpu, pUvm, accessCounterIndex, arg0)
334 #endif //__nvoc_uvm_h_disabled
335
336 #define uvmResetAccessCntrBuffer_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmResetAccessCntrBuffer(pGpu, pUvm, accessCounterIndex, arg0)
337
338 NV_STATUS uvmAccessCntrSetGranularity_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, ACCESS_CNTR_TYPE arg0, NvU32 arg1);
339
340
341 #ifdef __nvoc_uvm_h_disabled
uvmAccessCntrSetGranularity(OBJGPU * pGpu,struct OBJUVM * pUvm,NvU32 accessCounterIndex,ACCESS_CNTR_TYPE arg0,NvU32 arg1)342 static inline NV_STATUS uvmAccessCntrSetGranularity(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, ACCESS_CNTR_TYPE arg0, NvU32 arg1) {
343 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
344 return NV_ERR_NOT_SUPPORTED;
345 }
346 #else //__nvoc_uvm_h_disabled
347 #define uvmAccessCntrSetGranularity(pGpu, pUvm, accessCounterIndex, arg0, arg1) uvmAccessCntrSetGranularity_TU102(pGpu, pUvm, accessCounterIndex, arg0, arg1)
348 #endif //__nvoc_uvm_h_disabled
349
350 #define uvmAccessCntrSetGranularity_HAL(pGpu, pUvm, accessCounterIndex, arg0, arg1) uvmAccessCntrSetGranularity(pGpu, pUvm, accessCounterIndex, arg0, arg1)
351
352 NV_STATUS uvmAccessCntrSetThreshold_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0);
353
354
355 #ifdef __nvoc_uvm_h_disabled
uvmAccessCntrSetThreshold(OBJGPU * pGpu,struct OBJUVM * pUvm,NvU32 accessCounterIndex,NvU32 arg0)356 static inline NV_STATUS uvmAccessCntrSetThreshold(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0) {
357 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
358 return NV_ERR_NOT_SUPPORTED;
359 }
360 #else //__nvoc_uvm_h_disabled
361 #define uvmAccessCntrSetThreshold(pGpu, pUvm, accessCounterIndex, arg0) uvmAccessCntrSetThreshold_TU102(pGpu, pUvm, accessCounterIndex, arg0)
362 #endif //__nvoc_uvm_h_disabled
363
364 #define uvmAccessCntrSetThreshold_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmAccessCntrSetThreshold(pGpu, pUvm, accessCounterIndex, arg0)
365
366 NV_STATUS uvmAccessCntrSetCounterLimit_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0, NvU32 arg1);
367
368
369 #ifdef __nvoc_uvm_h_disabled
uvmAccessCntrSetCounterLimit(OBJGPU * pGpu,struct OBJUVM * pUvm,NvU32 accessCounterIndex,NvU32 arg0,NvU32 arg1)370 static inline NV_STATUS uvmAccessCntrSetCounterLimit(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0, NvU32 arg1) {
371 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
372 return NV_ERR_NOT_SUPPORTED;
373 }
374 #else //__nvoc_uvm_h_disabled
375 #define uvmAccessCntrSetCounterLimit(pGpu, pUvm, accessCounterIndex, arg0, arg1) uvmAccessCntrSetCounterLimit_GV100(pGpu, pUvm, accessCounterIndex, arg0, arg1)
376 #endif //__nvoc_uvm_h_disabled
377
378 #define uvmAccessCntrSetCounterLimit_HAL(pGpu, pUvm, accessCounterIndex, arg0, arg1) uvmAccessCntrSetCounterLimit(pGpu, pUvm, accessCounterIndex, arg0, arg1)
379
380 NV_STATUS uvmWriteAccessCntrBufferGetPtr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0);
381
382
383 #ifdef __nvoc_uvm_h_disabled
uvmWriteAccessCntrBufferGetPtr(OBJGPU * pGpu,struct OBJUVM * pUvm,NvU32 accessCounterIndex,NvU32 arg0)384 static inline NV_STATUS uvmWriteAccessCntrBufferGetPtr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU32 arg0) {
385 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
386 return NV_ERR_NOT_SUPPORTED;
387 }
388 #else //__nvoc_uvm_h_disabled
389 #define uvmWriteAccessCntrBufferGetPtr(pGpu, pUvm, accessCounterIndex, arg0) uvmWriteAccessCntrBufferGetPtr_TU102(pGpu, pUvm, accessCounterIndex, arg0)
390 #endif //__nvoc_uvm_h_disabled
391
392 #define uvmWriteAccessCntrBufferGetPtr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmWriteAccessCntrBufferGetPtr(pGpu, pUvm, accessCounterIndex, arg0)
393
394 NV_STATUS uvmEnableAccessCntr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool arg0);
395
396
397 #ifdef __nvoc_uvm_h_disabled
uvmEnableAccessCntr(OBJGPU * pGpu,struct OBJUVM * pUvm,NvU32 accessCounterIndex,NvBool arg0)398 static inline NV_STATUS uvmEnableAccessCntr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool arg0) {
399 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
400 return NV_ERR_NOT_SUPPORTED;
401 }
402 #else //__nvoc_uvm_h_disabled
403 #define uvmEnableAccessCntr(pGpu, pUvm, accessCounterIndex, arg0) uvmEnableAccessCntr_TU102(pGpu, pUvm, accessCounterIndex, arg0)
404 #endif //__nvoc_uvm_h_disabled
405
406 #define uvmEnableAccessCntr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmEnableAccessCntr(pGpu, pUvm, accessCounterIndex, arg0)
407
408 NV_STATUS uvmDisableAccessCntr_GV100(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool arg0);
409
410
411 #ifdef __nvoc_uvm_h_disabled
uvmDisableAccessCntr(OBJGPU * pGpu,struct OBJUVM * pUvm,NvU32 accessCounterIndex,NvBool arg0)412 static inline NV_STATUS uvmDisableAccessCntr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool arg0) {
413 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
414 return NV_ERR_NOT_SUPPORTED;
415 }
416 #else //__nvoc_uvm_h_disabled
417 #define uvmDisableAccessCntr(pGpu, pUvm, accessCounterIndex, arg0) uvmDisableAccessCntr_GV100(pGpu, pUvm, accessCounterIndex, arg0)
418 #endif //__nvoc_uvm_h_disabled
419
420 #define uvmDisableAccessCntr_HAL(pGpu, pUvm, accessCounterIndex, arg0) uvmDisableAccessCntr(pGpu, pUvm, accessCounterIndex, arg0)
421
422 NV_STATUS uvmEnableAccessCntrIntr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0);
423
424
425 #ifdef __nvoc_uvm_h_disabled
uvmEnableAccessCntrIntr(OBJGPU * pGpu,struct OBJUVM * pUvm,NvU32 arg0)426 static inline NV_STATUS uvmEnableAccessCntrIntr(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 arg0) {
427 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
428 return NV_ERR_NOT_SUPPORTED;
429 }
430 #else //__nvoc_uvm_h_disabled
431 #define uvmEnableAccessCntrIntr(pGpu, pUvm, arg0) uvmEnableAccessCntrIntr_TU102(pGpu, pUvm, arg0)
432 #endif //__nvoc_uvm_h_disabled
433
434 #define uvmEnableAccessCntrIntr_HAL(pGpu, pUvm, arg0) uvmEnableAccessCntrIntr(pGpu, pUvm, arg0)
435
436 NV_STATUS uvmDisableAccessCntrIntr_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm);
437
438
439 #ifdef __nvoc_uvm_h_disabled
uvmDisableAccessCntrIntr(OBJGPU * pGpu,struct OBJUVM * pUvm)440 static inline NV_STATUS uvmDisableAccessCntrIntr(OBJGPU *pGpu, struct OBJUVM *pUvm) {
441 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
442 return NV_ERR_NOT_SUPPORTED;
443 }
444 #else //__nvoc_uvm_h_disabled
445 #define uvmDisableAccessCntrIntr(pGpu, pUvm) uvmDisableAccessCntrIntr_TU102(pGpu, pUvm)
446 #endif //__nvoc_uvm_h_disabled
447
448 #define uvmDisableAccessCntrIntr_HAL(pGpu, pUvm) uvmDisableAccessCntrIntr(pGpu, pUvm)
449
450 NV_STATUS uvmGetAccessCntrRegisterMappings_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvP64 *arg0, NvP64 *arg1, NvP64 *arg2, NvP64 *arg3, NvP64 *arg4, NvP64 *arg5, NvU32 *arg6);
451
452
453 #ifdef __nvoc_uvm_h_disabled
uvmGetAccessCntrRegisterMappings(OBJGPU * pGpu,struct OBJUVM * pUvm,NvU32 accessCounterIndex,NvP64 * arg0,NvP64 * arg1,NvP64 * arg2,NvP64 * arg3,NvP64 * arg4,NvP64 * arg5,NvU32 * arg6)454 static inline NV_STATUS uvmGetAccessCntrRegisterMappings(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvP64 *arg0, NvP64 *arg1, NvP64 *arg2, NvP64 *arg3, NvP64 *arg4, NvP64 *arg5, NvU32 *arg6) {
455 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
456 return NV_ERR_NOT_SUPPORTED;
457 }
458 #else //__nvoc_uvm_h_disabled
459 #define uvmGetAccessCntrRegisterMappings(pGpu, pUvm, accessCounterIndex, arg0, arg1, arg2, arg3, arg4, arg5, arg6) uvmGetAccessCntrRegisterMappings_TU102(pGpu, pUvm, accessCounterIndex, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
460 #endif //__nvoc_uvm_h_disabled
461
462 #define uvmGetAccessCntrRegisterMappings_HAL(pGpu, pUvm, accessCounterIndex, arg0, arg1, arg2, arg3, arg4, arg5, arg6) uvmGetAccessCntrRegisterMappings(pGpu, pUvm, accessCounterIndex, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
463
464 NV_STATUS uvmAccessCntrService_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm);
465
466
467 #ifdef __nvoc_uvm_h_disabled
uvmAccessCntrService(OBJGPU * pGpu,struct OBJUVM * pUvm)468 static inline NV_STATUS uvmAccessCntrService(OBJGPU *pGpu, struct OBJUVM *pUvm) {
469 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
470 return NV_ERR_NOT_SUPPORTED;
471 }
472 #else //__nvoc_uvm_h_disabled
473 #define uvmAccessCntrService(pGpu, pUvm) uvmAccessCntrService_TU102(pGpu, pUvm)
474 #endif //__nvoc_uvm_h_disabled
475
476 #define uvmAccessCntrService_HAL(pGpu, pUvm) uvmAccessCntrService(pGpu, pUvm)
477
478 NvU32 uvmGetAccessCounterBufferSize_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex);
479
480
481 #ifdef __nvoc_uvm_h_disabled
uvmGetAccessCounterBufferSize(OBJGPU * pGpu,struct OBJUVM * pUvm,NvU32 accessCounterIndex)482 static inline NvU32 uvmGetAccessCounterBufferSize(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex) {
483 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
484 return 0;
485 }
486 #else //__nvoc_uvm_h_disabled
487 #define uvmGetAccessCounterBufferSize(pGpu, pUvm, accessCounterIndex) uvmGetAccessCounterBufferSize_TU102(pGpu, pUvm, accessCounterIndex)
488 #endif //__nvoc_uvm_h_disabled
489
490 #define uvmGetAccessCounterBufferSize_HAL(pGpu, pUvm, accessCounterIndex) uvmGetAccessCounterBufferSize(pGpu, pUvm, accessCounterIndex)
491
492 void uvmProgramWriteAccessCntrBufferAddress_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU64 addr);
493
494
495 #ifdef __nvoc_uvm_h_disabled
uvmProgramWriteAccessCntrBufferAddress(OBJGPU * pGpu,struct OBJUVM * pUvm,NvU32 accessCounterIndex,NvU64 addr)496 static inline void uvmProgramWriteAccessCntrBufferAddress(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvU64 addr) {
497 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
498 }
499 #else //__nvoc_uvm_h_disabled
500 #define uvmProgramWriteAccessCntrBufferAddress(pGpu, pUvm, accessCounterIndex, addr) uvmProgramWriteAccessCntrBufferAddress_TU102(pGpu, pUvm, accessCounterIndex, addr)
501 #endif //__nvoc_uvm_h_disabled
502
503 #define uvmProgramWriteAccessCntrBufferAddress_HAL(pGpu, pUvm, accessCounterIndex, addr) uvmProgramWriteAccessCntrBufferAddress(pGpu, pUvm, accessCounterIndex, addr)
504
505 void uvmProgramAccessCntrBufferEnabled_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool bEn);
506
507
508 #ifdef __nvoc_uvm_h_disabled
uvmProgramAccessCntrBufferEnabled(OBJGPU * pGpu,struct OBJUVM * pUvm,NvU32 accessCounterIndex,NvBool bEn)509 static inline void uvmProgramAccessCntrBufferEnabled(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex, NvBool bEn) {
510 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
511 }
512 #else //__nvoc_uvm_h_disabled
513 #define uvmProgramAccessCntrBufferEnabled(pGpu, pUvm, accessCounterIndex, bEn) uvmProgramAccessCntrBufferEnabled_TU102(pGpu, pUvm, accessCounterIndex, bEn)
514 #endif //__nvoc_uvm_h_disabled
515
516 #define uvmProgramAccessCntrBufferEnabled_HAL(pGpu, pUvm, accessCounterIndex, bEn) uvmProgramAccessCntrBufferEnabled(pGpu, pUvm, accessCounterIndex, bEn)
517
518 NvBool uvmIsAccessCntrBufferEnabled_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex);
519
520
521 #ifdef __nvoc_uvm_h_disabled
uvmIsAccessCntrBufferEnabled(OBJGPU * pGpu,struct OBJUVM * pUvm,NvU32 accessCounterIndex)522 static inline NvBool uvmIsAccessCntrBufferEnabled(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex) {
523 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
524 return NV_FALSE;
525 }
526 #else //__nvoc_uvm_h_disabled
527 #define uvmIsAccessCntrBufferEnabled(pGpu, pUvm, accessCounterIndex) uvmIsAccessCntrBufferEnabled_TU102(pGpu, pUvm, accessCounterIndex)
528 #endif //__nvoc_uvm_h_disabled
529
530 #define uvmIsAccessCntrBufferEnabled_HAL(pGpu, pUvm, accessCounterIndex) uvmIsAccessCntrBufferEnabled(pGpu, pUvm, accessCounterIndex)
531
532 NvBool uvmIsAccessCntrBufferPushed_TU102(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex);
533
534
535 #ifdef __nvoc_uvm_h_disabled
uvmIsAccessCntrBufferPushed(OBJGPU * pGpu,struct OBJUVM * pUvm,NvU32 accessCounterIndex)536 static inline NvBool uvmIsAccessCntrBufferPushed(OBJGPU *pGpu, struct OBJUVM *pUvm, NvU32 accessCounterIndex) {
537 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
538 return NV_FALSE;
539 }
540 #else //__nvoc_uvm_h_disabled
541 #define uvmIsAccessCntrBufferPushed(pGpu, pUvm, accessCounterIndex) uvmIsAccessCntrBufferPushed_TU102(pGpu, pUvm, accessCounterIndex)
542 #endif //__nvoc_uvm_h_disabled
543
544 #define uvmIsAccessCntrBufferPushed_HAL(pGpu, pUvm, accessCounterIndex) uvmIsAccessCntrBufferPushed(pGpu, pUvm, accessCounterIndex)
545
546 NvU32 uvmGetRegOffsetAccessCntrBufferPut_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex);
547
548
549 #ifdef __nvoc_uvm_h_disabled
uvmGetRegOffsetAccessCntrBufferPut(struct OBJUVM * pUvm,NvU32 accessCounterIndex)550 static inline NvU32 uvmGetRegOffsetAccessCntrBufferPut(struct OBJUVM *pUvm, NvU32 accessCounterIndex) {
551 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
552 return 0;
553 }
554 #else //__nvoc_uvm_h_disabled
555 #define uvmGetRegOffsetAccessCntrBufferPut(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferPut_TU102(pUvm, accessCounterIndex)
556 #endif //__nvoc_uvm_h_disabled
557
558 #define uvmGetRegOffsetAccessCntrBufferPut_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferPut(pUvm, accessCounterIndex)
559
560 NvU32 uvmGetRegOffsetAccessCntrBufferGet_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex);
561
562
563 #ifdef __nvoc_uvm_h_disabled
uvmGetRegOffsetAccessCntrBufferGet(struct OBJUVM * pUvm,NvU32 accessCounterIndex)564 static inline NvU32 uvmGetRegOffsetAccessCntrBufferGet(struct OBJUVM *pUvm, NvU32 accessCounterIndex) {
565 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
566 return 0;
567 }
568 #else //__nvoc_uvm_h_disabled
569 #define uvmGetRegOffsetAccessCntrBufferGet(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferGet_TU102(pUvm, accessCounterIndex)
570 #endif //__nvoc_uvm_h_disabled
571
572 #define uvmGetRegOffsetAccessCntrBufferGet_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferGet(pUvm, accessCounterIndex)
573
574 NvU32 uvmGetRegOffsetAccessCntrBufferHi_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex);
575
576
577 #ifdef __nvoc_uvm_h_disabled
uvmGetRegOffsetAccessCntrBufferHi(struct OBJUVM * pUvm,NvU32 accessCounterIndex)578 static inline NvU32 uvmGetRegOffsetAccessCntrBufferHi(struct OBJUVM *pUvm, NvU32 accessCounterIndex) {
579 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
580 return 0;
581 }
582 #else //__nvoc_uvm_h_disabled
583 #define uvmGetRegOffsetAccessCntrBufferHi(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferHi_TU102(pUvm, accessCounterIndex)
584 #endif //__nvoc_uvm_h_disabled
585
586 #define uvmGetRegOffsetAccessCntrBufferHi_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferHi(pUvm, accessCounterIndex)
587
588 NvU32 uvmGetRegOffsetAccessCntrBufferLo_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex);
589
590
591 #ifdef __nvoc_uvm_h_disabled
uvmGetRegOffsetAccessCntrBufferLo(struct OBJUVM * pUvm,NvU32 accessCounterIndex)592 static inline NvU32 uvmGetRegOffsetAccessCntrBufferLo(struct OBJUVM *pUvm, NvU32 accessCounterIndex) {
593 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
594 return 0;
595 }
596 #else //__nvoc_uvm_h_disabled
597 #define uvmGetRegOffsetAccessCntrBufferLo(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferLo_TU102(pUvm, accessCounterIndex)
598 #endif //__nvoc_uvm_h_disabled
599
600 #define uvmGetRegOffsetAccessCntrBufferLo_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferLo(pUvm, accessCounterIndex)
601
602 NvU32 uvmGetRegOffsetAccessCntrBufferConfig_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex);
603
604
605 #ifdef __nvoc_uvm_h_disabled
uvmGetRegOffsetAccessCntrBufferConfig(struct OBJUVM * pUvm,NvU32 accessCounterIndex)606 static inline NvU32 uvmGetRegOffsetAccessCntrBufferConfig(struct OBJUVM *pUvm, NvU32 accessCounterIndex) {
607 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
608 return 0;
609 }
610 #else //__nvoc_uvm_h_disabled
611 #define uvmGetRegOffsetAccessCntrBufferConfig(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferConfig_TU102(pUvm, accessCounterIndex)
612 #endif //__nvoc_uvm_h_disabled
613
614 #define uvmGetRegOffsetAccessCntrBufferConfig_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferConfig(pUvm, accessCounterIndex)
615
616 NvU32 uvmGetRegOffsetAccessCntrBufferInfo_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex);
617
618
619 #ifdef __nvoc_uvm_h_disabled
uvmGetRegOffsetAccessCntrBufferInfo(struct OBJUVM * pUvm,NvU32 accessCounterIndex)620 static inline NvU32 uvmGetRegOffsetAccessCntrBufferInfo(struct OBJUVM *pUvm, NvU32 accessCounterIndex) {
621 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
622 return 0;
623 }
624 #else //__nvoc_uvm_h_disabled
625 #define uvmGetRegOffsetAccessCntrBufferInfo(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferInfo_TU102(pUvm, accessCounterIndex)
626 #endif //__nvoc_uvm_h_disabled
627
628 #define uvmGetRegOffsetAccessCntrBufferInfo_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferInfo(pUvm, accessCounterIndex)
629
630 NvU32 uvmGetRegOffsetAccessCntrBufferSize_TU102(struct OBJUVM *pUvm, NvU32 accessCounterIndex);
631
632
633 #ifdef __nvoc_uvm_h_disabled
uvmGetRegOffsetAccessCntrBufferSize(struct OBJUVM * pUvm,NvU32 accessCounterIndex)634 static inline NvU32 uvmGetRegOffsetAccessCntrBufferSize(struct OBJUVM *pUvm, NvU32 accessCounterIndex) {
635 NV_ASSERT_FAILED_PRECOMP("OBJUVM was disabled!");
636 return 0;
637 }
638 #else //__nvoc_uvm_h_disabled
639 #define uvmGetRegOffsetAccessCntrBufferSize(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferSize_TU102(pUvm, accessCounterIndex)
640 #endif //__nvoc_uvm_h_disabled
641
642 #define uvmGetRegOffsetAccessCntrBufferSize_HAL(pUvm, accessCounterIndex) uvmGetRegOffsetAccessCntrBufferSize(pUvm, accessCounterIndex)
643
644 void uvmStateDestroy_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm);
645
uvmStateDestroy_DISPATCH(OBJGPU * pGpu,struct OBJUVM * pUvm)646 static inline void uvmStateDestroy_DISPATCH(OBJGPU *pGpu, struct OBJUVM *pUvm) {
647 pUvm->__uvmStateDestroy__(pGpu, pUvm);
648 }
649
650 NV_STATUS uvmStateInitUnlocked_IMPL(OBJGPU *pGpu, struct OBJUVM *pUvm);
651
uvmStateInitUnlocked_DISPATCH(OBJGPU * pGpu,struct OBJUVM * pUvm)652 static inline NV_STATUS uvmStateInitUnlocked_DISPATCH(OBJGPU *pGpu, struct OBJUVM *pUvm) {
653 return pUvm->__uvmStateInitUnlocked__(pGpu, pUvm);
654 }
655
656 NV_STATUS uvmAccessCntrBufferUnregister_IMPL(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex);
657
uvmAccessCntrBufferUnregister_ac1694(OBJGPU * arg0,struct OBJUVM * arg1,NvU32 accessCounterIndex)658 static inline NV_STATUS uvmAccessCntrBufferUnregister_ac1694(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex) {
659 return NV_OK;
660 }
661
uvmAccessCntrBufferUnregister_DISPATCH(OBJGPU * arg0,struct OBJUVM * arg1,NvU32 accessCounterIndex)662 static inline NV_STATUS uvmAccessCntrBufferUnregister_DISPATCH(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex) {
663 return arg1->__uvmAccessCntrBufferUnregister__(arg0, arg1, accessCounterIndex);
664 }
665
666 NV_STATUS uvmAccessCntrBufferRegister_IMPL(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex, NvU32 arg2, RmPhysAddr *arg3);
667
uvmAccessCntrBufferRegister_ac1694(OBJGPU * arg0,struct OBJUVM * arg1,NvU32 accessCounterIndex,NvU32 arg2,RmPhysAddr * arg3)668 static inline NV_STATUS uvmAccessCntrBufferRegister_ac1694(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex, NvU32 arg2, RmPhysAddr *arg3) {
669 return NV_OK;
670 }
671
uvmAccessCntrBufferRegister_DISPATCH(OBJGPU * arg0,struct OBJUVM * arg1,NvU32 accessCounterIndex,NvU32 arg2,RmPhysAddr * arg3)672 static inline NV_STATUS uvmAccessCntrBufferRegister_DISPATCH(OBJGPU *arg0, struct OBJUVM *arg1, NvU32 accessCounterIndex, NvU32 arg2, RmPhysAddr *arg3) {
673 return arg1->__uvmAccessCntrBufferRegister__(arg0, arg1, accessCounterIndex, arg2, arg3);
674 }
675
676 void uvmRegisterIntrService_IMPL(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[171]);
677
uvmRegisterIntrService_DISPATCH(OBJGPU * arg0,struct OBJUVM * pUvm,IntrServiceRecord arg1[171])678 static inline void uvmRegisterIntrService_DISPATCH(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceRecord arg1[171]) {
679 pUvm->__uvmRegisterIntrService__(arg0, pUvm, arg1);
680 }
681
682 NvU32 uvmServiceInterrupt_IMPL(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceServiceInterruptArguments *arg1);
683
uvmServiceInterrupt_DISPATCH(OBJGPU * arg0,struct OBJUVM * pUvm,IntrServiceServiceInterruptArguments * arg1)684 static inline NvU32 uvmServiceInterrupt_DISPATCH(OBJGPU *arg0, struct OBJUVM *pUvm, IntrServiceServiceInterruptArguments *arg1) {
685 return pUvm->__uvmServiceInterrupt__(arg0, pUvm, arg1);
686 }
687
uvmStateLoad_DISPATCH(POBJGPU pGpu,struct OBJUVM * pEngstate,NvU32 arg0)688 static inline NV_STATUS uvmStateLoad_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, NvU32 arg0) {
689 return pEngstate->__uvmStateLoad__(pGpu, pEngstate, arg0);
690 }
691
uvmStateUnload_DISPATCH(POBJGPU pGpu,struct OBJUVM * pEngstate,NvU32 arg0)692 static inline NV_STATUS uvmStateUnload_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, NvU32 arg0) {
693 return pEngstate->__uvmStateUnload__(pGpu, pEngstate, arg0);
694 }
695
uvmServiceNotificationInterrupt_DISPATCH(OBJGPU * pGpu,struct OBJUVM * pIntrService,IntrServiceServiceNotificationInterruptArguments * pParams)696 static inline NV_STATUS uvmServiceNotificationInterrupt_DISPATCH(OBJGPU *pGpu, struct OBJUVM *pIntrService, IntrServiceServiceNotificationInterruptArguments *pParams) {
697 return pIntrService->__uvmServiceNotificationInterrupt__(pGpu, pIntrService, pParams);
698 }
699
uvmStateInitLocked_DISPATCH(POBJGPU pGpu,struct OBJUVM * pEngstate)700 static inline NV_STATUS uvmStateInitLocked_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate) {
701 return pEngstate->__uvmStateInitLocked__(pGpu, pEngstate);
702 }
703
uvmStatePreLoad_DISPATCH(POBJGPU pGpu,struct OBJUVM * pEngstate,NvU32 arg0)704 static inline NV_STATUS uvmStatePreLoad_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, NvU32 arg0) {
705 return pEngstate->__uvmStatePreLoad__(pGpu, pEngstate, arg0);
706 }
707
uvmStatePostUnload_DISPATCH(POBJGPU pGpu,struct OBJUVM * pEngstate,NvU32 arg0)708 static inline NV_STATUS uvmStatePostUnload_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, NvU32 arg0) {
709 return pEngstate->__uvmStatePostUnload__(pGpu, pEngstate, arg0);
710 }
711
uvmStatePreUnload_DISPATCH(POBJGPU pGpu,struct OBJUVM * pEngstate,NvU32 arg0)712 static inline NV_STATUS uvmStatePreUnload_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, NvU32 arg0) {
713 return pEngstate->__uvmStatePreUnload__(pGpu, pEngstate, arg0);
714 }
715
uvmInitMissing_DISPATCH(POBJGPU pGpu,struct OBJUVM * pEngstate)716 static inline void uvmInitMissing_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate) {
717 pEngstate->__uvmInitMissing__(pGpu, pEngstate);
718 }
719
uvmStatePreInitLocked_DISPATCH(POBJGPU pGpu,struct OBJUVM * pEngstate)720 static inline NV_STATUS uvmStatePreInitLocked_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate) {
721 return pEngstate->__uvmStatePreInitLocked__(pGpu, pEngstate);
722 }
723
uvmStatePreInitUnlocked_DISPATCH(POBJGPU pGpu,struct OBJUVM * pEngstate)724 static inline NV_STATUS uvmStatePreInitUnlocked_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate) {
725 return pEngstate->__uvmStatePreInitUnlocked__(pGpu, pEngstate);
726 }
727
uvmClearInterrupt_DISPATCH(OBJGPU * pGpu,struct OBJUVM * pIntrService,IntrServiceClearInterruptArguments * pParams)728 static inline NvBool uvmClearInterrupt_DISPATCH(OBJGPU *pGpu, struct OBJUVM *pIntrService, IntrServiceClearInterruptArguments *pParams) {
729 return pIntrService->__uvmClearInterrupt__(pGpu, pIntrService, pParams);
730 }
731
uvmStatePostLoad_DISPATCH(POBJGPU pGpu,struct OBJUVM * pEngstate,NvU32 arg0)732 static inline NV_STATUS uvmStatePostLoad_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, NvU32 arg0) {
733 return pEngstate->__uvmStatePostLoad__(pGpu, pEngstate, arg0);
734 }
735
uvmConstructEngine_DISPATCH(POBJGPU pGpu,struct OBJUVM * pEngstate,ENGDESCRIPTOR arg0)736 static inline NV_STATUS uvmConstructEngine_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate, ENGDESCRIPTOR arg0) {
737 return pEngstate->__uvmConstructEngine__(pGpu, pEngstate, arg0);
738 }
739
uvmIsPresent_DISPATCH(POBJGPU pGpu,struct OBJUVM * pEngstate)740 static inline NvBool uvmIsPresent_DISPATCH(POBJGPU pGpu, struct OBJUVM *pEngstate) {
741 return pEngstate->__uvmIsPresent__(pGpu, pEngstate);
742 }
743
744 #undef PRIVATE_FIELD
745
746
747 #endif // UVM_H
748
749 #ifdef __cplusplus
750 } // extern "C"
751 #endif
752
753 #endif // _G_UVM_NVOC_H_
754