1 /* $NetBSD: bus.h,v 1.36 2021/01/23 19:38:08 christos Exp $ */
2
3 /*-
4 * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Copyright (c) 1996 Charles M. Hannum. All rights reserved.
35 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 * 1. Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * 2. Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in the
44 * documentation and/or other materials provided with the distribution.
45 * 3. All advertising materials mentioning features or use of this software
46 * must display the following acknowledgement:
47 * This product includes software developed by Christopher G. Demetriou
48 * for the NetBSD Project.
49 * 4. The name of the author may not be used to endorse or promote products
50 * derived from this software without specific prior written permission
51 *
52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 */
63
64 #ifndef _VAX_BUS_H_
65 #define _VAX_BUS_H_
66
67 #ifdef BUS_SPACE_DEBUG
68 #include <sys/systm.h> /* for printf() prototype */
69 /*
70 * Macros for sanity-checking the aligned-ness of pointers passed to
71 * bus space ops. These are not strictly necessary on the VAX, but
72 * could lead to performance improvements, and help catch problems
73 * with drivers that would creep up on other architectures.
74 */
75 #define __BUS_SPACE_ALIGNED_ADDRESS(p, t) \
76 ((((u_long)(p)) & (sizeof(t)-1)) == 0)
77
78 #define __BUS_SPACE_ADDRESS_SANITY(p, t, d) \
79 ({ \
80 if (__BUS_SPACE_ALIGNED_ADDRESS((p), t) == 0) { \
81 printf("%s 0x%lx not aligned to %d bytes %s:%d\n", \
82 d, (u_long)(p), sizeof(t), __FILE__, __LINE__); \
83 } \
84 (void) 0; \
85 })
86
87 #define BUS_SPACE_ALIGNED_POINTER(p, t) __BUS_SPACE_ALIGNED_ADDRESS(p, t)
88 #else
89 #define __BUS_SPACE_ADDRESS_SANITY(p,t,d) (void) 0
90 #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
91 #endif /* BUS_SPACE_DEBUG */
92
93 /*
94 * Bus address and size types
95 */
96 typedef paddr_t bus_addr_t;
97 typedef psize_t bus_size_t;
98
99 #define PRIxBUSADDR PRIxPADDR
100 #define PRIxBUSSIZE PRIxPSIZE
101 #define PRIuBUSSIZE PRIuPSIZE
102 /*
103 * Access methods for bus resources and address space.
104 */
105 typedef struct vax_bus_space *bus_space_tag_t;
106 typedef vaddr_t bus_space_handle_t;
107
108 #define PRIxBSH PRIxVADDR
109
110 struct vax_bus_space {
111 /* cookie */
112 void *vbs_cookie;
113
114 /* mapping/unmapping */
115 int (*vbs_map)(void *, bus_addr_t, bus_size_t, int,
116 bus_space_handle_t *, int);
117 void (*vbs_unmap)(void *, bus_space_handle_t, bus_size_t,
118 int);
119 int (*vbs_subregion)(void *, bus_space_handle_t, bus_size_t,
120 bus_size_t, bus_space_handle_t *);
121
122 /* allocation/deallocation */
123 int (*vbs_alloc)(void *, bus_addr_t, bus_addr_t, bus_size_t,
124 bus_size_t, bus_size_t, int, bus_addr_t *,
125 bus_space_handle_t *);
126 void (*vbs_free)(void *, bus_space_handle_t, bus_size_t);
127 /* mmap bus space for user */
128 paddr_t (*vbs_mmap)(void *, bus_addr_t, off_t, int, int);
129 };
130
131 /*
132 * int bus_space_map(bus_space_tag_t t, bus_addr_t addr,
133 * bus_size_t size, int flags, bus_space_handle_t *bshp);
134 *
135 * Map a region of bus space.
136 */
137
138 #define BUS_SPACE_MAP_CACHEABLE 0x01
139 #define BUS_SPACE_MAP_LINEAR 0x02
140 #define BUS_SPACE_MAP_PREFETCHABLE 0x04
141
142 #define bus_space_map(t, a, s, f, hp) \
143 (*(t)->vbs_map)((t)->vbs_cookie, (a), (s), (f), (hp), 1)
144 #define vax_bus_space_map_noacct(t, a, s, f, hp) \
145 (*(t)->vbs_map)((t)->vbs_cookie, (a), (s), (f), (hp), 0)
146
147 /*
148 * int bus_space_unmap(bus_space_tag_t t,
149 * bus_space_handle_t bsh, bus_size_t size);
150 *
151 * Unmap a region of bus space.
152 */
153
154 #define bus_space_unmap(t, h, s) \
155 (*(t)->vbs_unmap)((t)->vbs_cookie, (h), (s), 1)
156 #define vax_bus_space_unmap_noacct(t, h, s) \
157 (*(t)->vbs_unmap)((t)->vbs_cookie, (h), (s), 0)
158
159 /*
160 * int bus_space_subregion(bus_space_tag_t t,
161 * bus_space_handle_t bsh, bus_size_t offset, bus_size_t size,
162 * bus_space_handle_t *nbshp);
163 *
164 * Get a new handle for a subregion of an already-mapped area of bus space.
165 */
166
167 #define bus_space_subregion(t, h, o, s, nhp) \
168 (*(t)->vbs_subregion)((t)->vbs_cookie, (h), (o), (s), (nhp))
169
170 /*
171 * int bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart,
172 * bus_addr_t rend, bus_size_t size, bus_size_t align,
173 * bus_size_t boundary, int flags, bus_addr_t *addrp,
174 * bus_space_handle_t *bshp);
175 *
176 * Allocate a region of bus space.
177 */
178
179 #define bus_space_alloc(t, rs, re, s, a, b, f, ap, hp) \
180 (*(t)->vbs_alloc)((t)->vbs_cookie, (rs), (re), (s), (a), (b), \
181 (f), (ap), (hp))
182
183 /*
184 * int bus_space_free(bus_space_tag_t t,
185 * bus_space_handle_t bsh, bus_size_t size);
186 *
187 * Free a region of bus space.
188 */
189
190 #define bus_space_free(t, h, s) \
191 (*(t)->vbs_free)((t)->vbs_cookie, (h), (s))
192 /*
193 * Get kernel virtual address for ranges mapped BUS_SPACE_MAP_LINEAR.
194 */
195 #define bus_space_vaddr(t, h) \
196 ((void *) (h))
197 /*
198 * Mmap bus space for a user application.
199 */
200 #define bus_space_mmap(t, a, o, p, f) \
201 (*(t)->vbs_mmap)((t)->vbs_cookie, (a), (o), (p), (f))
202
203
204 /*
205 * u_intN_t bus_space_read_N(bus_space_tag_t tag,
206 * bus_space_handle_t bsh, bus_size_t offset);
207 *
208 * Read a 1, 2, 4, or 8 byte quantity from bus space
209 * described by tag/handle/offset.
210 */
211
212 #define bus_space_read_1(t, h, o) \
213 (__USE(t), (*(volatile uint8_t *)((h) + (o))))
214
215 #define bus_space_read_2(t, h, o) \
216 (__BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"), \
217 __USE(t), (*(volatile uint16_t *)((h) + (o))))
218
219 #define bus_space_read_4(t, h, o) \
220 (__BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"), \
221 __USE(t), (*(volatile uint32_t *)((h) + (o))))
222
223 /*
224 * void bus_space_read_multi_N(bus_space_tag_t tag,
225 * bus_space_handle_t bsh, bus_size_t offset,
226 * u_intN_t *addr, size_t count);
227 *
228 * Read `count' 1, 2, 4, or 8 byte quantities from bus space
229 * described by tag/handle/offset and copy into buffer provided.
230 */
231 static __inline void
232 vax_mem_read_multi_1(bus_space_tag_t, bus_space_handle_t, bus_size_t,
233 uint8_t *, size_t),
234 vax_mem_read_multi_2(bus_space_tag_t, bus_space_handle_t, bus_size_t,
235 uint16_t *, size_t),
236 vax_mem_read_multi_4(bus_space_tag_t, bus_space_handle_t, bus_size_t,
237 uint32_t *, size_t);
238
239 #define bus_space_read_multi_1(t, h, o, a, c) \
240 vax_mem_read_multi_1((t), (h), (o), (a), (c))
241
242 #define bus_space_read_multi_2(t, h, o, a, c) \
243 do { \
244 __BUS_SPACE_ADDRESS_SANITY((a), uint16_t, "buffer"); \
245 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"); \
246 vax_mem_read_multi_2((t), (h), (o), (a), (c)); \
247 } while (0)
248
249 #define bus_space_read_multi_4(t, h, o, a, c) \
250 do { \
251 __BUS_SPACE_ADDRESS_SANITY((a), uint32_t, "buffer"); \
252 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"); \
253 vax_mem_read_multi_4((t), (h), (o), (a), (c)); \
254 } while (0)
255
256 static __inline void
vax_mem_read_multi_1(bus_space_tag_t t,bus_space_handle_t h,bus_size_t o,uint8_t * a,size_t c)257 vax_mem_read_multi_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
258 uint8_t *a, size_t c)
259 {
260 const bus_addr_t addr = h + o;
261
262 for (; c != 0; c--, a++)
263 *a = *(volatile uint8_t *)(addr);
264 }
265
266 static __inline void
vax_mem_read_multi_2(bus_space_tag_t t,bus_space_handle_t h,bus_size_t o,uint16_t * a,size_t c)267 vax_mem_read_multi_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
268 uint16_t *a, size_t c)
269 {
270 const bus_addr_t addr = h + o;
271
272 for (; c != 0; c--, a++)
273 *a = *(volatile uint16_t *)(addr);
274 }
275
276 static __inline void
vax_mem_read_multi_4(bus_space_tag_t t,bus_space_handle_t h,bus_size_t o,uint32_t * a,size_t c)277 vax_mem_read_multi_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
278 uint32_t *a, size_t c)
279 {
280 const bus_addr_t addr = h + o;
281
282 for (; c != 0; c--, a++)
283 *a = *(volatile uint32_t *)(addr);
284 }
285
286 /*
287 * void bus_space_read_region_N(bus_space_tag_t tag,
288 * bus_space_handle_t bsh, bus_size_t offset,
289 * u_intN_t *addr, size_t count);
290 *
291 * Read `count' 1, 2, 4, or 8 byte quantities from bus space
292 * described by tag/handle and starting at `offset' and copy into
293 * buffer provided.
294 */
295
296 static __inline void vax_mem_read_region_1(bus_space_tag_t,
297 bus_space_handle_t, bus_size_t, uint8_t *, size_t);
298 static __inline void vax_mem_read_region_2(bus_space_tag_t,
299 bus_space_handle_t, bus_size_t, uint16_t *, size_t);
300 static __inline void vax_mem_read_region_4(bus_space_tag_t,
301 bus_space_handle_t, bus_size_t, uint32_t *, size_t);
302
303 #define bus_space_read_region_1(t, h, o, a, c) \
304 do { \
305 vax_mem_read_region_1((t), (h), (o), (a), (c)); \
306 } while (0)
307
308 #define bus_space_read_region_2(t, h, o, a, c) \
309 do { \
310 __BUS_SPACE_ADDRESS_SANITY((a), uint16_t, "buffer"); \
311 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"); \
312 vax_mem_read_region_2((t), (h), (o), (a), (c)); \
313 } while (0)
314
315 #define bus_space_read_region_4(t, h, o, a, c) \
316 do { \
317 __BUS_SPACE_ADDRESS_SANITY((a), uint32_t, "buffer"); \
318 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"); \
319 vax_mem_read_region_4((t), (h), (o), (a), (c)); \
320 } while (0)
321
322 static __inline void
vax_mem_read_region_1(bus_space_tag_t t,bus_space_handle_t h,bus_size_t o,uint8_t * a,size_t c)323 vax_mem_read_region_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
324 uint8_t *a, size_t c)
325 {
326 bus_addr_t addr = h + o;
327
328 for (; c != 0; c--, addr++, a++)
329 *a = *(volatile uint8_t *)(addr);
330 }
331
332 static __inline void
vax_mem_read_region_2(bus_space_tag_t t,bus_space_handle_t h,bus_size_t o,uint16_t * a,size_t c)333 vax_mem_read_region_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
334 uint16_t *a, size_t c)
335 {
336 bus_addr_t addr = h + o;
337
338 for (; c != 0; c--, addr += 2, a++)
339 *a = *(volatile uint16_t *)(addr);
340 }
341
342 static __inline void
vax_mem_read_region_4(bus_space_tag_t t,bus_space_handle_t h,bus_size_t o,uint32_t * a,size_t c)343 vax_mem_read_region_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
344 uint32_t *a, size_t c)
345 {
346 bus_addr_t addr = h + o;
347
348 for (; c != 0; c--, addr += 4, a++)
349 *a = *(volatile uint32_t *)(addr);
350 }
351
352 /*
353 * void bus_space_write_N(bus_space_tag_t tag,
354 * bus_space_handle_t bsh, bus_size_t offset,
355 * u_intN_t value);
356 *
357 * Write the 1, 2, 4, or 8 byte value `value' to bus space
358 * described by tag/handle/offset.
359 */
360
361 #define bus_space_write_1(t, h, o, v) \
362 do { \
363 __USE(t); \
364 ((void)(*(volatile uint8_t *)((h) + (o)) = (v))); \
365 } while (0)
366
367 #define bus_space_write_2(t, h, o, v) \
368 do { \
369 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"); \
370 __USE(t); \
371 ((void)(*(volatile uint16_t *)((h) + (o)) = (v))); \
372 } while (0)
373
374 #define bus_space_write_4(t, h, o, v) \
375 do { \
376 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"); \
377 __USE(t); \
378 ((void)(*(volatile uint32_t *)((h) + (o)) = (v))); \
379 } while (0)
380
381 /*
382 * void bus_space_write_multi_N(bus_space_tag_t tag,
383 * bus_space_handle_t bsh, bus_size_t offset,
384 * const u_intN_t *addr, size_t count);
385 *
386 * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
387 * provided to bus space described by tag/handle/offset.
388 */
389 static __inline void
390 vax_mem_write_multi_1(bus_space_tag_t, bus_space_handle_t, bus_size_t,
391 const uint8_t *, size_t),
392 vax_mem_write_multi_2(bus_space_tag_t, bus_space_handle_t, bus_size_t,
393 const uint16_t *, size_t),
394 vax_mem_write_multi_4(bus_space_tag_t, bus_space_handle_t, bus_size_t,
395 const uint32_t *, size_t);
396
397 #define bus_space_write_multi_1(t, h, o, a, c) \
398 do { \
399 vax_mem_write_multi_1((t), (h), (o), (a), (c)); \
400 } while (0)
401
402 #define bus_space_write_multi_2(t, h, o, a, c) \
403 do { \
404 __BUS_SPACE_ADDRESS_SANITY((a), uint16_t, "buffer"); \
405 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"); \
406 vax_mem_write_multi_2((t), (h), (o), (a), (c)); \
407 } while (0)
408
409 #define bus_space_write_multi_4(t, h, o, a, c) \
410 do { \
411 __BUS_SPACE_ADDRESS_SANITY((a), uint32_t, "buffer"); \
412 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"); \
413 vax_mem_write_multi_4((t), (h), (o), (a), (c)); \
414 } while (0)
415
416 static __inline void
vax_mem_write_multi_1(bus_space_tag_t t,bus_space_handle_t h,bus_size_t o,const uint8_t * a,size_t c)417 vax_mem_write_multi_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
418 const uint8_t *a, size_t c)
419 {
420 const bus_addr_t addr = h + o;
421
422 for (; c != 0; c--, a++)
423 *(volatile uint8_t *)(addr) = *a;
424 }
425
426 static __inline void
vax_mem_write_multi_2(bus_space_tag_t t,bus_space_handle_t h,bus_size_t o,const uint16_t * a,size_t c)427 vax_mem_write_multi_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
428 const uint16_t *a, size_t c)
429 {
430 const bus_addr_t addr = h + o;
431
432 for (; c != 0; c--, a++)
433 *(volatile uint16_t *)(addr) = *a;
434 }
435
436 static __inline void
vax_mem_write_multi_4(bus_space_tag_t t,bus_space_handle_t h,bus_size_t o,const uint32_t * a,size_t c)437 vax_mem_write_multi_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
438 const uint32_t *a, size_t c)
439 {
440 const bus_addr_t addr = h + o;
441
442 for (; c != 0; c--, a++)
443 *(volatile uint32_t *)(addr) = *a;
444 }
445
446 /*
447 * void bus_space_write_region_N(bus_space_tag_t tag,
448 * bus_space_handle_t bsh, bus_size_t offset,
449 * const u_intN_t *addr, size_t count);
450 *
451 * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
452 * to bus space described by tag/handle starting at `offset'.
453 */
454 static __inline void
455 vax_mem_write_region_1(bus_space_tag_t, bus_space_handle_t, bus_size_t,
456 const uint8_t *, size_t),
457 vax_mem_write_region_2(bus_space_tag_t, bus_space_handle_t, bus_size_t,
458 const uint16_t *, size_t),
459 vax_mem_write_region_4(bus_space_tag_t, bus_space_handle_t, bus_size_t,
460 const uint32_t *, size_t);
461
462 #define bus_space_write_region_1(t, h, o, a, c) \
463 vax_mem_write_region_1((t), (h), (o), (a), (c))
464
465 #define bus_space_write_region_2(t, h, o, a, c) \
466 do { \
467 __BUS_SPACE_ADDRESS_SANITY((a), uint16_t, "buffer"); \
468 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"); \
469 vax_mem_write_region_2((t), (h), (o), (a), (c)); \
470 } while (0)
471
472 #define bus_space_write_region_4(t, h, o, a, c) \
473 do { \
474 __BUS_SPACE_ADDRESS_SANITY((a), uint32_t, "buffer"); \
475 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"); \
476 vax_mem_write_region_4((t), (h), (o), (a), (c)); \
477 } while (0)
478
479 static __inline void
vax_mem_write_region_1(bus_space_tag_t t,bus_space_handle_t h,bus_size_t o,const uint8_t * a,size_t c)480 vax_mem_write_region_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
481 const uint8_t *a, size_t c)
482 {
483 bus_addr_t addr = h + o;
484
485 for (; c != 0; c--, addr++, a++)
486 *(volatile uint8_t *)(addr) = *a;
487 }
488
489 static __inline void
vax_mem_write_region_2(bus_space_tag_t t,bus_space_handle_t h,bus_size_t o,const uint16_t * a,size_t c)490 vax_mem_write_region_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
491 const uint16_t *a, size_t c)
492 {
493 bus_addr_t addr = h + o;
494
495 for (; c != 0; c--, addr++, a++)
496 *(volatile uint16_t *)(addr) = *a;
497 }
498
499 static __inline void
vax_mem_write_region_4(bus_space_tag_t t,bus_space_handle_t h,bus_size_t o,const uint32_t * a,size_t c)500 vax_mem_write_region_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
501 const uint32_t *a, size_t c)
502 {
503 bus_addr_t addr = h + o;
504
505 for (; c != 0; c--, addr++, a++)
506 *(volatile uint32_t *)(addr) = *a;
507 }
508
509 /*
510 * void bus_space_set_multi_N(bus_space_tag_t tag,
511 * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
512 * size_t count);
513 *
514 * Write the 1, 2, 4, or 8 byte value `val' to bus space described
515 * by tag/handle/offset `count' times.
516 */
517
518 static __inline void
519 vax_mem_set_multi_1(bus_space_tag_t, bus_space_handle_t, bus_size_t,
520 uint8_t, size_t),
521 vax_mem_set_multi_2(bus_space_tag_t, bus_space_handle_t, bus_size_t,
522 uint16_t, size_t),
523 vax_mem_set_multi_4(bus_space_tag_t, bus_space_handle_t, bus_size_t,
524 uint32_t, size_t);
525
526 #define bus_space_set_multi_1(t, h, o, v, c) \
527 vax_mem_set_multi_1((t), (h), (o), (v), (c))
528
529 #define bus_space_set_multi_2(t, h, o, v, c) \
530 do { \
531 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"); \
532 vax_mem_set_multi_2((t), (h), (o), (v), (c)); \
533 } while (0)
534
535 #define bus_space_set_multi_4(t, h, o, v, c) \
536 do { \
537 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"); \
538 vax_mem_set_multi_4((t), (h), (o), (v), (c)); \
539 } while (0)
540
541 static __inline void
vax_mem_set_multi_1(bus_space_tag_t t,bus_space_handle_t h,bus_size_t o,uint8_t v,size_t c)542 vax_mem_set_multi_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
543 uint8_t v, size_t c)
544 {
545 bus_addr_t addr = h + o;
546
547 while (c--)
548 *(volatile uint8_t *)(addr) = v;
549 }
550
551 static __inline void
vax_mem_set_multi_2(bus_space_tag_t t,bus_space_handle_t h,bus_size_t o,uint16_t v,size_t c)552 vax_mem_set_multi_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
553 uint16_t v, size_t c)
554 {
555 bus_addr_t addr = h + o;
556
557 while (c--)
558 *(volatile uint16_t *)(addr) = v;
559 }
560
561 static __inline void
vax_mem_set_multi_4(bus_space_tag_t t,bus_space_handle_t h,bus_size_t o,uint32_t v,size_t c)562 vax_mem_set_multi_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
563 uint32_t v, size_t c)
564 {
565 bus_addr_t addr = h + o;
566
567 while (c--)
568 *(volatile uint32_t *)(addr) = v;
569 }
570
571 /*
572 * void bus_space_set_region_N(bus_space_tag_t tag,
573 * bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
574 * size_t count);
575 *
576 * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
577 * by tag/handle starting at `offset'.
578 */
579
580 static __inline void
581 vax_mem_set_region_1(bus_space_tag_t, bus_space_handle_t, bus_size_t,
582 uint8_t, size_t),
583 vax_mem_set_region_2(bus_space_tag_t, bus_space_handle_t, bus_size_t,
584 uint16_t, size_t),
585 vax_mem_set_region_4(bus_space_tag_t, bus_space_handle_t, bus_size_t,
586 uint32_t, size_t);
587
588 #define bus_space_set_region_1(t, h, o, v, c) \
589 vax_mem_set_region_1((t), (h), (o), (v), (c))
590
591 #define bus_space_set_region_2(t, h, o, v, c) \
592 do { \
593 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint16_t, "bus addr"); \
594 vax_mem_set_region_2((t), (h), (o), (v), (c)); \
595 } while (0)
596
597 #define bus_space_set_region_4(t, h, o, v, c) \
598 do { \
599 __BUS_SPACE_ADDRESS_SANITY((h) + (o), uint32_t, "bus addr"); \
600 vax_mem_set_region_4((t), (h), (o), (v), (c)); \
601 } while (0)
602
603 static __inline void
vax_mem_set_region_1(bus_space_tag_t t,bus_space_handle_t h,bus_size_t o,uint8_t v,size_t c)604 vax_mem_set_region_1(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
605 uint8_t v, size_t c)
606 {
607 bus_addr_t addr = h + o;
608
609 for (; c != 0; c--, addr++)
610 *(volatile uint8_t *)(addr) = v;
611 }
612
613 static __inline void
vax_mem_set_region_2(bus_space_tag_t t,bus_space_handle_t h,bus_size_t o,uint16_t v,size_t c)614 vax_mem_set_region_2(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
615 uint16_t v, size_t c)
616 {
617 bus_addr_t addr = h + o;
618
619 for (; c != 0; c--, addr += 2)
620 *(volatile uint16_t *)(addr) = v;
621 }
622
623 static __inline void
vax_mem_set_region_4(bus_space_tag_t t,bus_space_handle_t h,bus_size_t o,uint32_t v,size_t c)624 vax_mem_set_region_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o,
625 uint32_t v, size_t c)
626 {
627 bus_addr_t addr = h + o;
628
629 for (; c != 0; c--, addr += 4)
630 *(volatile uint32_t *)(addr) = v;
631 }
632
633 /*
634 * void bus_space_copy_region_N(bus_space_tag_t tag,
635 * bus_space_handle_t bsh1, bus_size_t off1,
636 * bus_space_handle_t bsh2, bus_size_t off2,
637 * size_t count);
638 *
639 * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
640 * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
641 */
642
643 static __inline void
644 vax_mem_copy_region_1(bus_space_tag_t, bus_space_handle_t, bus_size_t,
645 bus_space_handle_t, bus_size_t, size_t),
646 vax_mem_copy_region_2(bus_space_tag_t, bus_space_handle_t, bus_size_t,
647 bus_space_handle_t, bus_size_t, size_t),
648 vax_mem_copy_region_4(bus_space_tag_t, bus_space_handle_t, bus_size_t,
649 bus_space_handle_t, bus_size_t, size_t);
650
651 #define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \
652 vax_mem_copy_region_1((t), (h1), (o1), (h2), (o2), (c))
653
654 #define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \
655 do { \
656 __BUS_SPACE_ADDRESS_SANITY((h1) + (o1), uint16_t, "bus addr 1"); \
657 __BUS_SPACE_ADDRESS_SANITY((h2) + (o2), uint16_t, "bus addr 2"); \
658 vax_mem_copy_region_2((t), (h1), (o1), (h2), (o2), (c)); \
659 } while (0)
660
661 #define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \
662 do { \
663 __BUS_SPACE_ADDRESS_SANITY((h1) + (o1), uint32_t, "bus addr 1"); \
664 __BUS_SPACE_ADDRESS_SANITY((h2) + (o2), uint32_t, "bus addr 2"); \
665 vax_mem_copy_region_4((t), (h1), (o1), (h2), (o2), (c)); \
666 } while (0)
667
668 static __inline void
vax_mem_copy_region_1(bus_space_tag_t t,bus_space_handle_t h1,bus_size_t o1,bus_space_handle_t h2,bus_size_t o2,size_t c)669 vax_mem_copy_region_1(bus_space_tag_t t, bus_space_handle_t h1, bus_size_t o1,
670 bus_space_handle_t h2, bus_size_t o2, size_t c)
671 {
672 bus_addr_t addr1 = h1 + o1;
673 bus_addr_t addr2 = h2 + o2;
674
675 if (addr1 >= addr2) {
676 /* src after dest: copy forward */
677 for (; c != 0; c--, addr1++, addr2++)
678 *(volatile uint8_t *)(addr2) =
679 *(volatile uint8_t *)(addr1);
680 } else {
681 /* dest after src: copy backwards */
682 for (addr1 += (c - 1), addr2 += (c - 1);
683 c != 0; c--, addr1--, addr2--)
684 *(volatile uint8_t *)(addr2) =
685 *(volatile uint8_t *)(addr1);
686 }
687 }
688
689 static __inline void
vax_mem_copy_region_2(bus_space_tag_t t,bus_space_handle_t h1,bus_size_t o1,bus_space_handle_t h2,bus_size_t o2,size_t c)690 vax_mem_copy_region_2(bus_space_tag_t t, bus_space_handle_t h1, bus_size_t o1,
691 bus_space_handle_t h2, bus_size_t o2, size_t c)
692 {
693 bus_addr_t addr1 = h1 + o1;
694 bus_addr_t addr2 = h2 + o2;
695
696 if (addr1 >= addr2) {
697 /* src after dest: copy forward */
698 for (; c != 0; c--, addr1 += 2, addr2 += 2)
699 *(volatile uint16_t *)(addr2) =
700 *(volatile uint16_t *)(addr1);
701 } else {
702 /* dest after src: copy backwards */
703 for (addr1 += 2 * (c - 1), addr2 += 2 * (c - 1);
704 c != 0; c--, addr1 -= 2, addr2 -= 2)
705 *(volatile uint16_t *)(addr2) =
706 *(volatile uint16_t *)(addr1);
707 }
708 }
709
710 static __inline void
vax_mem_copy_region_4(bus_space_tag_t t,bus_space_handle_t h1,bus_size_t o1,bus_space_handle_t h2,bus_size_t o2,size_t c)711 vax_mem_copy_region_4(bus_space_tag_t t, bus_space_handle_t h1, bus_size_t o1,
712 bus_space_handle_t h2, bus_size_t o2, size_t c)
713 {
714 bus_addr_t addr1 = h1 + o1;
715 bus_addr_t addr2 = h2 + o2;
716
717 if (addr1 >= addr2) {
718 /* src after dest: copy forward */
719 for (; c != 0; c--, addr1 += 4, addr2 += 4)
720 *(volatile uint32_t *)(addr2) =
721 *(volatile uint32_t *)(addr1);
722 } else {
723 /* dest after src: copy backwards */
724 for (addr1 += 4 * (c - 1), addr2 += 4 * (c - 1);
725 c != 0; c--, addr1 -= 4, addr2 -= 4)
726 *(volatile uint32_t *)(addr2) =
727 *(volatile uint32_t *)(addr1);
728 }
729 }
730
731
732 /*
733 * Bus read/write barrier methods.
734 *
735 * void bus_space_barrier(bus_space_tag_t tag,
736 * bus_space_handle_t bsh, bus_size_t offset,
737 * bus_size_t len, int flags);
738 *
739 * Note: the vax does not currently require barriers, but we must
740 * provide the flags to MI code.
741 */
742 #define bus_space_barrier(t, h, o, l, f) \
743 ((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
744 #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
745 #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
746
747
748 /*
749 * Flags used in various bus DMA methods.
750 */
751 #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */
752 #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */
753 #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */
754 #define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */
755 #define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */
756 #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */
757 #define BUS_DMA_BUS2 0x020
758 #define BUS_DMA_BUS3 0x040
759 #define BUS_DMA_BUS4 0x080
760 #define BUS_DMA_READ 0x100 /* mapping is device -> memory only */
761 #define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */
762 #define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */
763
764 #define VAX_BUS_DMA_SPILLPAGE BUS_DMA_BUS1 /* VS4000 kludge */
765 /*
766 * Private flags stored in the DMA map.
767 */
768 #define DMAMAP_HAS_SGMAP 0x80000000 /* sgva/len are valid */
769
770 /* Forwards needed by prototypes below. */
771 struct mbuf;
772 struct uio;
773 struct vax_sgmap;
774
775 /*
776 * Operations performed by bus_dmamap_sync().
777 */
778 #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */
779 #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */
780 #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */
781 #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */
782
783 /*
784 * vax_bus_t
785 *
786 * Busses supported by NetBSD/vax, used by internal
787 * utility functions. NOT TO BE USED BY MACHINE-INDEPENDENT
788 * CODE!
789 */
790 typedef enum {
791 VAX_BUS_MAINBUS,
792 VAX_BUS_SBI,
793 VAX_BUS_MASSBUS,
794 VAX_BUS_UNIBUS, /* Also handles QBUS */
795 VAX_BUS_BI,
796 VAX_BUS_XMI,
797 VAX_BUS_TURBOCHANNEL
798 } vax_bus_t;
799
800 typedef struct vax_bus_dma_tag *bus_dma_tag_t;
801 typedef struct vax_bus_dmamap *bus_dmamap_t;
802
803 #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0)
804
805 /*
806 * bus_dma_segment_t
807 *
808 * Describes a single contiguous DMA transaction. Values
809 * are suitable for programming into DMA registers.
810 */
811 struct vax_bus_dma_segment {
812 bus_addr_t ds_addr; /* DMA address */
813 bus_size_t ds_len; /* length of transfer */
814 };
815 typedef struct vax_bus_dma_segment bus_dma_segment_t;
816
817 struct proc;
818
819 /*
820 * bus_dma_tag_t
821 *
822 * A machine-dependent opaque type describing the implementation of
823 * DMA for a given bus.
824 */
825 struct vax_bus_dma_tag {
826 void *_cookie; /* cookie used in the guts */
827 bus_addr_t _wbase; /* DMA window base */
828 bus_size_t _wsize; /* DMA window size */
829
830 /*
831 * Some chipsets have a built-in boundary constraint, independent
832 * of what the device requests. This allows that boundary to
833 * be specified. If the device has a more restrictive constraint,
834 * the map will use that, otherwise this boundary will be used.
835 * This value is ignored if 0.
836 */
837 bus_size_t _boundary;
838
839 /*
840 * A bus may have more than one SGMAP window, so SGMAP
841 * windows also get a pointer to their SGMAP state.
842 */
843 struct vax_sgmap *_sgmap;
844
845 /*
846 * Internal-use only utility methods. NOT TO BE USED BY
847 * MACHINE-INDEPENDENT CODE!
848 */
849 bus_dma_tag_t (*_get_tag)(bus_dma_tag_t, vax_bus_t);
850
851 /*
852 * DMA mapping methods.
853 */
854 int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int,
855 bus_size_t, bus_size_t, int, bus_dmamap_t *);
856 void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t);
857 int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *,
858 bus_size_t, struct proc *, int);
859 int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t,
860 struct mbuf *, int);
861 int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t,
862 struct uio *, int);
863 int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t,
864 bus_dma_segment_t *, int, bus_size_t, int);
865 void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t);
866 void (*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t,
867 bus_addr_t, bus_size_t, int);
868
869 /*
870 * DMA memory utility functions.
871 */
872 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t,
873 bus_size_t, bus_dma_segment_t *, int, int *, int);
874 void (*_dmamem_free)(bus_dma_tag_t, bus_dma_segment_t *, int);
875 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *,
876 int, size_t, void **, int);
877 void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t);
878 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *,
879 int, off_t, int, int);
880 };
881
882 #define vaxbus_dma_get_tag(t, b) \
883 (*(t)->_get_tag)(t, b)
884
885 #define bus_dmamap_create(t, s, n, m, b, f, p) \
886 (*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
887 #define bus_dmamap_destroy(t, p) \
888 (*(t)->_dmamap_destroy)((t), (p))
889 #define bus_dmamap_load(t, m, b, s, p, f) \
890 (*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
891 #define bus_dmamap_load_mbuf(t, m, b, f) \
892 (*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
893 #define bus_dmamap_load_uio(t, m, u, f) \
894 (*(t)->_dmamap_load_uio)((t), (m), (u), (f))
895 #define bus_dmamap_load_raw(t, m, sg, n, s, f) \
896 (*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
897 #define bus_dmamap_unload(t, p) \
898 (*(t)->_dmamap_unload)((t), (p))
899 #define bus_dmamap_sync(t, p, o, l, ops) \
900 (*(t)->_dmamap_sync)((t), (p), (o), (l), (ops))
901 #define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \
902 (*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f))
903 #define bus_dmamem_free(t, sg, n) \
904 (*(t)->_dmamem_free)((t), (sg), (n))
905 #define bus_dmamem_map(t, sg, n, s, k, f) \
906 (*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
907 #define bus_dmamem_unmap(t, k, s) \
908 (*(t)->_dmamem_unmap)((t), (k), (s))
909 #define bus_dmamem_mmap(t, sg, n, o, p, f) \
910 (*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f))
911
912 #define bus_dmatag_subregion(t, mna, mxa, nt, f) EOPNOTSUPP
913 #define bus_dmatag_destroy(t)
914
915 /*
916 * bus_dmamap_t
917 *
918 * Describes a DMA mapping.
919 */
920 struct vax_bus_dmamap {
921 /*
922 * PRIVATE MEMBERS: not for use my machine-independent code.
923 */
924 bus_size_t _dm_size; /* largest DMA transfer mappable */
925 int _dm_segcnt; /* number of segs this map can map */
926 bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */
927 bus_size_t _dm_boundary; /* don't cross this */
928 int _dm_flags; /* misc. flags */
929
930 /*
931 * This is used only for SGMAP-mapped DMA, but we keep it
932 * here to avoid pointless indirection.
933 */
934 int _dm_pteidx; /* PTE index */
935 int _dm_ptecnt; /* PTE count */
936 u_long _dm_sgva; /* allocated sgva */
937 bus_size_t _dm_sgvalen; /* svga length */
938
939 /*
940 * PUBLIC MEMBERS: these are used by machine-independent code.
941 */
942 bus_size_t dm_maxsegsz; /* largest possible segment */
943 bus_size_t dm_mapsize; /* size of the mapping */
944 int dm_nsegs; /* # valid segments in mapping */
945 bus_dma_segment_t dm_segs[1]; /* segments; variable length */
946 };
947
948 /*#ifdef _VAX_BUS_DMA_PRIVATE */
949 int _bus_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t,
950 bus_size_t, int, bus_dmamap_t *);
951 void _bus_dmamap_destroy(bus_dma_tag_t, bus_dmamap_t);
952
953 int _bus_dmamap_load(bus_dma_tag_t, bus_dmamap_t,
954 void *, bus_size_t, struct proc *, int);
955 int _bus_dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t, struct mbuf *, int);
956 int _bus_dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t, struct uio *, int);
957 int _bus_dmamap_load_raw(bus_dma_tag_t,
958 bus_dmamap_t, bus_dma_segment_t *, int, bus_size_t, int);
959
960 void _bus_dmamap_unload(bus_dma_tag_t, bus_dmamap_t);
961 void _bus_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
962 bus_size_t, int);
963
964 int _bus_dmamem_alloc(bus_dma_tag_t tag, bus_size_t size,
965 bus_size_t alignment, bus_size_t boundary,
966 bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags);
967 void _bus_dmamem_free(bus_dma_tag_t tag, bus_dma_segment_t *segs, int nsegs);
968 int _bus_dmamem_map(bus_dma_tag_t tag, bus_dma_segment_t *segs,
969 int nsegs, size_t size, void **kvap, int flags);
970 void _bus_dmamem_unmap(bus_dma_tag_t tag, void *kva, size_t size);
971 paddr_t _bus_dmamem_mmap(bus_dma_tag_t tag, bus_dma_segment_t *segs,
972 int nsegs, off_t off, int prot, int flags);
973 /*#endif*/ /* _VAX_BUS_DMA_PRIVATE */
974
975 #endif /* _VAX_BUS_H_ */
976